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radeonsi: cleanly communicate whether si_shader_dump should check R600_DEBUG
[mesa.git] / src / gallium / drivers / radeonsi / si_debug.c
1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Marek Olšák <maraeo@gmail.com>
25 */
26
27 #include "si_pipe.h"
28 #include "sid.h"
29 #include "sid_tables.h"
30 #include "radeon/radeon_elf_util.h"
31 #include "ddebug/dd_util.h"
32 #include "util/u_memory.h"
33
34 DEBUG_GET_ONCE_OPTION(replace_shaders, "RADEON_REPLACE_SHADERS", NULL)
35
36 static void si_dump_shader(struct si_screen *sscreen,
37 struct si_shader_ctx_state *state, FILE *f)
38 {
39 struct si_shader *current = state->current;
40
41 if (!state->cso || !current)
42 return;
43
44 if (current->shader_log)
45 fwrite(current->shader_log, current->shader_log_size, 1, f);
46 else
47 si_shader_dump(sscreen, state->current, NULL,
48 state->cso->info.processor, f, false);
49 }
50
51 /**
52 * Shader compiles can be overridden with arbitrary ELF objects by setting
53 * the environment variable RADEON_REPLACE_SHADERS=num1:filename1[;num2:filename2]
54 */
55 bool si_replace_shader(unsigned num, struct radeon_shader_binary *binary)
56 {
57 const char *p = debug_get_option_replace_shaders();
58 const char *semicolon;
59 char *copy = NULL;
60 FILE *f;
61 long filesize, nread;
62 char *buf = NULL;
63 bool replaced = false;
64
65 if (!p)
66 return false;
67
68 while (*p) {
69 unsigned long i;
70 char *endp;
71 i = strtoul(p, &endp, 0);
72
73 p = endp;
74 if (*p != ':') {
75 fprintf(stderr, "RADEON_REPLACE_SHADERS formatted badly.\n");
76 exit(1);
77 }
78 ++p;
79
80 if (i == num)
81 break;
82
83 p = strchr(p, ';');
84 if (!p)
85 return false;
86 ++p;
87 }
88 if (!*p)
89 return false;
90
91 semicolon = strchr(p, ';');
92 if (semicolon) {
93 p = copy = strndup(p, semicolon - p);
94 if (!copy) {
95 fprintf(stderr, "out of memory\n");
96 return false;
97 }
98 }
99
100 fprintf(stderr, "radeonsi: replace shader %u by %s\n", num, p);
101
102 f = fopen(p, "r");
103 if (!f) {
104 perror("radeonsi: failed to open file");
105 goto out_free;
106 }
107
108 if (fseek(f, 0, SEEK_END) != 0)
109 goto file_error;
110
111 filesize = ftell(f);
112 if (filesize < 0)
113 goto file_error;
114
115 if (fseek(f, 0, SEEK_SET) != 0)
116 goto file_error;
117
118 buf = MALLOC(filesize);
119 if (!buf) {
120 fprintf(stderr, "out of memory\n");
121 goto out_close;
122 }
123
124 nread = fread(buf, 1, filesize, f);
125 if (nread != filesize)
126 goto file_error;
127
128 radeon_elf_read(buf, filesize, binary);
129 replaced = true;
130
131 out_close:
132 fclose(f);
133 out_free:
134 FREE(buf);
135 free(copy);
136 return replaced;
137
138 file_error:
139 perror("radeonsi: reading shader");
140 goto out_close;
141 }
142
143 /* Parsed IBs are difficult to read without colors. Use "less -R file" to
144 * read them, or use "aha -b -f file" to convert them to html.
145 */
146 #define COLOR_RESET "\033[0m"
147 #define COLOR_RED "\033[31m"
148 #define COLOR_GREEN "\033[1;32m"
149 #define COLOR_YELLOW "\033[1;33m"
150 #define COLOR_CYAN "\033[1;36m"
151
152 #define INDENT_PKT 8
153
154 static void print_spaces(FILE *f, unsigned num)
155 {
156 fprintf(f, "%*s", num, "");
157 }
158
159 static void print_value(FILE *file, uint32_t value, int bits)
160 {
161 /* Guess if it's int or float */
162 if (value <= (1 << 15)) {
163 if (value <= 9)
164 fprintf(file, "%u\n", value);
165 else
166 fprintf(file, "%u (0x%0*x)\n", value, bits / 4, value);
167 } else {
168 float f = uif(value);
169
170 if (fabs(f) < 100000 && f*10 == floor(f*10))
171 fprintf(file, "%.1ff (0x%0*x)\n", f, bits / 4, value);
172 else
173 /* Don't print more leading zeros than there are bits. */
174 fprintf(file, "0x%0*x\n", bits / 4, value);
175 }
176 }
177
178 static void print_named_value(FILE *file, const char *name, uint32_t value,
179 int bits)
180 {
181 print_spaces(file, INDENT_PKT);
182 fprintf(file, COLOR_YELLOW "%s" COLOR_RESET " <- ", name);
183 print_value(file, value, bits);
184 }
185
186 static void si_dump_reg(FILE *file, unsigned offset, uint32_t value,
187 uint32_t field_mask)
188 {
189 int r, f;
190
191 for (r = 0; r < ARRAY_SIZE(sid_reg_table); r++) {
192 const struct si_reg *reg = &sid_reg_table[r];
193 const char *reg_name = sid_strings + reg->name_offset;
194
195 if (reg->offset == offset) {
196 bool first_field = true;
197
198 print_spaces(file, INDENT_PKT);
199 fprintf(file, COLOR_YELLOW "%s" COLOR_RESET " <- ",
200 reg_name);
201
202 if (!reg->num_fields) {
203 print_value(file, value, 32);
204 return;
205 }
206
207 for (f = 0; f < reg->num_fields; f++) {
208 const struct si_field *field = sid_fields_table + reg->fields_offset + f;
209 const int *values_offsets = sid_strings_offsets + field->values_offset;
210 uint32_t val = (value & field->mask) >>
211 (ffs(field->mask) - 1);
212
213 if (!(field->mask & field_mask))
214 continue;
215
216 /* Indent the field. */
217 if (!first_field)
218 print_spaces(file,
219 INDENT_PKT + strlen(reg_name) + 4);
220
221 /* Print the field. */
222 fprintf(file, "%s = ", sid_strings + field->name_offset);
223
224 if (val < field->num_values && values_offsets[val] >= 0)
225 fprintf(file, "%s\n", sid_strings + values_offsets[val]);
226 else
227 print_value(file, val,
228 util_bitcount(field->mask));
229
230 first_field = false;
231 }
232 return;
233 }
234 }
235
236 print_spaces(file, INDENT_PKT);
237 fprintf(file, COLOR_YELLOW "0x%05x" COLOR_RESET " <- 0x%08x\n", offset, value);
238 }
239
240 static void si_parse_set_reg_packet(FILE *f, uint32_t *ib, unsigned count,
241 unsigned reg_offset)
242 {
243 unsigned reg = (ib[1] << 2) + reg_offset;
244 int i;
245
246 for (i = 0; i < count; i++)
247 si_dump_reg(f, reg + i*4, ib[2+i], ~0);
248 }
249
250 static uint32_t *si_parse_packet3(FILE *f, uint32_t *ib, int *num_dw,
251 int trace_id, enum chip_class chip_class)
252 {
253 unsigned count = PKT_COUNT_G(ib[0]);
254 unsigned op = PKT3_IT_OPCODE_G(ib[0]);
255 const char *predicate = PKT3_PREDICATE(ib[0]) ? "(predicate)" : "";
256 int i;
257
258 /* Print the name first. */
259 for (i = 0; i < ARRAY_SIZE(packet3_table); i++)
260 if (packet3_table[i].op == op)
261 break;
262
263 if (i < ARRAY_SIZE(packet3_table)) {
264 const char *name = sid_strings + packet3_table[i].name_offset;
265
266 if (op == PKT3_SET_CONTEXT_REG ||
267 op == PKT3_SET_CONFIG_REG ||
268 op == PKT3_SET_UCONFIG_REG ||
269 op == PKT3_SET_SH_REG)
270 fprintf(f, COLOR_CYAN "%s%s" COLOR_CYAN ":\n",
271 name, predicate);
272 else
273 fprintf(f, COLOR_GREEN "%s%s" COLOR_RESET ":\n",
274 name, predicate);
275 } else
276 fprintf(f, COLOR_RED "PKT3_UNKNOWN 0x%x%s" COLOR_RESET ":\n",
277 op, predicate);
278
279 /* Print the contents. */
280 switch (op) {
281 case PKT3_SET_CONTEXT_REG:
282 si_parse_set_reg_packet(f, ib, count, SI_CONTEXT_REG_OFFSET);
283 break;
284 case PKT3_SET_CONFIG_REG:
285 si_parse_set_reg_packet(f, ib, count, SI_CONFIG_REG_OFFSET);
286 break;
287 case PKT3_SET_UCONFIG_REG:
288 si_parse_set_reg_packet(f, ib, count, CIK_UCONFIG_REG_OFFSET);
289 break;
290 case PKT3_SET_SH_REG:
291 si_parse_set_reg_packet(f, ib, count, SI_SH_REG_OFFSET);
292 break;
293 case PKT3_ACQUIRE_MEM:
294 si_dump_reg(f, R_0301F0_CP_COHER_CNTL, ib[1], ~0);
295 si_dump_reg(f, R_0301F4_CP_COHER_SIZE, ib[2], ~0);
296 si_dump_reg(f, R_030230_CP_COHER_SIZE_HI, ib[3], ~0);
297 si_dump_reg(f, R_0301F8_CP_COHER_BASE, ib[4], ~0);
298 si_dump_reg(f, R_0301E4_CP_COHER_BASE_HI, ib[5], ~0);
299 print_named_value(f, "POLL_INTERVAL", ib[6], 16);
300 break;
301 case PKT3_SURFACE_SYNC:
302 if (chip_class >= CIK) {
303 si_dump_reg(f, R_0301F0_CP_COHER_CNTL, ib[1], ~0);
304 si_dump_reg(f, R_0301F4_CP_COHER_SIZE, ib[2], ~0);
305 si_dump_reg(f, R_0301F8_CP_COHER_BASE, ib[3], ~0);
306 } else {
307 si_dump_reg(f, R_0085F0_CP_COHER_CNTL, ib[1], ~0);
308 si_dump_reg(f, R_0085F4_CP_COHER_SIZE, ib[2], ~0);
309 si_dump_reg(f, R_0085F8_CP_COHER_BASE, ib[3], ~0);
310 }
311 print_named_value(f, "POLL_INTERVAL", ib[4], 16);
312 break;
313 case PKT3_EVENT_WRITE:
314 si_dump_reg(f, R_028A90_VGT_EVENT_INITIATOR, ib[1],
315 S_028A90_EVENT_TYPE(~0));
316 print_named_value(f, "EVENT_INDEX", (ib[1] >> 8) & 0xf, 4);
317 print_named_value(f, "INV_L2", (ib[1] >> 20) & 0x1, 1);
318 if (count > 0) {
319 print_named_value(f, "ADDRESS_LO", ib[2], 32);
320 print_named_value(f, "ADDRESS_HI", ib[3], 16);
321 }
322 break;
323 case PKT3_DRAW_INDEX_AUTO:
324 si_dump_reg(f, R_030930_VGT_NUM_INDICES, ib[1], ~0);
325 si_dump_reg(f, R_0287F0_VGT_DRAW_INITIATOR, ib[2], ~0);
326 break;
327 case PKT3_DRAW_INDEX_2:
328 si_dump_reg(f, R_028A78_VGT_DMA_MAX_SIZE, ib[1], ~0);
329 si_dump_reg(f, R_0287E8_VGT_DMA_BASE, ib[2], ~0);
330 si_dump_reg(f, R_0287E4_VGT_DMA_BASE_HI, ib[3], ~0);
331 si_dump_reg(f, R_030930_VGT_NUM_INDICES, ib[4], ~0);
332 si_dump_reg(f, R_0287F0_VGT_DRAW_INITIATOR, ib[5], ~0);
333 break;
334 case PKT3_INDEX_TYPE:
335 si_dump_reg(f, R_028A7C_VGT_DMA_INDEX_TYPE, ib[1], ~0);
336 break;
337 case PKT3_NUM_INSTANCES:
338 si_dump_reg(f, R_030934_VGT_NUM_INSTANCES, ib[1], ~0);
339 break;
340 case PKT3_WRITE_DATA:
341 si_dump_reg(f, R_370_CONTROL, ib[1], ~0);
342 si_dump_reg(f, R_371_DST_ADDR_LO, ib[2], ~0);
343 si_dump_reg(f, R_372_DST_ADDR_HI, ib[3], ~0);
344 for (i = 2; i < count; i++) {
345 print_spaces(f, INDENT_PKT);
346 fprintf(f, "0x%08x\n", ib[2+i]);
347 }
348 break;
349 case PKT3_CP_DMA:
350 si_dump_reg(f, R_410_CP_DMA_WORD0, ib[1], ~0);
351 si_dump_reg(f, R_411_CP_DMA_WORD1, ib[2], ~0);
352 si_dump_reg(f, R_412_CP_DMA_WORD2, ib[3], ~0);
353 si_dump_reg(f, R_413_CP_DMA_WORD3, ib[4], ~0);
354 si_dump_reg(f, R_414_COMMAND, ib[5], ~0);
355 break;
356 case PKT3_DMA_DATA:
357 si_dump_reg(f, R_500_DMA_DATA_WORD0, ib[1], ~0);
358 si_dump_reg(f, R_501_SRC_ADDR_LO, ib[2], ~0);
359 si_dump_reg(f, R_502_SRC_ADDR_HI, ib[3], ~0);
360 si_dump_reg(f, R_503_DST_ADDR_LO, ib[4], ~0);
361 si_dump_reg(f, R_504_DST_ADDR_HI, ib[5], ~0);
362 si_dump_reg(f, R_414_COMMAND, ib[6], ~0);
363 break;
364 case PKT3_INDIRECT_BUFFER_SI:
365 case PKT3_INDIRECT_BUFFER_CONST:
366 case PKT3_INDIRECT_BUFFER_CIK:
367 si_dump_reg(f, R_3F0_IB_BASE_LO, ib[1], ~0);
368 si_dump_reg(f, R_3F1_IB_BASE_HI, ib[2], ~0);
369 si_dump_reg(f, R_3F2_CONTROL, ib[3], ~0);
370 break;
371 case PKT3_CLEAR_STATE:
372 case PKT3_INCREMENT_DE_COUNTER:
373 case PKT3_PFP_SYNC_ME:
374 break;
375 case PKT3_NOP:
376 if (ib[0] == 0xffff1000) {
377 count = -1; /* One dword NOP. */
378 break;
379 } else if (count == 0 && SI_IS_TRACE_POINT(ib[1])) {
380 unsigned packet_id = SI_GET_TRACE_POINT_ID(ib[1]);
381
382 print_spaces(f, INDENT_PKT);
383 fprintf(f, COLOR_RED "Trace point ID: %u\n", packet_id);
384
385 if (trace_id == -1)
386 break; /* tracing was disabled */
387
388 print_spaces(f, INDENT_PKT);
389 if (packet_id < trace_id)
390 fprintf(f, COLOR_RED
391 "This trace point was reached by the CP."
392 COLOR_RESET "\n");
393 else if (packet_id == trace_id)
394 fprintf(f, COLOR_RED
395 "!!!!! This is the last trace point that "
396 "was reached by the CP !!!!!"
397 COLOR_RESET "\n");
398 else if (packet_id+1 == trace_id)
399 fprintf(f, COLOR_RED
400 "!!!!! This is the first trace point that "
401 "was NOT been reached by the CP !!!!!"
402 COLOR_RESET "\n");
403 else
404 fprintf(f, COLOR_RED
405 "!!!!! This trace point was NOT reached "
406 "by the CP !!!!!"
407 COLOR_RESET "\n");
408 break;
409 }
410 /* fall through, print all dwords */
411 default:
412 for (i = 0; i < count+1; i++) {
413 print_spaces(f, INDENT_PKT);
414 fprintf(f, "0x%08x\n", ib[1+i]);
415 }
416 }
417
418 ib += count + 2;
419 *num_dw -= count + 2;
420 return ib;
421 }
422
423 /**
424 * Parse and print an IB into a file.
425 *
426 * \param f file
427 * \param ib IB
428 * \param num_dw size of the IB
429 * \param chip_class chip class
430 * \param trace_id the last trace ID that is known to have been reached
431 * and executed by the CP, typically read from a buffer
432 */
433 static void si_parse_ib(FILE *f, uint32_t *ib, int num_dw, int trace_id,
434 const char *name, enum chip_class chip_class)
435 {
436 fprintf(f, "------------------ %s begin ------------------\n", name);
437
438 while (num_dw > 0) {
439 unsigned type = PKT_TYPE_G(ib[0]);
440
441 switch (type) {
442 case 3:
443 ib = si_parse_packet3(f, ib, &num_dw, trace_id,
444 chip_class);
445 break;
446 case 2:
447 /* type-2 nop */
448 if (ib[0] == 0x80000000) {
449 fprintf(f, COLOR_GREEN "NOP (type 2)" COLOR_RESET "\n");
450 ib++;
451 break;
452 }
453 /* fall through */
454 default:
455 fprintf(f, "Unknown packet type %i\n", type);
456 return;
457 }
458 }
459
460 fprintf(f, "------------------- %s end -------------------\n", name);
461 if (num_dw < 0) {
462 printf("Packet ends after the end of IB.\n");
463 exit(0);
464 }
465 fprintf(f, "\n");
466 }
467
468 static void si_dump_mmapped_reg(struct si_context *sctx, FILE *f,
469 unsigned offset)
470 {
471 struct radeon_winsys *ws = sctx->b.ws;
472 uint32_t value;
473
474 if (ws->read_registers(ws, offset, 1, &value))
475 si_dump_reg(f, offset, value, ~0);
476 }
477
478 static void si_dump_debug_registers(struct si_context *sctx, FILE *f)
479 {
480 if (sctx->screen->b.info.drm_major == 2 &&
481 sctx->screen->b.info.drm_minor < 42)
482 return; /* no radeon support */
483
484 fprintf(f, "Memory-mapped registers:\n");
485 si_dump_mmapped_reg(sctx, f, R_008010_GRBM_STATUS);
486
487 /* No other registers can be read on DRM < 3.1.0. */
488 if (sctx->screen->b.info.drm_major < 3 ||
489 sctx->screen->b.info.drm_minor < 1) {
490 fprintf(f, "\n");
491 return;
492 }
493
494 si_dump_mmapped_reg(sctx, f, R_008008_GRBM_STATUS2);
495 si_dump_mmapped_reg(sctx, f, R_008014_GRBM_STATUS_SE0);
496 si_dump_mmapped_reg(sctx, f, R_008018_GRBM_STATUS_SE1);
497 si_dump_mmapped_reg(sctx, f, R_008038_GRBM_STATUS_SE2);
498 si_dump_mmapped_reg(sctx, f, R_00803C_GRBM_STATUS_SE3);
499 si_dump_mmapped_reg(sctx, f, R_00D034_SDMA0_STATUS_REG);
500 si_dump_mmapped_reg(sctx, f, R_00D834_SDMA1_STATUS_REG);
501 si_dump_mmapped_reg(sctx, f, R_000E50_SRBM_STATUS);
502 si_dump_mmapped_reg(sctx, f, R_000E4C_SRBM_STATUS2);
503 si_dump_mmapped_reg(sctx, f, R_000E54_SRBM_STATUS3);
504 si_dump_mmapped_reg(sctx, f, R_008680_CP_STAT);
505 si_dump_mmapped_reg(sctx, f, R_008674_CP_STALLED_STAT1);
506 si_dump_mmapped_reg(sctx, f, R_008678_CP_STALLED_STAT2);
507 si_dump_mmapped_reg(sctx, f, R_008670_CP_STALLED_STAT3);
508 si_dump_mmapped_reg(sctx, f, R_008210_CP_CPC_STATUS);
509 si_dump_mmapped_reg(sctx, f, R_008214_CP_CPC_BUSY_STAT);
510 si_dump_mmapped_reg(sctx, f, R_008218_CP_CPC_STALLED_STAT1);
511 si_dump_mmapped_reg(sctx, f, R_00821C_CP_CPF_STATUS);
512 si_dump_mmapped_reg(sctx, f, R_008220_CP_CPF_BUSY_STAT);
513 si_dump_mmapped_reg(sctx, f, R_008224_CP_CPF_STALLED_STAT1);
514 fprintf(f, "\n");
515 }
516
517 static void si_dump_last_ib(struct si_context *sctx, FILE *f)
518 {
519 int last_trace_id = -1;
520
521 if (!sctx->last_gfx.ib)
522 return;
523
524 if (sctx->last_trace_buf) {
525 /* We are expecting that the ddebug pipe has already
526 * waited for the context, so this buffer should be idle.
527 * If the GPU is hung, there is no point in waiting for it.
528 */
529 uint32_t *map = sctx->b.ws->buffer_map(sctx->last_trace_buf->buf,
530 NULL,
531 PIPE_TRANSFER_UNSYNCHRONIZED |
532 PIPE_TRANSFER_READ);
533 if (map)
534 last_trace_id = *map;
535 }
536
537 if (sctx->init_config)
538 si_parse_ib(f, sctx->init_config->pm4, sctx->init_config->ndw,
539 -1, "IB2: Init config", sctx->b.chip_class);
540
541 if (sctx->init_config_gs_rings)
542 si_parse_ib(f, sctx->init_config_gs_rings->pm4,
543 sctx->init_config_gs_rings->ndw,
544 -1, "IB2: Init GS rings", sctx->b.chip_class);
545
546 si_parse_ib(f, sctx->last_gfx.ib, sctx->last_gfx.num_dw,
547 last_trace_id, "IB", sctx->b.chip_class);
548 }
549
550 static const char *priority_to_string(enum radeon_bo_priority priority)
551 {
552 #define ITEM(x) [RADEON_PRIO_##x] = #x
553 static const char *table[64] = {
554 ITEM(FENCE),
555 ITEM(TRACE),
556 ITEM(SO_FILLED_SIZE),
557 ITEM(QUERY),
558 ITEM(IB1),
559 ITEM(IB2),
560 ITEM(DRAW_INDIRECT),
561 ITEM(INDEX_BUFFER),
562 ITEM(VCE),
563 ITEM(UVD),
564 ITEM(SDMA_BUFFER),
565 ITEM(SDMA_TEXTURE),
566 ITEM(CP_DMA),
567 ITEM(CONST_BUFFER),
568 ITEM(DESCRIPTORS),
569 ITEM(BORDER_COLORS),
570 ITEM(SAMPLER_BUFFER),
571 ITEM(VERTEX_BUFFER),
572 ITEM(SHADER_RW_BUFFER),
573 ITEM(COMPUTE_GLOBAL),
574 ITEM(SAMPLER_TEXTURE),
575 ITEM(SHADER_RW_IMAGE),
576 ITEM(SAMPLER_TEXTURE_MSAA),
577 ITEM(COLOR_BUFFER),
578 ITEM(DEPTH_BUFFER),
579 ITEM(COLOR_BUFFER_MSAA),
580 ITEM(DEPTH_BUFFER_MSAA),
581 ITEM(CMASK),
582 ITEM(DCC),
583 ITEM(HTILE),
584 ITEM(SHADER_BINARY),
585 ITEM(SHADER_RINGS),
586 ITEM(SCRATCH_BUFFER),
587 };
588 #undef ITEM
589
590 assert(priority < ARRAY_SIZE(table));
591 return table[priority];
592 }
593
594 static int bo_list_compare_va(const struct radeon_bo_list_item *a,
595 const struct radeon_bo_list_item *b)
596 {
597 return a->vm_address < b->vm_address ? -1 :
598 a->vm_address > b->vm_address ? 1 : 0;
599 }
600
601 static void si_dump_bo_list(struct si_context *sctx,
602 const struct radeon_saved_cs *saved, FILE *f)
603 {
604 unsigned i,j;
605
606 if (!saved->bo_list)
607 return;
608
609 /* Sort the list according to VM adddresses first. */
610 qsort(saved->bo_list, saved->bo_count,
611 sizeof(saved->bo_list[0]), (void*)bo_list_compare_va);
612
613 fprintf(f, "Buffer list (in units of pages = 4kB):\n"
614 COLOR_YELLOW " Size VM start page "
615 "VM end page Usage" COLOR_RESET "\n");
616
617 for (i = 0; i < saved->bo_count; i++) {
618 /* Note: Buffer sizes are expected to be aligned to 4k by the winsys. */
619 const unsigned page_size = sctx->b.screen->info.gart_page_size;
620 uint64_t va = saved->bo_list[i].vm_address;
621 uint64_t size = saved->bo_list[i].bo_size;
622 bool hit = false;
623
624 /* If there's unused virtual memory between 2 buffers, print it. */
625 if (i) {
626 uint64_t previous_va_end = saved->bo_list[i-1].vm_address +
627 saved->bo_list[i-1].bo_size;
628
629 if (va > previous_va_end) {
630 fprintf(f, " %10"PRIu64" -- hole --\n",
631 (va - previous_va_end) / page_size);
632 }
633 }
634
635 /* Print the buffer. */
636 fprintf(f, " %10"PRIu64" 0x%013"PRIX64" 0x%013"PRIX64" ",
637 size / page_size, va / page_size, (va + size) / page_size);
638
639 /* Print the usage. */
640 for (j = 0; j < 64; j++) {
641 if (!(saved->bo_list[i].priority_usage & (1llu << j)))
642 continue;
643
644 fprintf(f, "%s%s", !hit ? "" : ", ", priority_to_string(j));
645 hit = true;
646 }
647 fprintf(f, "\n");
648 }
649 fprintf(f, "\nNote: The holes represent memory not used by the IB.\n"
650 " Other buffers can still be allocated there.\n\n");
651 }
652
653 static void si_dump_framebuffer(struct si_context *sctx, FILE *f)
654 {
655 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
656 struct r600_texture *rtex;
657 int i;
658
659 for (i = 0; i < state->nr_cbufs; i++) {
660 if (!state->cbufs[i])
661 continue;
662
663 rtex = (struct r600_texture*)state->cbufs[i]->texture;
664 fprintf(f, COLOR_YELLOW "Color buffer %i:" COLOR_RESET "\n", i);
665 r600_print_texture_info(rtex, f);
666 fprintf(f, "\n");
667 }
668
669 if (state->zsbuf) {
670 rtex = (struct r600_texture*)state->zsbuf->texture;
671 fprintf(f, COLOR_YELLOW "Depth-stencil buffer:" COLOR_RESET "\n");
672 r600_print_texture_info(rtex, f);
673 fprintf(f, "\n");
674 }
675 }
676
677 static void si_dump_descriptor_list(struct si_descriptors *desc,
678 const char *shader_name,
679 const char *elem_name,
680 unsigned num_elements,
681 FILE *f)
682 {
683 unsigned i, j;
684 uint32_t *cpu_list = desc->list;
685 uint32_t *gpu_list = desc->gpu_list;
686 const char *list_note = "GPU list";
687
688 if (!gpu_list) {
689 gpu_list = cpu_list;
690 list_note = "CPU list";
691 }
692
693 for (i = 0; i < num_elements; i++) {
694 fprintf(f, COLOR_GREEN "%s%s slot %u (%s):" COLOR_RESET "\n",
695 shader_name, elem_name, i, list_note);
696
697 switch (desc->element_dw_size) {
698 case 4:
699 for (j = 0; j < 4; j++)
700 si_dump_reg(f, R_008F00_SQ_BUF_RSRC_WORD0 + j*4,
701 gpu_list[j], 0xffffffff);
702 break;
703 case 8:
704 for (j = 0; j < 8; j++)
705 si_dump_reg(f, R_008F10_SQ_IMG_RSRC_WORD0 + j*4,
706 gpu_list[j], 0xffffffff);
707
708 fprintf(f, COLOR_CYAN " Buffer:" COLOR_RESET "\n");
709 for (j = 0; j < 4; j++)
710 si_dump_reg(f, R_008F00_SQ_BUF_RSRC_WORD0 + j*4,
711 gpu_list[4+j], 0xffffffff);
712 break;
713 case 16:
714 for (j = 0; j < 8; j++)
715 si_dump_reg(f, R_008F10_SQ_IMG_RSRC_WORD0 + j*4,
716 gpu_list[j], 0xffffffff);
717
718 fprintf(f, COLOR_CYAN " Buffer:" COLOR_RESET "\n");
719 for (j = 0; j < 4; j++)
720 si_dump_reg(f, R_008F00_SQ_BUF_RSRC_WORD0 + j*4,
721 gpu_list[4+j], 0xffffffff);
722
723 fprintf(f, COLOR_CYAN " FMASK:" COLOR_RESET "\n");
724 for (j = 0; j < 8; j++)
725 si_dump_reg(f, R_008F10_SQ_IMG_RSRC_WORD0 + j*4,
726 gpu_list[8+j], 0xffffffff);
727
728 fprintf(f, COLOR_CYAN " Sampler state:" COLOR_RESET "\n");
729 for (j = 0; j < 4; j++)
730 si_dump_reg(f, R_008F30_SQ_IMG_SAMP_WORD0 + j*4,
731 gpu_list[12+j], 0xffffffff);
732 break;
733 }
734
735 if (memcmp(gpu_list, cpu_list, desc->element_dw_size * 4) != 0) {
736 fprintf(f, COLOR_RED "!!!!! This slot was corrupted in GPU memory !!!!!"
737 COLOR_RESET "\n");
738 }
739
740 fprintf(f, "\n");
741 gpu_list += desc->element_dw_size;
742 cpu_list += desc->element_dw_size;
743 }
744 }
745
746 static void si_dump_descriptors(struct si_context *sctx,
747 struct si_shader_ctx_state *state,
748 FILE *f)
749 {
750 if (!state->cso || !state->current)
751 return;
752
753 unsigned type = state->cso->type;
754 const struct tgsi_shader_info *info = &state->cso->info;
755 struct si_descriptors *descs =
756 &sctx->descriptors[SI_DESCS_FIRST_SHADER +
757 type * SI_NUM_SHADER_DESCS];
758 static const char *shader_name[] = {"VS", "PS", "GS", "TCS", "TES", "CS"};
759
760 static const char *elem_name[] = {
761 " - Constant buffer",
762 " - Shader buffer",
763 " - Sampler",
764 " - Image",
765 };
766 unsigned num_elements[] = {
767 util_last_bit(info->const_buffers_declared),
768 util_last_bit(info->shader_buffers_declared),
769 util_last_bit(info->samplers_declared),
770 util_last_bit(info->images_declared),
771 };
772
773 if (type == PIPE_SHADER_VERTEX) {
774 si_dump_descriptor_list(&sctx->vertex_buffers, shader_name[type],
775 " - Vertex buffer", info->num_inputs, f);
776 }
777
778 for (unsigned i = 0; i < SI_NUM_SHADER_DESCS; ++i, ++descs)
779 si_dump_descriptor_list(descs, shader_name[type], elem_name[i],
780 num_elements[i], f);
781 }
782
783 static void si_dump_debug_state(struct pipe_context *ctx, FILE *f,
784 unsigned flags)
785 {
786 struct si_context *sctx = (struct si_context*)ctx;
787
788 if (flags & PIPE_DUMP_DEVICE_STATUS_REGISTERS)
789 si_dump_debug_registers(sctx, f);
790
791 if (flags & PIPE_DUMP_CURRENT_STATES)
792 si_dump_framebuffer(sctx, f);
793
794 if (flags & PIPE_DUMP_CURRENT_SHADERS) {
795 si_dump_shader(sctx->screen, &sctx->vs_shader, f);
796 si_dump_shader(sctx->screen, &sctx->tcs_shader, f);
797 si_dump_shader(sctx->screen, &sctx->tes_shader, f);
798 si_dump_shader(sctx->screen, &sctx->gs_shader, f);
799 si_dump_shader(sctx->screen, &sctx->ps_shader, f);
800
801 si_dump_descriptor_list(&sctx->descriptors[SI_DESCS_RW_BUFFERS],
802 "", "RW buffers", SI_NUM_RW_BUFFERS, f);
803 si_dump_descriptors(sctx, &sctx->vs_shader, f);
804 si_dump_descriptors(sctx, &sctx->tcs_shader, f);
805 si_dump_descriptors(sctx, &sctx->tes_shader, f);
806 si_dump_descriptors(sctx, &sctx->gs_shader, f);
807 si_dump_descriptors(sctx, &sctx->ps_shader, f);
808 }
809
810 if (flags & PIPE_DUMP_LAST_COMMAND_BUFFER) {
811 si_dump_bo_list(sctx, &sctx->last_gfx, f);
812 si_dump_last_ib(sctx, f);
813
814 fprintf(f, "Done.\n");
815
816 /* dump only once */
817 radeon_clear_saved_cs(&sctx->last_gfx);
818 r600_resource_reference(&sctx->last_trace_buf, NULL);
819 }
820 }
821
822 static void si_dump_dma(struct si_context *sctx,
823 struct radeon_saved_cs *saved, FILE *f)
824 {
825 static const char ib_name[] = "sDMA IB";
826 unsigned i;
827
828 si_dump_bo_list(sctx, saved, f);
829
830 fprintf(f, "------------------ %s begin ------------------\n", ib_name);
831
832 for (i = 0; i < saved->num_dw; ++i) {
833 fprintf(f, " %08x\n", saved->ib[i]);
834 }
835
836 fprintf(f, "------------------- %s end -------------------\n", ib_name);
837 fprintf(f, "\n");
838
839 fprintf(f, "SDMA Dump Done.\n");
840 }
841
842 static bool si_vm_fault_occured(struct si_context *sctx, uint32_t *out_addr)
843 {
844 char line[2000];
845 unsigned sec, usec;
846 int progress = 0;
847 uint64_t timestamp = 0;
848 bool fault = false;
849
850 FILE *p = popen("dmesg", "r");
851 if (!p)
852 return false;
853
854 while (fgets(line, sizeof(line), p)) {
855 char *msg, len;
856
857 if (!line[0] || line[0] == '\n')
858 continue;
859
860 /* Get the timestamp. */
861 if (sscanf(line, "[%u.%u]", &sec, &usec) != 2) {
862 static bool hit = false;
863 if (!hit) {
864 fprintf(stderr, "%s: failed to parse line '%s'\n",
865 __func__, line);
866 hit = true;
867 }
868 continue;
869 }
870 timestamp = sec * 1000000llu + usec;
871
872 /* If just updating the timestamp. */
873 if (!out_addr)
874 continue;
875
876 /* Process messages only if the timestamp is newer. */
877 if (timestamp <= sctx->dmesg_timestamp)
878 continue;
879
880 /* Only process the first VM fault. */
881 if (fault)
882 continue;
883
884 /* Remove trailing \n */
885 len = strlen(line);
886 if (len && line[len-1] == '\n')
887 line[len-1] = 0;
888
889 /* Get the message part. */
890 msg = strchr(line, ']');
891 if (!msg) {
892 assert(0);
893 continue;
894 }
895 msg++;
896
897 switch (progress) {
898 case 0:
899 if (strstr(msg, "GPU fault detected:"))
900 progress = 1;
901 break;
902 case 1:
903 msg = strstr(msg, "VM_CONTEXT1_PROTECTION_FAULT_ADDR");
904 if (msg) {
905 msg = strstr(msg, "0x");
906 if (msg) {
907 msg += 2;
908 if (sscanf(msg, "%X", out_addr) == 1)
909 fault = true;
910 }
911 }
912 progress = 0;
913 break;
914 default:
915 progress = 0;
916 }
917 }
918 pclose(p);
919
920 if (timestamp > sctx->dmesg_timestamp)
921 sctx->dmesg_timestamp = timestamp;
922 return fault;
923 }
924
925 void si_check_vm_faults(struct r600_common_context *ctx,
926 struct radeon_saved_cs *saved, enum ring_type ring)
927 {
928 struct si_context *sctx = (struct si_context *)ctx;
929 struct pipe_screen *screen = sctx->b.b.screen;
930 FILE *f;
931 uint32_t addr;
932 char cmd_line[4096];
933
934 if (!si_vm_fault_occured(sctx, &addr))
935 return;
936
937 f = dd_get_debug_file(false);
938 if (!f)
939 return;
940
941 fprintf(f, "VM fault report.\n\n");
942 if (os_get_command_line(cmd_line, sizeof(cmd_line)))
943 fprintf(f, "Command: %s\n", cmd_line);
944 fprintf(f, "Driver vendor: %s\n", screen->get_vendor(screen));
945 fprintf(f, "Device vendor: %s\n", screen->get_device_vendor(screen));
946 fprintf(f, "Device name: %s\n\n", screen->get_name(screen));
947 fprintf(f, "Failing VM page: 0x%08x\n\n", addr);
948
949 if (sctx->apitrace_call_number)
950 fprintf(f, "Last apitrace call: %u\n\n",
951 sctx->apitrace_call_number);
952
953 switch (ring) {
954 case RING_GFX:
955 si_dump_debug_state(&sctx->b.b, f,
956 PIPE_DUMP_CURRENT_STATES |
957 PIPE_DUMP_CURRENT_SHADERS |
958 PIPE_DUMP_LAST_COMMAND_BUFFER);
959 break;
960
961 case RING_DMA:
962 si_dump_dma(sctx, saved, f);
963 break;
964
965 default:
966 break;
967 }
968
969 fclose(f);
970
971 fprintf(stderr, "Detected a VM fault, exiting...\n");
972 exit(0);
973 }
974
975 void si_init_debug_functions(struct si_context *sctx)
976 {
977 sctx->b.b.dump_debug_state = si_dump_debug_state;
978 sctx->b.check_vm_faults = si_check_vm_faults;
979
980 /* Set the initial dmesg timestamp for this context, so that
981 * only new messages will be checked for VM faults.
982 */
983 if (sctx->screen->b.debug_flags & DBG_CHECK_VM)
984 si_vm_fault_occured(sctx, NULL);
985 }