radeonsi: parse SURFACE_SYNC correctly on CIK-VI
[mesa.git] / src / gallium / drivers / radeonsi / si_debug.c
1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Marek Olšák <maraeo@gmail.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "sid_tables.h"
31 #include "radeon/radeon_elf_util.h"
32 #include "ddebug/dd_util.h"
33 #include "util/u_memory.h"
34
35 DEBUG_GET_ONCE_OPTION(replace_shaders, "RADEON_REPLACE_SHADERS", NULL)
36
37 static void si_dump_shader(struct si_screen *sscreen,
38 struct si_shader_ctx_state *state, FILE *f)
39 {
40 struct si_shader *current = state->current;
41
42 if (!state->cso || !current)
43 return;
44
45 if (current->shader_log)
46 fwrite(current->shader_log, current->shader_log_size, 1, f);
47 else
48 si_shader_dump(sscreen, state->current, NULL,
49 state->cso->info.processor, f);
50 }
51
52 /**
53 * Shader compiles can be overridden with arbitrary ELF objects by setting
54 * the environment variable RADEON_REPLACE_SHADERS=num1:filename1[;num2:filename2]
55 */
56 bool si_replace_shader(unsigned num, struct radeon_shader_binary *binary)
57 {
58 const char *p = debug_get_option_replace_shaders();
59 const char *semicolon;
60 char *copy = NULL;
61 FILE *f;
62 long filesize, nread;
63 char *buf = NULL;
64 bool replaced = false;
65
66 if (!p)
67 return false;
68
69 while (*p) {
70 unsigned long i;
71 char *endp;
72 i = strtoul(p, &endp, 0);
73
74 p = endp;
75 if (*p != ':') {
76 fprintf(stderr, "RADEON_REPLACE_SHADERS formatted badly.\n");
77 exit(1);
78 }
79 ++p;
80
81 if (i == num)
82 break;
83
84 p = strchr(p, ';');
85 if (!p)
86 return false;
87 ++p;
88 }
89 if (!*p)
90 return false;
91
92 semicolon = strchr(p, ';');
93 if (semicolon) {
94 p = copy = strndup(p, semicolon - p);
95 if (!copy) {
96 fprintf(stderr, "out of memory\n");
97 return false;
98 }
99 }
100
101 fprintf(stderr, "radeonsi: replace shader %u by %s\n", num, p);
102
103 f = fopen(p, "r");
104 if (!f) {
105 perror("radeonsi: failed to open file");
106 goto out_free;
107 }
108
109 if (fseek(f, 0, SEEK_END) != 0)
110 goto file_error;
111
112 filesize = ftell(f);
113 if (filesize < 0)
114 goto file_error;
115
116 if (fseek(f, 0, SEEK_SET) != 0)
117 goto file_error;
118
119 buf = MALLOC(filesize);
120 if (!buf) {
121 fprintf(stderr, "out of memory\n");
122 goto out_close;
123 }
124
125 nread = fread(buf, 1, filesize, f);
126 if (nread != filesize)
127 goto file_error;
128
129 radeon_elf_read(buf, filesize, binary);
130 replaced = true;
131
132 out_close:
133 fclose(f);
134 out_free:
135 FREE(buf);
136 free(copy);
137 return replaced;
138
139 file_error:
140 perror("radeonsi: reading shader");
141 goto out_close;
142 }
143
144 /* Parsed IBs are difficult to read without colors. Use "less -R file" to
145 * read them, or use "aha -b -f file" to convert them to html.
146 */
147 #define COLOR_RESET "\033[0m"
148 #define COLOR_RED "\033[31m"
149 #define COLOR_GREEN "\033[1;32m"
150 #define COLOR_YELLOW "\033[1;33m"
151 #define COLOR_CYAN "\033[1;36m"
152
153 #define INDENT_PKT 8
154
155 static void print_spaces(FILE *f, unsigned num)
156 {
157 fprintf(f, "%*s", num, "");
158 }
159
160 static void print_value(FILE *file, uint32_t value, int bits)
161 {
162 /* Guess if it's int or float */
163 if (value <= (1 << 15)) {
164 if (value <= 9)
165 fprintf(file, "%u\n", value);
166 else
167 fprintf(file, "%u (0x%0*x)\n", value, bits / 4, value);
168 } else {
169 float f = uif(value);
170
171 if (fabs(f) < 100000 && f*10 == floor(f*10))
172 fprintf(file, "%.1ff (0x%0*x)\n", f, bits / 4, value);
173 else
174 /* Don't print more leading zeros than there are bits. */
175 fprintf(file, "0x%0*x\n", bits / 4, value);
176 }
177 }
178
179 static void print_named_value(FILE *file, const char *name, uint32_t value,
180 int bits)
181 {
182 print_spaces(file, INDENT_PKT);
183 fprintf(file, COLOR_YELLOW "%s" COLOR_RESET " <- ", name);
184 print_value(file, value, bits);
185 }
186
187 static void si_dump_reg(FILE *file, unsigned offset, uint32_t value,
188 uint32_t field_mask)
189 {
190 int r, f;
191
192 for (r = 0; r < ARRAY_SIZE(sid_reg_table); r++) {
193 const struct si_reg *reg = &sid_reg_table[r];
194 const char *reg_name = sid_strings + reg->name_offset;
195
196 if (reg->offset == offset) {
197 bool first_field = true;
198
199 print_spaces(file, INDENT_PKT);
200 fprintf(file, COLOR_YELLOW "%s" COLOR_RESET " <- ",
201 reg_name);
202
203 if (!reg->num_fields) {
204 print_value(file, value, 32);
205 return;
206 }
207
208 for (f = 0; f < reg->num_fields; f++) {
209 const struct si_field *field = sid_fields_table + reg->fields_offset + f;
210 const int *values_offsets = sid_strings_offsets + field->values_offset;
211 uint32_t val = (value & field->mask) >>
212 (ffs(field->mask) - 1);
213
214 if (!(field->mask & field_mask))
215 continue;
216
217 /* Indent the field. */
218 if (!first_field)
219 print_spaces(file,
220 INDENT_PKT + strlen(reg_name) + 4);
221
222 /* Print the field. */
223 fprintf(file, "%s = ", sid_strings + field->name_offset);
224
225 if (val < field->num_values && values_offsets[val] >= 0)
226 fprintf(file, "%s\n", sid_strings + values_offsets[val]);
227 else
228 print_value(file, val,
229 util_bitcount(field->mask));
230
231 first_field = false;
232 }
233 return;
234 }
235 }
236
237 fprintf(file, COLOR_YELLOW "0x%05x" COLOR_RESET " = 0x%08x", offset, value);
238 }
239
240 static void si_parse_set_reg_packet(FILE *f, uint32_t *ib, unsigned count,
241 unsigned reg_offset)
242 {
243 unsigned reg = (ib[1] << 2) + reg_offset;
244 int i;
245
246 for (i = 0; i < count; i++)
247 si_dump_reg(f, reg + i*4, ib[2+i], ~0);
248 }
249
250 static uint32_t *si_parse_packet3(FILE *f, uint32_t *ib, int *num_dw,
251 int trace_id, enum chip_class chip_class)
252 {
253 unsigned count = PKT_COUNT_G(ib[0]);
254 unsigned op = PKT3_IT_OPCODE_G(ib[0]);
255 const char *predicate = PKT3_PREDICATE(ib[0]) ? "(predicate)" : "";
256 int i;
257
258 /* Print the name first. */
259 for (i = 0; i < ARRAY_SIZE(packet3_table); i++)
260 if (packet3_table[i].op == op)
261 break;
262
263 if (i < ARRAY_SIZE(packet3_table)) {
264 const char *name = sid_strings + packet3_table[i].name_offset;
265
266 if (op == PKT3_SET_CONTEXT_REG ||
267 op == PKT3_SET_CONFIG_REG ||
268 op == PKT3_SET_UCONFIG_REG ||
269 op == PKT3_SET_SH_REG)
270 fprintf(f, COLOR_CYAN "%s%s" COLOR_CYAN ":\n",
271 name, predicate);
272 else
273 fprintf(f, COLOR_GREEN "%s%s" COLOR_RESET ":\n",
274 name, predicate);
275 } else
276 fprintf(f, COLOR_RED "PKT3_UNKNOWN 0x%x%s" COLOR_RESET ":\n",
277 op, predicate);
278
279 /* Print the contents. */
280 switch (op) {
281 case PKT3_SET_CONTEXT_REG:
282 si_parse_set_reg_packet(f, ib, count, SI_CONTEXT_REG_OFFSET);
283 break;
284 case PKT3_SET_CONFIG_REG:
285 si_parse_set_reg_packet(f, ib, count, SI_CONFIG_REG_OFFSET);
286 break;
287 case PKT3_SET_UCONFIG_REG:
288 si_parse_set_reg_packet(f, ib, count, CIK_UCONFIG_REG_OFFSET);
289 break;
290 case PKT3_SET_SH_REG:
291 si_parse_set_reg_packet(f, ib, count, SI_SH_REG_OFFSET);
292 break;
293 case PKT3_ACQUIRE_MEM:
294 si_dump_reg(f, R_0301F0_CP_COHER_CNTL, ib[1], ~0);
295 si_dump_reg(f, R_0301F4_CP_COHER_SIZE, ib[2], ~0);
296 si_dump_reg(f, R_030230_CP_COHER_SIZE_HI, ib[3], ~0);
297 si_dump_reg(f, R_0301F8_CP_COHER_BASE, ib[4], ~0);
298 si_dump_reg(f, R_0301E4_CP_COHER_BASE_HI, ib[5], ~0);
299 print_named_value(f, "POLL_INTERVAL", ib[6], 16);
300 break;
301 case PKT3_SURFACE_SYNC:
302 if (chip_class >= CIK) {
303 si_dump_reg(f, R_0301F0_CP_COHER_CNTL, ib[1], ~0);
304 si_dump_reg(f, R_0301F4_CP_COHER_SIZE, ib[2], ~0);
305 si_dump_reg(f, R_0301F8_CP_COHER_BASE, ib[3], ~0);
306 } else {
307 si_dump_reg(f, R_0085F0_CP_COHER_CNTL, ib[1], ~0);
308 si_dump_reg(f, R_0085F4_CP_COHER_SIZE, ib[2], ~0);
309 si_dump_reg(f, R_0085F8_CP_COHER_BASE, ib[3], ~0);
310 }
311 print_named_value(f, "POLL_INTERVAL", ib[4], 16);
312 break;
313 case PKT3_EVENT_WRITE:
314 si_dump_reg(f, R_028A90_VGT_EVENT_INITIATOR, ib[1],
315 S_028A90_EVENT_TYPE(~0));
316 print_named_value(f, "EVENT_INDEX", (ib[1] >> 8) & 0xf, 4);
317 print_named_value(f, "INV_L2", (ib[1] >> 20) & 0x1, 1);
318 if (count > 0) {
319 print_named_value(f, "ADDRESS_LO", ib[2], 32);
320 print_named_value(f, "ADDRESS_HI", ib[3], 16);
321 }
322 break;
323 case PKT3_DRAW_INDEX_AUTO:
324 si_dump_reg(f, R_030930_VGT_NUM_INDICES, ib[1], ~0);
325 si_dump_reg(f, R_0287F0_VGT_DRAW_INITIATOR, ib[2], ~0);
326 break;
327 case PKT3_DRAW_INDEX_2:
328 si_dump_reg(f, R_028A78_VGT_DMA_MAX_SIZE, ib[1], ~0);
329 si_dump_reg(f, R_0287E8_VGT_DMA_BASE, ib[2], ~0);
330 si_dump_reg(f, R_0287E4_VGT_DMA_BASE_HI, ib[3], ~0);
331 si_dump_reg(f, R_030930_VGT_NUM_INDICES, ib[4], ~0);
332 si_dump_reg(f, R_0287F0_VGT_DRAW_INITIATOR, ib[5], ~0);
333 break;
334 case PKT3_INDEX_TYPE:
335 si_dump_reg(f, R_028A7C_VGT_DMA_INDEX_TYPE, ib[1], ~0);
336 break;
337 case PKT3_NUM_INSTANCES:
338 si_dump_reg(f, R_030934_VGT_NUM_INSTANCES, ib[1], ~0);
339 break;
340 case PKT3_WRITE_DATA:
341 si_dump_reg(f, R_370_CONTROL, ib[1], ~0);
342 si_dump_reg(f, R_371_DST_ADDR_LO, ib[2], ~0);
343 si_dump_reg(f, R_372_DST_ADDR_HI, ib[3], ~0);
344 for (i = 2; i < count; i++) {
345 print_spaces(f, INDENT_PKT);
346 fprintf(f, "0x%08x\n", ib[2+i]);
347 }
348 break;
349 case PKT3_CP_DMA:
350 si_dump_reg(f, R_410_CP_DMA_WORD0, ib[1], ~0);
351 si_dump_reg(f, R_411_CP_DMA_WORD1, ib[2], ~0);
352 si_dump_reg(f, R_412_CP_DMA_WORD2, ib[3], ~0);
353 si_dump_reg(f, R_413_CP_DMA_WORD3, ib[4], ~0);
354 si_dump_reg(f, R_414_COMMAND, ib[5], ~0);
355 break;
356 case PKT3_DMA_DATA:
357 si_dump_reg(f, R_500_DMA_DATA_WORD0, ib[1], ~0);
358 si_dump_reg(f, R_501_SRC_ADDR_LO, ib[2], ~0);
359 si_dump_reg(f, R_502_SRC_ADDR_HI, ib[3], ~0);
360 si_dump_reg(f, R_503_DST_ADDR_LO, ib[4], ~0);
361 si_dump_reg(f, R_504_DST_ADDR_HI, ib[5], ~0);
362 si_dump_reg(f, R_414_COMMAND, ib[6], ~0);
363 break;
364 case PKT3_INDIRECT_BUFFER_SI:
365 case PKT3_INDIRECT_BUFFER_CONST:
366 case PKT3_INDIRECT_BUFFER_CIK:
367 si_dump_reg(f, R_3F0_IB_BASE_LO, ib[1], ~0);
368 si_dump_reg(f, R_3F1_IB_BASE_HI, ib[2], ~0);
369 si_dump_reg(f, R_3F2_CONTROL, ib[3], ~0);
370 break;
371 case PKT3_NOP:
372 if (ib[0] == 0xffff1000) {
373 count = -1; /* One dword NOP. */
374 break;
375 } else if (count == 0 && SI_IS_TRACE_POINT(ib[1])) {
376 unsigned packet_id = SI_GET_TRACE_POINT_ID(ib[1]);
377
378 print_spaces(f, INDENT_PKT);
379 fprintf(f, COLOR_RED "Trace point ID: %u\n", packet_id);
380
381 if (trace_id == -1)
382 break; /* tracing was disabled */
383
384 print_spaces(f, INDENT_PKT);
385 if (packet_id < trace_id)
386 fprintf(f, COLOR_RED
387 "This trace point was reached by the CP."
388 COLOR_RESET "\n");
389 else if (packet_id == trace_id)
390 fprintf(f, COLOR_RED
391 "!!!!! This is the last trace point that "
392 "was reached by the CP !!!!!"
393 COLOR_RESET "\n");
394 else if (packet_id+1 == trace_id)
395 fprintf(f, COLOR_RED
396 "!!!!! This is the first trace point that "
397 "was NOT been reached by the CP !!!!!"
398 COLOR_RESET "\n");
399 else
400 fprintf(f, COLOR_RED
401 "!!!!! This trace point was NOT reached "
402 "by the CP !!!!!"
403 COLOR_RESET "\n");
404 break;
405 }
406 /* fall through, print all dwords */
407 default:
408 for (i = 0; i < count+1; i++) {
409 print_spaces(f, INDENT_PKT);
410 fprintf(f, "0x%08x\n", ib[1+i]);
411 }
412 }
413
414 ib += count + 2;
415 *num_dw -= count + 2;
416 return ib;
417 }
418
419 /**
420 * Parse and print an IB into a file.
421 *
422 * \param f file
423 * \param ib IB
424 * \param num_dw size of the IB
425 * \param chip_class chip class
426 * \param trace_id the last trace ID that is known to have been reached
427 * and executed by the CP, typically read from a buffer
428 */
429 static void si_parse_ib(FILE *f, uint32_t *ib, int num_dw, int trace_id,
430 const char *name, enum chip_class chip_class)
431 {
432 fprintf(f, "------------------ %s begin ------------------\n", name);
433
434 while (num_dw > 0) {
435 unsigned type = PKT_TYPE_G(ib[0]);
436
437 switch (type) {
438 case 3:
439 ib = si_parse_packet3(f, ib, &num_dw, trace_id,
440 chip_class);
441 break;
442 case 2:
443 /* type-2 nop */
444 if (ib[0] == 0x80000000) {
445 fprintf(f, COLOR_GREEN "NOP (type 2)" COLOR_RESET "\n");
446 ib++;
447 break;
448 }
449 /* fall through */
450 default:
451 fprintf(f, "Unknown packet type %i\n", type);
452 return;
453 }
454 }
455
456 fprintf(f, "------------------- %s end -------------------\n", name);
457 if (num_dw < 0) {
458 printf("Packet ends after the end of IB.\n");
459 exit(0);
460 }
461 fprintf(f, "\n");
462 }
463
464 static void si_dump_mmapped_reg(struct si_context *sctx, FILE *f,
465 unsigned offset)
466 {
467 struct radeon_winsys *ws = sctx->b.ws;
468 uint32_t value;
469
470 if (ws->read_registers(ws, offset, 1, &value))
471 si_dump_reg(f, offset, value, ~0);
472 }
473
474 static void si_dump_debug_registers(struct si_context *sctx, FILE *f)
475 {
476 if (sctx->screen->b.info.drm_major == 2 &&
477 sctx->screen->b.info.drm_minor < 42)
478 return; /* no radeon support */
479
480 fprintf(f, "Memory-mapped registers:\n");
481 si_dump_mmapped_reg(sctx, f, R_008010_GRBM_STATUS);
482
483 /* No other registers can be read on DRM < 3.1.0. */
484 if (sctx->screen->b.info.drm_major < 3 ||
485 sctx->screen->b.info.drm_minor < 1) {
486 fprintf(f, "\n");
487 return;
488 }
489
490 si_dump_mmapped_reg(sctx, f, R_008008_GRBM_STATUS2);
491 si_dump_mmapped_reg(sctx, f, R_008014_GRBM_STATUS_SE0);
492 si_dump_mmapped_reg(sctx, f, R_008018_GRBM_STATUS_SE1);
493 si_dump_mmapped_reg(sctx, f, R_008038_GRBM_STATUS_SE2);
494 si_dump_mmapped_reg(sctx, f, R_00803C_GRBM_STATUS_SE3);
495 si_dump_mmapped_reg(sctx, f, R_00D034_SDMA0_STATUS_REG);
496 si_dump_mmapped_reg(sctx, f, R_00D834_SDMA1_STATUS_REG);
497 si_dump_mmapped_reg(sctx, f, R_000E50_SRBM_STATUS);
498 si_dump_mmapped_reg(sctx, f, R_000E4C_SRBM_STATUS2);
499 si_dump_mmapped_reg(sctx, f, R_000E54_SRBM_STATUS3);
500 si_dump_mmapped_reg(sctx, f, R_008680_CP_STAT);
501 si_dump_mmapped_reg(sctx, f, R_008674_CP_STALLED_STAT1);
502 si_dump_mmapped_reg(sctx, f, R_008678_CP_STALLED_STAT2);
503 si_dump_mmapped_reg(sctx, f, R_008670_CP_STALLED_STAT3);
504 si_dump_mmapped_reg(sctx, f, R_008210_CP_CPC_STATUS);
505 si_dump_mmapped_reg(sctx, f, R_008214_CP_CPC_BUSY_STAT);
506 si_dump_mmapped_reg(sctx, f, R_008218_CP_CPC_STALLED_STAT1);
507 si_dump_mmapped_reg(sctx, f, R_00821C_CP_CPF_STATUS);
508 si_dump_mmapped_reg(sctx, f, R_008220_CP_CPF_BUSY_STAT);
509 si_dump_mmapped_reg(sctx, f, R_008224_CP_CPF_STALLED_STAT1);
510 fprintf(f, "\n");
511 }
512
513 static void si_dump_last_ib(struct si_context *sctx, FILE *f)
514 {
515 int last_trace_id = -1;
516
517 if (!sctx->last_gfx.ib)
518 return;
519
520 if (sctx->last_trace_buf) {
521 /* We are expecting that the ddebug pipe has already
522 * waited for the context, so this buffer should be idle.
523 * If the GPU is hung, there is no point in waiting for it.
524 */
525 uint32_t *map = sctx->b.ws->buffer_map(sctx->last_trace_buf->buf,
526 NULL,
527 PIPE_TRANSFER_UNSYNCHRONIZED |
528 PIPE_TRANSFER_READ);
529 if (map)
530 last_trace_id = *map;
531 }
532
533 if (sctx->init_config)
534 si_parse_ib(f, sctx->init_config->pm4, sctx->init_config->ndw,
535 -1, "IB2: Init config", sctx->b.chip_class);
536
537 if (sctx->init_config_gs_rings)
538 si_parse_ib(f, sctx->init_config_gs_rings->pm4,
539 sctx->init_config_gs_rings->ndw,
540 -1, "IB2: Init GS rings", sctx->b.chip_class);
541
542 si_parse_ib(f, sctx->last_gfx.ib, sctx->last_gfx.num_dw,
543 last_trace_id, "IB", sctx->b.chip_class);
544 }
545
546 static const char *priority_to_string(enum radeon_bo_priority priority)
547 {
548 #define ITEM(x) [RADEON_PRIO_##x] = #x
549 static const char *table[64] = {
550 ITEM(FENCE),
551 ITEM(TRACE),
552 ITEM(SO_FILLED_SIZE),
553 ITEM(QUERY),
554 ITEM(IB1),
555 ITEM(IB2),
556 ITEM(DRAW_INDIRECT),
557 ITEM(INDEX_BUFFER),
558 ITEM(VCE),
559 ITEM(UVD),
560 ITEM(SDMA_BUFFER),
561 ITEM(SDMA_TEXTURE),
562 ITEM(CP_DMA),
563 ITEM(CONST_BUFFER),
564 ITEM(DESCRIPTORS),
565 ITEM(BORDER_COLORS),
566 ITEM(SAMPLER_BUFFER),
567 ITEM(VERTEX_BUFFER),
568 ITEM(SHADER_RW_BUFFER),
569 ITEM(COMPUTE_GLOBAL),
570 ITEM(SAMPLER_TEXTURE),
571 ITEM(SHADER_RW_IMAGE),
572 ITEM(SAMPLER_TEXTURE_MSAA),
573 ITEM(COLOR_BUFFER),
574 ITEM(DEPTH_BUFFER),
575 ITEM(COLOR_BUFFER_MSAA),
576 ITEM(DEPTH_BUFFER_MSAA),
577 ITEM(CMASK),
578 ITEM(DCC),
579 ITEM(HTILE),
580 ITEM(SHADER_BINARY),
581 ITEM(SHADER_RINGS),
582 ITEM(SCRATCH_BUFFER),
583 };
584 #undef ITEM
585
586 assert(priority < ARRAY_SIZE(table));
587 return table[priority];
588 }
589
590 static int bo_list_compare_va(const struct radeon_bo_list_item *a,
591 const struct radeon_bo_list_item *b)
592 {
593 return a->vm_address < b->vm_address ? -1 :
594 a->vm_address > b->vm_address ? 1 : 0;
595 }
596
597 static void si_dump_bo_list(struct si_context *sctx,
598 const struct radeon_saved_cs *saved, FILE *f)
599 {
600 unsigned i,j;
601
602 if (!saved->bo_list)
603 return;
604
605 /* Sort the list according to VM adddresses first. */
606 qsort(saved->bo_list, saved->bo_count,
607 sizeof(saved->bo_list[0]), (void*)bo_list_compare_va);
608
609 fprintf(f, "Buffer list (in units of pages = 4kB):\n"
610 COLOR_YELLOW " Size VM start page "
611 "VM end page Usage" COLOR_RESET "\n");
612
613 for (i = 0; i < saved->bo_count; i++) {
614 /* Note: Buffer sizes are expected to be aligned to 4k by the winsys. */
615 const unsigned page_size = sctx->b.screen->info.gart_page_size;
616 uint64_t va = saved->bo_list[i].vm_address;
617 uint64_t size = saved->bo_list[i].bo_size;
618 bool hit = false;
619
620 /* If there's unused virtual memory between 2 buffers, print it. */
621 if (i) {
622 uint64_t previous_va_end = saved->bo_list[i-1].vm_address +
623 saved->bo_list[i-1].bo_size;
624
625 if (va > previous_va_end) {
626 fprintf(f, " %10"PRIu64" -- hole --\n",
627 (va - previous_va_end) / page_size);
628 }
629 }
630
631 /* Print the buffer. */
632 fprintf(f, " %10"PRIu64" 0x%013"PRIx64" 0x%013"PRIx64" ",
633 size / page_size, va / page_size, (va + size) / page_size);
634
635 /* Print the usage. */
636 for (j = 0; j < 64; j++) {
637 if (!(saved->bo_list[i].priority_usage & (1llu << j)))
638 continue;
639
640 fprintf(f, "%s%s", !hit ? "" : ", ", priority_to_string(j));
641 hit = true;
642 }
643 fprintf(f, "\n");
644 }
645 fprintf(f, "\nNote: The holes represent memory not used by the IB.\n"
646 " Other buffers can still be allocated there.\n\n");
647 }
648
649 static void si_dump_framebuffer(struct si_context *sctx, FILE *f)
650 {
651 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
652 struct r600_texture *rtex;
653 int i;
654
655 for (i = 0; i < state->nr_cbufs; i++) {
656 if (!state->cbufs[i])
657 continue;
658
659 rtex = (struct r600_texture*)state->cbufs[i]->texture;
660 fprintf(f, COLOR_YELLOW "Color buffer %i:" COLOR_RESET "\n", i);
661 r600_print_texture_info(rtex, f);
662 fprintf(f, "\n");
663 }
664
665 if (state->zsbuf) {
666 rtex = (struct r600_texture*)state->zsbuf->texture;
667 fprintf(f, COLOR_YELLOW "Depth-stencil buffer:" COLOR_RESET "\n");
668 r600_print_texture_info(rtex, f);
669 fprintf(f, "\n");
670 }
671 }
672
673 static void si_dump_debug_state(struct pipe_context *ctx, FILE *f,
674 unsigned flags)
675 {
676 struct si_context *sctx = (struct si_context*)ctx;
677
678 if (flags & PIPE_DUMP_DEVICE_STATUS_REGISTERS)
679 si_dump_debug_registers(sctx, f);
680
681 if (flags & PIPE_DUMP_CURRENT_STATES)
682 si_dump_framebuffer(sctx, f);
683
684 if (flags & PIPE_DUMP_CURRENT_SHADERS) {
685 si_dump_shader(sctx->screen, &sctx->vs_shader, f);
686 si_dump_shader(sctx->screen, &sctx->tcs_shader, f);
687 si_dump_shader(sctx->screen, &sctx->tes_shader, f);
688 si_dump_shader(sctx->screen, &sctx->gs_shader, f);
689 si_dump_shader(sctx->screen, &sctx->ps_shader, f);
690 }
691
692 if (flags & PIPE_DUMP_LAST_COMMAND_BUFFER) {
693 si_dump_bo_list(sctx, &sctx->last_gfx, f);
694 si_dump_last_ib(sctx, f);
695
696 fprintf(f, "Done.\n");
697
698 /* dump only once */
699 radeon_clear_saved_cs(&sctx->last_gfx);
700 r600_resource_reference(&sctx->last_trace_buf, NULL);
701 }
702 }
703
704 static void si_dump_dma(struct si_context *sctx,
705 struct radeon_saved_cs *saved, FILE *f)
706 {
707 static const char ib_name[] = "sDMA IB";
708 unsigned i;
709
710 si_dump_bo_list(sctx, saved, f);
711
712 fprintf(f, "------------------ %s begin ------------------\n", ib_name);
713
714 for (i = 0; i < saved->num_dw; ++i) {
715 fprintf(f, " %08x\n", saved->ib[i]);
716 }
717
718 fprintf(f, "------------------- %s end -------------------\n", ib_name);
719 fprintf(f, "\n");
720
721 fprintf(f, "SDMA Dump Done.\n");
722 }
723
724 static bool si_vm_fault_occured(struct si_context *sctx, uint32_t *out_addr)
725 {
726 char line[2000];
727 unsigned sec, usec;
728 int progress = 0;
729 uint64_t timestamp = 0;
730 bool fault = false;
731
732 FILE *p = popen("dmesg", "r");
733 if (!p)
734 return false;
735
736 while (fgets(line, sizeof(line), p)) {
737 char *msg, len;
738
739 if (!line[0] || line[0] == '\n')
740 continue;
741
742 /* Get the timestamp. */
743 if (sscanf(line, "[%u.%u]", &sec, &usec) != 2) {
744 static bool hit = false;
745 if (!hit) {
746 fprintf(stderr, "%s: failed to parse line '%s'\n",
747 __func__, line);
748 hit = true;
749 }
750 continue;
751 }
752 timestamp = sec * 1000000llu + usec;
753
754 /* If just updating the timestamp. */
755 if (!out_addr)
756 continue;
757
758 /* Process messages only if the timestamp is newer. */
759 if (timestamp <= sctx->dmesg_timestamp)
760 continue;
761
762 /* Only process the first VM fault. */
763 if (fault)
764 continue;
765
766 /* Remove trailing \n */
767 len = strlen(line);
768 if (len && line[len-1] == '\n')
769 line[len-1] = 0;
770
771 /* Get the message part. */
772 msg = strchr(line, ']');
773 if (!msg) {
774 assert(0);
775 continue;
776 }
777 msg++;
778
779 switch (progress) {
780 case 0:
781 if (strstr(msg, "GPU fault detected:"))
782 progress = 1;
783 break;
784 case 1:
785 msg = strstr(msg, "VM_CONTEXT1_PROTECTION_FAULT_ADDR");
786 if (msg) {
787 msg = strstr(msg, "0x");
788 if (msg) {
789 msg += 2;
790 if (sscanf(msg, "%X", out_addr) == 1)
791 fault = true;
792 }
793 }
794 progress = 0;
795 break;
796 default:
797 progress = 0;
798 }
799 }
800 pclose(p);
801
802 if (timestamp > sctx->dmesg_timestamp)
803 sctx->dmesg_timestamp = timestamp;
804 return fault;
805 }
806
807 void si_check_vm_faults(struct r600_common_context *ctx,
808 struct radeon_saved_cs *saved, enum ring_type ring)
809 {
810 struct si_context *sctx = (struct si_context *)ctx;
811 struct pipe_screen *screen = sctx->b.b.screen;
812 FILE *f;
813 uint32_t addr;
814 char cmd_line[4096];
815
816 if (!si_vm_fault_occured(sctx, &addr))
817 return;
818
819 f = dd_get_debug_file(false);
820 if (!f)
821 return;
822
823 fprintf(f, "VM fault report.\n\n");
824 if (os_get_command_line(cmd_line, sizeof(cmd_line)))
825 fprintf(f, "Command: %s\n", cmd_line);
826 fprintf(f, "Driver vendor: %s\n", screen->get_vendor(screen));
827 fprintf(f, "Device vendor: %s\n", screen->get_device_vendor(screen));
828 fprintf(f, "Device name: %s\n\n", screen->get_name(screen));
829 fprintf(f, "Failing VM page: 0x%08x\n\n", addr);
830
831 if (sctx->apitrace_call_number)
832 fprintf(f, "Last apitrace call: %u\n\n",
833 sctx->apitrace_call_number);
834
835 switch (ring) {
836 case RING_GFX:
837 si_dump_debug_state(&sctx->b.b, f,
838 PIPE_DUMP_CURRENT_STATES |
839 PIPE_DUMP_CURRENT_SHADERS |
840 PIPE_DUMP_LAST_COMMAND_BUFFER);
841 break;
842
843 case RING_DMA:
844 si_dump_dma(sctx, saved, f);
845 break;
846
847 default:
848 break;
849 }
850
851 fclose(f);
852
853 fprintf(stderr, "Detected a VM fault, exiting...\n");
854 exit(0);
855 }
856
857 void si_init_debug_functions(struct si_context *sctx)
858 {
859 sctx->b.b.dump_debug_state = si_dump_debug_state;
860 sctx->b.check_vm_faults = si_check_vm_faults;
861
862 /* Set the initial dmesg timestamp for this context, so that
863 * only new messages will be checked for VM faults.
864 */
865 if (sctx->screen->b.debug_flags & DBG_CHECK_VM)
866 si_vm_fault_occured(sctx, NULL);
867 }