radeonsi: precompute si_*_descriptors_idx in si_shader_selector
[mesa.git] / src / gallium / drivers / radeonsi / si_descriptors.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 /* Resource binding slots and sampler states (each described with 8 or
26 * 4 dwords) are stored in lists in memory which is accessed by shaders
27 * using scalar load instructions.
28 *
29 * This file is responsible for managing such lists. It keeps a copy of all
30 * descriptors in CPU memory and re-uploads a whole list if some slots have
31 * been changed.
32 *
33 * This code is also reponsible for updating shader pointers to those lists.
34 *
35 * Note that CP DMA can't be used for updating the lists, because a GPU hang
36 * could leave the list in a mid-IB state and the next IB would get wrong
37 * descriptors and the whole context would be unusable at that point.
38 * (Note: The register shadowing can't be used due to the same reason)
39 *
40 * Also, uploading descriptors to newly allocated memory doesn't require
41 * a KCACHE flush.
42 *
43 *
44 * Possible scenarios for one 16 dword image+sampler slot:
45 *
46 * | Image | w/ FMASK | Buffer | NULL
47 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
48 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
49 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
50 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
51 *
52 * FMASK implies MSAA, therefore no sampler state.
53 * Sampler states are never unbound except when FMASK is bound.
54 */
55
56 #include "si_pipe.h"
57 #include "si_compute.h"
58 #include "si_build_pm4.h"
59 #include "sid.h"
60 #include "util/format/u_format.h"
61 #include "util/hash_table.h"
62 #include "util/u_idalloc.h"
63 #include "util/u_memory.h"
64 #include "util/u_upload_mgr.h"
65
66 /* NULL image and buffer descriptor for textures (alpha = 1) and images
67 * (alpha = 0).
68 *
69 * For images, all fields must be zero except for the swizzle, which
70 * supports arbitrary combinations of 0s and 1s. The texture type must be
71 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
72 *
73 * For buffers, all fields must be zero. If they are not, the hw hangs.
74 *
75 * This is the only reason why the buffer descriptor must be in words [4:7].
76 */
77 static uint32_t null_texture_descriptor[8] = {
78 0, 0, 0, S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1) | S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D)
79 /* the rest must contain zeros, which is also used by the buffer
80 * descriptor */
81 };
82
83 static uint32_t null_image_descriptor[8] = {
84 0, 0, 0, S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D)
85 /* the rest must contain zeros, which is also used by the buffer
86 * descriptor */
87 };
88
89 static uint64_t si_desc_extract_buffer_address(const uint32_t *desc)
90 {
91 uint64_t va = desc[0] | ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc[1]) << 32);
92
93 /* Sign-extend the 48-bit address. */
94 va <<= 16;
95 va = (int64_t)va >> 16;
96 return va;
97 }
98
99 static void si_init_descriptor_list(uint32_t *desc_list, unsigned element_dw_size,
100 unsigned num_elements, const uint32_t *null_descriptor)
101 {
102 int i;
103
104 /* Initialize the array to NULL descriptors if the element size is 8. */
105 if (null_descriptor) {
106 assert(element_dw_size % 8 == 0);
107 for (i = 0; i < num_elements * element_dw_size / 8; i++)
108 memcpy(desc_list + i * 8, null_descriptor, 8 * 4);
109 }
110 }
111
112 static void si_init_descriptors(struct si_descriptors *desc, short shader_userdata_rel_index,
113 unsigned element_dw_size, unsigned num_elements)
114 {
115 desc->list = CALLOC(num_elements, element_dw_size * 4);
116 desc->element_dw_size = element_dw_size;
117 desc->num_elements = num_elements;
118 desc->shader_userdata_offset = shader_userdata_rel_index * 4;
119 desc->slot_index_to_bind_directly = -1;
120 }
121
122 static void si_release_descriptors(struct si_descriptors *desc)
123 {
124 si_resource_reference(&desc->buffer, NULL);
125 FREE(desc->list);
126 }
127
128 static bool si_upload_descriptors(struct si_context *sctx, struct si_descriptors *desc)
129 {
130 unsigned slot_size = desc->element_dw_size * 4;
131 unsigned first_slot_offset = desc->first_active_slot * slot_size;
132 unsigned upload_size = desc->num_active_slots * slot_size;
133
134 /* Skip the upload if no shader is using the descriptors. dirty_mask
135 * will stay dirty and the descriptors will be uploaded when there is
136 * a shader using them.
137 */
138 if (!upload_size)
139 return true;
140
141 /* If there is just one active descriptor, bind it directly. */
142 if ((int)desc->first_active_slot == desc->slot_index_to_bind_directly &&
143 desc->num_active_slots == 1) {
144 uint32_t *descriptor = &desc->list[desc->slot_index_to_bind_directly * desc->element_dw_size];
145
146 /* The buffer is already in the buffer list. */
147 si_resource_reference(&desc->buffer, NULL);
148 desc->gpu_list = NULL;
149 desc->gpu_address = si_desc_extract_buffer_address(descriptor);
150 si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
151 return true;
152 }
153
154 uint32_t *ptr;
155 unsigned buffer_offset;
156 u_upload_alloc(sctx->b.const_uploader, first_slot_offset, upload_size,
157 si_optimal_tcc_alignment(sctx, upload_size), &buffer_offset,
158 (struct pipe_resource **)&desc->buffer, (void **)&ptr);
159 if (!desc->buffer) {
160 desc->gpu_address = 0;
161 return false; /* skip the draw call */
162 }
163
164 util_memcpy_cpu_to_le32(ptr, (char *)desc->list + first_slot_offset, upload_size);
165 desc->gpu_list = ptr - first_slot_offset / 4;
166
167 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, desc->buffer, RADEON_USAGE_READ,
168 RADEON_PRIO_DESCRIPTORS);
169
170 /* The shader pointer should point to slot 0. */
171 buffer_offset -= first_slot_offset;
172 desc->gpu_address = desc->buffer->gpu_address + buffer_offset;
173
174 assert(desc->buffer->flags & RADEON_FLAG_32BIT);
175 assert((desc->buffer->gpu_address >> 32) == sctx->screen->info.address32_hi);
176 assert((desc->gpu_address >> 32) == sctx->screen->info.address32_hi);
177
178 si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
179 return true;
180 }
181
182 static void
183 si_add_descriptors_to_bo_list(struct si_context *sctx, struct si_descriptors *desc)
184 {
185 if (!desc->buffer)
186 return;
187
188 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, desc->buffer, RADEON_USAGE_READ,
189 RADEON_PRIO_DESCRIPTORS);
190 }
191
192 /* SAMPLER VIEWS */
193
194 static inline enum radeon_bo_priority si_get_sampler_view_priority(struct si_resource *res)
195 {
196 if (res->b.b.target == PIPE_BUFFER)
197 return RADEON_PRIO_SAMPLER_BUFFER;
198
199 if (res->b.b.nr_samples > 1)
200 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
201
202 return RADEON_PRIO_SAMPLER_TEXTURE;
203 }
204
205 static struct si_descriptors *si_sampler_and_image_descriptors(struct si_context *sctx,
206 unsigned shader)
207 {
208 return &sctx->descriptors[si_sampler_and_image_descriptors_idx(shader)];
209 }
210
211 static void si_release_sampler_views(struct si_samplers *samplers)
212 {
213 int i;
214
215 for (i = 0; i < ARRAY_SIZE(samplers->views); i++) {
216 pipe_sampler_view_reference(&samplers->views[i], NULL);
217 }
218 }
219
220 static void si_sampler_view_add_buffer(struct si_context *sctx, struct pipe_resource *resource,
221 enum radeon_bo_usage usage, bool is_stencil_sampler,
222 bool check_mem)
223 {
224 struct si_texture *tex = (struct si_texture *)resource;
225 enum radeon_bo_priority priority;
226
227 if (!resource)
228 return;
229
230 /* Use the flushed depth texture if direct sampling is unsupported. */
231 if (resource->target != PIPE_BUFFER && tex->is_depth &&
232 !si_can_sample_zs(tex, is_stencil_sampler))
233 tex = tex->flushed_depth_texture;
234
235 priority = si_get_sampler_view_priority(&tex->buffer);
236 radeon_add_to_gfx_buffer_list_check_mem(sctx, &tex->buffer, usage, priority, check_mem);
237
238 if (resource->target == PIPE_BUFFER)
239 return;
240
241 /* Add separate DCC. */
242 if (tex->dcc_separate_buffer) {
243 radeon_add_to_gfx_buffer_list_check_mem(sctx, tex->dcc_separate_buffer, usage,
244 RADEON_PRIO_SEPARATE_META, check_mem);
245 }
246 }
247
248 static void si_sampler_views_begin_new_cs(struct si_context *sctx, struct si_samplers *samplers)
249 {
250 unsigned mask = samplers->enabled_mask;
251
252 /* Add buffers to the CS. */
253 while (mask) {
254 int i = u_bit_scan(&mask);
255 struct si_sampler_view *sview = (struct si_sampler_view *)samplers->views[i];
256
257 si_sampler_view_add_buffer(sctx, sview->base.texture, RADEON_USAGE_READ,
258 sview->is_stencil_sampler, false);
259 }
260 }
261
262 static bool si_sampler_views_check_encrypted(struct si_context *sctx, struct si_samplers *samplers,
263 unsigned samplers_declared)
264 {
265 unsigned mask = samplers->enabled_mask & samplers_declared;
266
267 /* Verify if a samplers uses an encrypted resource */
268 while (mask) {
269 int i = u_bit_scan(&mask);
270 struct si_sampler_view *sview = (struct si_sampler_view *)samplers->views[i];
271
272 struct si_resource *res = si_resource(sview->base.texture);
273 if (res->flags & RADEON_FLAG_ENCRYPTED)
274 return true;
275 }
276 return false;
277 }
278
279 /* Set buffer descriptor fields that can be changed by reallocations. */
280 static void si_set_buf_desc_address(struct si_resource *buf, uint64_t offset, uint32_t *state)
281 {
282 uint64_t va = buf->gpu_address + offset;
283
284 state[0] = va;
285 state[1] &= C_008F04_BASE_ADDRESS_HI;
286 state[1] |= S_008F04_BASE_ADDRESS_HI(va >> 32);
287 }
288
289 /* Set texture descriptor fields that can be changed by reallocations.
290 *
291 * \param tex texture
292 * \param base_level_info information of the level of BASE_ADDRESS
293 * \param base_level the level of BASE_ADDRESS
294 * \param first_level pipe_sampler_view.u.tex.first_level
295 * \param block_width util_format_get_blockwidth()
296 * \param is_stencil select between separate Z & Stencil
297 * \param state descriptor to update
298 */
299 void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture *tex,
300 const struct legacy_surf_level *base_level_info,
301 unsigned base_level, unsigned first_level, unsigned block_width,
302 bool is_stencil, bool force_dcc_off, uint32_t *state)
303 {
304 uint64_t va, meta_va = 0;
305
306 if (tex->is_depth && !si_can_sample_zs(tex, is_stencil)) {
307 tex = tex->flushed_depth_texture;
308 is_stencil = false;
309 }
310
311 va = tex->buffer.gpu_address;
312
313 if (sscreen->info.chip_class >= GFX9) {
314 /* Only stencil_offset needs to be added here. */
315 if (is_stencil)
316 va += tex->surface.u.gfx9.stencil_offset;
317 else
318 va += tex->surface.u.gfx9.surf_offset;
319 } else {
320 va += base_level_info->offset;
321 }
322
323 state[0] = va >> 8;
324 state[1] &= C_008F14_BASE_ADDRESS_HI;
325 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
326
327 /* Only macrotiled modes can set tile swizzle.
328 * GFX9 doesn't use (legacy) base_level_info.
329 */
330 if (sscreen->info.chip_class >= GFX9 || base_level_info->mode == RADEON_SURF_MODE_2D)
331 state[0] |= tex->surface.tile_swizzle;
332
333 if (sscreen->info.chip_class >= GFX8) {
334 state[6] &= C_008F28_COMPRESSION_EN;
335
336 if (!force_dcc_off && vi_dcc_enabled(tex, first_level)) {
337 meta_va =
338 (!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) + tex->surface.dcc_offset;
339
340 if (sscreen->info.chip_class == GFX8) {
341 meta_va += base_level_info->dcc_offset;
342 assert(base_level_info->mode == RADEON_SURF_MODE_2D);
343 }
344
345 unsigned dcc_tile_swizzle = tex->surface.tile_swizzle << 8;
346 dcc_tile_swizzle &= tex->surface.dcc_alignment - 1;
347 meta_va |= dcc_tile_swizzle;
348 } else if (vi_tc_compat_htile_enabled(tex, first_level,
349 is_stencil ? PIPE_MASK_S : PIPE_MASK_Z)) {
350 meta_va = tex->buffer.gpu_address + tex->surface.htile_offset;
351 }
352
353 if (meta_va)
354 state[6] |= S_008F28_COMPRESSION_EN(1);
355 }
356
357 if (sscreen->info.chip_class >= GFX8 && sscreen->info.chip_class <= GFX9)
358 state[7] = meta_va >> 8;
359
360 if (sscreen->info.chip_class >= GFX10) {
361 state[3] &= C_00A00C_SW_MODE;
362
363 if (is_stencil) {
364 state[3] |= S_00A00C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
365 } else {
366 state[3] |= S_00A00C_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode);
367 }
368
369 state[6] &= C_00A018_META_DATA_ADDRESS_LO & C_00A018_META_PIPE_ALIGNED;
370
371 if (meta_va) {
372 struct gfx9_surf_meta_flags meta = {
373 .rb_aligned = 1,
374 .pipe_aligned = 1,
375 };
376
377 if (tex->surface.dcc_offset)
378 meta = tex->surface.u.gfx9.dcc;
379
380 state[6] |= S_00A018_META_PIPE_ALIGNED(meta.pipe_aligned) |
381 S_00A018_META_DATA_ADDRESS_LO(meta_va >> 8);
382 }
383
384 state[7] = meta_va >> 16;
385 } else if (sscreen->info.chip_class == GFX9) {
386 state[3] &= C_008F1C_SW_MODE;
387 state[4] &= C_008F20_PITCH;
388
389 if (is_stencil) {
390 state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
391 state[4] |= S_008F20_PITCH(tex->surface.u.gfx9.stencil.epitch);
392 } else {
393 uint16_t epitch = tex->surface.u.gfx9.surf.epitch;
394 if (tex->buffer.b.b.format == PIPE_FORMAT_R8G8_R8B8_UNORM &&
395 block_width == 1) {
396 /* epitch is patched in ac_surface for sdma/vcn blocks to get
397 * a value expressed in elements unit.
398 * But here the texture is used with block_width == 1 so we
399 * need epitch in pixel units.
400 */
401 epitch = (epitch + 1) / tex->surface.blk_w - 1;
402 }
403 state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode);
404 state[4] |= S_008F20_PITCH(epitch);
405 }
406
407 state[5] &=
408 C_008F24_META_DATA_ADDRESS & C_008F24_META_PIPE_ALIGNED & C_008F24_META_RB_ALIGNED;
409 if (meta_va) {
410 struct gfx9_surf_meta_flags meta = {
411 .rb_aligned = 1,
412 .pipe_aligned = 1,
413 };
414
415 if (tex->surface.dcc_offset)
416 meta = tex->surface.u.gfx9.dcc;
417
418 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
419 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
420 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
421 }
422 } else {
423 /* GFX6-GFX8 */
424 unsigned pitch = base_level_info->nblk_x * block_width;
425 unsigned index = si_tile_mode_index(tex, base_level, is_stencil);
426
427 state[3] &= C_008F1C_TILING_INDEX;
428 state[3] |= S_008F1C_TILING_INDEX(index);
429 state[4] &= C_008F20_PITCH;
430 state[4] |= S_008F20_PITCH(pitch - 1);
431 }
432 }
433
434 static void si_set_sampler_state_desc(struct si_sampler_state *sstate,
435 struct si_sampler_view *sview, struct si_texture *tex,
436 uint32_t *desc)
437 {
438 if (sview && sview->is_integer)
439 memcpy(desc, sstate->integer_val, 4 * 4);
440 else if (tex && tex->upgraded_depth && (!sview || !sview->is_stencil_sampler))
441 memcpy(desc, sstate->upgraded_depth_val, 4 * 4);
442 else
443 memcpy(desc, sstate->val, 4 * 4);
444 }
445
446 static void si_set_sampler_view_desc(struct si_context *sctx, struct si_sampler_view *sview,
447 struct si_sampler_state *sstate, uint32_t *desc)
448 {
449 struct pipe_sampler_view *view = &sview->base;
450 struct si_texture *tex = (struct si_texture *)view->texture;
451 bool is_buffer = tex->buffer.b.b.target == PIPE_BUFFER;
452
453 if (unlikely(!is_buffer && sview->dcc_incompatible)) {
454 if (vi_dcc_enabled(tex, view->u.tex.first_level))
455 if (!si_texture_disable_dcc(sctx, tex))
456 si_decompress_dcc(sctx, tex);
457
458 sview->dcc_incompatible = false;
459 }
460
461 assert(tex); /* views with texture == NULL aren't supported */
462 memcpy(desc, sview->state, 8 * 4);
463
464 if (is_buffer) {
465 si_set_buf_desc_address(&tex->buffer, sview->base.u.buf.offset, desc + 4);
466 } else {
467 bool is_separate_stencil = tex->db_compatible && sview->is_stencil_sampler;
468
469 si_set_mutable_tex_desc_fields(sctx->screen, tex, sview->base_level_info, sview->base_level,
470 sview->base.u.tex.first_level, sview->block_width,
471 is_separate_stencil, false, desc);
472 }
473
474 if (!is_buffer && tex->surface.fmask_size) {
475 memcpy(desc + 8, sview->fmask_state, 8 * 4);
476 } else {
477 /* Disable FMASK and bind sampler state in [12:15]. */
478 memcpy(desc + 8, null_texture_descriptor, 4 * 4);
479
480 if (sstate)
481 si_set_sampler_state_desc(sstate, sview, is_buffer ? NULL : tex, desc + 12);
482 }
483 }
484
485 static bool color_needs_decompression(struct si_texture *tex)
486 {
487 return tex->surface.fmask_size ||
488 (tex->dirty_level_mask && (tex->cmask_buffer || tex->surface.dcc_offset));
489 }
490
491 static bool depth_needs_decompression(struct si_texture *tex)
492 {
493 /* If the depth/stencil texture is TC-compatible, no decompression
494 * will be done. The decompression function will only flush DB caches
495 * to make it coherent with shaders. That's necessary because the driver
496 * doesn't flush DB caches in any other case.
497 */
498 return tex->db_compatible;
499 }
500
501 static void si_set_sampler_view(struct si_context *sctx, unsigned shader, unsigned slot,
502 struct pipe_sampler_view *view, bool disallow_early_out)
503 {
504 struct si_samplers *samplers = &sctx->samplers[shader];
505 struct si_sampler_view *sview = (struct si_sampler_view *)view;
506 struct si_descriptors *descs = si_sampler_and_image_descriptors(sctx, shader);
507 unsigned desc_slot = si_get_sampler_slot(slot);
508 uint32_t *desc = descs->list + desc_slot * 16;
509
510 if (samplers->views[slot] == view && !disallow_early_out)
511 return;
512
513 if (view) {
514 struct si_texture *tex = (struct si_texture *)view->texture;
515
516 si_set_sampler_view_desc(sctx, sview, samplers->sampler_states[slot], desc);
517
518 if (tex->buffer.b.b.target == PIPE_BUFFER) {
519 tex->buffer.bind_history |= PIPE_BIND_SAMPLER_VIEW;
520 samplers->needs_depth_decompress_mask &= ~(1u << slot);
521 samplers->needs_color_decompress_mask &= ~(1u << slot);
522 } else {
523 if (depth_needs_decompression(tex)) {
524 samplers->needs_depth_decompress_mask |= 1u << slot;
525 } else {
526 samplers->needs_depth_decompress_mask &= ~(1u << slot);
527 }
528 if (color_needs_decompression(tex)) {
529 samplers->needs_color_decompress_mask |= 1u << slot;
530 } else {
531 samplers->needs_color_decompress_mask &= ~(1u << slot);
532 }
533
534 if (vi_dcc_enabled(tex, view->u.tex.first_level) &&
535 p_atomic_read(&tex->framebuffers_bound))
536 sctx->need_check_render_feedback = true;
537 }
538
539 pipe_sampler_view_reference(&samplers->views[slot], view);
540 samplers->enabled_mask |= 1u << slot;
541
542 /* Since this can flush, it must be done after enabled_mask is
543 * updated. */
544 si_sampler_view_add_buffer(sctx, view->texture, RADEON_USAGE_READ, sview->is_stencil_sampler,
545 true);
546 } else {
547 pipe_sampler_view_reference(&samplers->views[slot], NULL);
548 memcpy(desc, null_texture_descriptor, 8 * 4);
549 /* Only clear the lower dwords of FMASK. */
550 memcpy(desc + 8, null_texture_descriptor, 4 * 4);
551 /* Re-set the sampler state if we are transitioning from FMASK. */
552 if (samplers->sampler_states[slot])
553 si_set_sampler_state_desc(samplers->sampler_states[slot], NULL, NULL, desc + 12);
554
555 samplers->enabled_mask &= ~(1u << slot);
556 samplers->needs_depth_decompress_mask &= ~(1u << slot);
557 samplers->needs_color_decompress_mask &= ~(1u << slot);
558 }
559
560 sctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
561 }
562
563 static void si_update_shader_needs_decompress_mask(struct si_context *sctx, unsigned shader)
564 {
565 struct si_samplers *samplers = &sctx->samplers[shader];
566 unsigned shader_bit = 1 << shader;
567
568 if (samplers->needs_depth_decompress_mask || samplers->needs_color_decompress_mask ||
569 sctx->images[shader].needs_color_decompress_mask)
570 sctx->shader_needs_decompress_mask |= shader_bit;
571 else
572 sctx->shader_needs_decompress_mask &= ~shader_bit;
573 }
574
575 static void si_set_sampler_views(struct pipe_context *ctx, enum pipe_shader_type shader,
576 unsigned start, unsigned count, struct pipe_sampler_view **views)
577 {
578 struct si_context *sctx = (struct si_context *)ctx;
579 int i;
580
581 if (!count || shader >= SI_NUM_SHADERS)
582 return;
583
584 if (views) {
585 for (i = 0; i < count; i++)
586 si_set_sampler_view(sctx, shader, start + i, views[i], false);
587 } else {
588 for (i = 0; i < count; i++)
589 si_set_sampler_view(sctx, shader, start + i, NULL, false);
590 }
591
592 si_update_shader_needs_decompress_mask(sctx, shader);
593 }
594
595 static void si_samplers_update_needs_color_decompress_mask(struct si_samplers *samplers)
596 {
597 unsigned mask = samplers->enabled_mask;
598
599 while (mask) {
600 int i = u_bit_scan(&mask);
601 struct pipe_resource *res = samplers->views[i]->texture;
602
603 if (res && res->target != PIPE_BUFFER) {
604 struct si_texture *tex = (struct si_texture *)res;
605
606 if (color_needs_decompression(tex)) {
607 samplers->needs_color_decompress_mask |= 1u << i;
608 } else {
609 samplers->needs_color_decompress_mask &= ~(1u << i);
610 }
611 }
612 }
613 }
614
615 /* IMAGE VIEWS */
616
617 static void si_release_image_views(struct si_images *images)
618 {
619 unsigned i;
620
621 for (i = 0; i < SI_NUM_IMAGES; ++i) {
622 struct pipe_image_view *view = &images->views[i];
623
624 pipe_resource_reference(&view->resource, NULL);
625 }
626 }
627
628 static void si_image_views_begin_new_cs(struct si_context *sctx, struct si_images *images)
629 {
630 uint mask = images->enabled_mask;
631
632 /* Add buffers to the CS. */
633 while (mask) {
634 int i = u_bit_scan(&mask);
635 struct pipe_image_view *view = &images->views[i];
636
637 assert(view->resource);
638
639 si_sampler_view_add_buffer(sctx, view->resource, RADEON_USAGE_READWRITE, false, false);
640 }
641 }
642
643 static bool si_image_views_check_encrypted(struct si_context *sctx, struct si_images *images,
644 unsigned images_declared)
645 {
646 uint mask = images->enabled_mask & images_declared;
647
648 while (mask) {
649 int i = u_bit_scan(&mask);
650 struct pipe_image_view *view = &images->views[i];
651
652 assert(view->resource);
653
654 struct si_texture *tex = (struct si_texture *)view->resource;
655 if (tex->buffer.flags & RADEON_FLAG_ENCRYPTED)
656 return true;
657 }
658 return false;
659 }
660
661 static void si_disable_shader_image(struct si_context *ctx, unsigned shader, unsigned slot)
662 {
663 struct si_images *images = &ctx->images[shader];
664
665 if (images->enabled_mask & (1u << slot)) {
666 struct si_descriptors *descs = si_sampler_and_image_descriptors(ctx, shader);
667 unsigned desc_slot = si_get_image_slot(slot);
668
669 pipe_resource_reference(&images->views[slot].resource, NULL);
670 images->needs_color_decompress_mask &= ~(1 << slot);
671
672 memcpy(descs->list + desc_slot * 8, null_image_descriptor, 8 * 4);
673 images->enabled_mask &= ~(1u << slot);
674 ctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
675 }
676 }
677
678 static void si_mark_image_range_valid(const struct pipe_image_view *view)
679 {
680 struct si_resource *res = si_resource(view->resource);
681
682 if (res->b.b.target != PIPE_BUFFER)
683 return;
684
685 util_range_add(&res->b.b, &res->valid_buffer_range, view->u.buf.offset,
686 view->u.buf.offset + view->u.buf.size);
687 }
688
689 static void si_set_shader_image_desc(struct si_context *ctx, const struct pipe_image_view *view,
690 bool skip_decompress, uint32_t *desc, uint32_t *fmask_desc)
691 {
692 struct si_screen *screen = ctx->screen;
693 struct si_resource *res;
694
695 res = si_resource(view->resource);
696
697 if (res->b.b.target == PIPE_BUFFER || view->shader_access & SI_IMAGE_ACCESS_AS_BUFFER) {
698 if (view->access & PIPE_IMAGE_ACCESS_WRITE)
699 si_mark_image_range_valid(view);
700
701 si_make_buffer_descriptor(screen, res, view->format, view->u.buf.offset, view->u.buf.size,
702 desc);
703 si_set_buf_desc_address(res, view->u.buf.offset, desc + 4);
704 } else {
705 static const unsigned char swizzle[4] = {0, 1, 2, 3};
706 struct si_texture *tex = (struct si_texture *)res;
707 unsigned level = view->u.tex.level;
708 unsigned width, height, depth, hw_level;
709 bool uses_dcc = vi_dcc_enabled(tex, level);
710 unsigned access = view->access;
711
712 assert(!tex->is_depth);
713 assert(fmask_desc || tex->surface.fmask_offset == 0);
714
715 if (uses_dcc && !skip_decompress &&
716 !(access & SI_IMAGE_ACCESS_DCC_OFF) &&
717 (access & PIPE_IMAGE_ACCESS_WRITE ||
718 !vi_dcc_formats_compatible(screen, res->b.b.format, view->format))) {
719 /* If DCC can't be disabled, at least decompress it.
720 * The decompression is relatively cheap if the surface
721 * has been decompressed already.
722 */
723 if (!si_texture_disable_dcc(ctx, tex))
724 si_decompress_dcc(ctx, tex);
725 }
726
727 if (ctx->chip_class >= GFX9) {
728 /* Always set the base address. The swizzle modes don't
729 * allow setting mipmap level offsets as the base.
730 */
731 width = res->b.b.width0;
732 height = res->b.b.height0;
733 depth = res->b.b.depth0;
734 hw_level = level;
735 } else {
736 /* Always force the base level to the selected level.
737 *
738 * This is required for 3D textures, where otherwise
739 * selecting a single slice for non-layered bindings
740 * fails. It doesn't hurt the other targets.
741 */
742 width = u_minify(res->b.b.width0, level);
743 height = u_minify(res->b.b.height0, level);
744 depth = u_minify(res->b.b.depth0, level);
745 hw_level = 0;
746 }
747
748 screen->make_texture_descriptor(
749 screen, tex, false, res->b.b.target, view->format, swizzle, hw_level, hw_level,
750 view->u.tex.first_layer, view->u.tex.last_layer, width, height, depth, desc, fmask_desc);
751 si_set_mutable_tex_desc_fields(screen, tex, &tex->surface.u.legacy.level[level], level, level,
752 util_format_get_blockwidth(view->format), false,
753 view->access & SI_IMAGE_ACCESS_DCC_OFF, desc);
754 }
755 }
756
757 static void si_set_shader_image(struct si_context *ctx, unsigned shader, unsigned slot,
758 const struct pipe_image_view *view, bool skip_decompress)
759 {
760 struct si_images *images = &ctx->images[shader];
761 struct si_descriptors *descs = si_sampler_and_image_descriptors(ctx, shader);
762 struct si_resource *res;
763
764 if (!view || !view->resource) {
765 si_disable_shader_image(ctx, shader, slot);
766 return;
767 }
768
769 res = si_resource(view->resource);
770
771 si_set_shader_image_desc(ctx, view, skip_decompress, descs->list + si_get_image_slot(slot) * 8,
772 descs->list + si_get_image_slot(slot + SI_NUM_IMAGES) * 8);
773
774 if (&images->views[slot] != view)
775 util_copy_image_view(&images->views[slot], view);
776
777 if (res->b.b.target == PIPE_BUFFER || view->shader_access & SI_IMAGE_ACCESS_AS_BUFFER) {
778 images->needs_color_decompress_mask &= ~(1 << slot);
779 res->bind_history |= PIPE_BIND_SHADER_IMAGE;
780 } else {
781 struct si_texture *tex = (struct si_texture *)res;
782 unsigned level = view->u.tex.level;
783
784 if (color_needs_decompression(tex)) {
785 images->needs_color_decompress_mask |= 1 << slot;
786 } else {
787 images->needs_color_decompress_mask &= ~(1 << slot);
788 }
789
790 if (vi_dcc_enabled(tex, level) && p_atomic_read(&tex->framebuffers_bound))
791 ctx->need_check_render_feedback = true;
792 }
793
794 images->enabled_mask |= 1u << slot;
795 ctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
796
797 /* Since this can flush, it must be done after enabled_mask is updated. */
798 si_sampler_view_add_buffer(
799 ctx, &res->b.b,
800 (view->access & PIPE_IMAGE_ACCESS_WRITE) ? RADEON_USAGE_READWRITE : RADEON_USAGE_READ, false,
801 true);
802 }
803
804 static void si_set_shader_images(struct pipe_context *pipe, enum pipe_shader_type shader,
805 unsigned start_slot, unsigned count,
806 const struct pipe_image_view *views)
807 {
808 struct si_context *ctx = (struct si_context *)pipe;
809 unsigned i, slot;
810
811 assert(shader < SI_NUM_SHADERS);
812
813 if (!count)
814 return;
815
816 assert(start_slot + count <= SI_NUM_IMAGES);
817
818 if (views) {
819 for (i = 0, slot = start_slot; i < count; ++i, ++slot)
820 si_set_shader_image(ctx, shader, slot, &views[i], false);
821 } else {
822 for (i = 0, slot = start_slot; i < count; ++i, ++slot)
823 si_set_shader_image(ctx, shader, slot, NULL, false);
824 }
825
826 if (shader == PIPE_SHADER_COMPUTE &&
827 ctx->cs_shader_state.program &&
828 start_slot < ctx->cs_shader_state.program->sel.cs_num_images_in_user_sgprs)
829 ctx->compute_image_sgprs_dirty = true;
830
831 si_update_shader_needs_decompress_mask(ctx, shader);
832 }
833
834 static void si_images_update_needs_color_decompress_mask(struct si_images *images)
835 {
836 unsigned mask = images->enabled_mask;
837
838 while (mask) {
839 int i = u_bit_scan(&mask);
840 struct pipe_resource *res = images->views[i].resource;
841
842 if (res && res->target != PIPE_BUFFER) {
843 struct si_texture *tex = (struct si_texture *)res;
844
845 if (color_needs_decompression(tex)) {
846 images->needs_color_decompress_mask |= 1 << i;
847 } else {
848 images->needs_color_decompress_mask &= ~(1 << i);
849 }
850 }
851 }
852 }
853
854 void si_update_ps_colorbuf0_slot(struct si_context *sctx)
855 {
856 struct si_buffer_resources *buffers = &sctx->rw_buffers;
857 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
858 unsigned slot = SI_PS_IMAGE_COLORBUF0;
859 struct pipe_surface *surf = NULL;
860
861 /* si_texture_disable_dcc can get us here again. */
862 if (sctx->blitter->running)
863 return;
864
865 /* See whether FBFETCH is used and color buffer 0 is set. */
866 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_fbfetch &&
867 sctx->framebuffer.state.nr_cbufs && sctx->framebuffer.state.cbufs[0])
868 surf = sctx->framebuffer.state.cbufs[0];
869
870 /* Return if FBFETCH transitions from disabled to disabled. */
871 if (!buffers->buffers[slot] && !surf)
872 return;
873
874 sctx->ps_uses_fbfetch = surf != NULL;
875 si_update_ps_iter_samples(sctx);
876
877 if (surf) {
878 struct si_texture *tex = (struct si_texture *)surf->texture;
879 struct pipe_image_view view = {0};
880
881 assert(tex);
882 assert(!tex->is_depth);
883
884 /* Disable DCC, because the texture is used as both a sampler
885 * and color buffer.
886 */
887 si_texture_disable_dcc(sctx, tex);
888
889 if (tex->buffer.b.b.nr_samples <= 1 && tex->cmask_buffer) {
890 /* Disable CMASK. */
891 assert(tex->cmask_buffer != &tex->buffer);
892 si_eliminate_fast_color_clear(sctx, tex, NULL);
893 si_texture_discard_cmask(sctx->screen, tex);
894 }
895
896 view.resource = surf->texture;
897 view.format = surf->format;
898 view.access = PIPE_IMAGE_ACCESS_READ;
899 view.u.tex.first_layer = surf->u.tex.first_layer;
900 view.u.tex.last_layer = surf->u.tex.last_layer;
901 view.u.tex.level = surf->u.tex.level;
902
903 /* Set the descriptor. */
904 uint32_t *desc = descs->list + slot * 4;
905 memset(desc, 0, 16 * 4);
906 si_set_shader_image_desc(sctx, &view, true, desc, desc + 8);
907
908 pipe_resource_reference(&buffers->buffers[slot], &tex->buffer.b.b);
909 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READ,
910 RADEON_PRIO_SHADER_RW_IMAGE);
911 buffers->enabled_mask |= 1llu << slot;
912 } else {
913 /* Clear the descriptor. */
914 memset(descs->list + slot * 4, 0, 8 * 4);
915 pipe_resource_reference(&buffers->buffers[slot], NULL);
916 buffers->enabled_mask &= ~(1llu << slot);
917 }
918
919 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
920 }
921
922 /* SAMPLER STATES */
923
924 static void si_bind_sampler_states(struct pipe_context *ctx, enum pipe_shader_type shader,
925 unsigned start, unsigned count, void **states)
926 {
927 struct si_context *sctx = (struct si_context *)ctx;
928 struct si_samplers *samplers = &sctx->samplers[shader];
929 struct si_descriptors *desc = si_sampler_and_image_descriptors(sctx, shader);
930 struct si_sampler_state **sstates = (struct si_sampler_state **)states;
931 int i;
932
933 if (!count || shader >= SI_NUM_SHADERS || !sstates)
934 return;
935
936 for (i = 0; i < count; i++) {
937 unsigned slot = start + i;
938 unsigned desc_slot = si_get_sampler_slot(slot);
939
940 if (!sstates[i] || sstates[i] == samplers->sampler_states[slot])
941 continue;
942
943 #ifndef NDEBUG
944 assert(sstates[i]->magic == SI_SAMPLER_STATE_MAGIC);
945 #endif
946 samplers->sampler_states[slot] = sstates[i];
947
948 /* If FMASK is bound, don't overwrite it.
949 * The sampler state will be set after FMASK is unbound.
950 */
951 struct si_sampler_view *sview = (struct si_sampler_view *)samplers->views[slot];
952
953 struct si_texture *tex = NULL;
954
955 if (sview && sview->base.texture && sview->base.texture->target != PIPE_BUFFER)
956 tex = (struct si_texture *)sview->base.texture;
957
958 if (tex && tex->surface.fmask_size)
959 continue;
960
961 si_set_sampler_state_desc(sstates[i], sview, tex, desc->list + desc_slot * 16 + 12);
962
963 sctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
964 }
965 }
966
967 /* BUFFER RESOURCES */
968
969 static void si_init_buffer_resources(struct si_buffer_resources *buffers,
970 struct si_descriptors *descs, unsigned num_buffers,
971 short shader_userdata_rel_index,
972 enum radeon_bo_priority priority,
973 enum radeon_bo_priority priority_constbuf)
974 {
975 buffers->priority = priority;
976 buffers->priority_constbuf = priority_constbuf;
977 buffers->buffers = CALLOC(num_buffers, sizeof(struct pipe_resource *));
978 buffers->offsets = CALLOC(num_buffers, sizeof(buffers->offsets[0]));
979
980 si_init_descriptors(descs, shader_userdata_rel_index, 4, num_buffers);
981 }
982
983 static void si_release_buffer_resources(struct si_buffer_resources *buffers,
984 struct si_descriptors *descs)
985 {
986 int i;
987
988 for (i = 0; i < descs->num_elements; i++) {
989 pipe_resource_reference(&buffers->buffers[i], NULL);
990 }
991
992 FREE(buffers->buffers);
993 FREE(buffers->offsets);
994 }
995
996 static void si_buffer_resources_begin_new_cs(struct si_context *sctx,
997 struct si_buffer_resources *buffers)
998 {
999 uint64_t mask = buffers->enabled_mask;
1000
1001 /* Add buffers to the CS. */
1002 while (mask) {
1003 int i = u_bit_scan64(&mask);
1004
1005 radeon_add_to_buffer_list(
1006 sctx, sctx->gfx_cs, si_resource(buffers->buffers[i]),
1007 buffers->writable_mask & (1llu << i) ? RADEON_USAGE_READWRITE : RADEON_USAGE_READ,
1008 i < SI_NUM_SHADER_BUFFERS ? buffers->priority : buffers->priority_constbuf);
1009 }
1010 }
1011
1012 static bool si_buffer_resources_check_encrypted(struct si_context *sctx,
1013 struct si_buffer_resources *buffers)
1014 {
1015 uint64_t mask = buffers->enabled_mask;
1016
1017 while (mask) {
1018 int i = u_bit_scan64(&mask);
1019
1020 /* only check for reads */
1021 if ((buffers->writable_mask & (1llu << i)) == 0 &&
1022 (si_resource(buffers->buffers[i])->flags & RADEON_FLAG_ENCRYPTED))
1023 return true;
1024 }
1025
1026 return false;
1027 }
1028
1029 static void si_get_buffer_from_descriptors(struct si_buffer_resources *buffers,
1030 struct si_descriptors *descs, unsigned idx,
1031 struct pipe_resource **buf, unsigned *offset,
1032 unsigned *size)
1033 {
1034 pipe_resource_reference(buf, buffers->buffers[idx]);
1035 if (*buf) {
1036 struct si_resource *res = si_resource(*buf);
1037 const uint32_t *desc = descs->list + idx * 4;
1038 uint64_t va;
1039
1040 *size = desc[2];
1041
1042 assert(G_008F04_STRIDE(desc[1]) == 0);
1043 va = si_desc_extract_buffer_address(desc);
1044
1045 assert(va >= res->gpu_address && va + *size <= res->gpu_address + res->bo_size);
1046 *offset = va - res->gpu_address;
1047 }
1048 }
1049
1050 /* VERTEX BUFFERS */
1051
1052 static void si_vertex_buffers_begin_new_cs(struct si_context *sctx)
1053 {
1054 int count = sctx->num_vertex_elements;
1055 int i;
1056
1057 for (i = 0; i < count; i++) {
1058 int vb = sctx->vertex_elements->vertex_buffer_index[i];
1059
1060 if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
1061 continue;
1062 if (!sctx->vertex_buffer[vb].buffer.resource)
1063 continue;
1064
1065 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
1066 si_resource(sctx->vertex_buffer[vb].buffer.resource),
1067 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
1068 }
1069
1070 if (!sctx->vb_descriptors_buffer)
1071 return;
1072 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, sctx->vb_descriptors_buffer, RADEON_USAGE_READ,
1073 RADEON_PRIO_DESCRIPTORS);
1074 }
1075
1076 bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
1077 {
1078 unsigned i, count = sctx->num_vertex_elements;
1079 uint32_t *ptr;
1080
1081 if (!sctx->vertex_buffers_dirty || !count)
1082 return true;
1083
1084 struct si_vertex_elements *velems = sctx->vertex_elements;
1085 unsigned alloc_size = velems->vb_desc_list_alloc_size;
1086
1087 if (alloc_size) {
1088 /* Vertex buffer descriptors are the only ones which are uploaded
1089 * directly through a staging buffer and don't go through
1090 * the fine-grained upload path.
1091 */
1092 u_upload_alloc(sctx->b.const_uploader, 0, alloc_size,
1093 si_optimal_tcc_alignment(sctx, alloc_size), &sctx->vb_descriptors_offset,
1094 (struct pipe_resource **)&sctx->vb_descriptors_buffer, (void **)&ptr);
1095 if (!sctx->vb_descriptors_buffer) {
1096 sctx->vb_descriptors_offset = 0;
1097 sctx->vb_descriptors_gpu_list = NULL;
1098 return false;
1099 }
1100
1101 sctx->vb_descriptors_gpu_list = ptr;
1102 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, sctx->vb_descriptors_buffer, RADEON_USAGE_READ,
1103 RADEON_PRIO_DESCRIPTORS);
1104 sctx->vertex_buffer_pointer_dirty = true;
1105 sctx->prefetch_L2_mask |= SI_PREFETCH_VBO_DESCRIPTORS;
1106 } else {
1107 si_resource_reference(&sctx->vb_descriptors_buffer, NULL);
1108 sctx->vertex_buffer_pointer_dirty = false;
1109 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VBO_DESCRIPTORS;
1110 }
1111
1112 assert(count <= SI_MAX_ATTRIBS);
1113
1114 unsigned first_vb_use_mask = velems->first_vb_use_mask;
1115 unsigned num_vbos_in_user_sgprs = sctx->screen->num_vbos_in_user_sgprs;
1116
1117 for (i = 0; i < count; i++) {
1118 struct pipe_vertex_buffer *vb;
1119 struct si_resource *buf;
1120 unsigned vbo_index = velems->vertex_buffer_index[i];
1121 uint32_t *desc = i < num_vbos_in_user_sgprs ? &sctx->vb_descriptor_user_sgprs[i * 4]
1122 : &ptr[(i - num_vbos_in_user_sgprs) * 4];
1123
1124 vb = &sctx->vertex_buffer[vbo_index];
1125 buf = si_resource(vb->buffer.resource);
1126 if (!buf) {
1127 memset(desc, 0, 16);
1128 continue;
1129 }
1130
1131 int64_t offset = (int64_t)((int)vb->buffer_offset) + velems->src_offset[i];
1132
1133 if (offset >= buf->b.b.width0) {
1134 assert(offset < buf->b.b.width0);
1135 memset(desc, 0, 16);
1136 continue;
1137 }
1138
1139 uint64_t va = buf->gpu_address + offset;
1140
1141 int64_t num_records = (int64_t)buf->b.b.width0 - offset;
1142 if (sctx->chip_class != GFX8 && vb->stride) {
1143 /* Round up by rounding down and adding 1 */
1144 num_records = (num_records - velems->format_size[i]) / vb->stride + 1;
1145 }
1146 assert(num_records >= 0 && num_records <= UINT_MAX);
1147
1148 uint32_t rsrc_word3 = velems->rsrc_word3[i];
1149
1150 /* OOB_SELECT chooses the out-of-bounds check:
1151 * - 1: index >= NUM_RECORDS (Structured)
1152 * - 3: offset >= NUM_RECORDS (Raw)
1153 */
1154 if (sctx->chip_class >= GFX10)
1155 rsrc_word3 |= S_008F0C_OOB_SELECT(vb->stride ? V_008F0C_OOB_SELECT_STRUCTURED
1156 : V_008F0C_OOB_SELECT_RAW);
1157
1158 desc[0] = va;
1159 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(vb->stride);
1160 desc[2] = num_records;
1161 desc[3] = rsrc_word3;
1162
1163 if (first_vb_use_mask & (1 << i)) {
1164 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, si_resource(vb->buffer.resource),
1165 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
1166 }
1167 }
1168
1169 /* Don't flush the const cache. It would have a very negative effect
1170 * on performance (confirmed by testing). New descriptors are always
1171 * uploaded to a fresh new buffer, so I don't think flushing the const
1172 * cache is needed. */
1173 si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
1174 sctx->vertex_buffer_user_sgprs_dirty = num_vbos_in_user_sgprs > 0;
1175 sctx->vertex_buffers_dirty = false;
1176 return true;
1177 }
1178
1179 /* CONSTANT BUFFERS */
1180
1181 static struct si_descriptors *si_const_and_shader_buffer_descriptors(struct si_context *sctx,
1182 unsigned shader)
1183 {
1184 return &sctx->descriptors[si_const_and_shader_buffer_descriptors_idx(shader)];
1185 }
1186
1187 void si_upload_const_buffer(struct si_context *sctx, struct si_resource **buf, const uint8_t *ptr,
1188 unsigned size, uint32_t *const_offset)
1189 {
1190 void *tmp;
1191
1192 u_upload_alloc(sctx->b.const_uploader, 0, size, si_optimal_tcc_alignment(sctx, size),
1193 const_offset, (struct pipe_resource **)buf, &tmp);
1194 if (*buf)
1195 util_memcpy_cpu_to_le32(tmp, ptr, size);
1196 }
1197
1198 static void si_set_constant_buffer(struct si_context *sctx, struct si_buffer_resources *buffers,
1199 unsigned descriptors_idx, uint slot,
1200 const struct pipe_constant_buffer *input)
1201 {
1202 struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
1203 assert(slot < descs->num_elements);
1204 pipe_resource_reference(&buffers->buffers[slot], NULL);
1205
1206 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1207 * with a NULL buffer). We need to use a dummy buffer instead. */
1208 if (sctx->chip_class == GFX7 && (!input || (!input->buffer && !input->user_buffer)))
1209 input = &sctx->null_const_buf;
1210
1211 if (input && (input->buffer || input->user_buffer)) {
1212 struct pipe_resource *buffer = NULL;
1213 uint64_t va;
1214 unsigned buffer_offset;
1215
1216 /* Upload the user buffer if needed. */
1217 if (input->user_buffer) {
1218 si_upload_const_buffer(sctx, (struct si_resource **)&buffer, input->user_buffer,
1219 input->buffer_size, &buffer_offset);
1220 if (!buffer) {
1221 /* Just unbind on failure. */
1222 si_set_constant_buffer(sctx, buffers, descriptors_idx, slot, NULL);
1223 return;
1224 }
1225 } else {
1226 pipe_resource_reference(&buffer, input->buffer);
1227 buffer_offset = input->buffer_offset;
1228 }
1229
1230 va = si_resource(buffer)->gpu_address + buffer_offset;
1231
1232 /* Set the descriptor. */
1233 uint32_t *desc = descs->list + slot * 4;
1234 desc[0] = va;
1235 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(0);
1236 desc[2] = input->buffer_size;
1237 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1238 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
1239
1240 if (sctx->chip_class >= GFX10) {
1241 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
1242 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | S_008F0C_RESOURCE_LEVEL(1);
1243 } else {
1244 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1245 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1246 }
1247
1248 buffers->buffers[slot] = buffer;
1249 buffers->offsets[slot] = buffer_offset;
1250 radeon_add_to_gfx_buffer_list_check_mem(sctx, si_resource(buffer), RADEON_USAGE_READ,
1251 buffers->priority_constbuf, true);
1252 buffers->enabled_mask |= 1llu << slot;
1253 } else {
1254 /* Clear the descriptor. */
1255 memset(descs->list + slot * 4, 0, sizeof(uint32_t) * 4);
1256 buffers->enabled_mask &= ~(1llu << slot);
1257 }
1258
1259 sctx->descriptors_dirty |= 1u << descriptors_idx;
1260 }
1261
1262 static void si_pipe_set_constant_buffer(struct pipe_context *ctx, enum pipe_shader_type shader,
1263 uint slot, const struct pipe_constant_buffer *input)
1264 {
1265 struct si_context *sctx = (struct si_context *)ctx;
1266
1267 if (shader >= SI_NUM_SHADERS)
1268 return;
1269
1270 if (slot == 0 && input && input->buffer &&
1271 !(si_resource(input->buffer)->flags & RADEON_FLAG_32BIT)) {
1272 assert(!"constant buffer 0 must have a 32-bit VM address, use const_uploader");
1273 return;
1274 }
1275
1276 if (input && input->buffer)
1277 si_resource(input->buffer)->bind_history |= PIPE_BIND_CONSTANT_BUFFER;
1278
1279 slot = si_get_constbuf_slot(slot);
1280 si_set_constant_buffer(sctx, &sctx->const_and_shader_buffers[shader],
1281 si_const_and_shader_buffer_descriptors_idx(shader), slot, input);
1282 }
1283
1284 void si_get_pipe_constant_buffer(struct si_context *sctx, uint shader, uint slot,
1285 struct pipe_constant_buffer *cbuf)
1286 {
1287 cbuf->user_buffer = NULL;
1288 si_get_buffer_from_descriptors(
1289 &sctx->const_and_shader_buffers[shader], si_const_and_shader_buffer_descriptors(sctx, shader),
1290 si_get_constbuf_slot(slot), &cbuf->buffer, &cbuf->buffer_offset, &cbuf->buffer_size);
1291 }
1292
1293 /* SHADER BUFFERS */
1294
1295 static void si_set_shader_buffer(struct si_context *sctx, struct si_buffer_resources *buffers,
1296 unsigned descriptors_idx, uint slot,
1297 const struct pipe_shader_buffer *sbuffer, bool writable,
1298 enum radeon_bo_priority priority)
1299 {
1300 struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
1301 uint32_t *desc = descs->list + slot * 4;
1302
1303 if (!sbuffer || !sbuffer->buffer) {
1304 pipe_resource_reference(&buffers->buffers[slot], NULL);
1305 memset(desc, 0, sizeof(uint32_t) * 4);
1306 buffers->enabled_mask &= ~(1llu << slot);
1307 buffers->writable_mask &= ~(1llu << slot);
1308 sctx->descriptors_dirty |= 1u << descriptors_idx;
1309 return;
1310 }
1311
1312 struct si_resource *buf = si_resource(sbuffer->buffer);
1313 uint64_t va = buf->gpu_address + sbuffer->buffer_offset;
1314
1315 desc[0] = va;
1316 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(0);
1317 desc[2] = sbuffer->buffer_size;
1318 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1319 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
1320
1321 if (sctx->chip_class >= GFX10) {
1322 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
1323 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | S_008F0C_RESOURCE_LEVEL(1);
1324 } else {
1325 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1326 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1327 }
1328
1329 pipe_resource_reference(&buffers->buffers[slot], &buf->b.b);
1330 buffers->offsets[slot] = sbuffer->buffer_offset;
1331 radeon_add_to_gfx_buffer_list_check_mem(
1332 sctx, buf, writable ? RADEON_USAGE_READWRITE : RADEON_USAGE_READ, priority, true);
1333 if (writable)
1334 buffers->writable_mask |= 1llu << slot;
1335 else
1336 buffers->writable_mask &= ~(1llu << slot);
1337
1338 buffers->enabled_mask |= 1llu << slot;
1339 sctx->descriptors_dirty |= 1lu << descriptors_idx;
1340
1341 util_range_add(&buf->b.b, &buf->valid_buffer_range, sbuffer->buffer_offset,
1342 sbuffer->buffer_offset + sbuffer->buffer_size);
1343 }
1344
1345 static void si_set_shader_buffers(struct pipe_context *ctx, enum pipe_shader_type shader,
1346 unsigned start_slot, unsigned count,
1347 const struct pipe_shader_buffer *sbuffers,
1348 unsigned writable_bitmask)
1349 {
1350 struct si_context *sctx = (struct si_context *)ctx;
1351 struct si_buffer_resources *buffers = &sctx->const_and_shader_buffers[shader];
1352 unsigned descriptors_idx = si_const_and_shader_buffer_descriptors_idx(shader);
1353 unsigned i;
1354
1355 assert(start_slot + count <= SI_NUM_SHADER_BUFFERS);
1356
1357 if (shader == PIPE_SHADER_COMPUTE &&
1358 sctx->cs_shader_state.program &&
1359 start_slot < sctx->cs_shader_state.program->sel.cs_num_shaderbufs_in_user_sgprs)
1360 sctx->compute_shaderbuf_sgprs_dirty = true;
1361
1362 for (i = 0; i < count; ++i) {
1363 const struct pipe_shader_buffer *sbuffer = sbuffers ? &sbuffers[i] : NULL;
1364 unsigned slot = si_get_shaderbuf_slot(start_slot + i);
1365
1366 if (sbuffer && sbuffer->buffer)
1367 si_resource(sbuffer->buffer)->bind_history |= PIPE_BIND_SHADER_BUFFER;
1368
1369 si_set_shader_buffer(sctx, buffers, descriptors_idx, slot, sbuffer,
1370 !!(writable_bitmask & (1u << i)), buffers->priority);
1371 }
1372 }
1373
1374 void si_get_shader_buffers(struct si_context *sctx, enum pipe_shader_type shader, uint start_slot,
1375 uint count, struct pipe_shader_buffer *sbuf)
1376 {
1377 struct si_buffer_resources *buffers = &sctx->const_and_shader_buffers[shader];
1378 struct si_descriptors *descs = si_const_and_shader_buffer_descriptors(sctx, shader);
1379
1380 for (unsigned i = 0; i < count; ++i) {
1381 si_get_buffer_from_descriptors(buffers, descs, si_get_shaderbuf_slot(start_slot + i),
1382 &sbuf[i].buffer, &sbuf[i].buffer_offset, &sbuf[i].buffer_size);
1383 }
1384 }
1385
1386 /* RING BUFFERS */
1387
1388 void si_set_rw_buffer(struct si_context *sctx, uint slot, const struct pipe_constant_buffer *input)
1389 {
1390 si_set_constant_buffer(sctx, &sctx->rw_buffers, SI_DESCS_RW_BUFFERS, slot, input);
1391 }
1392
1393 void si_set_rw_shader_buffer(struct si_context *sctx, uint slot,
1394 const struct pipe_shader_buffer *sbuffer)
1395 {
1396 si_set_shader_buffer(sctx, &sctx->rw_buffers, SI_DESCS_RW_BUFFERS, slot, sbuffer, true,
1397 RADEON_PRIO_SHADER_RW_BUFFER);
1398 }
1399
1400 void si_set_ring_buffer(struct si_context *sctx, uint slot, struct pipe_resource *buffer,
1401 unsigned stride, unsigned num_records, bool add_tid, bool swizzle,
1402 unsigned element_size, unsigned index_stride, uint64_t offset)
1403 {
1404 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1405 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1406
1407 /* The stride field in the resource descriptor has 14 bits */
1408 assert(stride < (1 << 14));
1409
1410 assert(slot < descs->num_elements);
1411 pipe_resource_reference(&buffers->buffers[slot], NULL);
1412
1413 if (buffer) {
1414 uint64_t va;
1415
1416 va = si_resource(buffer)->gpu_address + offset;
1417
1418 switch (element_size) {
1419 default:
1420 assert(!"Unsupported ring buffer element size");
1421 case 0:
1422 case 2:
1423 element_size = 0;
1424 break;
1425 case 4:
1426 element_size = 1;
1427 break;
1428 case 8:
1429 element_size = 2;
1430 break;
1431 case 16:
1432 element_size = 3;
1433 break;
1434 }
1435
1436 switch (index_stride) {
1437 default:
1438 assert(!"Unsupported ring buffer index stride");
1439 case 0:
1440 case 8:
1441 index_stride = 0;
1442 break;
1443 case 16:
1444 index_stride = 1;
1445 break;
1446 case 32:
1447 index_stride = 2;
1448 break;
1449 case 64:
1450 index_stride = 3;
1451 break;
1452 }
1453
1454 if (sctx->chip_class >= GFX8 && stride)
1455 num_records *= stride;
1456
1457 /* Set the descriptor. */
1458 uint32_t *desc = descs->list + slot * 4;
1459 desc[0] = va;
1460 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride) |
1461 S_008F04_SWIZZLE_ENABLE(swizzle);
1462 desc[2] = num_records;
1463 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1464 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1465 S_008F0C_INDEX_STRIDE(index_stride) | S_008F0C_ADD_TID_ENABLE(add_tid);
1466
1467 if (sctx->chip_class >= GFX9)
1468 assert(!swizzle || element_size == 1); /* always 4 bytes on GFX9 */
1469 else
1470 desc[3] |= S_008F0C_ELEMENT_SIZE(element_size);
1471
1472 if (sctx->chip_class >= GFX10) {
1473 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
1474 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) | S_008F0C_RESOURCE_LEVEL(1);
1475 } else {
1476 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1477 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1478 }
1479
1480 pipe_resource_reference(&buffers->buffers[slot], buffer);
1481 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, si_resource(buffer), RADEON_USAGE_READWRITE,
1482 buffers->priority);
1483 buffers->enabled_mask |= 1llu << slot;
1484 } else {
1485 /* Clear the descriptor. */
1486 memset(descs->list + slot * 4, 0, sizeof(uint32_t) * 4);
1487 buffers->enabled_mask &= ~(1llu << slot);
1488 }
1489
1490 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
1491 }
1492
1493 /* INTERNAL CONST BUFFERS */
1494
1495 static void si_set_polygon_stipple(struct pipe_context *ctx, const struct pipe_poly_stipple *state)
1496 {
1497 struct si_context *sctx = (struct si_context *)ctx;
1498 struct pipe_constant_buffer cb = {};
1499 unsigned stipple[32];
1500 int i;
1501
1502 for (i = 0; i < 32; i++)
1503 stipple[i] = util_bitreverse(state->stipple[i]);
1504
1505 cb.user_buffer = stipple;
1506 cb.buffer_size = sizeof(stipple);
1507
1508 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE, &cb);
1509 }
1510
1511 /* TEXTURE METADATA ENABLE/DISABLE */
1512
1513 static void si_resident_handles_update_needs_color_decompress(struct si_context *sctx)
1514 {
1515 util_dynarray_clear(&sctx->resident_tex_needs_color_decompress);
1516 util_dynarray_clear(&sctx->resident_img_needs_color_decompress);
1517
1518 util_dynarray_foreach (&sctx->resident_tex_handles, struct si_texture_handle *, tex_handle) {
1519 struct pipe_resource *res = (*tex_handle)->view->texture;
1520 struct si_texture *tex;
1521
1522 if (!res || res->target == PIPE_BUFFER)
1523 continue;
1524
1525 tex = (struct si_texture *)res;
1526 if (!color_needs_decompression(tex))
1527 continue;
1528
1529 util_dynarray_append(&sctx->resident_tex_needs_color_decompress, struct si_texture_handle *,
1530 *tex_handle);
1531 }
1532
1533 util_dynarray_foreach (&sctx->resident_img_handles, struct si_image_handle *, img_handle) {
1534 struct pipe_image_view *view = &(*img_handle)->view;
1535 struct pipe_resource *res = view->resource;
1536 struct si_texture *tex;
1537
1538 if (!res || res->target == PIPE_BUFFER)
1539 continue;
1540
1541 tex = (struct si_texture *)res;
1542 if (!color_needs_decompression(tex))
1543 continue;
1544
1545 util_dynarray_append(&sctx->resident_img_needs_color_decompress, struct si_image_handle *,
1546 *img_handle);
1547 }
1548 }
1549
1550 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1551 * while the texture is bound, possibly by a different context. In that case,
1552 * call this function to update needs_*_decompress_masks.
1553 */
1554 void si_update_needs_color_decompress_masks(struct si_context *sctx)
1555 {
1556 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
1557 si_samplers_update_needs_color_decompress_mask(&sctx->samplers[i]);
1558 si_images_update_needs_color_decompress_mask(&sctx->images[i]);
1559 si_update_shader_needs_decompress_mask(sctx, i);
1560 }
1561
1562 si_resident_handles_update_needs_color_decompress(sctx);
1563 }
1564
1565 /* BUFFER DISCARD/INVALIDATION */
1566
1567 /* Reset descriptors of buffer resources after \p buf has been invalidated.
1568 * If buf == NULL, reset all descriptors.
1569 */
1570 static void si_reset_buffer_resources(struct si_context *sctx, struct si_buffer_resources *buffers,
1571 unsigned descriptors_idx, uint64_t slot_mask,
1572 struct pipe_resource *buf, enum radeon_bo_priority priority)
1573 {
1574 struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
1575 uint64_t mask = buffers->enabled_mask & slot_mask;
1576
1577 while (mask) {
1578 unsigned i = u_bit_scan64(&mask);
1579 struct pipe_resource *buffer = buffers->buffers[i];
1580
1581 if (buffer && (!buf || buffer == buf)) {
1582 si_set_buf_desc_address(si_resource(buffer), buffers->offsets[i], descs->list + i * 4);
1583 sctx->descriptors_dirty |= 1u << descriptors_idx;
1584
1585 radeon_add_to_gfx_buffer_list_check_mem(
1586 sctx, si_resource(buffer),
1587 buffers->writable_mask & (1llu << i) ? RADEON_USAGE_READWRITE : RADEON_USAGE_READ,
1588 priority, true);
1589 }
1590 }
1591 }
1592
1593 /* Update all buffer bindings where the buffer is bound, including
1594 * all resource descriptors. This is invalidate_buffer without
1595 * the invalidation.
1596 *
1597 * If buf == NULL, update all buffer bindings.
1598 */
1599 void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf)
1600 {
1601 struct si_resource *buffer = si_resource(buf);
1602 unsigned i, shader;
1603 unsigned num_elems = sctx->num_vertex_elements;
1604
1605 /* We changed the buffer, now we need to bind it where the old one
1606 * was bound. This consists of 2 things:
1607 * 1) Updating the resource descriptor and dirtying it.
1608 * 2) Adding a relocation to the CS, so that it's usable.
1609 */
1610
1611 /* Vertex buffers. */
1612 if (!buffer) {
1613 if (num_elems)
1614 sctx->vertex_buffers_dirty = true;
1615 } else if (buffer->bind_history & PIPE_BIND_VERTEX_BUFFER) {
1616 for (i = 0; i < num_elems; i++) {
1617 int vb = sctx->vertex_elements->vertex_buffer_index[i];
1618
1619 if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
1620 continue;
1621 if (!sctx->vertex_buffer[vb].buffer.resource)
1622 continue;
1623
1624 if (sctx->vertex_buffer[vb].buffer.resource == buf) {
1625 sctx->vertex_buffers_dirty = true;
1626 break;
1627 }
1628 }
1629 }
1630
1631 /* Streamout buffers. (other internal buffers can't be invalidated) */
1632 if (!buffer || buffer->bind_history & PIPE_BIND_STREAM_OUTPUT) {
1633 for (i = SI_VS_STREAMOUT_BUF0; i <= SI_VS_STREAMOUT_BUF3; i++) {
1634 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1635 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1636 struct pipe_resource *buffer = buffers->buffers[i];
1637
1638 if (!buffer || (buf && buffer != buf))
1639 continue;
1640
1641 si_set_buf_desc_address(si_resource(buffer), buffers->offsets[i], descs->list + i * 4);
1642 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
1643
1644 radeon_add_to_gfx_buffer_list_check_mem(sctx, si_resource(buffer), RADEON_USAGE_WRITE,
1645 RADEON_PRIO_SHADER_RW_BUFFER, true);
1646
1647 /* Update the streamout state. */
1648 if (sctx->streamout.begin_emitted)
1649 si_emit_streamout_end(sctx);
1650 sctx->streamout.append_bitmask = sctx->streamout.enabled_mask;
1651 si_streamout_buffers_dirty(sctx);
1652 }
1653 }
1654
1655 /* Constant and shader buffers. */
1656 if (!buffer || buffer->bind_history & PIPE_BIND_CONSTANT_BUFFER) {
1657 for (shader = 0; shader < SI_NUM_SHADERS; shader++)
1658 si_reset_buffer_resources(sctx, &sctx->const_and_shader_buffers[shader],
1659 si_const_and_shader_buffer_descriptors_idx(shader),
1660 u_bit_consecutive64(SI_NUM_SHADER_BUFFERS, SI_NUM_CONST_BUFFERS),
1661 buf, sctx->const_and_shader_buffers[shader].priority_constbuf);
1662 }
1663
1664 if (!buffer || buffer->bind_history & PIPE_BIND_SHADER_BUFFER) {
1665 for (shader = 0; shader < SI_NUM_SHADERS; shader++)
1666 si_reset_buffer_resources(sctx, &sctx->const_and_shader_buffers[shader],
1667 si_const_and_shader_buffer_descriptors_idx(shader),
1668 u_bit_consecutive64(0, SI_NUM_SHADER_BUFFERS), buf,
1669 sctx->const_and_shader_buffers[shader].priority);
1670 }
1671
1672 if (!buffer || buffer->bind_history & PIPE_BIND_SAMPLER_VIEW) {
1673 /* Texture buffers - update bindings. */
1674 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1675 struct si_samplers *samplers = &sctx->samplers[shader];
1676 struct si_descriptors *descs = si_sampler_and_image_descriptors(sctx, shader);
1677 unsigned mask = samplers->enabled_mask;
1678
1679 while (mask) {
1680 unsigned i = u_bit_scan(&mask);
1681 struct pipe_resource *buffer = samplers->views[i]->texture;
1682
1683 if (buffer && buffer->target == PIPE_BUFFER && (!buf || buffer == buf)) {
1684 unsigned desc_slot = si_get_sampler_slot(i);
1685
1686 si_set_buf_desc_address(si_resource(buffer), samplers->views[i]->u.buf.offset,
1687 descs->list + desc_slot * 16 + 4);
1688 sctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
1689
1690 radeon_add_to_gfx_buffer_list_check_mem(sctx, si_resource(buffer), RADEON_USAGE_READ,
1691 RADEON_PRIO_SAMPLER_BUFFER, true);
1692 }
1693 }
1694 }
1695 }
1696
1697 /* Shader images */
1698 if (!buffer || buffer->bind_history & PIPE_BIND_SHADER_IMAGE) {
1699 for (shader = 0; shader < SI_NUM_SHADERS; ++shader) {
1700 struct si_images *images = &sctx->images[shader];
1701 struct si_descriptors *descs = si_sampler_and_image_descriptors(sctx, shader);
1702 unsigned mask = images->enabled_mask;
1703
1704 while (mask) {
1705 unsigned i = u_bit_scan(&mask);
1706 struct pipe_resource *buffer = images->views[i].resource;
1707
1708 if (buffer && buffer->target == PIPE_BUFFER && (!buf || buffer == buf)) {
1709 unsigned desc_slot = si_get_image_slot(i);
1710
1711 if (images->views[i].access & PIPE_IMAGE_ACCESS_WRITE)
1712 si_mark_image_range_valid(&images->views[i]);
1713
1714 si_set_buf_desc_address(si_resource(buffer), images->views[i].u.buf.offset,
1715 descs->list + desc_slot * 8 + 4);
1716 sctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
1717
1718 radeon_add_to_gfx_buffer_list_check_mem(sctx, si_resource(buffer),
1719 RADEON_USAGE_READWRITE,
1720 RADEON_PRIO_SAMPLER_BUFFER, true);
1721 }
1722 }
1723 }
1724 }
1725
1726 /* Bindless texture handles */
1727 if (!buffer || buffer->texture_handle_allocated) {
1728 struct si_descriptors *descs = &sctx->bindless_descriptors;
1729
1730 util_dynarray_foreach (&sctx->resident_tex_handles, struct si_texture_handle *, tex_handle) {
1731 struct pipe_sampler_view *view = (*tex_handle)->view;
1732 unsigned desc_slot = (*tex_handle)->desc_slot;
1733 struct pipe_resource *buffer = view->texture;
1734
1735 if (buffer && buffer->target == PIPE_BUFFER && (!buf || buffer == buf)) {
1736 si_set_buf_desc_address(si_resource(buffer), view->u.buf.offset,
1737 descs->list + desc_slot * 16 + 4);
1738
1739 (*tex_handle)->desc_dirty = true;
1740 sctx->bindless_descriptors_dirty = true;
1741
1742 radeon_add_to_gfx_buffer_list_check_mem(sctx, si_resource(buffer), RADEON_USAGE_READ,
1743 RADEON_PRIO_SAMPLER_BUFFER, true);
1744 }
1745 }
1746 }
1747
1748 /* Bindless image handles */
1749 if (!buffer || buffer->image_handle_allocated) {
1750 struct si_descriptors *descs = &sctx->bindless_descriptors;
1751
1752 util_dynarray_foreach (&sctx->resident_img_handles, struct si_image_handle *, img_handle) {
1753 struct pipe_image_view *view = &(*img_handle)->view;
1754 unsigned desc_slot = (*img_handle)->desc_slot;
1755 struct pipe_resource *buffer = view->resource;
1756
1757 if (buffer && buffer->target == PIPE_BUFFER && (!buf || buffer == buf)) {
1758 if (view->access & PIPE_IMAGE_ACCESS_WRITE)
1759 si_mark_image_range_valid(view);
1760
1761 si_set_buf_desc_address(si_resource(buffer), view->u.buf.offset,
1762 descs->list + desc_slot * 16 + 4);
1763
1764 (*img_handle)->desc_dirty = true;
1765 sctx->bindless_descriptors_dirty = true;
1766
1767 radeon_add_to_gfx_buffer_list_check_mem(
1768 sctx, si_resource(buffer), RADEON_USAGE_READWRITE, RADEON_PRIO_SAMPLER_BUFFER, true);
1769 }
1770 }
1771 }
1772
1773 if (buffer) {
1774 /* Do the same for other contexts. They will invoke this function
1775 * with buffer == NULL.
1776 */
1777 unsigned new_counter = p_atomic_inc_return(&sctx->screen->dirty_buf_counter);
1778
1779 /* Skip the update for the current context, because we have already updated
1780 * the buffer bindings.
1781 */
1782 if (new_counter == sctx->last_dirty_buf_counter + 1)
1783 sctx->last_dirty_buf_counter = new_counter;
1784 }
1785 }
1786
1787 static void si_upload_bindless_descriptor(struct si_context *sctx, unsigned desc_slot,
1788 unsigned num_dwords)
1789 {
1790 struct si_descriptors *desc = &sctx->bindless_descriptors;
1791 unsigned desc_slot_offset = desc_slot * 16;
1792 uint32_t *data;
1793 uint64_t va;
1794
1795 data = desc->list + desc_slot_offset;
1796 va = desc->gpu_address + desc_slot_offset * 4;
1797
1798 si_cp_write_data(sctx, desc->buffer, va - desc->buffer->gpu_address, num_dwords * 4, V_370_TC_L2,
1799 V_370_ME, data);
1800 }
1801
1802 static void si_upload_bindless_descriptors(struct si_context *sctx)
1803 {
1804 if (!sctx->bindless_descriptors_dirty)
1805 return;
1806
1807 /* Wait for graphics/compute to be idle before updating the resident
1808 * descriptors directly in memory, in case the GPU is using them.
1809 */
1810 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH;
1811 sctx->emit_cache_flush(sctx);
1812
1813 util_dynarray_foreach (&sctx->resident_tex_handles, struct si_texture_handle *, tex_handle) {
1814 unsigned desc_slot = (*tex_handle)->desc_slot;
1815
1816 if (!(*tex_handle)->desc_dirty)
1817 continue;
1818
1819 si_upload_bindless_descriptor(sctx, desc_slot, 16);
1820 (*tex_handle)->desc_dirty = false;
1821 }
1822
1823 util_dynarray_foreach (&sctx->resident_img_handles, struct si_image_handle *, img_handle) {
1824 unsigned desc_slot = (*img_handle)->desc_slot;
1825
1826 if (!(*img_handle)->desc_dirty)
1827 continue;
1828
1829 si_upload_bindless_descriptor(sctx, desc_slot, 8);
1830 (*img_handle)->desc_dirty = false;
1831 }
1832
1833 /* Invalidate L1 because it doesn't know that L2 changed. */
1834 sctx->flags |= SI_CONTEXT_INV_SCACHE;
1835 sctx->emit_cache_flush(sctx);
1836
1837 sctx->bindless_descriptors_dirty = false;
1838 }
1839
1840 /* Update mutable image descriptor fields of all resident textures. */
1841 static void si_update_bindless_texture_descriptor(struct si_context *sctx,
1842 struct si_texture_handle *tex_handle)
1843 {
1844 struct si_sampler_view *sview = (struct si_sampler_view *)tex_handle->view;
1845 struct si_descriptors *desc = &sctx->bindless_descriptors;
1846 unsigned desc_slot_offset = tex_handle->desc_slot * 16;
1847 uint32_t desc_list[16];
1848
1849 if (sview->base.texture->target == PIPE_BUFFER)
1850 return;
1851
1852 memcpy(desc_list, desc->list + desc_slot_offset, sizeof(desc_list));
1853 si_set_sampler_view_desc(sctx, sview, &tex_handle->sstate, desc->list + desc_slot_offset);
1854
1855 if (memcmp(desc_list, desc->list + desc_slot_offset, sizeof(desc_list))) {
1856 tex_handle->desc_dirty = true;
1857 sctx->bindless_descriptors_dirty = true;
1858 }
1859 }
1860
1861 static void si_update_bindless_image_descriptor(struct si_context *sctx,
1862 struct si_image_handle *img_handle)
1863 {
1864 struct si_descriptors *desc = &sctx->bindless_descriptors;
1865 unsigned desc_slot_offset = img_handle->desc_slot * 16;
1866 struct pipe_image_view *view = &img_handle->view;
1867 struct pipe_resource *res = view->resource;
1868 uint32_t image_desc[16];
1869 unsigned desc_size = (res->nr_samples >= 2 ? 16 : 8) * 4;
1870
1871 if (res->target == PIPE_BUFFER)
1872 return;
1873
1874 memcpy(image_desc, desc->list + desc_slot_offset, desc_size);
1875 si_set_shader_image_desc(sctx, view, true, desc->list + desc_slot_offset,
1876 desc->list + desc_slot_offset + 8);
1877
1878 if (memcmp(image_desc, desc->list + desc_slot_offset, desc_size)) {
1879 img_handle->desc_dirty = true;
1880 sctx->bindless_descriptors_dirty = true;
1881 }
1882 }
1883
1884 static void si_update_all_resident_texture_descriptors(struct si_context *sctx)
1885 {
1886 util_dynarray_foreach (&sctx->resident_tex_handles, struct si_texture_handle *, tex_handle) {
1887 si_update_bindless_texture_descriptor(sctx, *tex_handle);
1888 }
1889
1890 util_dynarray_foreach (&sctx->resident_img_handles, struct si_image_handle *, img_handle) {
1891 si_update_bindless_image_descriptor(sctx, *img_handle);
1892 }
1893
1894 si_upload_bindless_descriptors(sctx);
1895 }
1896
1897 /* Update mutable image descriptor fields of all bound textures. */
1898 void si_update_all_texture_descriptors(struct si_context *sctx)
1899 {
1900 unsigned shader;
1901
1902 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1903 struct si_samplers *samplers = &sctx->samplers[shader];
1904 struct si_images *images = &sctx->images[shader];
1905 unsigned mask;
1906
1907 /* Images. */
1908 mask = images->enabled_mask;
1909 while (mask) {
1910 unsigned i = u_bit_scan(&mask);
1911 struct pipe_image_view *view = &images->views[i];
1912
1913 if (!view->resource || view->resource->target == PIPE_BUFFER)
1914 continue;
1915
1916 si_set_shader_image(sctx, shader, i, view, true);
1917 }
1918
1919 /* Sampler views. */
1920 mask = samplers->enabled_mask;
1921 while (mask) {
1922 unsigned i = u_bit_scan(&mask);
1923 struct pipe_sampler_view *view = samplers->views[i];
1924
1925 if (!view || !view->texture || view->texture->target == PIPE_BUFFER)
1926 continue;
1927
1928 si_set_sampler_view(sctx, shader, i, samplers->views[i], true);
1929 }
1930
1931 si_update_shader_needs_decompress_mask(sctx, shader);
1932 }
1933
1934 si_update_all_resident_texture_descriptors(sctx);
1935 si_update_ps_colorbuf0_slot(sctx);
1936 }
1937
1938 /* SHADER USER DATA */
1939
1940 static void si_mark_shader_pointers_dirty(struct si_context *sctx, unsigned shader)
1941 {
1942 sctx->shader_pointers_dirty |=
1943 u_bit_consecutive(SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS, SI_NUM_SHADER_DESCS);
1944
1945 if (shader == PIPE_SHADER_VERTEX) {
1946 sctx->vertex_buffer_pointer_dirty = sctx->vb_descriptors_buffer != NULL;
1947 sctx->vertex_buffer_user_sgprs_dirty =
1948 sctx->num_vertex_elements > 0 && sctx->screen->num_vbos_in_user_sgprs;
1949 }
1950
1951 si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
1952 }
1953
1954 void si_shader_pointers_mark_dirty(struct si_context *sctx)
1955 {
1956 sctx->shader_pointers_dirty = u_bit_consecutive(0, SI_NUM_DESCS);
1957 sctx->vertex_buffer_pointer_dirty = sctx->vb_descriptors_buffer != NULL;
1958 sctx->vertex_buffer_user_sgprs_dirty =
1959 sctx->num_vertex_elements > 0 && sctx->screen->num_vbos_in_user_sgprs;
1960 si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
1961 sctx->graphics_bindless_pointer_dirty = sctx->bindless_descriptors.buffer != NULL;
1962 sctx->compute_bindless_pointer_dirty = sctx->bindless_descriptors.buffer != NULL;
1963 sctx->compute_shaderbuf_sgprs_dirty = true;
1964 sctx->compute_image_sgprs_dirty = true;
1965 }
1966
1967 /* Set a base register address for user data constants in the given shader.
1968 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
1969 */
1970 static void si_set_user_data_base(struct si_context *sctx, unsigned shader, uint32_t new_base)
1971 {
1972 uint32_t *base = &sctx->shader_pointers.sh_base[shader];
1973
1974 if (*base != new_base) {
1975 *base = new_base;
1976
1977 if (new_base)
1978 si_mark_shader_pointers_dirty(sctx, shader);
1979
1980 /* Any change in enabled shader stages requires re-emitting
1981 * the VS state SGPR, because it contains the clamp_vertex_color
1982 * state, which can be done in VS, TES, and GS.
1983 */
1984 sctx->last_vs_state = ~0;
1985 }
1986 }
1987
1988 /* This must be called when these are changed between enabled and disabled
1989 * - geometry shader
1990 * - tessellation evaluation shader
1991 * - NGG
1992 */
1993 void si_shader_change_notify(struct si_context *sctx)
1994 {
1995 /* VS can be bound as VS, ES, or LS. */
1996 if (sctx->tes_shader.cso) {
1997 if (sctx->chip_class >= GFX10) {
1998 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B430_SPI_SHADER_USER_DATA_HS_0);
1999 } else if (sctx->chip_class == GFX9) {
2000 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B430_SPI_SHADER_USER_DATA_LS_0);
2001 } else {
2002 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B530_SPI_SHADER_USER_DATA_LS_0);
2003 }
2004 } else if (sctx->chip_class >= GFX10) {
2005 if (sctx->ngg || sctx->gs_shader.cso) {
2006 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B230_SPI_SHADER_USER_DATA_GS_0);
2007 } else {
2008 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0);
2009 }
2010 } else if (sctx->gs_shader.cso) {
2011 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B330_SPI_SHADER_USER_DATA_ES_0);
2012 } else {
2013 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0);
2014 }
2015
2016 /* TES can be bound as ES, VS, or not bound. */
2017 if (sctx->tes_shader.cso) {
2018 if (sctx->chip_class >= GFX10) {
2019 if (sctx->ngg || sctx->gs_shader.cso) {
2020 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, R_00B230_SPI_SHADER_USER_DATA_GS_0);
2021 } else {
2022 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, R_00B130_SPI_SHADER_USER_DATA_VS_0);
2023 }
2024 } else if (sctx->gs_shader.cso) {
2025 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, R_00B330_SPI_SHADER_USER_DATA_ES_0);
2026 } else {
2027 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, R_00B130_SPI_SHADER_USER_DATA_VS_0);
2028 }
2029 } else {
2030 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, 0);
2031 }
2032 }
2033
2034 static void si_emit_shader_pointer_head(struct radeon_cmdbuf *cs, unsigned sh_offset,
2035 unsigned pointer_count)
2036 {
2037 SI_CHECK_SHADOWED_REGS(sh_offset, pointer_count);
2038 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count, 0));
2039 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
2040 }
2041
2042 static void si_emit_shader_pointer_body(struct si_screen *sscreen, struct radeon_cmdbuf *cs,
2043 uint64_t va)
2044 {
2045 radeon_emit(cs, va);
2046
2047 assert(va == 0 || (va >> 32) == sscreen->info.address32_hi);
2048 }
2049
2050 static void si_emit_shader_pointer(struct si_context *sctx, struct si_descriptors *desc,
2051 unsigned sh_base)
2052 {
2053 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2054 unsigned sh_offset = sh_base + desc->shader_userdata_offset;
2055
2056 si_emit_shader_pointer_head(cs, sh_offset, 1);
2057 si_emit_shader_pointer_body(sctx->screen, cs, desc->gpu_address);
2058 }
2059
2060 static void si_emit_consecutive_shader_pointers(struct si_context *sctx, unsigned pointer_mask,
2061 unsigned sh_base)
2062 {
2063 if (!sh_base)
2064 return;
2065
2066 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2067 unsigned mask = sctx->shader_pointers_dirty & pointer_mask;
2068
2069 while (mask) {
2070 int start, count;
2071 u_bit_scan_consecutive_range(&mask, &start, &count);
2072
2073 struct si_descriptors *descs = &sctx->descriptors[start];
2074 unsigned sh_offset = sh_base + descs->shader_userdata_offset;
2075
2076 si_emit_shader_pointer_head(cs, sh_offset, count);
2077 for (int i = 0; i < count; i++)
2078 si_emit_shader_pointer_body(sctx->screen, cs, descs[i].gpu_address);
2079 }
2080 }
2081
2082 static void si_emit_global_shader_pointers(struct si_context *sctx, struct si_descriptors *descs)
2083 {
2084 if (sctx->chip_class >= GFX10) {
2085 si_emit_shader_pointer(sctx, descs, R_00B030_SPI_SHADER_USER_DATA_PS_0);
2086 /* HW VS stage only used in non-NGG mode. */
2087 si_emit_shader_pointer(sctx, descs, R_00B130_SPI_SHADER_USER_DATA_VS_0);
2088 si_emit_shader_pointer(sctx, descs, R_00B230_SPI_SHADER_USER_DATA_GS_0);
2089 si_emit_shader_pointer(sctx, descs, R_00B430_SPI_SHADER_USER_DATA_HS_0);
2090 return;
2091 } else if (sctx->chip_class == GFX9 && sctx->shadowed_regs) {
2092 /* We can't use the COMMON registers with register shadowing. */
2093 si_emit_shader_pointer(sctx, descs, R_00B030_SPI_SHADER_USER_DATA_PS_0);
2094 si_emit_shader_pointer(sctx, descs, R_00B130_SPI_SHADER_USER_DATA_VS_0);
2095 si_emit_shader_pointer(sctx, descs, R_00B330_SPI_SHADER_USER_DATA_ES_0);
2096 si_emit_shader_pointer(sctx, descs, R_00B430_SPI_SHADER_USER_DATA_LS_0);
2097 return;
2098 } else if (sctx->chip_class == GFX9) {
2099 /* Broadcast it to all shader stages. */
2100 si_emit_shader_pointer(sctx, descs, R_00B530_SPI_SHADER_USER_DATA_COMMON_0);
2101 return;
2102 }
2103
2104 si_emit_shader_pointer(sctx, descs, R_00B030_SPI_SHADER_USER_DATA_PS_0);
2105 si_emit_shader_pointer(sctx, descs, R_00B130_SPI_SHADER_USER_DATA_VS_0);
2106 si_emit_shader_pointer(sctx, descs, R_00B330_SPI_SHADER_USER_DATA_ES_0);
2107 si_emit_shader_pointer(sctx, descs, R_00B230_SPI_SHADER_USER_DATA_GS_0);
2108 si_emit_shader_pointer(sctx, descs, R_00B430_SPI_SHADER_USER_DATA_HS_0);
2109 si_emit_shader_pointer(sctx, descs, R_00B530_SPI_SHADER_USER_DATA_LS_0);
2110 }
2111
2112 void si_emit_graphics_shader_pointers(struct si_context *sctx)
2113 {
2114 uint32_t *sh_base = sctx->shader_pointers.sh_base;
2115
2116 if (sctx->shader_pointers_dirty & (1 << SI_DESCS_RW_BUFFERS)) {
2117 si_emit_global_shader_pointers(sctx, &sctx->descriptors[SI_DESCS_RW_BUFFERS]);
2118 }
2119
2120 si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(VERTEX),
2121 sh_base[PIPE_SHADER_VERTEX]);
2122 si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(TESS_EVAL),
2123 sh_base[PIPE_SHADER_TESS_EVAL]);
2124 si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(FRAGMENT),
2125 sh_base[PIPE_SHADER_FRAGMENT]);
2126 si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(TESS_CTRL),
2127 sh_base[PIPE_SHADER_TESS_CTRL]);
2128 si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(GEOMETRY),
2129 sh_base[PIPE_SHADER_GEOMETRY]);
2130
2131 sctx->shader_pointers_dirty &= ~u_bit_consecutive(SI_DESCS_RW_BUFFERS, SI_DESCS_FIRST_COMPUTE);
2132
2133 if (sctx->vertex_buffer_pointer_dirty && sctx->num_vertex_elements) {
2134 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2135
2136 /* Find the location of the VB descriptor pointer. */
2137 unsigned sh_dw_offset = SI_VS_NUM_USER_SGPR;
2138 if (sctx->chip_class >= GFX9) {
2139 if (sctx->tes_shader.cso)
2140 sh_dw_offset = GFX9_TCS_NUM_USER_SGPR;
2141 else if (sctx->gs_shader.cso)
2142 sh_dw_offset = GFX9_VSGS_NUM_USER_SGPR;
2143 }
2144
2145 unsigned sh_offset = sh_base[PIPE_SHADER_VERTEX] + sh_dw_offset * 4;
2146 si_emit_shader_pointer_head(cs, sh_offset, 1);
2147 si_emit_shader_pointer_body(
2148 sctx->screen, cs, sctx->vb_descriptors_buffer->gpu_address + sctx->vb_descriptors_offset);
2149 sctx->vertex_buffer_pointer_dirty = false;
2150 }
2151
2152 if (sctx->vertex_buffer_user_sgprs_dirty && sctx->num_vertex_elements &&
2153 sctx->screen->num_vbos_in_user_sgprs) {
2154 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2155 unsigned num_desc = MIN2(sctx->num_vertex_elements, sctx->screen->num_vbos_in_user_sgprs);
2156 unsigned sh_offset = sh_base[PIPE_SHADER_VERTEX] + SI_SGPR_VS_VB_DESCRIPTOR_FIRST * 4;
2157
2158 si_emit_shader_pointer_head(cs, sh_offset, num_desc * 4);
2159 radeon_emit_array(cs, sctx->vb_descriptor_user_sgprs, num_desc * 4);
2160 sctx->vertex_buffer_user_sgprs_dirty = false;
2161 }
2162
2163 if (sctx->graphics_bindless_pointer_dirty) {
2164 si_emit_global_shader_pointers(sctx, &sctx->bindless_descriptors);
2165 sctx->graphics_bindless_pointer_dirty = false;
2166 }
2167 }
2168
2169 void si_emit_compute_shader_pointers(struct si_context *sctx)
2170 {
2171 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2172 struct si_shader_selector *shader = &sctx->cs_shader_state.program->sel;
2173 unsigned base = R_00B900_COMPUTE_USER_DATA_0;
2174
2175 si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(COMPUTE),
2176 R_00B900_COMPUTE_USER_DATA_0);
2177 sctx->shader_pointers_dirty &= ~SI_DESCS_SHADER_MASK(COMPUTE);
2178
2179 if (sctx->compute_bindless_pointer_dirty) {
2180 si_emit_shader_pointer(sctx, &sctx->bindless_descriptors, base);
2181 sctx->compute_bindless_pointer_dirty = false;
2182 }
2183
2184 /* Set shader buffer descriptors in user SGPRs. */
2185 unsigned num_shaderbufs = shader->cs_num_shaderbufs_in_user_sgprs;
2186 if (num_shaderbufs && sctx->compute_shaderbuf_sgprs_dirty) {
2187 struct si_descriptors *desc = si_const_and_shader_buffer_descriptors(sctx, PIPE_SHADER_COMPUTE);
2188
2189 si_emit_shader_pointer_head(cs, R_00B900_COMPUTE_USER_DATA_0 +
2190 shader->cs_shaderbufs_sgpr_index * 4,
2191 num_shaderbufs * 4);
2192
2193 for (unsigned i = 0; i < num_shaderbufs; i++)
2194 radeon_emit_array(cs, &desc->list[si_get_shaderbuf_slot(i) * 4], 4);
2195
2196 sctx->compute_shaderbuf_sgprs_dirty = false;
2197 }
2198
2199 /* Set image descriptors in user SGPRs. */
2200 unsigned num_images = shader->cs_num_images_in_user_sgprs;
2201 if (num_images && sctx->compute_image_sgprs_dirty) {
2202 struct si_descriptors *desc = si_sampler_and_image_descriptors(sctx, PIPE_SHADER_COMPUTE);
2203
2204 si_emit_shader_pointer_head(cs, R_00B900_COMPUTE_USER_DATA_0 +
2205 shader->cs_images_sgpr_index * 4,
2206 shader->cs_images_num_sgprs);
2207
2208 for (unsigned i = 0; i < num_images; i++) {
2209 unsigned desc_offset = si_get_image_slot(i) * 8;
2210 unsigned num_sgprs = 8;
2211
2212 /* Image buffers are in desc[4..7]. */
2213 if (shader->info.image_buffers & (1 << i)) {
2214 desc_offset += 4;
2215 num_sgprs = 4;
2216 }
2217
2218 radeon_emit_array(cs, &desc->list[desc_offset], num_sgprs);
2219 }
2220
2221 sctx->compute_image_sgprs_dirty = false;
2222 }
2223 }
2224
2225 /* BINDLESS */
2226
2227 static void si_init_bindless_descriptors(struct si_context *sctx, struct si_descriptors *desc,
2228 short shader_userdata_rel_index, unsigned num_elements)
2229 {
2230 ASSERTED unsigned desc_slot;
2231
2232 si_init_descriptors(desc, shader_userdata_rel_index, 16, num_elements);
2233 sctx->bindless_descriptors.num_active_slots = num_elements;
2234
2235 /* The first bindless descriptor is stored at slot 1, because 0 is not
2236 * considered to be a valid handle.
2237 */
2238 sctx->num_bindless_descriptors = 1;
2239
2240 /* Track which bindless slots are used (or not). */
2241 util_idalloc_init(&sctx->bindless_used_slots);
2242 util_idalloc_resize(&sctx->bindless_used_slots, num_elements);
2243
2244 /* Reserve slot 0 because it's an invalid handle for bindless. */
2245 desc_slot = util_idalloc_alloc(&sctx->bindless_used_slots);
2246 assert(desc_slot == 0);
2247 }
2248
2249 static void si_release_bindless_descriptors(struct si_context *sctx)
2250 {
2251 si_release_descriptors(&sctx->bindless_descriptors);
2252 util_idalloc_fini(&sctx->bindless_used_slots);
2253 }
2254
2255 static unsigned si_get_first_free_bindless_slot(struct si_context *sctx)
2256 {
2257 struct si_descriptors *desc = &sctx->bindless_descriptors;
2258 unsigned desc_slot;
2259
2260 desc_slot = util_idalloc_alloc(&sctx->bindless_used_slots);
2261 if (desc_slot >= desc->num_elements) {
2262 /* The array of bindless descriptors is full, resize it. */
2263 unsigned slot_size = desc->element_dw_size * 4;
2264 unsigned new_num_elements = desc->num_elements * 2;
2265
2266 desc->list =
2267 REALLOC(desc->list, desc->num_elements * slot_size, new_num_elements * slot_size);
2268 desc->num_elements = new_num_elements;
2269 desc->num_active_slots = new_num_elements;
2270 }
2271
2272 assert(desc_slot);
2273 return desc_slot;
2274 }
2275
2276 static unsigned si_create_bindless_descriptor(struct si_context *sctx, uint32_t *desc_list,
2277 unsigned size)
2278 {
2279 struct si_descriptors *desc = &sctx->bindless_descriptors;
2280 unsigned desc_slot, desc_slot_offset;
2281
2282 /* Find a free slot. */
2283 desc_slot = si_get_first_free_bindless_slot(sctx);
2284
2285 /* For simplicity, sampler and image bindless descriptors use fixed
2286 * 16-dword slots for now. Image descriptors only need 8-dword but this
2287 * doesn't really matter because no real apps use image handles.
2288 */
2289 desc_slot_offset = desc_slot * 16;
2290
2291 /* Copy the descriptor into the array. */
2292 memcpy(desc->list + desc_slot_offset, desc_list, size);
2293
2294 /* Re-upload the whole array of bindless descriptors into a new buffer.
2295 */
2296 if (!si_upload_descriptors(sctx, desc))
2297 return 0;
2298
2299 /* Make sure to re-emit the shader pointers for all stages. */
2300 sctx->graphics_bindless_pointer_dirty = true;
2301 sctx->compute_bindless_pointer_dirty = true;
2302
2303 return desc_slot;
2304 }
2305
2306 static void si_update_bindless_buffer_descriptor(struct si_context *sctx, unsigned desc_slot,
2307 struct pipe_resource *resource, uint64_t offset,
2308 bool *desc_dirty)
2309 {
2310 struct si_descriptors *desc = &sctx->bindless_descriptors;
2311 struct si_resource *buf = si_resource(resource);
2312 unsigned desc_slot_offset = desc_slot * 16;
2313 uint32_t *desc_list = desc->list + desc_slot_offset + 4;
2314 uint64_t old_desc_va;
2315
2316 assert(resource->target == PIPE_BUFFER);
2317
2318 /* Retrieve the old buffer addr from the descriptor. */
2319 old_desc_va = si_desc_extract_buffer_address(desc_list);
2320
2321 if (old_desc_va != buf->gpu_address + offset) {
2322 /* The buffer has been invalidated when the handle wasn't
2323 * resident, update the descriptor and the dirty flag.
2324 */
2325 si_set_buf_desc_address(buf, offset, &desc_list[0]);
2326
2327 *desc_dirty = true;
2328 }
2329 }
2330
2331 static uint64_t si_create_texture_handle(struct pipe_context *ctx, struct pipe_sampler_view *view,
2332 const struct pipe_sampler_state *state)
2333 {
2334 struct si_sampler_view *sview = (struct si_sampler_view *)view;
2335 struct si_context *sctx = (struct si_context *)ctx;
2336 struct si_texture_handle *tex_handle;
2337 struct si_sampler_state *sstate;
2338 uint32_t desc_list[16];
2339 uint64_t handle;
2340
2341 tex_handle = CALLOC_STRUCT(si_texture_handle);
2342 if (!tex_handle)
2343 return 0;
2344
2345 memset(desc_list, 0, sizeof(desc_list));
2346 si_init_descriptor_list(&desc_list[0], 16, 1, null_texture_descriptor);
2347
2348 sstate = ctx->create_sampler_state(ctx, state);
2349 if (!sstate) {
2350 FREE(tex_handle);
2351 return 0;
2352 }
2353
2354 si_set_sampler_view_desc(sctx, sview, sstate, &desc_list[0]);
2355 memcpy(&tex_handle->sstate, sstate, sizeof(*sstate));
2356 ctx->delete_sampler_state(ctx, sstate);
2357
2358 tex_handle->desc_slot = si_create_bindless_descriptor(sctx, desc_list, sizeof(desc_list));
2359 if (!tex_handle->desc_slot) {
2360 FREE(tex_handle);
2361 return 0;
2362 }
2363
2364 handle = tex_handle->desc_slot;
2365
2366 if (!_mesa_hash_table_insert(sctx->tex_handles, (void *)(uintptr_t)handle, tex_handle)) {
2367 FREE(tex_handle);
2368 return 0;
2369 }
2370
2371 pipe_sampler_view_reference(&tex_handle->view, view);
2372
2373 si_resource(sview->base.texture)->texture_handle_allocated = true;
2374
2375 return handle;
2376 }
2377
2378 static void si_delete_texture_handle(struct pipe_context *ctx, uint64_t handle)
2379 {
2380 struct si_context *sctx = (struct si_context *)ctx;
2381 struct si_texture_handle *tex_handle;
2382 struct hash_entry *entry;
2383
2384 entry = _mesa_hash_table_search(sctx->tex_handles, (void *)(uintptr_t)handle);
2385 if (!entry)
2386 return;
2387
2388 tex_handle = (struct si_texture_handle *)entry->data;
2389
2390 /* Allow this descriptor slot to be re-used. */
2391 util_idalloc_free(&sctx->bindless_used_slots, tex_handle->desc_slot);
2392
2393 pipe_sampler_view_reference(&tex_handle->view, NULL);
2394 _mesa_hash_table_remove(sctx->tex_handles, entry);
2395 FREE(tex_handle);
2396 }
2397
2398 static void si_make_texture_handle_resident(struct pipe_context *ctx, uint64_t handle,
2399 bool resident)
2400 {
2401 struct si_context *sctx = (struct si_context *)ctx;
2402 struct si_texture_handle *tex_handle;
2403 struct si_sampler_view *sview;
2404 struct hash_entry *entry;
2405
2406 entry = _mesa_hash_table_search(sctx->tex_handles, (void *)(uintptr_t)handle);
2407 if (!entry)
2408 return;
2409
2410 tex_handle = (struct si_texture_handle *)entry->data;
2411 sview = (struct si_sampler_view *)tex_handle->view;
2412
2413 if (resident) {
2414 if (sview->base.texture->target != PIPE_BUFFER) {
2415 struct si_texture *tex = (struct si_texture *)sview->base.texture;
2416
2417 if (depth_needs_decompression(tex)) {
2418 util_dynarray_append(&sctx->resident_tex_needs_depth_decompress,
2419 struct si_texture_handle *, tex_handle);
2420 }
2421
2422 if (color_needs_decompression(tex)) {
2423 util_dynarray_append(&sctx->resident_tex_needs_color_decompress,
2424 struct si_texture_handle *, tex_handle);
2425 }
2426
2427 if (vi_dcc_enabled(tex, sview->base.u.tex.first_level) &&
2428 p_atomic_read(&tex->framebuffers_bound))
2429 sctx->need_check_render_feedback = true;
2430
2431 si_update_bindless_texture_descriptor(sctx, tex_handle);
2432 } else {
2433 si_update_bindless_buffer_descriptor(sctx, tex_handle->desc_slot, sview->base.texture,
2434 sview->base.u.buf.offset, &tex_handle->desc_dirty);
2435 }
2436
2437 /* Re-upload the descriptor if it has been updated while it
2438 * wasn't resident.
2439 */
2440 if (tex_handle->desc_dirty)
2441 sctx->bindless_descriptors_dirty = true;
2442
2443 /* Add the texture handle to the per-context list. */
2444 util_dynarray_append(&sctx->resident_tex_handles, struct si_texture_handle *, tex_handle);
2445
2446 /* Add the buffers to the current CS in case si_begin_new_cs()
2447 * is not going to be called.
2448 */
2449 si_sampler_view_add_buffer(sctx, sview->base.texture, RADEON_USAGE_READ,
2450 sview->is_stencil_sampler, false);
2451 } else {
2452 /* Remove the texture handle from the per-context list. */
2453 util_dynarray_delete_unordered(&sctx->resident_tex_handles, struct si_texture_handle *,
2454 tex_handle);
2455
2456 if (sview->base.texture->target != PIPE_BUFFER) {
2457 util_dynarray_delete_unordered(&sctx->resident_tex_needs_depth_decompress,
2458 struct si_texture_handle *, tex_handle);
2459
2460 util_dynarray_delete_unordered(&sctx->resident_tex_needs_color_decompress,
2461 struct si_texture_handle *, tex_handle);
2462 }
2463 }
2464 }
2465
2466 static uint64_t si_create_image_handle(struct pipe_context *ctx, const struct pipe_image_view *view)
2467 {
2468 struct si_context *sctx = (struct si_context *)ctx;
2469 struct si_image_handle *img_handle;
2470 uint32_t desc_list[16];
2471 uint64_t handle;
2472
2473 if (!view || !view->resource)
2474 return 0;
2475
2476 img_handle = CALLOC_STRUCT(si_image_handle);
2477 if (!img_handle)
2478 return 0;
2479
2480 memset(desc_list, 0, sizeof(desc_list));
2481 si_init_descriptor_list(&desc_list[0], 8, 2, null_image_descriptor);
2482
2483 si_set_shader_image_desc(sctx, view, false, &desc_list[0], &desc_list[8]);
2484
2485 img_handle->desc_slot = si_create_bindless_descriptor(sctx, desc_list, sizeof(desc_list));
2486 if (!img_handle->desc_slot) {
2487 FREE(img_handle);
2488 return 0;
2489 }
2490
2491 handle = img_handle->desc_slot;
2492
2493 if (!_mesa_hash_table_insert(sctx->img_handles, (void *)(uintptr_t)handle, img_handle)) {
2494 FREE(img_handle);
2495 return 0;
2496 }
2497
2498 util_copy_image_view(&img_handle->view, view);
2499
2500 si_resource(view->resource)->image_handle_allocated = true;
2501
2502 return handle;
2503 }
2504
2505 static void si_delete_image_handle(struct pipe_context *ctx, uint64_t handle)
2506 {
2507 struct si_context *sctx = (struct si_context *)ctx;
2508 struct si_image_handle *img_handle;
2509 struct hash_entry *entry;
2510
2511 entry = _mesa_hash_table_search(sctx->img_handles, (void *)(uintptr_t)handle);
2512 if (!entry)
2513 return;
2514
2515 img_handle = (struct si_image_handle *)entry->data;
2516
2517 util_copy_image_view(&img_handle->view, NULL);
2518 _mesa_hash_table_remove(sctx->img_handles, entry);
2519 FREE(img_handle);
2520 }
2521
2522 static void si_make_image_handle_resident(struct pipe_context *ctx, uint64_t handle,
2523 unsigned access, bool resident)
2524 {
2525 struct si_context *sctx = (struct si_context *)ctx;
2526 struct si_image_handle *img_handle;
2527 struct pipe_image_view *view;
2528 struct si_resource *res;
2529 struct hash_entry *entry;
2530
2531 entry = _mesa_hash_table_search(sctx->img_handles, (void *)(uintptr_t)handle);
2532 if (!entry)
2533 return;
2534
2535 img_handle = (struct si_image_handle *)entry->data;
2536 view = &img_handle->view;
2537 res = si_resource(view->resource);
2538
2539 if (resident) {
2540 if (res->b.b.target != PIPE_BUFFER) {
2541 struct si_texture *tex = (struct si_texture *)res;
2542 unsigned level = view->u.tex.level;
2543
2544 if (color_needs_decompression(tex)) {
2545 util_dynarray_append(&sctx->resident_img_needs_color_decompress,
2546 struct si_image_handle *, img_handle);
2547 }
2548
2549 if (vi_dcc_enabled(tex, level) && p_atomic_read(&tex->framebuffers_bound))
2550 sctx->need_check_render_feedback = true;
2551
2552 si_update_bindless_image_descriptor(sctx, img_handle);
2553 } else {
2554 si_update_bindless_buffer_descriptor(sctx, img_handle->desc_slot, view->resource,
2555 view->u.buf.offset, &img_handle->desc_dirty);
2556 }
2557
2558 /* Re-upload the descriptor if it has been updated while it
2559 * wasn't resident.
2560 */
2561 if (img_handle->desc_dirty)
2562 sctx->bindless_descriptors_dirty = true;
2563
2564 /* Add the image handle to the per-context list. */
2565 util_dynarray_append(&sctx->resident_img_handles, struct si_image_handle *, img_handle);
2566
2567 /* Add the buffers to the current CS in case si_begin_new_cs()
2568 * is not going to be called.
2569 */
2570 si_sampler_view_add_buffer(
2571 sctx, view->resource,
2572 (access & PIPE_IMAGE_ACCESS_WRITE) ? RADEON_USAGE_READWRITE : RADEON_USAGE_READ, false,
2573 false);
2574 } else {
2575 /* Remove the image handle from the per-context list. */
2576 util_dynarray_delete_unordered(&sctx->resident_img_handles, struct si_image_handle *,
2577 img_handle);
2578
2579 if (res->b.b.target != PIPE_BUFFER) {
2580 util_dynarray_delete_unordered(&sctx->resident_img_needs_color_decompress,
2581 struct si_image_handle *, img_handle);
2582 }
2583 }
2584 }
2585
2586 static void si_resident_buffers_add_all_to_bo_list(struct si_context *sctx)
2587 {
2588 unsigned num_resident_tex_handles, num_resident_img_handles;
2589
2590 num_resident_tex_handles = sctx->resident_tex_handles.size / sizeof(struct si_texture_handle *);
2591 num_resident_img_handles = sctx->resident_img_handles.size / sizeof(struct si_image_handle *);
2592
2593 /* Add all resident texture handles. */
2594 util_dynarray_foreach (&sctx->resident_tex_handles, struct si_texture_handle *, tex_handle) {
2595 struct si_sampler_view *sview = (struct si_sampler_view *)(*tex_handle)->view;
2596
2597 si_sampler_view_add_buffer(sctx, sview->base.texture, RADEON_USAGE_READ,
2598 sview->is_stencil_sampler, false);
2599 }
2600
2601 /* Add all resident image handles. */
2602 util_dynarray_foreach (&sctx->resident_img_handles, struct si_image_handle *, img_handle) {
2603 struct pipe_image_view *view = &(*img_handle)->view;
2604
2605 si_sampler_view_add_buffer(sctx, view->resource, RADEON_USAGE_READWRITE, false, false);
2606 }
2607
2608 sctx->num_resident_handles += num_resident_tex_handles + num_resident_img_handles;
2609 assert(sctx->bo_list_add_all_resident_resources);
2610 sctx->bo_list_add_all_resident_resources = false;
2611 }
2612
2613 /* INIT/DEINIT/UPLOAD */
2614
2615 void si_init_all_descriptors(struct si_context *sctx)
2616 {
2617 int i;
2618 unsigned first_shader = sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE;
2619
2620 for (i = first_shader; i < SI_NUM_SHADERS; i++) {
2621 bool is_2nd =
2622 sctx->chip_class >= GFX9 && (i == PIPE_SHADER_TESS_CTRL || i == PIPE_SHADER_GEOMETRY);
2623 unsigned num_sampler_slots = SI_NUM_IMAGE_SLOTS / 2 + SI_NUM_SAMPLERS;
2624 unsigned num_buffer_slots = SI_NUM_SHADER_BUFFERS + SI_NUM_CONST_BUFFERS;
2625 int rel_dw_offset;
2626 struct si_descriptors *desc;
2627
2628 if (is_2nd) {
2629 if (i == PIPE_SHADER_TESS_CTRL) {
2630 rel_dw_offset =
2631 (R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS - R_00B430_SPI_SHADER_USER_DATA_LS_0) / 4;
2632 } else if (sctx->chip_class >= GFX10) { /* PIPE_SHADER_GEOMETRY */
2633 rel_dw_offset =
2634 (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS - R_00B230_SPI_SHADER_USER_DATA_GS_0) / 4;
2635 } else {
2636 rel_dw_offset =
2637 (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS - R_00B330_SPI_SHADER_USER_DATA_ES_0) / 4;
2638 }
2639 } else {
2640 rel_dw_offset = SI_SGPR_CONST_AND_SHADER_BUFFERS;
2641 }
2642 desc = si_const_and_shader_buffer_descriptors(sctx, i);
2643 si_init_buffer_resources(&sctx->const_and_shader_buffers[i], desc, num_buffer_slots,
2644 rel_dw_offset, RADEON_PRIO_SHADER_RW_BUFFER,
2645 RADEON_PRIO_CONST_BUFFER);
2646 desc->slot_index_to_bind_directly = si_get_constbuf_slot(0);
2647
2648 if (is_2nd) {
2649 if (i == PIPE_SHADER_TESS_CTRL) {
2650 rel_dw_offset =
2651 (R_00B40C_SPI_SHADER_USER_DATA_ADDR_HI_HS - R_00B430_SPI_SHADER_USER_DATA_LS_0) / 4;
2652 } else if (sctx->chip_class >= GFX10) { /* PIPE_SHADER_GEOMETRY */
2653 rel_dw_offset =
2654 (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS - R_00B230_SPI_SHADER_USER_DATA_GS_0) / 4;
2655 } else {
2656 rel_dw_offset =
2657 (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS - R_00B330_SPI_SHADER_USER_DATA_ES_0) / 4;
2658 }
2659 } else {
2660 rel_dw_offset = SI_SGPR_SAMPLERS_AND_IMAGES;
2661 }
2662
2663 desc = si_sampler_and_image_descriptors(sctx, i);
2664 si_init_descriptors(desc, rel_dw_offset, 16, num_sampler_slots);
2665
2666 int j;
2667 for (j = 0; j < SI_NUM_IMAGE_SLOTS; j++)
2668 memcpy(desc->list + j * 8, null_image_descriptor, 8 * 4);
2669 for (; j < SI_NUM_IMAGE_SLOTS + SI_NUM_SAMPLERS * 2; j++)
2670 memcpy(desc->list + j * 8, null_texture_descriptor, 8 * 4);
2671 }
2672
2673 si_init_buffer_resources(&sctx->rw_buffers, &sctx->descriptors[SI_DESCS_RW_BUFFERS],
2674 SI_NUM_RW_BUFFERS, SI_SGPR_RW_BUFFERS,
2675 /* The second priority is used by
2676 * const buffers in RW buffer slots. */
2677 RADEON_PRIO_SHADER_RINGS, RADEON_PRIO_CONST_BUFFER);
2678 sctx->descriptors[SI_DESCS_RW_BUFFERS].num_active_slots = SI_NUM_RW_BUFFERS;
2679
2680 /* Initialize an array of 1024 bindless descriptors, when the limit is
2681 * reached, just make it larger and re-upload the whole array.
2682 */
2683 si_init_bindless_descriptors(sctx, &sctx->bindless_descriptors,
2684 SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES, 1024);
2685
2686 sctx->descriptors_dirty = u_bit_consecutive(0, SI_NUM_DESCS);
2687
2688 /* Set pipe_context functions. */
2689 sctx->b.bind_sampler_states = si_bind_sampler_states;
2690 sctx->b.set_shader_images = si_set_shader_images;
2691 sctx->b.set_constant_buffer = si_pipe_set_constant_buffer;
2692 sctx->b.set_shader_buffers = si_set_shader_buffers;
2693 sctx->b.set_sampler_views = si_set_sampler_views;
2694 sctx->b.create_texture_handle = si_create_texture_handle;
2695 sctx->b.delete_texture_handle = si_delete_texture_handle;
2696 sctx->b.make_texture_handle_resident = si_make_texture_handle_resident;
2697 sctx->b.create_image_handle = si_create_image_handle;
2698 sctx->b.delete_image_handle = si_delete_image_handle;
2699 sctx->b.make_image_handle_resident = si_make_image_handle_resident;
2700
2701 if (!sctx->has_graphics)
2702 return;
2703
2704 sctx->b.set_polygon_stipple = si_set_polygon_stipple;
2705
2706 /* Shader user data. */
2707 sctx->atoms.s.shader_pointers.emit = si_emit_graphics_shader_pointers;
2708
2709 /* Set default and immutable mappings. */
2710 if (sctx->ngg) {
2711 assert(sctx->chip_class >= GFX10);
2712 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B230_SPI_SHADER_USER_DATA_GS_0);
2713 } else {
2714 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0);
2715 }
2716
2717 if (sctx->chip_class == GFX9) {
2718 si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL, R_00B430_SPI_SHADER_USER_DATA_LS_0);
2719 si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY, R_00B330_SPI_SHADER_USER_DATA_ES_0);
2720 } else {
2721 si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL, R_00B430_SPI_SHADER_USER_DATA_HS_0);
2722 si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY, R_00B230_SPI_SHADER_USER_DATA_GS_0);
2723 }
2724 si_set_user_data_base(sctx, PIPE_SHADER_FRAGMENT, R_00B030_SPI_SHADER_USER_DATA_PS_0);
2725 }
2726
2727 static bool si_upload_shader_descriptors(struct si_context *sctx, unsigned mask)
2728 {
2729 unsigned dirty = sctx->descriptors_dirty & mask;
2730
2731 /* Assume nothing will go wrong: */
2732 sctx->shader_pointers_dirty |= dirty;
2733
2734 while (dirty) {
2735 unsigned i = u_bit_scan(&dirty);
2736
2737 if (!si_upload_descriptors(sctx, &sctx->descriptors[i]))
2738 return false;
2739 }
2740
2741 sctx->descriptors_dirty &= ~mask;
2742
2743 si_upload_bindless_descriptors(sctx);
2744
2745 return true;
2746 }
2747
2748 bool si_upload_graphics_shader_descriptors(struct si_context *sctx)
2749 {
2750 const unsigned mask = u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE);
2751 return si_upload_shader_descriptors(sctx, mask);
2752 }
2753
2754 bool si_upload_compute_shader_descriptors(struct si_context *sctx)
2755 {
2756 /* Does not update rw_buffers as that is not needed for compute shaders
2757 * and the input buffer is using the same SGPR's anyway.
2758 */
2759 const unsigned mask =
2760 u_bit_consecutive(SI_DESCS_FIRST_COMPUTE, SI_NUM_DESCS - SI_DESCS_FIRST_COMPUTE);
2761 return si_upload_shader_descriptors(sctx, mask);
2762 }
2763
2764 void si_release_all_descriptors(struct si_context *sctx)
2765 {
2766 int i;
2767
2768 for (i = 0; i < SI_NUM_SHADERS; i++) {
2769 si_release_buffer_resources(&sctx->const_and_shader_buffers[i],
2770 si_const_and_shader_buffer_descriptors(sctx, i));
2771 si_release_sampler_views(&sctx->samplers[i]);
2772 si_release_image_views(&sctx->images[i]);
2773 }
2774 si_release_buffer_resources(&sctx->rw_buffers, &sctx->descriptors[SI_DESCS_RW_BUFFERS]);
2775 for (i = 0; i < SI_NUM_VERTEX_BUFFERS; i++)
2776 pipe_vertex_buffer_unreference(&sctx->vertex_buffer[i]);
2777
2778 for (i = 0; i < SI_NUM_DESCS; ++i)
2779 si_release_descriptors(&sctx->descriptors[i]);
2780
2781 si_resource_reference(&sctx->vb_descriptors_buffer, NULL);
2782 sctx->vb_descriptors_gpu_list = NULL; /* points into a mapped buffer */
2783
2784 si_release_bindless_descriptors(sctx);
2785 }
2786
2787 bool si_gfx_resources_check_encrypted(struct si_context *sctx)
2788 {
2789 bool use_encrypted_bo = false;
2790 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
2791 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
2792 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
2793 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
2794 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
2795 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
2796 };
2797
2798 for (unsigned i = 0; i < SI_NUM_GRAPHICS_SHADERS && !use_encrypted_bo; i++) {
2799 if (!current_shader[i]->cso)
2800 continue;
2801
2802 use_encrypted_bo |=
2803 si_buffer_resources_check_encrypted(sctx, &sctx->const_and_shader_buffers[i]);
2804 use_encrypted_bo |=
2805 si_sampler_views_check_encrypted(sctx, &sctx->samplers[i],
2806 current_shader[i]->cso->info.samplers_declared);
2807 use_encrypted_bo |= si_image_views_check_encrypted(sctx, &sctx->images[i],
2808 current_shader[i]->cso->info.images_declared);
2809 }
2810 use_encrypted_bo |= si_buffer_resources_check_encrypted(sctx, &sctx->rw_buffers);
2811
2812 struct si_state_blend *blend = sctx->queued.named.blend;
2813 for (int i = 0; i < sctx->framebuffer.state.nr_cbufs && !use_encrypted_bo; i++) {
2814 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2815 if (surf && surf->texture) {
2816 struct si_texture *tex = (struct si_texture *)surf->texture;
2817 if (!(tex->buffer.flags & RADEON_FLAG_ENCRYPTED))
2818 continue;
2819 /* Are we reading from this framebuffer (blend) */
2820 if ((blend->blend_enable_4bit >> (4 * i)) & 0xf) {
2821 /* TODO: blend op */
2822 use_encrypted_bo = true;
2823 }
2824 }
2825 }
2826
2827 /* TODO: we should assert that either use_encrypted_bo is false,
2828 * or all writable buffers are encrypted.
2829 */
2830 return use_encrypted_bo;
2831 }
2832
2833 void si_gfx_resources_add_all_to_bo_list(struct si_context *sctx)
2834 {
2835 for (unsigned i = 0; i < SI_NUM_GRAPHICS_SHADERS; i++) {
2836 si_buffer_resources_begin_new_cs(sctx, &sctx->const_and_shader_buffers[i]);
2837 si_sampler_views_begin_new_cs(sctx, &sctx->samplers[i]);
2838 si_image_views_begin_new_cs(sctx, &sctx->images[i]);
2839 }
2840 si_buffer_resources_begin_new_cs(sctx, &sctx->rw_buffers);
2841 si_vertex_buffers_begin_new_cs(sctx);
2842
2843 if (sctx->bo_list_add_all_resident_resources)
2844 si_resident_buffers_add_all_to_bo_list(sctx);
2845
2846 assert(sctx->bo_list_add_all_gfx_resources);
2847 sctx->bo_list_add_all_gfx_resources = false;
2848 }
2849
2850 bool si_compute_resources_check_encrypted(struct si_context *sctx)
2851 {
2852 unsigned sh = PIPE_SHADER_COMPUTE;
2853
2854 struct si_shader_info* info = &sctx->cs_shader_state.program->sel.info;
2855
2856 /* TODO: we should assert that either use_encrypted_bo is false,
2857 * or all writable buffers are encrypted.
2858 */
2859 return si_buffer_resources_check_encrypted(sctx, &sctx->const_and_shader_buffers[sh]) ||
2860 si_sampler_views_check_encrypted(sctx, &sctx->samplers[sh], info->samplers_declared) ||
2861 si_image_views_check_encrypted(sctx, &sctx->images[sh], info->images_declared) ||
2862 si_buffer_resources_check_encrypted(sctx, &sctx->rw_buffers);
2863 }
2864
2865 void si_compute_resources_add_all_to_bo_list(struct si_context *sctx)
2866 {
2867 unsigned sh = PIPE_SHADER_COMPUTE;
2868
2869 si_buffer_resources_begin_new_cs(sctx, &sctx->const_and_shader_buffers[sh]);
2870 si_sampler_views_begin_new_cs(sctx, &sctx->samplers[sh]);
2871 si_image_views_begin_new_cs(sctx, &sctx->images[sh]);
2872 si_buffer_resources_begin_new_cs(sctx, &sctx->rw_buffers);
2873
2874 if (sctx->bo_list_add_all_resident_resources)
2875 si_resident_buffers_add_all_to_bo_list(sctx);
2876
2877 assert(sctx->bo_list_add_all_compute_resources);
2878 sctx->bo_list_add_all_compute_resources = false;
2879 }
2880
2881 void si_add_all_descriptors_to_bo_list(struct si_context *sctx)
2882 {
2883 for (unsigned i = 0; i < SI_NUM_DESCS; ++i)
2884 si_add_descriptors_to_bo_list(sctx, &sctx->descriptors[i]);
2885 si_add_descriptors_to_bo_list(sctx, &sctx->bindless_descriptors);
2886
2887 sctx->bo_list_add_all_resident_resources = true;
2888 sctx->bo_list_add_all_gfx_resources = true;
2889 sctx->bo_list_add_all_compute_resources = true;
2890 }
2891
2892 void si_set_active_descriptors(struct si_context *sctx, unsigned desc_idx, uint64_t new_active_mask)
2893 {
2894 struct si_descriptors *desc = &sctx->descriptors[desc_idx];
2895
2896 /* Ignore no-op updates and updates that disable all slots. */
2897 if (!new_active_mask ||