3e354d106b0de67cf9ecc0da52fb3d2e827376c5
[mesa.git] / src / gallium / drivers / radeonsi / si_descriptors.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 /* Resource binding slots and sampler states (each described with 8 or
26 * 4 dwords) are stored in lists in memory which is accessed by shaders
27 * using scalar load instructions.
28 *
29 * This file is responsible for managing such lists. It keeps a copy of all
30 * descriptors in CPU memory and re-uploads a whole list if some slots have
31 * been changed.
32 *
33 * This code is also reponsible for updating shader pointers to those lists.
34 *
35 * Note that CP DMA can't be used for updating the lists, because a GPU hang
36 * could leave the list in a mid-IB state and the next IB would get wrong
37 * descriptors and the whole context would be unusable at that point.
38 * (Note: The register shadowing can't be used due to the same reason)
39 *
40 * Also, uploading descriptors to newly allocated memory doesn't require
41 * a KCACHE flush.
42 *
43 *
44 * Possible scenarios for one 16 dword image+sampler slot:
45 *
46 * | Image | w/ FMASK | Buffer | NULL
47 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
48 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
49 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
50 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
51 *
52 * FMASK implies MSAA, therefore no sampler state.
53 * Sampler states are never unbound except when FMASK is bound.
54 */
55
56 #include "si_pipe.h"
57 #include "si_compute.h"
58 #include "sid.h"
59 #include "util/format/u_format.h"
60 #include "util/hash_table.h"
61 #include "util/u_idalloc.h"
62 #include "util/u_memory.h"
63 #include "util/u_upload_mgr.h"
64
65 /* NULL image and buffer descriptor for textures (alpha = 1) and images
66 * (alpha = 0).
67 *
68 * For images, all fields must be zero except for the swizzle, which
69 * supports arbitrary combinations of 0s and 1s. The texture type must be
70 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
71 *
72 * For buffers, all fields must be zero. If they are not, the hw hangs.
73 *
74 * This is the only reason why the buffer descriptor must be in words [4:7].
75 */
76 static uint32_t null_texture_descriptor[8] = {
77 0, 0, 0, S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1) | S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D)
78 /* the rest must contain zeros, which is also used by the buffer
79 * descriptor */
80 };
81
82 static uint32_t null_image_descriptor[8] = {
83 0, 0, 0, S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D)
84 /* the rest must contain zeros, which is also used by the buffer
85 * descriptor */
86 };
87
88 static uint64_t si_desc_extract_buffer_address(const uint32_t *desc)
89 {
90 uint64_t va = desc[0] | ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc[1]) << 32);
91
92 /* Sign-extend the 48-bit address. */
93 va <<= 16;
94 va = (int64_t)va >> 16;
95 return va;
96 }
97
98 static void si_init_descriptor_list(uint32_t *desc_list, unsigned element_dw_size,
99 unsigned num_elements, const uint32_t *null_descriptor)
100 {
101 int i;
102
103 /* Initialize the array to NULL descriptors if the element size is 8. */
104 if (null_descriptor) {
105 assert(element_dw_size % 8 == 0);
106 for (i = 0; i < num_elements * element_dw_size / 8; i++)
107 memcpy(desc_list + i * 8, null_descriptor, 8 * 4);
108 }
109 }
110
111 static void si_init_descriptors(struct si_descriptors *desc, short shader_userdata_rel_index,
112 unsigned element_dw_size, unsigned num_elements)
113 {
114 desc->list = CALLOC(num_elements, element_dw_size * 4);
115 desc->element_dw_size = element_dw_size;
116 desc->num_elements = num_elements;
117 desc->shader_userdata_offset = shader_userdata_rel_index * 4;
118 desc->slot_index_to_bind_directly = -1;
119 }
120
121 static void si_release_descriptors(struct si_descriptors *desc)
122 {
123 si_resource_reference(&desc->buffer, NULL);
124 FREE(desc->list);
125 }
126
127 static bool si_upload_descriptors(struct si_context *sctx, struct si_descriptors *desc)
128 {
129 unsigned slot_size = desc->element_dw_size * 4;
130 unsigned first_slot_offset = desc->first_active_slot * slot_size;
131 unsigned upload_size = desc->num_active_slots * slot_size;
132
133 /* Skip the upload if no shader is using the descriptors. dirty_mask
134 * will stay dirty and the descriptors will be uploaded when there is
135 * a shader using them.
136 */
137 if (!upload_size)
138 return true;
139
140 /* If there is just one active descriptor, bind it directly. */
141 if ((int)desc->first_active_slot == desc->slot_index_to_bind_directly &&
142 desc->num_active_slots == 1) {
143 uint32_t *descriptor = &desc->list[desc->slot_index_to_bind_directly * desc->element_dw_size];
144
145 /* The buffer is already in the buffer list. */
146 si_resource_reference(&desc->buffer, NULL);
147 desc->gpu_list = NULL;
148 desc->gpu_address = si_desc_extract_buffer_address(descriptor);
149 si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
150 return true;
151 }
152
153 uint32_t *ptr;
154 unsigned buffer_offset;
155 u_upload_alloc(sctx->b.const_uploader, first_slot_offset, upload_size,
156 si_optimal_tcc_alignment(sctx, upload_size), &buffer_offset,
157 (struct pipe_resource **)&desc->buffer, (void **)&ptr);
158 if (!desc->buffer) {
159 desc->gpu_address = 0;
160 return false; /* skip the draw call */
161 }
162
163 util_memcpy_cpu_to_le32(ptr, (char *)desc->list + first_slot_offset, upload_size);
164 desc->gpu_list = ptr - first_slot_offset / 4;
165
166 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, desc->buffer, RADEON_USAGE_READ,
167 RADEON_PRIO_DESCRIPTORS);
168
169 /* The shader pointer should point to slot 0. */
170 buffer_offset -= first_slot_offset;
171 desc->gpu_address = desc->buffer->gpu_address + buffer_offset;
172
173 assert(desc->buffer->flags & RADEON_FLAG_32BIT);
174 assert((desc->buffer->gpu_address >> 32) == sctx->screen->info.address32_hi);
175 assert((desc->gpu_address >> 32) == sctx->screen->info.address32_hi);
176
177 si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
178 return true;
179 }
180
181 static void
182 si_add_descriptors_to_bo_list(struct si_context *sctx, struct si_descriptors *desc)
183 {
184 if (!desc->buffer)
185 return;
186
187 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, desc->buffer, RADEON_USAGE_READ,
188 RADEON_PRIO_DESCRIPTORS);
189 }
190
191 /* SAMPLER VIEWS */
192
193 static inline enum radeon_bo_priority si_get_sampler_view_priority(struct si_resource *res)
194 {
195 if (res->b.b.target == PIPE_BUFFER)
196 return RADEON_PRIO_SAMPLER_BUFFER;
197
198 if (res->b.b.nr_samples > 1)
199 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
200
201 return RADEON_PRIO_SAMPLER_TEXTURE;
202 }
203
204 static struct si_descriptors *si_sampler_and_image_descriptors(struct si_context *sctx,
205 unsigned shader)
206 {
207 return &sctx->descriptors[si_sampler_and_image_descriptors_idx(shader)];
208 }
209
210 static void si_release_sampler_views(struct si_samplers *samplers)
211 {
212 int i;
213
214 for (i = 0; i < ARRAY_SIZE(samplers->views); i++) {
215 pipe_sampler_view_reference(&samplers->views[i], NULL);
216 }
217 }
218
219 static void si_sampler_view_add_buffer(struct si_context *sctx, struct pipe_resource *resource,
220 enum radeon_bo_usage usage, bool is_stencil_sampler,
221 bool check_mem)
222 {
223 struct si_texture *tex = (struct si_texture *)resource;
224 enum radeon_bo_priority priority;
225
226 if (!resource)
227 return;
228
229 /* Use the flushed depth texture if direct sampling is unsupported. */
230 if (resource->target != PIPE_BUFFER && tex->is_depth &&
231 !si_can_sample_zs(tex, is_stencil_sampler))
232 tex = tex->flushed_depth_texture;
233
234 priority = si_get_sampler_view_priority(&tex->buffer);
235 radeon_add_to_gfx_buffer_list_check_mem(sctx, &tex->buffer, usage, priority, check_mem);
236
237 if (resource->target == PIPE_BUFFER)
238 return;
239
240 /* Add separate DCC. */
241 if (tex->dcc_separate_buffer) {
242 radeon_add_to_gfx_buffer_list_check_mem(sctx, tex->dcc_separate_buffer, usage,
243 RADEON_PRIO_SEPARATE_META, check_mem);
244 }
245 }
246
247 static void si_sampler_views_begin_new_cs(struct si_context *sctx, struct si_samplers *samplers)
248 {
249 unsigned mask = samplers->enabled_mask;
250
251 /* Add buffers to the CS. */
252 while (mask) {
253 int i = u_bit_scan(&mask);
254 struct si_sampler_view *sview = (struct si_sampler_view *)samplers->views[i];
255
256 si_sampler_view_add_buffer(sctx, sview->base.texture, RADEON_USAGE_READ,
257 sview->is_stencil_sampler, false);
258 }
259 }
260
261 static bool si_sampler_views_check_encrypted(struct si_context *sctx, struct si_samplers *samplers,
262 unsigned samplers_declared)
263 {
264 unsigned mask = samplers->enabled_mask & samplers_declared;
265
266 /* Verify if a samplers uses an encrypted resource */
267 while (mask) {
268 int i = u_bit_scan(&mask);
269 struct si_sampler_view *sview = (struct si_sampler_view *)samplers->views[i];
270
271 struct si_resource *res = si_resource(sview->base.texture);
272 if (res->flags & RADEON_FLAG_ENCRYPTED)
273 return true;
274 }
275 return false;
276 }
277
278 /* Set buffer descriptor fields that can be changed by reallocations. */
279 static void si_set_buf_desc_address(struct si_resource *buf, uint64_t offset, uint32_t *state)
280 {
281 uint64_t va = buf->gpu_address + offset;
282
283 state[0] = va;
284 state[1] &= C_008F04_BASE_ADDRESS_HI;
285 state[1] |= S_008F04_BASE_ADDRESS_HI(va >> 32);
286 }
287
288 /* Set texture descriptor fields that can be changed by reallocations.
289 *
290 * \param tex texture
291 * \param base_level_info information of the level of BASE_ADDRESS
292 * \param base_level the level of BASE_ADDRESS
293 * \param first_level pipe_sampler_view.u.tex.first_level
294 * \param block_width util_format_get_blockwidth()
295 * \param is_stencil select between separate Z & Stencil
296 * \param state descriptor to update
297 */
298 void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture *tex,
299 const struct legacy_surf_level *base_level_info,
300 unsigned base_level, unsigned first_level, unsigned block_width,
301 bool is_stencil, bool force_dcc_off, uint32_t *state)
302 {
303 uint64_t va, meta_va = 0;
304
305 if (tex->is_depth && !si_can_sample_zs(tex, is_stencil)) {
306 tex = tex->flushed_depth_texture;
307 is_stencil = false;
308 }
309
310 va = tex->buffer.gpu_address;
311
312 if (sscreen->info.chip_class >= GFX9) {
313 /* Only stencil_offset needs to be added here. */
314 if (is_stencil)
315 va += tex->surface.u.gfx9.stencil_offset;
316 else
317 va += tex->surface.u.gfx9.surf_offset;
318 } else {
319 va += base_level_info->offset;
320 }
321
322 state[0] = va >> 8;
323 state[1] &= C_008F14_BASE_ADDRESS_HI;
324 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
325
326 /* Only macrotiled modes can set tile swizzle.
327 * GFX9 doesn't use (legacy) base_level_info.
328 */
329 if (sscreen->info.chip_class >= GFX9 || base_level_info->mode == RADEON_SURF_MODE_2D)
330 state[0] |= tex->surface.tile_swizzle;
331
332 if (sscreen->info.chip_class >= GFX8) {
333 state[6] &= C_008F28_COMPRESSION_EN;
334
335 if (!force_dcc_off && vi_dcc_enabled(tex, first_level)) {
336 meta_va =
337 (!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) + tex->surface.dcc_offset;
338
339 if (sscreen->info.chip_class == GFX8) {
340 meta_va += base_level_info->dcc_offset;
341 assert(base_level_info->mode == RADEON_SURF_MODE_2D);
342 }
343
344 unsigned dcc_tile_swizzle = tex->surface.tile_swizzle << 8;
345 dcc_tile_swizzle &= tex->surface.dcc_alignment - 1;
346 meta_va |= dcc_tile_swizzle;
347 } else if (vi_tc_compat_htile_enabled(tex, first_level,
348 is_stencil ? PIPE_MASK_S : PIPE_MASK_Z)) {
349 meta_va = tex->buffer.gpu_address + tex->surface.htile_offset;
350 }
351
352 if (meta_va)
353 state[6] |= S_008F28_COMPRESSION_EN(1);
354 }
355
356 if (sscreen->info.chip_class >= GFX8 && sscreen->info.chip_class <= GFX9)
357 state[7] = meta_va >> 8;
358
359 if (sscreen->info.chip_class >= GFX10) {
360 state[3] &= C_00A00C_SW_MODE;
361
362 if (is_stencil) {
363 state[3] |= S_00A00C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
364 } else {
365 state[3] |= S_00A00C_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode);
366 }
367
368 state[6] &= C_00A018_META_DATA_ADDRESS_LO & C_00A018_META_PIPE_ALIGNED;
369
370 if (meta_va) {
371 struct gfx9_surf_meta_flags meta = {
372 .rb_aligned = 1,
373 .pipe_aligned = 1,
374 };
375
376 if (tex->surface.dcc_offset)
377 meta = tex->surface.u.gfx9.dcc;
378
379 state[6] |= S_00A018_META_PIPE_ALIGNED(meta.pipe_aligned) |
380 S_00A018_META_DATA_ADDRESS_LO(meta_va >> 8);
381 }
382
383 state[7] = meta_va >> 16;
384 } else if (sscreen->info.chip_class == GFX9) {
385 state[3] &= C_008F1C_SW_MODE;
386 state[4] &= C_008F20_PITCH;
387
388 if (is_stencil) {
389 state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
390 state[4] |= S_008F20_PITCH(tex->surface.u.gfx9.stencil.epitch);
391 } else {
392 state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode);
393 state[4] |= S_008F20_PITCH(tex->surface.u.gfx9.surf.epitch);
394 }
395
396 state[5] &=
397 C_008F24_META_DATA_ADDRESS & C_008F24_META_PIPE_ALIGNED & C_008F24_META_RB_ALIGNED;
398 if (meta_va) {
399 struct gfx9_surf_meta_flags meta = {
400 .rb_aligned = 1,
401 .pipe_aligned = 1,
402 };
403
404 if (tex->surface.dcc_offset)
405 meta = tex->surface.u.gfx9.dcc;
406
407 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
408 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
409 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
410 }
411 } else {
412 /* GFX6-GFX8 */
413 unsigned pitch = base_level_info->nblk_x * block_width;
414 unsigned index = si_tile_mode_index(tex, base_level, is_stencil);
415
416 state[3] &= C_008F1C_TILING_INDEX;
417 state[3] |= S_008F1C_TILING_INDEX(index);
418 state[4] &= C_008F20_PITCH;
419 state[4] |= S_008F20_PITCH(pitch - 1);
420 }
421 }
422
423 static void si_set_sampler_state_desc(struct si_sampler_state *sstate,
424 struct si_sampler_view *sview, struct si_texture *tex,
425 uint32_t *desc)
426 {
427 if (sview && sview->is_integer)
428 memcpy(desc, sstate->integer_val, 4 * 4);
429 else if (tex && tex->upgraded_depth && (!sview || !sview->is_stencil_sampler))
430 memcpy(desc, sstate->upgraded_depth_val, 4 * 4);
431 else
432 memcpy(desc, sstate->val, 4 * 4);
433 }
434
435 static void si_set_sampler_view_desc(struct si_context *sctx, struct si_sampler_view *sview,
436 struct si_sampler_state *sstate, uint32_t *desc)
437 {
438 struct pipe_sampler_view *view = &sview->base;
439 struct si_texture *tex = (struct si_texture *)view->texture;
440 bool is_buffer = tex->buffer.b.b.target == PIPE_BUFFER;
441
442 if (unlikely(!is_buffer && sview->dcc_incompatible)) {
443 if (vi_dcc_enabled(tex, view->u.tex.first_level))
444 if (!si_texture_disable_dcc(sctx, tex))
445 si_decompress_dcc(sctx, tex);
446
447 sview->dcc_incompatible = false;
448 }
449
450 assert(tex); /* views with texture == NULL aren't supported */
451 memcpy(desc, sview->state, 8 * 4);
452
453 if (is_buffer) {
454 si_set_buf_desc_address(&tex->buffer, sview->base.u.buf.offset, desc + 4);
455 } else {
456 bool is_separate_stencil = tex->db_compatible && sview->is_stencil_sampler;
457
458 si_set_mutable_tex_desc_fields(sctx->screen, tex, sview->base_level_info, sview->base_level,
459 sview->base.u.tex.first_level, sview->block_width,
460 is_separate_stencil, false, desc);
461 }
462
463 if (!is_buffer && tex->surface.fmask_size) {
464 memcpy(desc + 8, sview->fmask_state, 8 * 4);
465 } else {
466 /* Disable FMASK and bind sampler state in [12:15]. */
467 memcpy(desc + 8, null_texture_descriptor, 4 * 4);
468
469 if (sstate)
470 si_set_sampler_state_desc(sstate, sview, is_buffer ? NULL : tex, desc + 12);
471 }
472 }
473
474 static bool color_needs_decompression(struct si_texture *tex)
475 {
476 return tex->surface.fmask_size ||
477 (tex->dirty_level_mask && (tex->cmask_buffer || tex->surface.dcc_offset));
478 }
479
480 static bool depth_needs_decompression(struct si_texture *tex)
481 {
482 /* If the depth/stencil texture is TC-compatible, no decompression
483 * will be done. The decompression function will only flush DB caches
484 * to make it coherent with shaders. That's necessary because the driver
485 * doesn't flush DB caches in any other case.
486 */
487 return tex->db_compatible;
488 }
489
490 static void si_set_sampler_view(struct si_context *sctx, unsigned shader, unsigned slot,
491 struct pipe_sampler_view *view, bool disallow_early_out)
492 {
493 struct si_samplers *samplers = &sctx->samplers[shader];
494 struct si_sampler_view *sview = (struct si_sampler_view *)view;
495 struct si_descriptors *descs = si_sampler_and_image_descriptors(sctx, shader);
496 unsigned desc_slot = si_get_sampler_slot(slot);
497 uint32_t *desc = descs->list + desc_slot * 16;
498
499 if (samplers->views[slot] == view && !disallow_early_out)
500 return;
501
502 if (view) {
503 struct si_texture *tex = (struct si_texture *)view->texture;
504
505 si_set_sampler_view_desc(sctx, sview, samplers->sampler_states[slot], desc);
506
507 if (tex->buffer.b.b.target == PIPE_BUFFER) {
508 tex->buffer.bind_history |= PIPE_BIND_SAMPLER_VIEW;
509 samplers->needs_depth_decompress_mask &= ~(1u << slot);
510 samplers->needs_color_decompress_mask &= ~(1u << slot);
511 } else {
512 if (depth_needs_decompression(tex)) {
513 samplers->needs_depth_decompress_mask |= 1u << slot;
514 } else {
515 samplers->needs_depth_decompress_mask &= ~(1u << slot);
516 }
517 if (color_needs_decompression(tex)) {
518 samplers->needs_color_decompress_mask |= 1u << slot;
519 } else {
520 samplers->needs_color_decompress_mask &= ~(1u << slot);
521 }
522
523 if (vi_dcc_enabled(tex, view->u.tex.first_level) &&
524 p_atomic_read(&tex->framebuffers_bound))
525 sctx->need_check_render_feedback = true;
526 }
527
528 pipe_sampler_view_reference(&samplers->views[slot], view);
529 samplers->enabled_mask |= 1u << slot;
530
531 /* Since this can flush, it must be done after enabled_mask is
532 * updated. */
533 si_sampler_view_add_buffer(sctx, view->texture, RADEON_USAGE_READ, sview->is_stencil_sampler,
534 true);
535 } else {
536 pipe_sampler_view_reference(&samplers->views[slot], NULL);
537 memcpy(desc, null_texture_descriptor, 8 * 4);
538 /* Only clear the lower dwords of FMASK. */
539 memcpy(desc + 8, null_texture_descriptor, 4 * 4);
540 /* Re-set the sampler state if we are transitioning from FMASK. */
541 if (samplers->sampler_states[slot])
542 si_set_sampler_state_desc(samplers->sampler_states[slot], NULL, NULL, desc + 12);
543
544 samplers->enabled_mask &= ~(1u << slot);
545 samplers->needs_depth_decompress_mask &= ~(1u << slot);
546 samplers->needs_color_decompress_mask &= ~(1u << slot);
547 }
548
549 sctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
550 }
551
552 static void si_update_shader_needs_decompress_mask(struct si_context *sctx, unsigned shader)
553 {
554 struct si_samplers *samplers = &sctx->samplers[shader];
555 unsigned shader_bit = 1 << shader;
556
557 if (samplers->needs_depth_decompress_mask || samplers->needs_color_decompress_mask ||
558 sctx->images[shader].needs_color_decompress_mask)
559 sctx->shader_needs_decompress_mask |= shader_bit;
560 else
561 sctx->shader_needs_decompress_mask &= ~shader_bit;
562 }
563
564 static void si_set_sampler_views(struct pipe_context *ctx, enum pipe_shader_type shader,
565 unsigned start, unsigned count, struct pipe_sampler_view **views)
566 {
567 struct si_context *sctx = (struct si_context *)ctx;
568 int i;
569
570 if (!count || shader >= SI_NUM_SHADERS)
571 return;
572
573 if (views) {
574 for (i = 0; i < count; i++)
575 si_set_sampler_view(sctx, shader, start + i, views[i], false);
576 } else {
577 for (i = 0; i < count; i++)
578 si_set_sampler_view(sctx, shader, start + i, NULL, false);
579 }
580
581 si_update_shader_needs_decompress_mask(sctx, shader);
582 }
583
584 static void si_samplers_update_needs_color_decompress_mask(struct si_samplers *samplers)
585 {
586 unsigned mask = samplers->enabled_mask;
587
588 while (mask) {
589 int i = u_bit_scan(&mask);
590 struct pipe_resource *res = samplers->views[i]->texture;
591
592 if (res && res->target != PIPE_BUFFER) {
593 struct si_texture *tex = (struct si_texture *)res;
594
595 if (color_needs_decompression(tex)) {
596 samplers->needs_color_decompress_mask |= 1u << i;
597 } else {
598 samplers->needs_color_decompress_mask &= ~(1u << i);
599 }
600 }
601 }
602 }
603
604 /* IMAGE VIEWS */
605
606 static void si_release_image_views(struct si_images *images)
607 {
608 unsigned i;
609
610 for (i = 0; i < SI_NUM_IMAGES; ++i) {
611 struct pipe_image_view *view = &images->views[i];
612
613 pipe_resource_reference(&view->resource, NULL);
614 }
615 }
616
617 static void si_image_views_begin_new_cs(struct si_context *sctx, struct si_images *images)
618 {
619 uint mask = images->enabled_mask;
620
621 /* Add buffers to the CS. */
622 while (mask) {
623 int i = u_bit_scan(&mask);
624 struct pipe_image_view *view = &images->views[i];
625
626 assert(view->resource);
627
628 si_sampler_view_add_buffer(sctx, view->resource, RADEON_USAGE_READWRITE, false, false);
629 }
630 }
631
632 static bool si_image_views_check_encrypted(struct si_context *sctx, struct si_images *images,
633 unsigned images_declared)
634 {
635 uint mask = images->enabled_mask & images_declared;
636
637 while (mask) {
638 int i = u_bit_scan(&mask);
639 struct pipe_image_view *view = &images->views[i];
640
641 assert(view->resource);
642
643 struct si_texture *tex = (struct si_texture *)view->resource;
644 if (tex->buffer.flags & RADEON_FLAG_ENCRYPTED)
645 return true;
646 }
647 return false;
648 }
649
650 static void si_disable_shader_image(struct si_context *ctx, unsigned shader, unsigned slot)
651 {
652 struct si_images *images = &ctx->images[shader];
653
654 if (images->enabled_mask & (1u << slot)) {
655 struct si_descriptors *descs = si_sampler_and_image_descriptors(ctx, shader);
656 unsigned desc_slot = si_get_image_slot(slot);
657
658 pipe_resource_reference(&images->views[slot].resource, NULL);
659 images->needs_color_decompress_mask &= ~(1 << slot);
660
661 memcpy(descs->list + desc_slot * 8, null_image_descriptor, 8 * 4);
662 images->enabled_mask &= ~(1u << slot);
663 ctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
664 }
665 }
666
667 static void si_mark_image_range_valid(const struct pipe_image_view *view)
668 {
669 struct si_resource *res = si_resource(view->resource);
670
671 if (res->b.b.target != PIPE_BUFFER)
672 return;
673
674 util_range_add(&res->b.b, &res->valid_buffer_range, view->u.buf.offset,
675 view->u.buf.offset + view->u.buf.size);
676 }
677
678 static void si_set_shader_image_desc(struct si_context *ctx, const struct pipe_image_view *view,
679 bool skip_decompress, uint32_t *desc, uint32_t *fmask_desc)
680 {
681 struct si_screen *screen = ctx->screen;
682 struct si_resource *res;
683
684 res = si_resource(view->resource);
685
686 if (res->b.b.target == PIPE_BUFFER || view->shader_access & SI_IMAGE_ACCESS_AS_BUFFER) {
687 if (view->access & PIPE_IMAGE_ACCESS_WRITE)
688 si_mark_image_range_valid(view);
689
690 si_make_buffer_descriptor(screen, res, view->format, view->u.buf.offset, view->u.buf.size,
691 desc);
692 si_set_buf_desc_address(res, view->u.buf.offset, desc + 4);
693 } else {
694 static const unsigned char swizzle[4] = {0, 1, 2, 3};
695 struct si_texture *tex = (struct si_texture *)res;
696 unsigned level = view->u.tex.level;
697 unsigned width, height, depth, hw_level;
698 bool uses_dcc = vi_dcc_enabled(tex, level);
699 unsigned access = view->access;
700
701 assert(!tex->is_depth);
702 assert(fmask_desc || tex->surface.fmask_offset == 0);
703
704 if (uses_dcc && !skip_decompress &&
705 !(access & SI_IMAGE_ACCESS_DCC_OFF) &&
706 (access & PIPE_IMAGE_ACCESS_WRITE ||
707 !vi_dcc_formats_compatible(screen, res->b.b.format, view->format))) {
708 /* If DCC can't be disabled, at least decompress it.
709 * The decompression is relatively cheap if the surface
710 * has been decompressed already.
711 */
712 if (!si_texture_disable_dcc(ctx, tex))
713 si_decompress_dcc(ctx, tex);
714 }
715
716 if (ctx->chip_class >= GFX9) {
717 /* Always set the base address. The swizzle modes don't
718 * allow setting mipmap level offsets as the base.
719 */
720 width = res->b.b.width0;
721 height = res->b.b.height0;
722 depth = res->b.b.depth0;
723 hw_level = level;
724 } else {
725 /* Always force the base level to the selected level.
726 *
727 * This is required for 3D textures, where otherwise
728 * selecting a single slice for non-layered bindings
729 * fails. It doesn't hurt the other targets.
730 */
731 width = u_minify(res->b.b.width0, level);
732 height = u_minify(res->b.b.height0, level);
733 depth = u_minify(res->b.b.depth0, level);
734 hw_level = 0;
735 }
736
737 screen->make_texture_descriptor(
738 screen, tex, false, res->b.b.target, view->format, swizzle, hw_level, hw_level,
739 view->u.tex.first_layer, view->u.tex.last_layer, width, height, depth, desc, fmask_desc);
740 si_set_mutable_tex_desc_fields(screen, tex, &tex->surface.u.legacy.level[level], level, level,
741 util_format_get_blockwidth(view->format), false,
742 view->access & SI_IMAGE_ACCESS_DCC_OFF, desc);
743 }
744 }
745
746 static void si_set_shader_image(struct si_context *ctx, unsigned shader, unsigned slot,
747 const struct pipe_image_view *view, bool skip_decompress)
748 {
749 struct si_images *images = &ctx->images[shader];
750 struct si_descriptors *descs = si_sampler_and_image_descriptors(ctx, shader);
751 struct si_resource *res;
752
753 if (!view || !view->resource) {
754 si_disable_shader_image(ctx, shader, slot);
755 return;
756 }
757
758 res = si_resource(view->resource);
759
760 si_set_shader_image_desc(ctx, view, skip_decompress, descs->list + si_get_image_slot(slot) * 8,
761 descs->list + si_get_image_slot(slot + SI_NUM_IMAGES) * 8);
762
763 if (&images->views[slot] != view)
764 util_copy_image_view(&images->views[slot], view);
765
766 if (res->b.b.target == PIPE_BUFFER || view->shader_access & SI_IMAGE_ACCESS_AS_BUFFER) {
767 images->needs_color_decompress_mask &= ~(1 << slot);
768 res->bind_history |= PIPE_BIND_SHADER_IMAGE;
769 } else {
770 struct si_texture *tex = (struct si_texture *)res;
771 unsigned level = view->u.tex.level;
772
773 if (color_needs_decompression(tex)) {
774 images->needs_color_decompress_mask |= 1 << slot;
775 } else {
776 images->needs_color_decompress_mask &= ~(1 << slot);
777 }
778
779 if (vi_dcc_enabled(tex, level) && p_atomic_read(&tex->framebuffers_bound))
780 ctx->need_check_render_feedback = true;
781 }
782
783 images->enabled_mask |= 1u << slot;
784 ctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
785
786 /* Since this can flush, it must be done after enabled_mask is updated. */
787 si_sampler_view_add_buffer(
788 ctx, &res->b.b,
789 (view->access & PIPE_IMAGE_ACCESS_WRITE) ? RADEON_USAGE_READWRITE : RADEON_USAGE_READ, false,
790 true);
791 }
792
793 static void si_set_shader_images(struct pipe_context *pipe, enum pipe_shader_type shader,
794 unsigned start_slot, unsigned count,
795 const struct pipe_image_view *views)
796 {
797 struct si_context *ctx = (struct si_context *)pipe;
798 unsigned i, slot;
799
800 assert(shader < SI_NUM_SHADERS);
801
802 if (!count)
803 return;
804
805 assert(start_slot + count <= SI_NUM_IMAGES);
806
807 if (views) {
808 for (i = 0, slot = start_slot; i < count; ++i, ++slot)
809 si_set_shader_image(ctx, shader, slot, &views[i], false);
810 } else {
811 for (i = 0, slot = start_slot; i < count; ++i, ++slot)
812 si_set_shader_image(ctx, shader, slot, NULL, false);
813 }
814
815 si_update_shader_needs_decompress_mask(ctx, shader);
816 }
817
818 static void si_images_update_needs_color_decompress_mask(struct si_images *images)
819 {
820 unsigned mask = images->enabled_mask;
821
822 while (mask) {
823 int i = u_bit_scan(&mask);
824 struct pipe_resource *res = images->views[i].resource;
825
826 if (res && res->target != PIPE_BUFFER) {
827 struct si_texture *tex = (struct si_texture *)res;
828
829 if (color_needs_decompression(tex)) {
830 images->needs_color_decompress_mask |= 1 << i;
831 } else {
832 images->needs_color_decompress_mask &= ~(1 << i);
833 }
834 }
835 }
836 }
837
838 void si_update_ps_colorbuf0_slot(struct si_context *sctx)
839 {
840 struct si_buffer_resources *buffers = &sctx->rw_buffers;
841 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
842 unsigned slot = SI_PS_IMAGE_COLORBUF0;
843 struct pipe_surface *surf = NULL;
844
845 /* si_texture_disable_dcc can get us here again. */
846 if (sctx->blitter->running)
847 return;
848
849 /* See whether FBFETCH is used and color buffer 0 is set. */
850 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_fbfetch &&
851 sctx->framebuffer.state.nr_cbufs && sctx->framebuffer.state.cbufs[0])
852 surf = sctx->framebuffer.state.cbufs[0];
853
854 /* Return if FBFETCH transitions from disabled to disabled. */
855 if (!buffers->buffers[slot] && !surf)
856 return;
857
858 sctx->ps_uses_fbfetch = surf != NULL;
859 si_update_ps_iter_samples(sctx);
860
861 if (surf) {
862 struct si_texture *tex = (struct si_texture *)surf->texture;
863 struct pipe_image_view view = {0};
864
865 assert(tex);
866 assert(!tex->is_depth);
867
868 /* Disable DCC, because the texture is used as both a sampler
869 * and color buffer.
870 */
871 si_texture_disable_dcc(sctx, tex);
872
873 if (tex->buffer.b.b.nr_samples <= 1 && tex->cmask_buffer) {
874 /* Disable CMASK. */
875 assert(tex->cmask_buffer != &tex->buffer);
876 si_eliminate_fast_color_clear(sctx, tex, NULL);
877 si_texture_discard_cmask(sctx->screen, tex);
878 }
879
880 view.resource = surf->texture;
881 view.format = surf->format;
882 view.access = PIPE_IMAGE_ACCESS_READ;
883 view.u.tex.first_layer = surf->u.tex.first_layer;
884 view.u.tex.last_layer = surf->u.tex.last_layer;
885 view.u.tex.level = surf->u.tex.level;
886
887 /* Set the descriptor. */
888 uint32_t *desc = descs->list + slot * 4;
889 memset(desc, 0, 16 * 4);
890 si_set_shader_image_desc(sctx, &view, true, desc, desc + 8);
891
892 pipe_resource_reference(&buffers->buffers[slot], &tex->buffer.b.b);
893 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READ,
894 RADEON_PRIO_SHADER_RW_IMAGE);
895 buffers->enabled_mask |= 1u << slot;
896 } else {
897 /* Clear the descriptor. */
898 memset(descs->list + slot * 4, 0, 8 * 4);
899 pipe_resource_reference(&buffers->buffers[slot], NULL);
900 buffers->enabled_mask &= ~(1u << slot);
901 }
902
903 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
904 }
905
906 /* SAMPLER STATES */
907
908 static void si_bind_sampler_states(struct pipe_context *ctx, enum pipe_shader_type shader,
909 unsigned start, unsigned count, void **states)
910 {
911 struct si_context *sctx = (struct si_context *)ctx;
912 struct si_samplers *samplers = &sctx->samplers[shader];
913 struct si_descriptors *desc = si_sampler_and_image_descriptors(sctx, shader);
914 struct si_sampler_state **sstates = (struct si_sampler_state **)states;
915 int i;
916
917 if (!count || shader >= SI_NUM_SHADERS || !sstates)
918 return;
919
920 for (i = 0; i < count; i++) {
921 unsigned slot = start + i;
922 unsigned desc_slot = si_get_sampler_slot(slot);
923
924 if (!sstates[i] || sstates[i] == samplers->sampler_states[slot])
925 continue;
926
927 #ifndef NDEBUG
928 assert(sstates[i]->magic == SI_SAMPLER_STATE_MAGIC);
929 #endif
930 samplers->sampler_states[slot] = sstates[i];
931
932 /* If FMASK is bound, don't overwrite it.
933 * The sampler state will be set after FMASK is unbound.
934 */
935 struct si_sampler_view *sview = (struct si_sampler_view *)samplers->views[slot];
936
937 struct si_texture *tex = NULL;
938
939 if (sview && sview->base.texture && sview->base.texture->target != PIPE_BUFFER)
940 tex = (struct si_texture *)sview->base.texture;
941
942 if (tex && tex->surface.fmask_size)
943 continue;
944
945 si_set_sampler_state_desc(sstates[i], sview, tex, desc->list + desc_slot * 16 + 12);
946
947 sctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
948 }
949 }
950
951 /* BUFFER RESOURCES */
952
953 static void si_init_buffer_resources(struct si_buffer_resources *buffers,
954 struct si_descriptors *descs, unsigned num_buffers,
955 short shader_userdata_rel_index,
956 enum radeon_bo_priority priority,
957 enum radeon_bo_priority priority_constbuf)
958 {
959 buffers->priority = priority;
960 buffers->priority_constbuf = priority_constbuf;
961 buffers->buffers = CALLOC(num_buffers, sizeof(struct pipe_resource *));
962 buffers->offsets = CALLOC(num_buffers, sizeof(buffers->offsets[0]));
963
964 si_init_descriptors(descs, shader_userdata_rel_index, 4, num_buffers);
965 }
966
967 static void si_release_buffer_resources(struct si_buffer_resources *buffers,
968 struct si_descriptors *descs)
969 {
970 int i;
971
972 for (i = 0; i < descs->num_elements; i++) {
973 pipe_resource_reference(&buffers->buffers[i], NULL);
974 }
975
976 FREE(buffers->buffers);
977 FREE(buffers->offsets);
978 }
979
980 static void si_buffer_resources_begin_new_cs(struct si_context *sctx,
981 struct si_buffer_resources *buffers)
982 {
983 unsigned mask = buffers->enabled_mask;
984
985 /* Add buffers to the CS. */
986 while (mask) {
987 int i = u_bit_scan(&mask);
988
989 radeon_add_to_buffer_list(
990 sctx, sctx->gfx_cs, si_resource(buffers->buffers[i]),
991 buffers->writable_mask & (1u << i) ? RADEON_USAGE_READWRITE : RADEON_USAGE_READ,
992 i < SI_NUM_SHADER_BUFFERS ? buffers->priority : buffers->priority_constbuf);
993 }
994 }
995
996 static bool si_buffer_resources_check_encrypted(struct si_context *sctx,
997 struct si_buffer_resources *buffers)
998 {
999 unsigned mask = buffers->enabled_mask;
1000
1001 while (mask) {
1002 int i = u_bit_scan(&mask);
1003
1004 /* only check for reads */
1005 if ((buffers->writable_mask & (1u << i)) == 0 &&
1006 (si_resource(buffers->buffers[i])->flags & RADEON_FLAG_ENCRYPTED))
1007 return true;
1008 }
1009
1010 return false;
1011 }
1012
1013 static void si_get_buffer_from_descriptors(struct si_buffer_resources *buffers,
1014 struct si_descriptors *descs, unsigned idx,
1015 struct pipe_resource **buf, unsigned *offset,
1016 unsigned *size)
1017 {
1018 pipe_resource_reference(buf, buffers->buffers[idx]);
1019 if (*buf) {
1020 struct si_resource *res = si_resource(*buf);
1021 const uint32_t *desc = descs->list + idx * 4;
1022 uint64_t va;
1023
1024 *size = desc[2];
1025
1026 assert(G_008F04_STRIDE(desc[1]) == 0);
1027 va = si_desc_extract_buffer_address(desc);
1028
1029 assert(va >= res->gpu_address && va + *size <= res->gpu_address + res->bo_size);
1030 *offset = va - res->gpu_address;
1031 }
1032 }
1033
1034 /* VERTEX BUFFERS */
1035
1036 static void si_vertex_buffers_begin_new_cs(struct si_context *sctx)
1037 {
1038 int count = sctx->num_vertex_elements;
1039 int i;
1040
1041 for (i = 0; i < count; i++) {
1042 int vb = sctx->vertex_elements->vertex_buffer_index[i];
1043
1044 if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
1045 continue;
1046 if (!sctx->vertex_buffer[vb].buffer.resource)
1047 continue;
1048
1049 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
1050 si_resource(sctx->vertex_buffer[vb].buffer.resource),
1051 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
1052 }
1053
1054 if (!sctx->vb_descriptors_buffer)
1055 return;
1056 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, sctx->vb_descriptors_buffer, RADEON_USAGE_READ,
1057 RADEON_PRIO_DESCRIPTORS);
1058 }
1059
1060 bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
1061 {
1062 unsigned i, count = sctx->num_vertex_elements;
1063 uint32_t *ptr;
1064
1065 if (!sctx->vertex_buffers_dirty || !count)
1066 return true;
1067
1068 struct si_vertex_elements *velems = sctx->vertex_elements;
1069 unsigned alloc_size = velems->vb_desc_list_alloc_size;
1070
1071 if (alloc_size) {
1072 /* Vertex buffer descriptors are the only ones which are uploaded
1073 * directly through a staging buffer and don't go through
1074 * the fine-grained upload path.
1075 */
1076 u_upload_alloc(sctx->b.const_uploader, 0, alloc_size,
1077 si_optimal_tcc_alignment(sctx, alloc_size), &sctx->vb_descriptors_offset,
1078 (struct pipe_resource **)&sctx->vb_descriptors_buffer, (void **)&ptr);
1079 if (!sctx->vb_descriptors_buffer) {
1080 sctx->vb_descriptors_offset = 0;
1081 sctx->vb_descriptors_gpu_list = NULL;
1082 return false;
1083 }
1084
1085 sctx->vb_descriptors_gpu_list = ptr;
1086 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, sctx->vb_descriptors_buffer, RADEON_USAGE_READ,
1087 RADEON_PRIO_DESCRIPTORS);
1088 sctx->vertex_buffer_pointer_dirty = true;
1089 sctx->prefetch_L2_mask |= SI_PREFETCH_VBO_DESCRIPTORS;
1090 } else {
1091 si_resource_reference(&sctx->vb_descriptors_buffer, NULL);
1092 sctx->vertex_buffer_pointer_dirty = false;
1093 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VBO_DESCRIPTORS;
1094 }
1095
1096 assert(count <= SI_MAX_ATTRIBS);
1097
1098 unsigned first_vb_use_mask = velems->first_vb_use_mask;
1099 unsigned num_vbos_in_user_sgprs = sctx->screen->num_vbos_in_user_sgprs;
1100
1101 for (i = 0; i < count; i++) {
1102 struct pipe_vertex_buffer *vb;
1103 struct si_resource *buf;
1104 unsigned vbo_index = velems->vertex_buffer_index[i];
1105 uint32_t *desc = i < num_vbos_in_user_sgprs ? &sctx->vb_descriptor_user_sgprs[i * 4]
1106 : &ptr[(i - num_vbos_in_user_sgprs) * 4];
1107
1108 vb = &sctx->vertex_buffer[vbo_index];
1109 buf = si_resource(vb->buffer.resource);
1110 if (!buf) {
1111 memset(desc, 0, 16);
1112 continue;
1113 }
1114
1115 int64_t offset = (int64_t)((int)vb->buffer_offset) + velems->src_offset[i];
1116
1117 if (offset >= buf->b.b.width0) {
1118 assert(offset < buf->b.b.width0);
1119 memset(desc, 0, 16);
1120 continue;
1121 }
1122
1123 uint64_t va = buf->gpu_address + offset;
1124
1125 int64_t num_records = (int64_t)buf->b.b.width0 - offset;
1126 if (sctx->chip_class != GFX8 && vb->stride) {
1127 /* Round up by rounding down and adding 1 */
1128 num_records = (num_records - velems->format_size[i]) / vb->stride + 1;
1129 }
1130 assert(num_records >= 0 && num_records <= UINT_MAX);
1131
1132 uint32_t rsrc_word3 = velems->rsrc_word3[i];
1133
1134 /* OOB_SELECT chooses the out-of-bounds check:
1135 * - 1: index >= NUM_RECORDS (Structured)
1136 * - 3: offset >= NUM_RECORDS (Raw)
1137 */
1138 if (sctx->chip_class >= GFX10)
1139 rsrc_word3 |= S_008F0C_OOB_SELECT(vb->stride ? V_008F0C_OOB_SELECT_STRUCTURED
1140 : V_008F0C_OOB_SELECT_RAW);
1141
1142 desc[0] = va;
1143 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(vb->stride);
1144 desc[2] = num_records;
1145 desc[3] = rsrc_word3;
1146
1147 if (first_vb_use_mask & (1 << i)) {
1148 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, si_resource(vb->buffer.resource),
1149 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
1150 }
1151 }
1152
1153 /* Don't flush the const cache. It would have a very negative effect
1154 * on performance (confirmed by testing). New descriptors are always
1155 * uploaded to a fresh new buffer, so I don't think flushing the const
1156 * cache is needed. */
1157 si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
1158 sctx->vertex_buffer_user_sgprs_dirty = num_vbos_in_user_sgprs > 0;
1159 sctx->vertex_buffers_dirty = false;
1160 return true;
1161 }
1162
1163 /* CONSTANT BUFFERS */
1164
1165 static struct si_descriptors *si_const_and_shader_buffer_descriptors(struct si_context *sctx,
1166 unsigned shader)
1167 {
1168 return &sctx->descriptors[si_const_and_shader_buffer_descriptors_idx(shader)];
1169 }
1170
1171 void si_upload_const_buffer(struct si_context *sctx, struct si_resource **buf, const uint8_t *ptr,
1172 unsigned size, uint32_t *const_offset)
1173 {
1174 void *tmp;
1175
1176 u_upload_alloc(sctx->b.const_uploader, 0, size, si_optimal_tcc_alignment(sctx, size),
1177 const_offset, (struct pipe_resource **)buf, &tmp);
1178 if (*buf)
1179 util_memcpy_cpu_to_le32(tmp, ptr, size);
1180 }
1181
1182 static void si_set_constant_buffer(struct si_context *sctx, struct si_buffer_resources *buffers,
1183 unsigned descriptors_idx, uint slot,
1184 const struct pipe_constant_buffer *input)
1185 {
1186 struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
1187 assert(slot < descs->num_elements);
1188 pipe_resource_reference(&buffers->buffers[slot], NULL);
1189
1190 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1191 * with a NULL buffer). We need to use a dummy buffer instead. */
1192 if (sctx->chip_class == GFX7 && (!input || (!input->buffer && !input->user_buffer)))
1193 input = &sctx->null_const_buf;
1194
1195 if (input && (input->buffer || input->user_buffer)) {
1196 struct pipe_resource *buffer = NULL;
1197 uint64_t va;
1198 unsigned buffer_offset;
1199
1200 /* Upload the user buffer if needed. */
1201 if (input->user_buffer) {
1202 si_upload_const_buffer(sctx, (struct si_resource **)&buffer, input->user_buffer,
1203 input->buffer_size, &buffer_offset);
1204 if (!buffer) {
1205 /* Just unbind on failure. */
1206 si_set_constant_buffer(sctx, buffers, descriptors_idx, slot, NULL);
1207 return;
1208 }
1209 } else {
1210 pipe_resource_reference(&buffer, input->buffer);
1211 buffer_offset = input->buffer_offset;
1212 }
1213
1214 va = si_resource(buffer)->gpu_address + buffer_offset;
1215
1216 /* Set the descriptor. */
1217 uint32_t *desc = descs->list + slot * 4;
1218 desc[0] = va;
1219 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(0);
1220 desc[2] = input->buffer_size;
1221 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1222 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
1223
1224 if (sctx->chip_class >= GFX10) {
1225 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
1226 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | S_008F0C_RESOURCE_LEVEL(1);
1227 } else {
1228 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1229 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1230 }
1231
1232 buffers->buffers[slot] = buffer;
1233 buffers->offsets[slot] = buffer_offset;
1234 radeon_add_to_gfx_buffer_list_check_mem(sctx, si_resource(buffer), RADEON_USAGE_READ,
1235 buffers->priority_constbuf, true);
1236 buffers->enabled_mask |= 1u << slot;
1237 } else {
1238 /* Clear the descriptor. */
1239 memset(descs->list + slot * 4, 0, sizeof(uint32_t) * 4);
1240 buffers->enabled_mask &= ~(1u << slot);
1241 }
1242
1243 sctx->descriptors_dirty |= 1u << descriptors_idx;
1244 }
1245
1246 static void si_pipe_set_constant_buffer(struct pipe_context *ctx, enum pipe_shader_type shader,
1247 uint slot, const struct pipe_constant_buffer *input)
1248 {
1249 struct si_context *sctx = (struct si_context *)ctx;
1250
1251 if (shader >= SI_NUM_SHADERS)
1252 return;
1253
1254 if (slot == 0 && input && input->buffer &&
1255 !(si_resource(input->buffer)->flags & RADEON_FLAG_32BIT)) {
1256 assert(!"constant buffer 0 must have a 32-bit VM address, use const_uploader");
1257 return;
1258 }
1259
1260 if (input && input->buffer)
1261 si_resource(input->buffer)->bind_history |= PIPE_BIND_CONSTANT_BUFFER;
1262
1263 slot = si_get_constbuf_slot(slot);
1264 si_set_constant_buffer(sctx, &sctx->const_and_shader_buffers[shader],
1265 si_const_and_shader_buffer_descriptors_idx(shader), slot, input);
1266 }
1267
1268 void si_get_pipe_constant_buffer(struct si_context *sctx, uint shader, uint slot,
1269 struct pipe_constant_buffer *cbuf)
1270 {
1271 cbuf->user_buffer = NULL;
1272 si_get_buffer_from_descriptors(
1273 &sctx->const_and_shader_buffers[shader], si_const_and_shader_buffer_descriptors(sctx, shader),
1274 si_get_constbuf_slot(slot), &cbuf->buffer, &cbuf->buffer_offset, &cbuf->buffer_size);
1275 }
1276
1277 /* SHADER BUFFERS */
1278
1279 static void si_set_shader_buffer(struct si_context *sctx, struct si_buffer_resources *buffers,
1280 unsigned descriptors_idx, uint slot,
1281 const struct pipe_shader_buffer *sbuffer, bool writable,
1282 enum radeon_bo_priority priority)
1283 {
1284 struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
1285 uint32_t *desc = descs->list + slot * 4;
1286
1287 if (!sbuffer || !sbuffer->buffer) {
1288 pipe_resource_reference(&buffers->buffers[slot], NULL);
1289 memset(desc, 0, sizeof(uint32_t) * 4);
1290 buffers->enabled_mask &= ~(1u << slot);
1291 buffers->writable_mask &= ~(1u << slot);
1292 sctx->descriptors_dirty |= 1u << descriptors_idx;
1293 return;
1294 }
1295
1296 struct si_resource *buf = si_resource(sbuffer->buffer);
1297 uint64_t va = buf->gpu_address + sbuffer->buffer_offset;
1298
1299 desc[0] = va;
1300 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(0);
1301 desc[2] = sbuffer->buffer_size;
1302 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1303 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
1304
1305 if (sctx->chip_class >= GFX10) {
1306 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
1307 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | S_008F0C_RESOURCE_LEVEL(1);
1308 } else {
1309 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1310 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1311 }
1312
1313 pipe_resource_reference(&buffers->buffers[slot], &buf->b.b);
1314 buffers->offsets[slot] = sbuffer->buffer_offset;
1315 radeon_add_to_gfx_buffer_list_check_mem(
1316 sctx, buf, writable ? RADEON_USAGE_READWRITE : RADEON_USAGE_READ, priority, true);
1317 if (writable)
1318 buffers->writable_mask |= 1u << slot;
1319 else
1320 buffers->writable_mask &= ~(1u << slot);
1321
1322 buffers->enabled_mask |= 1u << slot;
1323 sctx->descriptors_dirty |= 1u << descriptors_idx;
1324
1325 util_range_add(&buf->b.b, &buf->valid_buffer_range, sbuffer->buffer_offset,
1326 sbuffer->buffer_offset + sbuffer->buffer_size);
1327 }
1328
1329 static void si_set_shader_buffers(struct pipe_context *ctx, enum pipe_shader_type shader,
1330 unsigned start_slot, unsigned count,
1331 const struct pipe_shader_buffer *sbuffers,
1332 unsigned writable_bitmask)
1333 {
1334 struct si_context *sctx = (struct si_context *)ctx;
1335 struct si_buffer_resources *buffers = &sctx->const_and_shader_buffers[shader];
1336 unsigned descriptors_idx = si_const_and_shader_buffer_descriptors_idx(shader);
1337 unsigned i;
1338
1339 assert(start_slot + count <= SI_NUM_SHADER_BUFFERS);
1340
1341 for (i = 0; i < count; ++i) {
1342 const struct pipe_shader_buffer *sbuffer = sbuffers ? &sbuffers[i] : NULL;
1343 unsigned slot = si_get_shaderbuf_slot(start_slot + i);
1344
1345 if (sbuffer && sbuffer->buffer)
1346 si_resource(sbuffer->buffer)->bind_history |= PIPE_BIND_SHADER_BUFFER;
1347
1348 si_set_shader_buffer(sctx, buffers, descriptors_idx, slot, sbuffer,
1349 !!(writable_bitmask & (1u << i)), buffers->priority);
1350 }
1351 }
1352
1353 void si_get_shader_buffers(struct si_context *sctx, enum pipe_shader_type shader, uint start_slot,
1354 uint count, struct pipe_shader_buffer *sbuf)
1355 {
1356 struct si_buffer_resources *buffers = &sctx->const_and_shader_buffers[shader];
1357 struct si_descriptors *descs = si_const_and_shader_buffer_descriptors(sctx, shader);
1358
1359 for (unsigned i = 0; i < count; ++i) {
1360 si_get_buffer_from_descriptors(buffers, descs, si_get_shaderbuf_slot(start_slot + i),
1361 &sbuf[i].buffer, &sbuf[i].buffer_offset, &sbuf[i].buffer_size);
1362 }
1363 }
1364
1365 /* RING BUFFERS */
1366
1367 void si_set_rw_buffer(struct si_context *sctx, uint slot, const struct pipe_constant_buffer *input)
1368 {
1369 si_set_constant_buffer(sctx, &sctx->rw_buffers, SI_DESCS_RW_BUFFERS, slot, input);
1370 }
1371
1372 void si_set_rw_shader_buffer(struct si_context *sctx, uint slot,
1373 const struct pipe_shader_buffer *sbuffer)
1374 {
1375 si_set_shader_buffer(sctx, &sctx->rw_buffers, SI_DESCS_RW_BUFFERS, slot, sbuffer, true,
1376 RADEON_PRIO_SHADER_RW_BUFFER);
1377 }
1378
1379 void si_set_ring_buffer(struct si_context *sctx, uint slot, struct pipe_resource *buffer,
1380 unsigned stride, unsigned num_records, bool add_tid, bool swizzle,
1381 unsigned element_size, unsigned index_stride, uint64_t offset)
1382 {
1383 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1384 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1385
1386 /* The stride field in the resource descriptor has 14 bits */
1387 assert(stride < (1 << 14));
1388
1389 assert(slot < descs->num_elements);
1390 pipe_resource_reference(&buffers->buffers[slot], NULL);
1391
1392 if (buffer) {
1393 uint64_t va;
1394
1395 va = si_resource(buffer)->gpu_address + offset;
1396
1397 switch (element_size) {
1398 default:
1399 assert(!"Unsupported ring buffer element size");
1400 case 0:
1401 case 2:
1402 element_size = 0;
1403 break;
1404 case 4:
1405 element_size = 1;
1406 break;
1407 case 8:
1408 element_size = 2;
1409 break;
1410 case 16:
1411 element_size = 3;
1412 break;
1413 }
1414
1415 switch (index_stride) {
1416 default:
1417 assert(!"Unsupported ring buffer index stride");
1418 case 0:
1419 case 8:
1420 index_stride = 0;
1421 break;
1422 case 16:
1423 index_stride = 1;
1424 break;
1425 case 32:
1426 index_stride = 2;
1427 break;
1428 case 64:
1429 index_stride = 3;
1430 break;
1431 }
1432
1433 if (sctx->chip_class >= GFX8 && stride)
1434 num_records *= stride;
1435
1436 /* Set the descriptor. */
1437 uint32_t *desc = descs->list + slot * 4;
1438 desc[0] = va;
1439 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride) |
1440 S_008F04_SWIZZLE_ENABLE(swizzle);
1441 desc[2] = num_records;
1442 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1443 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1444 S_008F0C_INDEX_STRIDE(index_stride) | S_008F0C_ADD_TID_ENABLE(add_tid);
1445
1446 if (sctx->chip_class >= GFX9)
1447 assert(!swizzle || element_size == 1); /* always 4 bytes on GFX9 */
1448 else
1449 desc[3] |= S_008F0C_ELEMENT_SIZE(element_size);
1450
1451 if (sctx->chip_class >= GFX10) {
1452 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
1453 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) | S_008F0C_RESOURCE_LEVEL(1);
1454 } else {
1455 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1456 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1457 }
1458
1459 pipe_resource_reference(&buffers->buffers[slot], buffer);
1460 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, si_resource(buffer), RADEON_USAGE_READWRITE,
1461 buffers->priority);
1462 buffers->enabled_mask |= 1u << slot;
1463 } else {
1464 /* Clear the descriptor. */
1465 memset(descs->list + slot * 4, 0, sizeof(uint32_t) * 4);
1466 buffers->enabled_mask &= ~(1u << slot);
1467 }
1468
1469 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
1470 }
1471
1472 /* INTERNAL CONST BUFFERS */
1473
1474 static void si_set_polygon_stipple(struct pipe_context *ctx, const struct pipe_poly_stipple *state)
1475 {
1476 struct si_context *sctx = (struct si_context *)ctx;
1477 struct pipe_constant_buffer cb = {};
1478 unsigned stipple[32];
1479 int i;
1480
1481 for (i = 0; i < 32; i++)
1482 stipple[i] = util_bitreverse(state->stipple[i]);
1483
1484 cb.user_buffer = stipple;
1485 cb.buffer_size = sizeof(stipple);
1486
1487 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE, &cb);
1488 }
1489
1490 /* TEXTURE METADATA ENABLE/DISABLE */
1491
1492 static void si_resident_handles_update_needs_color_decompress(struct si_context *sctx)
1493 {
1494 util_dynarray_clear(&sctx->resident_tex_needs_color_decompress);
1495 util_dynarray_clear(&sctx->resident_img_needs_color_decompress);
1496
1497 util_dynarray_foreach (&sctx->resident_tex_handles, struct si_texture_handle *, tex_handle) {
1498 struct pipe_resource *res = (*tex_handle)->view->texture;
1499 struct si_texture *tex;
1500
1501 if (!res || res->target == PIPE_BUFFER)
1502 continue;
1503
1504 tex = (struct si_texture *)res;
1505 if (!color_needs_decompression(tex))
1506 continue;
1507
1508 util_dynarray_append(&sctx->resident_tex_needs_color_decompress, struct si_texture_handle *,
1509 *tex_handle);
1510 }
1511
1512 util_dynarray_foreach (&sctx->resident_img_handles, struct si_image_handle *, img_handle) {
1513 struct pipe_image_view *view = &(*img_handle)->view;
1514 struct pipe_resource *res = view->resource;
1515 struct si_texture *tex;
1516
1517 if (!res || res->target == PIPE_BUFFER)
1518 continue;
1519
1520 tex = (struct si_texture *)res;
1521 if (!color_needs_decompression(tex))
1522 continue;
1523
1524 util_dynarray_append(&sctx->resident_img_needs_color_decompress, struct si_image_handle *,
1525 *img_handle);
1526 }
1527 }
1528
1529 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1530 * while the texture is bound, possibly by a different context. In that case,
1531 * call this function to update needs_*_decompress_masks.
1532 */
1533 void si_update_needs_color_decompress_masks(struct si_context *sctx)
1534 {
1535 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
1536 si_samplers_update_needs_color_decompress_mask(&sctx->samplers[i]);
1537 si_images_update_needs_color_decompress_mask(&sctx->images[i]);
1538 si_update_shader_needs_decompress_mask(sctx, i);
1539 }
1540
1541 si_resident_handles_update_needs_color_decompress(sctx);
1542 }
1543
1544 /* BUFFER DISCARD/INVALIDATION */
1545
1546 /* Reset descriptors of buffer resources after \p buf has been invalidated.
1547 * If buf == NULL, reset all descriptors.
1548 */
1549 static void si_reset_buffer_resources(struct si_context *sctx, struct si_buffer_resources *buffers,
1550 unsigned descriptors_idx, unsigned slot_mask,
1551 struct pipe_resource *buf, enum radeon_bo_priority priority)
1552 {
1553 struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
1554 unsigned mask = buffers->enabled_mask & slot_mask;
1555
1556 while (mask) {
1557 unsigned i = u_bit_scan(&mask);
1558 struct pipe_resource *buffer = buffers->buffers[i];
1559
1560 if (buffer && (!buf || buffer == buf)) {
1561 si_set_buf_desc_address(si_resource(buffer), buffers->offsets[i], descs->list + i * 4);
1562 sctx->descriptors_dirty |= 1u << descriptors_idx;
1563
1564 radeon_add_to_gfx_buffer_list_check_mem(
1565 sctx, si_resource(buffer),
1566 buffers->writable_mask & (1u << i) ? RADEON_USAGE_READWRITE : RADEON_USAGE_READ,
1567 priority, true);
1568 }
1569 }
1570 }
1571
1572 /* Update all buffer bindings where the buffer is bound, including
1573 * all resource descriptors. This is invalidate_buffer without
1574 * the invalidation.
1575 *
1576 * If buf == NULL, update all buffer bindings.
1577 */
1578 void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf)
1579 {
1580 struct si_resource *buffer = si_resource(buf);
1581 unsigned i, shader;
1582 unsigned num_elems = sctx->num_vertex_elements;
1583
1584 /* We changed the buffer, now we need to bind it where the old one
1585 * was bound. This consists of 2 things:
1586 * 1) Updating the resource descriptor and dirtying it.
1587 * 2) Adding a relocation to the CS, so that it's usable.
1588 */
1589
1590 /* Vertex buffers. */
1591 if (!buffer) {
1592 if (num_elems)
1593 sctx->vertex_buffers_dirty = true;
1594 } else if (buffer->bind_history & PIPE_BIND_VERTEX_BUFFER) {
1595 for (i = 0; i < num_elems; i++) {
1596 int vb = sctx->vertex_elements->vertex_buffer_index[i];
1597
1598 if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
1599 continue;
1600 if (!sctx->vertex_buffer[vb].buffer.resource)
1601 continue;
1602
1603 if (sctx->vertex_buffer[vb].buffer.resource == buf) {
1604 sctx->vertex_buffers_dirty = true;
1605 break;
1606 }
1607 }
1608 }
1609
1610 /* Streamout buffers. (other internal buffers can't be invalidated) */
1611 if (!buffer || buffer->bind_history & PIPE_BIND_STREAM_OUTPUT) {
1612 for (i = SI_VS_STREAMOUT_BUF0; i <= SI_VS_STREAMOUT_BUF3; i++) {
1613 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1614 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1615 struct pipe_resource *buffer = buffers->buffers[i];
1616
1617 if (!buffer || (buf && buffer != buf))
1618 continue;
1619
1620 si_set_buf_desc_address(si_resource(buffer), buffers->offsets[i], descs->list + i * 4);
1621 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
1622
1623 radeon_add_to_gfx_buffer_list_check_mem(sctx, si_resource(buffer), RADEON_USAGE_WRITE,
1624 RADEON_PRIO_SHADER_RW_BUFFER, true);
1625
1626 /* Update the streamout state. */
1627 if (sctx->streamout.begin_emitted)
1628 si_emit_streamout_end(sctx);
1629 sctx->streamout.append_bitmask = sctx->streamout.enabled_mask;
1630 si_streamout_buffers_dirty(sctx);
1631 }
1632 }
1633
1634 /* Constant and shader buffers. */
1635 if (!buffer || buffer->bind_history & PIPE_BIND_CONSTANT_BUFFER) {
1636 for (shader = 0; shader < SI_NUM_SHADERS; shader++)
1637 si_reset_buffer_resources(sctx, &sctx->const_and_shader_buffers[shader],
1638 si_const_and_shader_buffer_descriptors_idx(shader),
1639 u_bit_consecutive(SI_NUM_SHADER_BUFFERS, SI_NUM_CONST_BUFFERS),
1640 buf, sctx->const_and_shader_buffers[shader].priority_constbuf);
1641 }
1642
1643 if (!buffer || buffer->bind_history & PIPE_BIND_SHADER_BUFFER) {
1644 for (shader = 0; shader < SI_NUM_SHADERS; shader++)
1645 si_reset_buffer_resources(sctx, &sctx->const_and_shader_buffers[shader],
1646 si_const_and_shader_buffer_descriptors_idx(shader),
1647 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS), buf,
1648 sctx->const_and_shader_buffers[shader].priority);
1649 }
1650
1651 if (!buffer || buffer->bind_history & PIPE_BIND_SAMPLER_VIEW) {
1652 /* Texture buffers - update bindings. */
1653 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1654 struct si_samplers *samplers = &sctx->samplers[shader];
1655 struct si_descriptors *descs = si_sampler_and_image_descriptors(sctx, shader);
1656 unsigned mask = samplers->enabled_mask;
1657
1658 while (mask) {
1659 unsigned i = u_bit_scan(&mask);
1660 struct pipe_resource *buffer = samplers->views[i]->texture;
1661
1662 if (buffer && buffer->target == PIPE_BUFFER && (!buf || buffer == buf)) {
1663 unsigned desc_slot = si_get_sampler_slot(i);
1664
1665 si_set_buf_desc_address(si_resource(buffer), samplers->views[i]->u.buf.offset,
1666 descs->list + desc_slot * 16 + 4);
1667 sctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
1668
1669 radeon_add_to_gfx_buffer_list_check_mem(sctx, si_resource(buffer), RADEON_USAGE_READ,
1670 RADEON_PRIO_SAMPLER_BUFFER, true);
1671 }
1672 }
1673 }
1674 }
1675
1676 /* Shader images */
1677 if (!buffer || buffer->bind_history & PIPE_BIND_SHADER_IMAGE) {
1678 for (shader = 0; shader < SI_NUM_SHADERS; ++shader) {
1679 struct si_images *images = &sctx->images[shader];
1680 struct si_descriptors *descs = si_sampler_and_image_descriptors(sctx, shader);
1681 unsigned mask = images->enabled_mask;
1682
1683 while (mask) {
1684 unsigned i = u_bit_scan(&mask);
1685 struct pipe_resource *buffer = images->views[i].resource;
1686
1687 if (buffer && buffer->target == PIPE_BUFFER && (!buf || buffer == buf)) {
1688 unsigned desc_slot = si_get_image_slot(i);
1689
1690 if (images->views[i].access & PIPE_IMAGE_ACCESS_WRITE)
1691 si_mark_image_range_valid(&images->views[i]);
1692
1693 si_set_buf_desc_address(si_resource(buffer), images->views[i].u.buf.offset,
1694 descs->list + desc_slot * 8 + 4);
1695 sctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
1696
1697 radeon_add_to_gfx_buffer_list_check_mem(sctx, si_resource(buffer),
1698 RADEON_USAGE_READWRITE,
1699 RADEON_PRIO_SAMPLER_BUFFER, true);
1700 }
1701 }
1702 }
1703 }
1704
1705 /* Bindless texture handles */
1706 if (!buffer || buffer->texture_handle_allocated) {
1707 struct si_descriptors *descs = &sctx->bindless_descriptors;
1708
1709 util_dynarray_foreach (&sctx->resident_tex_handles, struct si_texture_handle *, tex_handle) {
1710 struct pipe_sampler_view *view = (*tex_handle)->view;
1711 unsigned desc_slot = (*tex_handle)->desc_slot;
1712 struct pipe_resource *buffer = view->texture;
1713
1714 if (buffer && buffer->target == PIPE_BUFFER && (!buf || buffer == buf)) {
1715 si_set_buf_desc_address(si_resource(buffer), view->u.buf.offset,
1716 descs->list + desc_slot * 16 + 4);
1717
1718 (*tex_handle)->desc_dirty = true;
1719 sctx->bindless_descriptors_dirty = true;
1720
1721 radeon_add_to_gfx_buffer_list_check_mem(sctx, si_resource(buffer), RADEON_USAGE_READ,
1722 RADEON_PRIO_SAMPLER_BUFFER, true);
1723 }
1724 }
1725 }
1726
1727 /* Bindless image handles */
1728 if (!buffer || buffer->image_handle_allocated) {
1729 struct si_descriptors *descs = &sctx->bindless_descriptors;
1730
1731 util_dynarray_foreach (&sctx->resident_img_handles, struct si_image_handle *, img_handle) {
1732 struct pipe_image_view *view = &(*img_handle)->view;
1733 unsigned desc_slot = (*img_handle)->desc_slot;
1734 struct pipe_resource *buffer = view->resource;
1735
1736 if (buffer && buffer->target == PIPE_BUFFER && (!buf || buffer == buf)) {
1737 if (view->access & PIPE_IMAGE_ACCESS_WRITE)
1738 si_mark_image_range_valid(view);
1739
1740 si_set_buf_desc_address(si_resource(buffer), view->u.buf.offset,
1741 descs->list + desc_slot * 16 + 4);
1742
1743 (*img_handle)->desc_dirty = true;
1744 sctx->bindless_descriptors_dirty = true;
1745
1746 radeon_add_to_gfx_buffer_list_check_mem(
1747 sctx, si_resource(buffer), RADEON_USAGE_READWRITE, RADEON_PRIO_SAMPLER_BUFFER, true);
1748 }
1749 }
1750 }
1751
1752 if (buffer) {
1753 /* Do the same for other contexts. They will invoke this function
1754 * with buffer == NULL.
1755 */
1756 unsigned new_counter = p_atomic_inc_return(&sctx->screen->dirty_buf_counter);
1757
1758 /* Skip the update for the current context, because we have already updated
1759 * the buffer bindings.
1760 */
1761 if (new_counter == sctx->last_dirty_buf_counter + 1)
1762 sctx->last_dirty_buf_counter = new_counter;
1763 }
1764 }
1765
1766 static void si_upload_bindless_descriptor(struct si_context *sctx, unsigned desc_slot,
1767 unsigned num_dwords)
1768 {
1769 struct si_descriptors *desc = &sctx->bindless_descriptors;
1770 unsigned desc_slot_offset = desc_slot * 16;
1771 uint32_t *data;
1772 uint64_t va;
1773
1774 data = desc->list + desc_slot_offset;
1775 va = desc->gpu_address + desc_slot_offset * 4;
1776
1777 si_cp_write_data(sctx, desc->buffer, va - desc->buffer->gpu_address, num_dwords * 4, V_370_TC_L2,
1778 V_370_ME, data);
1779 }
1780
1781 static void si_upload_bindless_descriptors(struct si_context *sctx)
1782 {
1783 if (!sctx->bindless_descriptors_dirty)
1784 return;
1785
1786 /* Wait for graphics/compute to be idle before updating the resident
1787 * descriptors directly in memory, in case the GPU is using them.
1788 */
1789 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH;
1790 sctx->emit_cache_flush(sctx);
1791
1792 util_dynarray_foreach (&sctx->resident_tex_handles, struct si_texture_handle *, tex_handle) {
1793 unsigned desc_slot = (*tex_handle)->desc_slot;
1794
1795 if (!(*tex_handle)->desc_dirty)
1796 continue;
1797
1798 si_upload_bindless_descriptor(sctx, desc_slot, 16);
1799 (*tex_handle)->desc_dirty = false;
1800 }
1801
1802 util_dynarray_foreach (&sctx->resident_img_handles, struct si_image_handle *, img_handle) {
1803 unsigned desc_slot = (*img_handle)->desc_slot;
1804
1805 if (!(*img_handle)->desc_dirty)
1806 continue;
1807
1808 si_upload_bindless_descriptor(sctx, desc_slot, 8);
1809 (*img_handle)->desc_dirty = false;
1810 }
1811
1812 /* Invalidate L1 because it doesn't know that L2 changed. */
1813 sctx->flags |= SI_CONTEXT_INV_SCACHE;
1814 sctx->emit_cache_flush(sctx);
1815
1816 sctx->bindless_descriptors_dirty = false;
1817 }
1818
1819 /* Update mutable image descriptor fields of all resident textures. */
1820 static void si_update_bindless_texture_descriptor(struct si_context *sctx,
1821 struct si_texture_handle *tex_handle)
1822 {
1823 struct si_sampler_view *sview = (struct si_sampler_view *)tex_handle->view;
1824 struct si_descriptors *desc = &sctx->bindless_descriptors;
1825 unsigned desc_slot_offset = tex_handle->desc_slot * 16;
1826 uint32_t desc_list[16];
1827
1828 if (sview->base.texture->target == PIPE_BUFFER)
1829 return;
1830
1831 memcpy(desc_list, desc->list + desc_slot_offset, sizeof(desc_list));
1832 si_set_sampler_view_desc(sctx, sview, &tex_handle->sstate, desc->list + desc_slot_offset);
1833
1834 if (memcmp(desc_list, desc->list + desc_slot_offset, sizeof(desc_list))) {
1835 tex_handle->desc_dirty = true;
1836 sctx->bindless_descriptors_dirty = true;
1837 }
1838 }
1839
1840 static void si_update_bindless_image_descriptor(struct si_context *sctx,
1841 struct si_image_handle *img_handle)
1842 {
1843 struct si_descriptors *desc = &sctx->bindless_descriptors;
1844 unsigned desc_slot_offset = img_handle->desc_slot * 16;
1845 struct pipe_image_view *view = &img_handle->view;
1846 struct pipe_resource *res = view->resource;
1847 uint32_t image_desc[16];
1848 unsigned desc_size = (res->nr_samples >= 2 ? 16 : 8) * 4;
1849
1850 if (res->target == PIPE_BUFFER)
1851 return;
1852
1853 memcpy(image_desc, desc->list + desc_slot_offset, desc_size);
1854 si_set_shader_image_desc(sctx, view, true, desc->list + desc_slot_offset,
1855 desc->list + desc_slot_offset + 8);
1856
1857 if (memcmp(image_desc, desc->list + desc_slot_offset, desc_size)) {
1858 img_handle->desc_dirty = true;
1859 sctx->bindless_descriptors_dirty = true;
1860 }
1861 }
1862
1863 static void si_update_all_resident_texture_descriptors(struct si_context *sctx)
1864 {
1865 util_dynarray_foreach (&sctx->resident_tex_handles, struct si_texture_handle *, tex_handle) {
1866 si_update_bindless_texture_descriptor(sctx, *tex_handle);
1867 }
1868
1869 util_dynarray_foreach (&sctx->resident_img_handles, struct si_image_handle *, img_handle) {
1870 si_update_bindless_image_descriptor(sctx, *img_handle);
1871 }
1872
1873 si_upload_bindless_descriptors(sctx);
1874 }
1875
1876 /* Update mutable image descriptor fields of all bound textures. */
1877 void si_update_all_texture_descriptors(struct si_context *sctx)
1878 {
1879 unsigned shader;
1880
1881 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1882 struct si_samplers *samplers = &sctx->samplers[shader];
1883 struct si_images *images = &sctx->images[shader];
1884 unsigned mask;
1885
1886 /* Images. */
1887 mask = images->enabled_mask;
1888 while (mask) {
1889 unsigned i = u_bit_scan(&mask);
1890 struct pipe_image_view *view = &images->views[i];
1891
1892 if (!view->resource || view->resource->target == PIPE_BUFFER)
1893 continue;
1894
1895 si_set_shader_image(sctx, shader, i, view, true);
1896 }
1897
1898 /* Sampler views. */
1899 mask = samplers->enabled_mask;
1900 while (mask) {
1901 unsigned i = u_bit_scan(&mask);
1902 struct pipe_sampler_view *view = samplers->views[i];
1903
1904 if (!view || !view->texture || view->texture->target == PIPE_BUFFER)
1905 continue;
1906
1907 si_set_sampler_view(sctx, shader, i, samplers->views[i], true);
1908 }
1909
1910 si_update_shader_needs_decompress_mask(sctx, shader);
1911 }
1912
1913 si_update_all_resident_texture_descriptors(sctx);
1914 si_update_ps_colorbuf0_slot(sctx);
1915 }
1916
1917 /* SHADER USER DATA */
1918
1919 static void si_mark_shader_pointers_dirty(struct si_context *sctx, unsigned shader)
1920 {
1921 sctx->shader_pointers_dirty |=
1922 u_bit_consecutive(SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS, SI_NUM_SHADER_DESCS);
1923
1924 if (shader == PIPE_SHADER_VERTEX) {
1925 sctx->vertex_buffer_pointer_dirty = sctx->vb_descriptors_buffer != NULL;
1926 sctx->vertex_buffer_user_sgprs_dirty =
1927 sctx->num_vertex_elements > 0 && sctx->screen->num_vbos_in_user_sgprs;
1928 }
1929
1930 si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
1931 }
1932
1933 void si_shader_pointers_mark_dirty(struct si_context *sctx)
1934 {
1935 sctx->shader_pointers_dirty = u_bit_consecutive(0, SI_NUM_DESCS);
1936 sctx->vertex_buffer_pointer_dirty = sctx->vb_descriptors_buffer != NULL;
1937 sctx->vertex_buffer_user_sgprs_dirty =
1938 sctx->num_vertex_elements > 0 && sctx->screen->num_vbos_in_user_sgprs;
1939 si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
1940 sctx->graphics_bindless_pointer_dirty = sctx->bindless_descriptors.buffer != NULL;
1941 sctx->compute_bindless_pointer_dirty = sctx->bindless_descriptors.buffer != NULL;
1942 }
1943
1944 /* Set a base register address for user data constants in the given shader.
1945 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
1946 */
1947 static void si_set_user_data_base(struct si_context *sctx, unsigned shader, uint32_t new_base)
1948 {
1949 uint32_t *base = &sctx->shader_pointers.sh_base[shader];
1950
1951 if (*base != new_base) {
1952 *base = new_base;
1953
1954 if (new_base)
1955 si_mark_shader_pointers_dirty(sctx, shader);
1956
1957 /* Any change in enabled shader stages requires re-emitting
1958 * the VS state SGPR, because it contains the clamp_vertex_color
1959 * state, which can be done in VS, TES, and GS.
1960 */
1961 sctx->last_vs_state = ~0;
1962 }
1963 }
1964
1965 /* This must be called when these are changed between enabled and disabled
1966 * - geometry shader
1967 * - tessellation evaluation shader
1968 * - NGG
1969 */
1970 void si_shader_change_notify(struct si_context *sctx)
1971 {
1972 /* VS can be bound as VS, ES, or LS. */
1973 if (sctx->tes_shader.cso) {
1974 if (sctx->chip_class >= GFX10) {
1975 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B430_SPI_SHADER_USER_DATA_HS_0);
1976 } else if (sctx->chip_class == GFX9) {
1977 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B430_SPI_SHADER_USER_DATA_LS_0);
1978 } else {
1979 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B530_SPI_SHADER_USER_DATA_LS_0);
1980 }
1981 } else if (sctx->chip_class >= GFX10) {
1982 if (sctx->ngg || sctx->gs_shader.cso) {
1983 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B230_SPI_SHADER_USER_DATA_GS_0);
1984 } else {
1985 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0);
1986 }
1987 } else if (sctx->gs_shader.cso) {
1988 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B330_SPI_SHADER_USER_DATA_ES_0);
1989 } else {
1990 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0);
1991 }
1992
1993 /* TES can be bound as ES, VS, or not bound. */
1994 if (sctx->tes_shader.cso) {
1995 if (sctx->chip_class >= GFX10) {
1996 if (sctx->ngg || sctx->gs_shader.cso) {
1997 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, R_00B230_SPI_SHADER_USER_DATA_GS_0);
1998 } else {
1999 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, R_00B130_SPI_SHADER_USER_DATA_VS_0);
2000 }
2001 } else if (sctx->gs_shader.cso) {
2002 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, R_00B330_SPI_SHADER_USER_DATA_ES_0);
2003 } else {
2004 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, R_00B130_SPI_SHADER_USER_DATA_VS_0);
2005 }
2006 } else {
2007 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, 0);
2008 }
2009 }
2010
2011 static void si_emit_shader_pointer_head(struct radeon_cmdbuf *cs, unsigned sh_offset,
2012 unsigned pointer_count)
2013 {
2014 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count, 0));
2015 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
2016 }
2017
2018 static void si_emit_shader_pointer_body(struct si_screen *sscreen, struct radeon_cmdbuf *cs,
2019 uint64_t va)
2020 {
2021 radeon_emit(cs, va);
2022
2023 assert(va == 0 || (va >> 32) == sscreen->info.address32_hi);
2024 }
2025
2026 static void si_emit_shader_pointer(struct si_context *sctx, struct si_descriptors *desc,
2027 unsigned sh_base)
2028 {
2029 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2030 unsigned sh_offset = sh_base + desc->shader_userdata_offset;
2031
2032 si_emit_shader_pointer_head(cs, sh_offset, 1);
2033 si_emit_shader_pointer_body(sctx->screen, cs, desc->gpu_address);
2034 }
2035
2036 static void si_emit_consecutive_shader_pointers(struct si_context *sctx, unsigned pointer_mask,
2037 unsigned sh_base)
2038 {
2039 if (!sh_base)
2040 return;
2041
2042 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2043 unsigned mask = sctx->shader_pointers_dirty & pointer_mask;
2044
2045 while (mask) {
2046 int start, count;
2047 u_bit_scan_consecutive_range(&mask, &start, &count);
2048
2049 struct si_descriptors *descs = &sctx->descriptors[start];
2050 unsigned sh_offset = sh_base + descs->shader_userdata_offset;
2051
2052 si_emit_shader_pointer_head(cs, sh_offset, count);
2053 for (int i = 0; i < count; i++)
2054 si_emit_shader_pointer_body(sctx->screen, cs, descs[i].gpu_address);
2055 }
2056 }
2057
2058 static void si_emit_global_shader_pointers(struct si_context *sctx, struct si_descriptors *descs)
2059 {
2060 if (sctx->chip_class >= GFX10) {
2061 si_emit_shader_pointer(sctx, descs, R_00B030_SPI_SHADER_USER_DATA_PS_0);
2062 /* HW VS stage only used in non-NGG mode. */
2063 si_emit_shader_pointer(sctx, descs, R_00B130_SPI_SHADER_USER_DATA_VS_0);
2064 si_emit_shader_pointer(sctx, descs, R_00B230_SPI_SHADER_USER_DATA_GS_0);
2065 si_emit_shader_pointer(sctx, descs, R_00B430_SPI_SHADER_USER_DATA_HS_0);
2066 return;
2067 } else if (sctx->chip_class == GFX9) {
2068 /* Broadcast it to all shader stages. */
2069 si_emit_shader_pointer(sctx, descs, R_00B530_SPI_SHADER_USER_DATA_COMMON_0);
2070 return;
2071 }
2072
2073 si_emit_shader_pointer(sctx, descs, R_00B030_SPI_SHADER_USER_DATA_PS_0);
2074 si_emit_shader_pointer(sctx, descs, R_00B130_SPI_SHADER_USER_DATA_VS_0);
2075 si_emit_shader_pointer(sctx, descs, R_00B330_SPI_SHADER_USER_DATA_ES_0);
2076 si_emit_shader_pointer(sctx, descs, R_00B230_SPI_SHADER_USER_DATA_GS_0);
2077 si_emit_shader_pointer(sctx, descs, R_00B430_SPI_SHADER_USER_DATA_HS_0);
2078 si_emit_shader_pointer(sctx, descs, R_00B530_SPI_SHADER_USER_DATA_LS_0);
2079 }
2080
2081 void si_emit_graphics_shader_pointers(struct si_context *sctx)
2082 {
2083 uint32_t *sh_base = sctx->shader_pointers.sh_base;
2084
2085 if (sctx->shader_pointers_dirty & (1 << SI_DESCS_RW_BUFFERS)) {
2086 si_emit_global_shader_pointers(sctx, &sctx->descriptors[SI_DESCS_RW_BUFFERS]);
2087 }
2088
2089 si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(VERTEX),
2090 sh_base[PIPE_SHADER_VERTEX]);
2091 si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(TESS_EVAL),
2092 sh_base[PIPE_SHADER_TESS_EVAL]);
2093 si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(FRAGMENT),
2094 sh_base[PIPE_SHADER_FRAGMENT]);
2095 si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(TESS_CTRL),
2096 sh_base[PIPE_SHADER_TESS_CTRL]);
2097 si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(GEOMETRY),
2098 sh_base[PIPE_SHADER_GEOMETRY]);
2099
2100 sctx->shader_pointers_dirty &= ~u_bit_consecutive(SI_DESCS_RW_BUFFERS, SI_DESCS_FIRST_COMPUTE);
2101
2102 if (sctx->vertex_buffer_pointer_dirty && sctx->num_vertex_elements) {
2103 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2104
2105 /* Find the location of the VB descriptor pointer. */
2106 unsigned sh_dw_offset = SI_VS_NUM_USER_SGPR;
2107 if (sctx->chip_class >= GFX9) {
2108 if (sctx->tes_shader.cso)
2109 sh_dw_offset = GFX9_TCS_NUM_USER_SGPR;
2110 else if (sctx->gs_shader.cso)
2111 sh_dw_offset = GFX9_VSGS_NUM_USER_SGPR;
2112 }
2113
2114 unsigned sh_offset = sh_base[PIPE_SHADER_VERTEX] + sh_dw_offset * 4;
2115 si_emit_shader_pointer_head(cs, sh_offset, 1);
2116 si_emit_shader_pointer_body(
2117 sctx->screen, cs, sctx->vb_descriptors_buffer->gpu_address + sctx->vb_descriptors_offset);
2118 sctx->vertex_buffer_pointer_dirty = false;
2119 }
2120
2121 if (sctx->vertex_buffer_user_sgprs_dirty && sctx->num_vertex_elements &&
2122 sctx->screen->num_vbos_in_user_sgprs) {
2123 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2124 unsigned num_desc = MIN2(sctx->num_vertex_elements, sctx->screen->num_vbos_in_user_sgprs);
2125 unsigned sh_offset = sh_base[PIPE_SHADER_VERTEX] + SI_SGPR_VS_VB_DESCRIPTOR_FIRST * 4;
2126
2127 si_emit_shader_pointer_head(cs, sh_offset, num_desc * 4);
2128 radeon_emit_array(cs, sctx->vb_descriptor_user_sgprs, num_desc * 4);
2129 sctx->vertex_buffer_user_sgprs_dirty = false;
2130 }
2131
2132 if (sctx->graphics_bindless_pointer_dirty) {
2133 si_emit_global_shader_pointers(sctx, &sctx->bindless_descriptors);
2134 sctx->graphics_bindless_pointer_dirty = false;
2135 }
2136 }
2137
2138 void si_emit_compute_shader_pointers(struct si_context *sctx)
2139 {
2140 unsigned base = R_00B900_COMPUTE_USER_DATA_0;
2141
2142 si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(COMPUTE),
2143 R_00B900_COMPUTE_USER_DATA_0);
2144 sctx->shader_pointers_dirty &= ~SI_DESCS_SHADER_MASK(COMPUTE);
2145
2146 if (sctx->compute_bindless_pointer_dirty) {
2147 si_emit_shader_pointer(sctx, &sctx->bindless_descriptors, base);
2148 sctx->compute_bindless_pointer_dirty = false;
2149 }
2150 }
2151
2152 /* BINDLESS */
2153
2154 static void si_init_bindless_descriptors(struct si_context *sctx, struct si_descriptors *desc,
2155 short shader_userdata_rel_index, unsigned num_elements)
2156 {
2157 ASSERTED unsigned desc_slot;
2158
2159 si_init_descriptors(desc, shader_userdata_rel_index, 16, num_elements);
2160 sctx->bindless_descriptors.num_active_slots = num_elements;
2161
2162 /* The first bindless descriptor is stored at slot 1, because 0 is not
2163 * considered to be a valid handle.
2164 */
2165 sctx->num_bindless_descriptors = 1;
2166
2167 /* Track which bindless slots are used (or not). */
2168 util_idalloc_init(&sctx->bindless_used_slots);
2169 util_idalloc_resize(&sctx->bindless_used_slots, num_elements);
2170
2171 /* Reserve slot 0 because it's an invalid handle for bindless. */
2172 desc_slot = util_idalloc_alloc(&sctx->bindless_used_slots);
2173 assert(desc_slot == 0);
2174 }
2175
2176 static void si_release_bindless_descriptors(struct si_context *sctx)
2177 {
2178 si_release_descriptors(&sctx->bindless_descriptors);
2179 util_idalloc_fini(&sctx->bindless_used_slots);
2180 }
2181
2182 static unsigned si_get_first_free_bindless_slot(struct si_context *sctx)
2183 {
2184 struct si_descriptors *desc = &sctx->bindless_descriptors;
2185 unsigned desc_slot;
2186
2187 desc_slot = util_idalloc_alloc(&sctx->bindless_used_slots);
2188 if (desc_slot >= desc->num_elements) {
2189 /* The array of bindless descriptors is full, resize it. */
2190 unsigned slot_size = desc->element_dw_size * 4;
2191 unsigned new_num_elements = desc->num_elements * 2;
2192
2193 desc->list =
2194 REALLOC(desc->list, desc->num_elements * slot_size, new_num_elements * slot_size);
2195 desc->num_elements = new_num_elements;
2196 desc->num_active_slots = new_num_elements;
2197 }
2198
2199 assert(desc_slot);
2200 return desc_slot;
2201 }
2202
2203 static unsigned si_create_bindless_descriptor(struct si_context *sctx, uint32_t *desc_list,
2204 unsigned size)
2205 {
2206 struct si_descriptors *desc = &sctx->bindless_descriptors;
2207 unsigned desc_slot, desc_slot_offset;
2208
2209 /* Find a free slot. */
2210 desc_slot = si_get_first_free_bindless_slot(sctx);
2211
2212 /* For simplicity, sampler and image bindless descriptors use fixed
2213 * 16-dword slots for now. Image descriptors only need 8-dword but this
2214 * doesn't really matter because no real apps use image handles.
2215 */
2216 desc_slot_offset = desc_slot * 16;
2217
2218 /* Copy the descriptor into the array. */
2219 memcpy(desc->list + desc_slot_offset, desc_list, size);
2220
2221 /* Re-upload the whole array of bindless descriptors into a new buffer.
2222 */
2223 if (!si_upload_descriptors(sctx, desc))
2224 return 0;
2225
2226 /* Make sure to re-emit the shader pointers for all stages. */
2227 sctx->graphics_bindless_pointer_dirty = true;
2228 sctx->compute_bindless_pointer_dirty = true;
2229
2230 return desc_slot;
2231 }
2232
2233 static void si_update_bindless_buffer_descriptor(struct si_context *sctx, unsigned desc_slot,
2234 struct pipe_resource *resource, uint64_t offset,
2235 bool *desc_dirty)
2236 {
2237 struct si_descriptors *desc = &sctx->bindless_descriptors;
2238 struct si_resource *buf = si_resource(resource);
2239 unsigned desc_slot_offset = desc_slot * 16;
2240 uint32_t *desc_list = desc->list + desc_slot_offset + 4;
2241 uint64_t old_desc_va;
2242
2243 assert(resource->target == PIPE_BUFFER);
2244
2245 /* Retrieve the old buffer addr from the descriptor. */
2246 old_desc_va = si_desc_extract_buffer_address(desc_list);
2247
2248 if (old_desc_va != buf->gpu_address + offset) {
2249 /* The buffer has been invalidated when the handle wasn't
2250 * resident, update the descriptor and the dirty flag.
2251 */
2252 si_set_buf_desc_address(buf, offset, &desc_list[0]);
2253
2254 *desc_dirty = true;
2255 }
2256 }
2257
2258 static uint64_t si_create_texture_handle(struct pipe_context *ctx, struct pipe_sampler_view *view,
2259 const struct pipe_sampler_state *state)
2260 {
2261 struct si_sampler_view *sview = (struct si_sampler_view *)view;
2262 struct si_context *sctx = (struct si_context *)ctx;
2263 struct si_texture_handle *tex_handle;
2264 struct si_sampler_state *sstate;
2265 uint32_t desc_list[16];
2266 uint64_t handle;
2267
2268 tex_handle = CALLOC_STRUCT(si_texture_handle);
2269 if (!tex_handle)
2270 return 0;
2271
2272 memset(desc_list, 0, sizeof(desc_list));
2273 si_init_descriptor_list(&desc_list[0], 16, 1, null_texture_descriptor);
2274
2275 sstate = ctx->create_sampler_state(ctx, state);
2276 if (!sstate) {
2277 FREE(tex_handle);
2278 return 0;
2279 }
2280
2281 si_set_sampler_view_desc(sctx, sview, sstate, &desc_list[0]);
2282 memcpy(&tex_handle->sstate, sstate, sizeof(*sstate));
2283 ctx->delete_sampler_state(ctx, sstate);
2284
2285 tex_handle->desc_slot = si_create_bindless_descriptor(sctx, desc_list, sizeof(desc_list));
2286 if (!tex_handle->desc_slot) {
2287 FREE(tex_handle);
2288 return 0;
2289 }
2290
2291 handle = tex_handle->desc_slot;
2292
2293 if (!_mesa_hash_table_insert(sctx->tex_handles, (void *)(uintptr_t)handle, tex_handle)) {
2294 FREE(tex_handle);
2295 return 0;
2296 }
2297
2298 pipe_sampler_view_reference(&tex_handle->view, view);
2299
2300 si_resource(sview->base.texture)->texture_handle_allocated = true;
2301
2302 return handle;
2303 }
2304
2305 static void si_delete_texture_handle(struct pipe_context *ctx, uint64_t handle)
2306 {
2307 struct si_context *sctx = (struct si_context *)ctx;
2308 struct si_texture_handle *tex_handle;
2309 struct hash_entry *entry;
2310
2311 entry = _mesa_hash_table_search(sctx->tex_handles, (void *)(uintptr_t)handle);
2312 if (!entry)
2313 return;
2314
2315 tex_handle = (struct si_texture_handle *)entry->data;
2316
2317 /* Allow this descriptor slot to be re-used. */
2318 util_idalloc_free(&sctx->bindless_used_slots, tex_handle->desc_slot);
2319
2320 pipe_sampler_view_reference(&tex_handle->view, NULL);
2321 _mesa_hash_table_remove(sctx->tex_handles, entry);
2322 FREE(tex_handle);
2323 }
2324
2325 static void si_make_texture_handle_resident(struct pipe_context *ctx, uint64_t handle,
2326 bool resident)
2327 {
2328 struct si_context *sctx = (struct si_context *)ctx;
2329 struct si_texture_handle *tex_handle;
2330 struct si_sampler_view *sview;
2331 struct hash_entry *entry;
2332
2333 entry = _mesa_hash_table_search(sctx->tex_handles, (void *)(uintptr_t)handle);
2334 if (!entry)
2335 return;
2336
2337 tex_handle = (struct si_texture_handle *)entry->data;
2338 sview = (struct si_sampler_view *)tex_handle->view;
2339
2340 if (resident) {
2341 if (sview->base.texture->target != PIPE_BUFFER) {
2342 struct si_texture *tex = (struct si_texture *)sview->base.texture;
2343
2344 if (depth_needs_decompression(tex)) {
2345 util_dynarray_append(&sctx->resident_tex_needs_depth_decompress,
2346 struct si_texture_handle *, tex_handle);
2347 }
2348
2349 if (color_needs_decompression(tex)) {
2350 util_dynarray_append(&sctx->resident_tex_needs_color_decompress,
2351 struct si_texture_handle *, tex_handle);
2352 }
2353
2354 if (vi_dcc_enabled(tex, sview->base.u.tex.first_level) &&
2355 p_atomic_read(&tex->framebuffers_bound))
2356 sctx->need_check_render_feedback = true;
2357
2358 si_update_bindless_texture_descriptor(sctx, tex_handle);
2359 } else {
2360 si_update_bindless_buffer_descriptor(sctx, tex_handle->desc_slot, sview->base.texture,
2361 sview->base.u.buf.offset, &tex_handle->desc_dirty);
2362 }
2363
2364 /* Re-upload the descriptor if it has been updated while it
2365 * wasn't resident.
2366 */
2367 if (tex_handle->desc_dirty)
2368 sctx->bindless_descriptors_dirty = true;
2369
2370 /* Add the texture handle to the per-context list. */
2371 util_dynarray_append(&sctx->resident_tex_handles, struct si_texture_handle *, tex_handle);
2372
2373 /* Add the buffers to the current CS in case si_begin_new_cs()
2374 * is not going to be called.
2375 */
2376 si_sampler_view_add_buffer(sctx, sview->base.texture, RADEON_USAGE_READ,
2377 sview->is_stencil_sampler, false);
2378 } else {
2379 /* Remove the texture handle from the per-context list. */
2380 util_dynarray_delete_unordered(&sctx->resident_tex_handles, struct si_texture_handle *,
2381 tex_handle);
2382
2383 if (sview->base.texture->target != PIPE_BUFFER) {
2384 util_dynarray_delete_unordered(&sctx->resident_tex_needs_depth_decompress,
2385 struct si_texture_handle *, tex_handle);
2386
2387 util_dynarray_delete_unordered(&sctx->resident_tex_needs_color_decompress,
2388 struct si_texture_handle *, tex_handle);
2389 }
2390 }
2391 }
2392
2393 static uint64_t si_create_image_handle(struct pipe_context *ctx, const struct pipe_image_view *view)
2394 {
2395 struct si_context *sctx = (struct si_context *)ctx;
2396 struct si_image_handle *img_handle;
2397 uint32_t desc_list[16];
2398 uint64_t handle;
2399
2400 if (!view || !view->resource)
2401 return 0;
2402
2403 img_handle = CALLOC_STRUCT(si_image_handle);
2404 if (!img_handle)
2405 return 0;
2406
2407 memset(desc_list, 0, sizeof(desc_list));
2408 si_init_descriptor_list(&desc_list[0], 8, 2, null_image_descriptor);
2409
2410 si_set_shader_image_desc(sctx, view, false, &desc_list[0], &desc_list[8]);
2411
2412 img_handle->desc_slot = si_create_bindless_descriptor(sctx, desc_list, sizeof(desc_list));
2413 if (!img_handle->desc_slot) {
2414 FREE(img_handle);
2415 return 0;
2416 }
2417
2418 handle = img_handle->desc_slot;
2419
2420 if (!_mesa_hash_table_insert(sctx->img_handles, (void *)(uintptr_t)handle, img_handle)) {
2421 FREE(img_handle);
2422 return 0;
2423 }
2424
2425 util_copy_image_view(&img_handle->view, view);
2426
2427 si_resource(view->resource)->image_handle_allocated = true;
2428
2429 return handle;
2430 }
2431
2432 static void si_delete_image_handle(struct pipe_context *ctx, uint64_t handle)
2433 {
2434 struct si_context *sctx = (struct si_context *)ctx;
2435 struct si_image_handle *img_handle;
2436 struct hash_entry *entry;
2437
2438 entry = _mesa_hash_table_search(sctx->img_handles, (void *)(uintptr_t)handle);
2439 if (!entry)
2440 return;
2441
2442 img_handle = (struct si_image_handle *)entry->data;
2443
2444 util_copy_image_view(&img_handle->view, NULL);
2445 _mesa_hash_table_remove(sctx->img_handles, entry);
2446 FREE(img_handle);
2447 }
2448
2449 static void si_make_image_handle_resident(struct pipe_context *ctx, uint64_t handle,
2450 unsigned access, bool resident)
2451 {
2452 struct si_context *sctx = (struct si_context *)ctx;
2453 struct si_image_handle *img_handle;
2454 struct pipe_image_view *view;
2455 struct si_resource *res;
2456 struct hash_entry *entry;
2457
2458 entry = _mesa_hash_table_search(sctx->img_handles, (void *)(uintptr_t)handle);
2459 if (!entry)
2460 return;
2461
2462 img_handle = (struct si_image_handle *)entry->data;
2463 view = &img_handle->view;
2464 res = si_resource(view->resource);
2465
2466 if (resident) {
2467 if (res->b.b.target != PIPE_BUFFER) {
2468 struct si_texture *tex = (struct si_texture *)res;
2469 unsigned level = view->u.tex.level;
2470
2471 if (color_needs_decompression(tex)) {
2472 util_dynarray_append(&sctx->resident_img_needs_color_decompress,
2473 struct si_image_handle *, img_handle);
2474 }
2475
2476 if (vi_dcc_enabled(tex, level) && p_atomic_read(&tex->framebuffers_bound))
2477 sctx->need_check_render_feedback = true;
2478
2479 si_update_bindless_image_descriptor(sctx, img_handle);
2480 } else {
2481 si_update_bindless_buffer_descriptor(sctx, img_handle->desc_slot, view->resource,
2482 view->u.buf.offset, &img_handle->desc_dirty);
2483 }
2484
2485 /* Re-upload the descriptor if it has been updated while it
2486 * wasn't resident.
2487 */
2488 if (img_handle->desc_dirty)
2489 sctx->bindless_descriptors_dirty = true;
2490
2491 /* Add the image handle to the per-context list. */
2492 util_dynarray_append(&sctx->resident_img_handles, struct si_image_handle *, img_handle);
2493
2494 /* Add the buffers to the current CS in case si_begin_new_cs()
2495 * is not going to be called.
2496 */
2497 si_sampler_view_add_buffer(
2498 sctx, view->resource,
2499 (access & PIPE_IMAGE_ACCESS_WRITE) ? RADEON_USAGE_READWRITE : RADEON_USAGE_READ, false,
2500 false);
2501 } else {
2502 /* Remove the image handle from the per-context list. */
2503 util_dynarray_delete_unordered(&sctx->resident_img_handles, struct si_image_handle *,
2504 img_handle);
2505
2506 if (res->b.b.target != PIPE_BUFFER) {
2507 util_dynarray_delete_unordered(&sctx->resident_img_needs_color_decompress,
2508 struct si_image_handle *, img_handle);
2509 }
2510 }
2511 }
2512
2513 static void si_resident_buffers_add_all_to_bo_list(struct si_context *sctx)
2514 {
2515 unsigned num_resident_tex_handles, num_resident_img_handles;
2516
2517 num_resident_tex_handles = sctx->resident_tex_handles.size / sizeof(struct si_texture_handle *);
2518 num_resident_img_handles = sctx->resident_img_handles.size / sizeof(struct si_image_handle *);
2519
2520 /* Add all resident texture handles. */
2521 util_dynarray_foreach (&sctx->resident_tex_handles, struct si_texture_handle *, tex_handle) {
2522 struct si_sampler_view *sview = (struct si_sampler_view *)(*tex_handle)->view;
2523
2524 si_sampler_view_add_buffer(sctx, sview->base.texture, RADEON_USAGE_READ,
2525 sview->is_stencil_sampler, false);
2526 }
2527
2528 /* Add all resident image handles. */
2529 util_dynarray_foreach (&sctx->resident_img_handles, struct si_image_handle *, img_handle) {
2530 struct pipe_image_view *view = &(*img_handle)->view;
2531
2532 si_sampler_view_add_buffer(sctx, view->resource, RADEON_USAGE_READWRITE, false, false);
2533 }
2534
2535 sctx->num_resident_handles += num_resident_tex_handles + num_resident_img_handles;
2536 assert(sctx->bo_list_add_all_resident_resources);
2537 sctx->bo_list_add_all_resident_resources = false;
2538 }
2539
2540 /* INIT/DEINIT/UPLOAD */
2541
2542 void si_init_all_descriptors(struct si_context *sctx)
2543 {
2544 int i;
2545 unsigned first_shader = sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE;
2546
2547 for (i = first_shader; i < SI_NUM_SHADERS; i++) {
2548 bool is_2nd =
2549 sctx->chip_class >= GFX9 && (i == PIPE_SHADER_TESS_CTRL || i == PIPE_SHADER_GEOMETRY);
2550 unsigned num_sampler_slots = SI_NUM_IMAGE_SLOTS / 2 + SI_NUM_SAMPLERS;
2551 unsigned num_buffer_slots = SI_NUM_SHADER_BUFFERS + SI_NUM_CONST_BUFFERS;
2552 int rel_dw_offset;
2553 struct si_descriptors *desc;
2554
2555 if (is_2nd) {
2556 if (i == PIPE_SHADER_TESS_CTRL) {
2557 rel_dw_offset =
2558 (R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS - R_00B430_SPI_SHADER_USER_DATA_LS_0) / 4;
2559 } else if (sctx->chip_class >= GFX10) { /* PIPE_SHADER_GEOMETRY */
2560 rel_dw_offset =
2561 (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS - R_00B230_SPI_SHADER_USER_DATA_GS_0) / 4;
2562 } else {
2563 rel_dw_offset =
2564 (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS - R_00B330_SPI_SHADER_USER_DATA_ES_0) / 4;
2565 }
2566 } else {
2567 rel_dw_offset = SI_SGPR_CONST_AND_SHADER_BUFFERS;
2568 }
2569 desc = si_const_and_shader_buffer_descriptors(sctx, i);
2570 si_init_buffer_resources(&sctx->const_and_shader_buffers[i], desc, num_buffer_slots,
2571 rel_dw_offset, RADEON_PRIO_SHADER_RW_BUFFER,
2572 RADEON_PRIO_CONST_BUFFER);
2573 desc->slot_index_to_bind_directly = si_get_constbuf_slot(0);
2574
2575 if (is_2nd) {
2576 if (i == PIPE_SHADER_TESS_CTRL) {
2577 rel_dw_offset =
2578 (R_00B40C_SPI_SHADER_USER_DATA_ADDR_HI_HS - R_00B430_SPI_SHADER_USER_DATA_LS_0) / 4;
2579 } else if (sctx->chip_class >= GFX10) { /* PIPE_SHADER_GEOMETRY */
2580 rel_dw_offset =
2581 (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS - R_00B230_SPI_SHADER_USER_DATA_GS_0) / 4;
2582 } else {
2583 rel_dw_offset =
2584 (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS - R_00B330_SPI_SHADER_USER_DATA_ES_0) / 4;
2585 }
2586 } else {
2587 rel_dw_offset = SI_SGPR_SAMPLERS_AND_IMAGES;
2588 }
2589
2590 desc = si_sampler_and_image_descriptors(sctx, i);
2591 si_init_descriptors(desc, rel_dw_offset, 16, num_sampler_slots);
2592
2593 int j;
2594 for (j = 0; j < SI_NUM_IMAGE_SLOTS; j++)
2595 memcpy(desc->list + j * 8, null_image_descriptor, 8 * 4);
2596 for (; j < SI_NUM_IMAGE_SLOTS + SI_NUM_SAMPLERS * 2; j++)
2597 memcpy(desc->list + j * 8, null_texture_descriptor, 8 * 4);
2598 }
2599
2600 si_init_buffer_resources(&sctx->rw_buffers, &sctx->descriptors[SI_DESCS_RW_BUFFERS],
2601 SI_NUM_RW_BUFFERS, SI_SGPR_RW_BUFFERS,
2602 /* The second priority is used by
2603 * const buffers in RW buffer slots. */
2604 RADEON_PRIO_SHADER_RINGS, RADEON_PRIO_CONST_BUFFER);
2605 sctx->descriptors[SI_DESCS_RW_BUFFERS].num_active_slots = SI_NUM_RW_BUFFERS;
2606
2607 /* Initialize an array of 1024 bindless descriptors, when the limit is
2608 * reached, just make it larger and re-upload the whole array.
2609 */
2610 si_init_bindless_descriptors(sctx, &sctx->bindless_descriptors,
2611 SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES, 1024);
2612
2613 sctx->descriptors_dirty = u_bit_consecutive(0, SI_NUM_DESCS);
2614
2615 /* Set pipe_context functions. */
2616 sctx->b.bind_sampler_states = si_bind_sampler_states;
2617 sctx->b.set_shader_images = si_set_shader_images;
2618 sctx->b.set_constant_buffer = si_pipe_set_constant_buffer;
2619 sctx->b.set_shader_buffers = si_set_shader_buffers;
2620 sctx->b.set_sampler_views = si_set_sampler_views;
2621 sctx->b.create_texture_handle = si_create_texture_handle;
2622 sctx->b.delete_texture_handle = si_delete_texture_handle;
2623 sctx->b.make_texture_handle_resident = si_make_texture_handle_resident;
2624 sctx->b.create_image_handle = si_create_image_handle;
2625 sctx->b.delete_image_handle = si_delete_image_handle;
2626 sctx->b.make_image_handle_resident = si_make_image_handle_resident;
2627
2628 if (!sctx->has_graphics)
2629 return;
2630
2631 sctx->b.set_polygon_stipple = si_set_polygon_stipple;
2632
2633 /* Shader user data. */
2634 sctx->atoms.s.shader_pointers.emit = si_emit_graphics_shader_pointers;
2635
2636 /* Set default and immutable mappings. */
2637 if (sctx->ngg) {
2638 assert(sctx->chip_class >= GFX10);
2639 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B230_SPI_SHADER_USER_DATA_GS_0);
2640 } else {
2641 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0);
2642 }
2643
2644 if (sctx->chip_class == GFX9) {
2645 si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL, R_00B430_SPI_SHADER_USER_DATA_LS_0);
2646 si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY, R_00B330_SPI_SHADER_USER_DATA_ES_0);
2647 } else {
2648 si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL, R_00B430_SPI_SHADER_USER_DATA_HS_0);
2649 si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY, R_00B230_SPI_SHADER_USER_DATA_GS_0);
2650 }
2651 si_set_user_data_base(sctx, PIPE_SHADER_FRAGMENT, R_00B030_SPI_SHADER_USER_DATA_PS_0);
2652 }
2653
2654 static bool si_upload_shader_descriptors(struct si_context *sctx, unsigned mask)
2655 {
2656 unsigned dirty = sctx->descriptors_dirty & mask;
2657
2658 /* Assume nothing will go wrong: */
2659 sctx->shader_pointers_dirty |= dirty;
2660
2661 while (dirty) {
2662 unsigned i = u_bit_scan(&dirty);
2663
2664 if (!si_upload_descriptors(sctx, &sctx->descriptors[i]))
2665 return false;
2666 }
2667
2668 sctx->descriptors_dirty &= ~mask;
2669
2670 si_upload_bindless_descriptors(sctx);
2671
2672 return true;
2673 }
2674
2675 bool si_upload_graphics_shader_descriptors(struct si_context *sctx)
2676 {
2677 const unsigned mask = u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE);
2678 return si_upload_shader_descriptors(sctx, mask);
2679 }
2680
2681 bool si_upload_compute_shader_descriptors(struct si_context *sctx)
2682 {
2683 /* Does not update rw_buffers as that is not needed for compute shaders
2684 * and the input buffer is using the same SGPR's anyway.
2685 */
2686 const unsigned mask =
2687 u_bit_consecutive(SI_DESCS_FIRST_COMPUTE, SI_NUM_DESCS - SI_DESCS_FIRST_COMPUTE);
2688 return si_upload_shader_descriptors(sctx, mask);
2689 }
2690
2691 void si_release_all_descriptors(struct si_context *sctx)
2692 {
2693 int i;
2694
2695 for (i = 0; i < SI_NUM_SHADERS; i++) {
2696 si_release_buffer_resources(&sctx->const_and_shader_buffers[i],
2697 si_const_and_shader_buffer_descriptors(sctx, i));
2698 si_release_sampler_views(&sctx->samplers[i]);
2699 si_release_image_views(&sctx->images[i]);
2700 }
2701 si_release_buffer_resources(&sctx->rw_buffers, &sctx->descriptors[SI_DESCS_RW_BUFFERS]);
2702 for (i = 0; i < SI_NUM_VERTEX_BUFFERS; i++)
2703 pipe_vertex_buffer_unreference(&sctx->vertex_buffer[i]);
2704
2705 for (i = 0; i < SI_NUM_DESCS; ++i)
2706 si_release_descriptors(&sctx->descriptors[i]);
2707
2708 si_resource_reference(&sctx->vb_descriptors_buffer, NULL);
2709 sctx->vb_descriptors_gpu_list = NULL; /* points into a mapped buffer */
2710
2711 si_release_bindless_descriptors(sctx);
2712 }
2713
2714 bool si_gfx_resources_check_encrypted(struct si_context *sctx)
2715 {
2716 bool use_encrypted_bo = false;
2717 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
2718 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
2719 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
2720 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
2721 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
2722 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
2723 };
2724
2725 for (unsigned i = 0; i < SI_NUM_GRAPHICS_SHADERS && !use_encrypted_bo; i++) {
2726 if (!current_shader[i]->cso)
2727 continue;
2728
2729 use_encrypted_bo |=
2730 si_buffer_resources_check_encrypted(sctx, &sctx->const_and_shader_buffers[i]);
2731 use_encrypted_bo |=
2732 si_sampler_views_check_encrypted(sctx, &sctx->samplers[i],
2733 current_shader[i]->cso->info.samplers_declared);
2734 use_encrypted_bo |= si_image_views_check_encrypted(sctx, &sctx->images[i],
2735 current_shader[i]->cso->info.images_declared);
2736 }
2737 use_encrypted_bo |= si_buffer_resources_check_encrypted(sctx, &sctx->rw_buffers);
2738
2739 struct si_state_blend *blend = sctx->queued.named.blend;
2740 for (int i = 0; i < sctx->framebuffer.state.nr_cbufs && !use_encrypted_bo; i++) {
2741 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2742 if (surf && surf->texture) {
2743 struct si_texture *tex = (struct si_texture *)surf->texture;
2744 if (!(tex->buffer.flags & RADEON_FLAG_ENCRYPTED))
2745 continue;
2746 /* Are we reading from this framebuffer (blend) */
2747 if ((blend->blend_enable_4bit >> (4 * i)) & 0xf) {
2748 /* TODO: blend op */
2749 use_encrypted_bo = true;
2750 }
2751 }
2752 }
2753
2754 /* TODO: we should assert that either use_encrypted_bo is false,
2755 * or all writable buffers are encrypted.
2756 */
2757 return use_encrypted_bo;
2758 }
2759
2760 void si_gfx_resources_add_all_to_bo_list(struct si_context *sctx)
2761 {
2762 for (unsigned i = 0; i < SI_NUM_GRAPHICS_SHADERS; i++) {
2763 si_buffer_resources_begin_new_cs(sctx, &sctx->const_and_shader_buffers[i]);
2764 si_sampler_views_begin_new_cs(sctx, &sctx->samplers[i]);
2765 si_image_views_begin_new_cs(sctx, &sctx->images[i]);
2766 }
2767 si_buffer_resources_begin_new_cs(sctx, &sctx->rw_buffers);
2768 si_vertex_buffers_begin_new_cs(sctx);
2769
2770 if (sctx->bo_list_add_all_resident_resources)
2771 si_resident_buffers_add_all_to_bo_list(sctx);
2772
2773 assert(sctx->bo_list_add_all_gfx_resources);
2774 sctx->bo_list_add_all_gfx_resources = false;
2775 }
2776
2777 bool si_compute_resources_check_encrypted(struct si_context *sctx)
2778 {
2779 unsigned sh = PIPE_SHADER_COMPUTE;
2780
2781 struct si_shader_info* info = &sctx->cs_shader_state.program->sel.info;
2782
2783 /* TODO: we should assert that either use_encrypted_bo is false,
2784 * or all writable buffers are encrypted.
2785 */
2786 return si_buffer_resources_check_encrypted(sctx, &sctx->const_and_shader_buffers[sh]) ||
2787 si_sampler_views_check_encrypted(sctx, &sctx->samplers[sh], info->samplers_declared) ||
2788 si_image_views_check_encrypted(sctx, &sctx->images[sh], info->images_declared) ||
2789 si_buffer_resources_check_encrypted(sctx, &sctx->rw_buffers);
2790 }
2791
2792 void si_compute_resources_add_all_to_bo_list(struct si_context *sctx)
2793 {
2794 unsigned sh = PIPE_SHADER_COMPUTE;
2795
2796 si_buffer_resources_begin_new_cs(sctx, &sctx->const_and_shader_buffers[sh]);
2797 si_sampler_views_begin_new_cs(sctx, &sctx->samplers[sh]);
2798 si_image_views_begin_new_cs(sctx, &sctx->images[sh]);
2799 si_buffer_resources_begin_new_cs(sctx, &sctx->rw_buffers);
2800
2801 if (sctx->bo_list_add_all_resident_resources)
2802 si_resident_buffers_add_all_to_bo_list(sctx);
2803
2804 assert(sctx->bo_list_add_all_compute_resources);
2805 sctx->bo_list_add_all_compute_resources = false;
2806 }
2807
2808 void si_add_all_descriptors_to_bo_list(struct si_context *sctx)
2809 {
2810 for (unsigned i = 0; i < SI_NUM_DESCS; ++i)
2811 si_add_descriptors_to_bo_list(sctx, &sctx->descriptors[i]);
2812 si_add_descriptors_to_bo_list(sctx, &sctx->bindless_descriptors);
2813
2814 sctx->bo_list_add_all_resident_resources = true;
2815 sctx->bo_list_add_all_gfx_resources = true;
2816 sctx->bo_list_add_all_compute_resources = true;
2817 }
2818
2819 void si_set_active_descriptors(struct si_context *sctx, unsigned desc_idx, uint64_t new_active_mask)
2820 {
2821 struct si_descriptors *desc = &sctx->descriptors[desc_idx];
2822
2823 /* Ignore no-op updates and updates that disable all slots. */
2824 if (!new_active_mask ||
2825 new_active_mask == u_bit_consecutive64(desc->first_active_slot, desc->num_active_slots))
2826 return;
2827
2828 int first, count;
2829 u_bit_scan_consecutive_range64(&new_active_mask, &first, &count);
2830 assert(new_active_mask == 0);
2831
2832 /* Upload/dump descriptors if slots are being enabled. */
2833 if (first < desc->first_active_slot ||
2834 first + count > desc->first_active_slot + desc->num_active_slots)
2835 sctx->descriptors_dirty |= 1u << desc_idx;
2836
2837 desc->first_active_slot = first;
2838 desc->num_active_slots = count;
2839 }
2840
2841 void si_set_active_descriptors_for_shader(struct si_context *sctx, struct si_shader_selector *sel)
2842 {
2843 if (!sel)
2844 return;
2845
2846 si_set_active_descriptors(sctx, si_const_and_shader_buffer_descriptors_idx(sel->type),
2847 sel->active_const_and_shader_buffers);
2848 si_set_active_descriptors(sctx, si_sampler_and_image_descriptors_idx(sel->type),
2849 sel->active_samplers_and_images);
2850 }