865f0b1b771aa04c94f848f7a149234d4e19feca
[mesa.git] / src / gallium / drivers / radeonsi / si_descriptors.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 /* Resource binding slots and sampler states (each described with 8 or
26 * 4 dwords) are stored in lists in memory which is accessed by shaders
27 * using scalar load instructions.
28 *
29 * This file is responsible for managing such lists. It keeps a copy of all
30 * descriptors in CPU memory and re-uploads a whole list if some slots have
31 * been changed.
32 *
33 * This code is also reponsible for updating shader pointers to those lists.
34 *
35 * Note that CP DMA can't be used for updating the lists, because a GPU hang
36 * could leave the list in a mid-IB state and the next IB would get wrong
37 * descriptors and the whole context would be unusable at that point.
38 * (Note: The register shadowing can't be used due to the same reason)
39 *
40 * Also, uploading descriptors to newly allocated memory doesn't require
41 * a KCACHE flush.
42 *
43 *
44 * Possible scenarios for one 16 dword image+sampler slot:
45 *
46 * | Image | w/ FMASK | Buffer | NULL
47 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
48 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
49 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
50 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
51 *
52 * FMASK implies MSAA, therefore no sampler state.
53 * Sampler states are never unbound except when FMASK is bound.
54 */
55
56 #include "si_pipe.h"
57 #include "si_compute.h"
58 #include "sid.h"
59 #include "util/format/u_format.h"
60 #include "util/hash_table.h"
61 #include "util/u_idalloc.h"
62 #include "util/u_memory.h"
63 #include "util/u_upload_mgr.h"
64
65 /* NULL image and buffer descriptor for textures (alpha = 1) and images
66 * (alpha = 0).
67 *
68 * For images, all fields must be zero except for the swizzle, which
69 * supports arbitrary combinations of 0s and 1s. The texture type must be
70 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
71 *
72 * For buffers, all fields must be zero. If they are not, the hw hangs.
73 *
74 * This is the only reason why the buffer descriptor must be in words [4:7].
75 */
76 static uint32_t null_texture_descriptor[8] = {
77 0, 0, 0, S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1) | S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D)
78 /* the rest must contain zeros, which is also used by the buffer
79 * descriptor */
80 };
81
82 static uint32_t null_image_descriptor[8] = {
83 0, 0, 0, S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D)
84 /* the rest must contain zeros, which is also used by the buffer
85 * descriptor */
86 };
87
88 static uint64_t si_desc_extract_buffer_address(const uint32_t *desc)
89 {
90 uint64_t va = desc[0] | ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc[1]) << 32);
91
92 /* Sign-extend the 48-bit address. */
93 va <<= 16;
94 va = (int64_t)va >> 16;
95 return va;
96 }
97
98 static void si_init_descriptor_list(uint32_t *desc_list, unsigned element_dw_size,
99 unsigned num_elements, const uint32_t *null_descriptor)
100 {
101 int i;
102
103 /* Initialize the array to NULL descriptors if the element size is 8. */
104 if (null_descriptor) {
105 assert(element_dw_size % 8 == 0);
106 for (i = 0; i < num_elements * element_dw_size / 8; i++)
107 memcpy(desc_list + i * 8, null_descriptor, 8 * 4);
108 }
109 }
110
111 static void si_init_descriptors(struct si_descriptors *desc, short shader_userdata_rel_index,
112 unsigned element_dw_size, unsigned num_elements)
113 {
114 desc->list = CALLOC(num_elements, element_dw_size * 4);
115 desc->element_dw_size = element_dw_size;
116 desc->num_elements = num_elements;
117 desc->shader_userdata_offset = shader_userdata_rel_index * 4;
118 desc->slot_index_to_bind_directly = -1;
119 }
120
121 static void si_release_descriptors(struct si_descriptors *desc)
122 {
123 si_resource_reference(&desc->buffer, NULL);
124 FREE(desc->list);
125 }
126
127 static bool si_upload_descriptors(struct si_context *sctx, struct si_descriptors *desc)
128 {
129 unsigned slot_size = desc->element_dw_size * 4;
130 unsigned first_slot_offset = desc->first_active_slot * slot_size;
131 unsigned upload_size = desc->num_active_slots * slot_size;
132
133 /* Skip the upload if no shader is using the descriptors. dirty_mask
134 * will stay dirty and the descriptors will be uploaded when there is
135 * a shader using them.
136 */
137 if (!upload_size)
138 return true;
139
140 /* If there is just one active descriptor, bind it directly. */
141 if ((int)desc->first_active_slot == desc->slot_index_to_bind_directly &&
142 desc->num_active_slots == 1) {
143 uint32_t *descriptor = &desc->list[desc->slot_index_to_bind_directly * desc->element_dw_size];
144
145 /* The buffer is already in the buffer list. */
146 si_resource_reference(&desc->buffer, NULL);
147 desc->gpu_list = NULL;
148 desc->gpu_address = si_desc_extract_buffer_address(descriptor);
149 si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
150 return true;
151 }
152
153 uint32_t *ptr;
154 unsigned buffer_offset;
155 u_upload_alloc(sctx->b.const_uploader, first_slot_offset, upload_size,
156 si_optimal_tcc_alignment(sctx, upload_size), &buffer_offset,
157 (struct pipe_resource **)&desc->buffer, (void **)&ptr);
158 if (!desc->buffer) {
159 desc->gpu_address = 0;
160 return false; /* skip the draw call */
161 }
162
163 util_memcpy_cpu_to_le32(ptr, (char *)desc->list + first_slot_offset, upload_size);
164 desc->gpu_list = ptr - first_slot_offset / 4;
165
166 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, desc->buffer, RADEON_USAGE_READ,
167 RADEON_PRIO_DESCRIPTORS);
168
169 /* The shader pointer should point to slot 0. */
170 buffer_offset -= first_slot_offset;
171 desc->gpu_address = desc->buffer->gpu_address + buffer_offset;
172
173 assert(desc->buffer->flags & RADEON_FLAG_32BIT);
174 assert((desc->buffer->gpu_address >> 32) == sctx->screen->info.address32_hi);
175 assert((desc->gpu_address >> 32) == sctx->screen->info.address32_hi);
176
177 si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
178 return true;
179 }
180
181 static void
182 si_add_descriptors_to_bo_list(struct si_context *sctx, struct si_descriptors *desc)
183 {
184 if (!desc->buffer)
185 return;
186
187 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, desc->buffer, RADEON_USAGE_READ,
188 RADEON_PRIO_DESCRIPTORS);
189 }
190
191 /* SAMPLER VIEWS */
192
193 static inline enum radeon_bo_priority si_get_sampler_view_priority(struct si_resource *res)
194 {
195 if (res->b.b.target == PIPE_BUFFER)
196 return RADEON_PRIO_SAMPLER_BUFFER;
197
198 if (res->b.b.nr_samples > 1)
199 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
200
201 return RADEON_PRIO_SAMPLER_TEXTURE;
202 }
203
204 static struct si_descriptors *si_sampler_and_image_descriptors(struct si_context *sctx,
205 unsigned shader)
206 {
207 return &sctx->descriptors[si_sampler_and_image_descriptors_idx(shader)];
208 }
209
210 static void si_release_sampler_views(struct si_samplers *samplers)
211 {
212 int i;
213
214 for (i = 0; i < ARRAY_SIZE(samplers->views); i++) {
215 pipe_sampler_view_reference(&samplers->views[i], NULL);
216 }
217 }
218
219 static void si_sampler_view_add_buffer(struct si_context *sctx, struct pipe_resource *resource,
220 enum radeon_bo_usage usage, bool is_stencil_sampler,
221 bool check_mem)
222 {
223 struct si_texture *tex = (struct si_texture *)resource;
224 enum radeon_bo_priority priority;
225
226 if (!resource)
227 return;
228
229 /* Use the flushed depth texture if direct sampling is unsupported. */
230 if (resource->target != PIPE_BUFFER && tex->is_depth &&
231 !si_can_sample_zs(tex, is_stencil_sampler))
232 tex = tex->flushed_depth_texture;
233
234 priority = si_get_sampler_view_priority(&tex->buffer);
235 radeon_add_to_gfx_buffer_list_check_mem(sctx, &tex->buffer, usage, priority, check_mem);
236
237 if (resource->target == PIPE_BUFFER)
238 return;
239
240 /* Add separate DCC. */
241 if (tex->dcc_separate_buffer) {
242 radeon_add_to_gfx_buffer_list_check_mem(sctx, tex->dcc_separate_buffer, usage,
243 RADEON_PRIO_SEPARATE_META, check_mem);
244 }
245 }
246
247 static void si_sampler_views_begin_new_cs(struct si_context *sctx, struct si_samplers *samplers)
248 {
249 unsigned mask = samplers->enabled_mask;
250
251 /* Add buffers to the CS. */
252 while (mask) {
253 int i = u_bit_scan(&mask);
254 struct si_sampler_view *sview = (struct si_sampler_view *)samplers->views[i];
255
256 si_sampler_view_add_buffer(sctx, sview->base.texture, RADEON_USAGE_READ,
257 sview->is_stencil_sampler, false);
258 }
259 }
260
261 static bool si_sampler_views_check_encrypted(struct si_context *sctx, struct si_samplers *samplers,
262 unsigned samplers_declared)
263 {
264 unsigned mask = samplers->enabled_mask & samplers_declared;
265
266 /* Verify if a samplers uses an encrypted resource */
267 while (mask) {
268 int i = u_bit_scan(&mask);
269 struct si_sampler_view *sview = (struct si_sampler_view *)samplers->views[i];
270
271 struct si_resource *res = si_resource(sview->base.texture);
272 if (res->flags & RADEON_FLAG_ENCRYPTED)
273 return true;
274 }
275 return false;
276 }
277
278 /* Set buffer descriptor fields that can be changed by reallocations. */
279 static void si_set_buf_desc_address(struct si_resource *buf, uint64_t offset, uint32_t *state)
280 {
281 uint64_t va = buf->gpu_address + offset;
282
283 state[0] = va;
284 state[1] &= C_008F04_BASE_ADDRESS_HI;
285 state[1] |= S_008F04_BASE_ADDRESS_HI(va >> 32);
286 }
287
288 /* Set texture descriptor fields that can be changed by reallocations.
289 *
290 * \param tex texture
291 * \param base_level_info information of the level of BASE_ADDRESS
292 * \param base_level the level of BASE_ADDRESS
293 * \param first_level pipe_sampler_view.u.tex.first_level
294 * \param block_width util_format_get_blockwidth()
295 * \param is_stencil select between separate Z & Stencil
296 * \param state descriptor to update
297 */
298 void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture *tex,
299 const struct legacy_surf_level *base_level_info,
300 unsigned base_level, unsigned first_level, unsigned block_width,
301 bool is_stencil, bool force_dcc_off, uint32_t *state)
302 {
303 uint64_t va, meta_va = 0;
304
305 if (tex->is_depth && !si_can_sample_zs(tex, is_stencil)) {
306 tex = tex->flushed_depth_texture;
307 is_stencil = false;
308 }
309
310 va = tex->buffer.gpu_address;
311
312 if (sscreen->info.chip_class >= GFX9) {
313 /* Only stencil_offset needs to be added here. */
314 if (is_stencil)
315 va += tex->surface.u.gfx9.stencil_offset;
316 else
317 va += tex->surface.u.gfx9.surf_offset;
318 } else {
319 va += base_level_info->offset;
320 }
321
322 state[0] = va >> 8;
323 state[1] &= C_008F14_BASE_ADDRESS_HI;
324 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
325
326 /* Only macrotiled modes can set tile swizzle.
327 * GFX9 doesn't use (legacy) base_level_info.
328 */
329 if (sscreen->info.chip_class >= GFX9 || base_level_info->mode == RADEON_SURF_MODE_2D)
330 state[0] |= tex->surface.tile_swizzle;
331
332 if (sscreen->info.chip_class >= GFX8) {
333 state[6] &= C_008F28_COMPRESSION_EN;
334
335 if (!force_dcc_off && vi_dcc_enabled(tex, first_level)) {
336 meta_va =
337 (!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) + tex->surface.dcc_offset;
338
339 if (sscreen->info.chip_class == GFX8) {
340 meta_va += base_level_info->dcc_offset;
341 assert(base_level_info->mode == RADEON_SURF_MODE_2D);
342 }
343
344 unsigned dcc_tile_swizzle = tex->surface.tile_swizzle << 8;
345 dcc_tile_swizzle &= tex->surface.dcc_alignment - 1;
346 meta_va |= dcc_tile_swizzle;
347 } else if (vi_tc_compat_htile_enabled(tex, first_level,
348 is_stencil ? PIPE_MASK_S : PIPE_MASK_Z)) {
349 meta_va = tex->buffer.gpu_address + tex->surface.htile_offset;
350 }
351
352 if (meta_va)
353 state[6] |= S_008F28_COMPRESSION_EN(1);
354 }
355
356 if (sscreen->info.chip_class >= GFX8 && sscreen->info.chip_class <= GFX9)
357 state[7] = meta_va >> 8;
358
359 if (sscreen->info.chip_class >= GFX10) {
360 state[3] &= C_00A00C_SW_MODE;
361
362 if (is_stencil) {
363 state[3] |= S_00A00C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
364 } else {
365 state[3] |= S_00A00C_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode);
366 }
367
368 state[6] &= C_00A018_META_DATA_ADDRESS_LO & C_00A018_META_PIPE_ALIGNED;
369
370 if (meta_va) {
371 struct gfx9_surf_meta_flags meta = {
372 .rb_aligned = 1,
373 .pipe_aligned = 1,
374 };
375
376 if (tex->surface.dcc_offset)
377 meta = tex->surface.u.gfx9.dcc;
378
379 state[6] |= S_00A018_META_PIPE_ALIGNED(meta.pipe_aligned) |
380 S_00A018_META_DATA_ADDRESS_LO(meta_va >> 8);
381 }
382
383 state[7] = meta_va >> 16;
384 } else if (sscreen->info.chip_class == GFX9) {
385 state[3] &= C_008F1C_SW_MODE;
386 state[4] &= C_008F20_PITCH;
387
388 if (is_stencil) {
389 state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
390 state[4] |= S_008F20_PITCH(tex->surface.u.gfx9.stencil.epitch);
391 } else {
392 state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode);
393 state[4] |= S_008F20_PITCH(tex->surface.u.gfx9.surf.epitch);
394 }
395
396 state[5] &=
397 C_008F24_META_DATA_ADDRESS & C_008F24_META_PIPE_ALIGNED & C_008F24_META_RB_ALIGNED;
398 if (meta_va) {
399 struct gfx9_surf_meta_flags meta = {
400 .rb_aligned = 1,
401 .pipe_aligned = 1,
402 };
403
404 if (tex->surface.dcc_offset)
405 meta = tex->surface.u.gfx9.dcc;
406
407 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
408 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
409 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
410 }
411 } else {
412 /* GFX6-GFX8 */
413 unsigned pitch = base_level_info->nblk_x * block_width;
414 unsigned index = si_tile_mode_index(tex, base_level, is_stencil);
415
416 state[3] &= C_008F1C_TILING_INDEX;
417 state[3] |= S_008F1C_TILING_INDEX(index);
418 state[4] &= C_008F20_PITCH;
419 state[4] |= S_008F20_PITCH(pitch - 1);
420 }
421 }
422
423 static void si_set_sampler_state_desc(struct si_sampler_state *sstate,
424 struct si_sampler_view *sview, struct si_texture *tex,
425 uint32_t *desc)
426 {
427 if (sview && sview->is_integer)
428 memcpy(desc, sstate->integer_val, 4 * 4);
429 else if (tex && tex->upgraded_depth && (!sview || !sview->is_stencil_sampler))
430 memcpy(desc, sstate->upgraded_depth_val, 4 * 4);
431 else
432 memcpy(desc, sstate->val, 4 * 4);
433 }
434
435 static void si_set_sampler_view_desc(struct si_context *sctx, struct si_sampler_view *sview,
436 struct si_sampler_state *sstate, uint32_t *desc)
437 {
438 struct pipe_sampler_view *view = &sview->base;
439 struct si_texture *tex = (struct si_texture *)view->texture;
440 bool is_buffer = tex->buffer.b.b.target == PIPE_BUFFER;
441
442 if (unlikely(!is_buffer && sview->dcc_incompatible)) {
443 if (vi_dcc_enabled(tex, view->u.tex.first_level))
444 if (!si_texture_disable_dcc(sctx, tex))
445 si_decompress_dcc(sctx, tex);
446
447 sview->dcc_incompatible = false;
448 }
449
450 assert(tex); /* views with texture == NULL aren't supported */
451 memcpy(desc, sview->state, 8 * 4);
452
453 if (is_buffer) {
454 si_set_buf_desc_address(&tex->buffer, sview->base.u.buf.offset, desc + 4);
455 } else {
456 bool is_separate_stencil = tex->db_compatible && sview->is_stencil_sampler;
457
458 si_set_mutable_tex_desc_fields(sctx->screen, tex, sview->base_level_info, sview->base_level,
459 sview->base.u.tex.first_level, sview->block_width,
460 is_separate_stencil, false, desc);
461 }
462
463 if (!is_buffer && tex->surface.fmask_size) {
464 memcpy(desc + 8, sview->fmask_state, 8 * 4);
465 } else {
466 /* Disable FMASK and bind sampler state in [12:15]. */
467 memcpy(desc + 8, null_texture_descriptor, 4 * 4);
468
469 if (sstate)
470 si_set_sampler_state_desc(sstate, sview, is_buffer ? NULL : tex, desc + 12);
471 }
472 }
473
474 static bool color_needs_decompression(struct si_texture *tex)
475 {
476 return tex->surface.fmask_size ||
477 (tex->dirty_level_mask && (tex->cmask_buffer || tex->surface.dcc_offset));
478 }
479
480 static bool depth_needs_decompression(struct si_texture *tex)
481 {
482 /* If the depth/stencil texture is TC-compatible, no decompression
483 * will be done. The decompression function will only flush DB caches
484 * to make it coherent with shaders. That's necessary because the driver
485 * doesn't flush DB caches in any other case.
486 */
487 return tex->db_compatible;
488 }
489
490 static void si_set_sampler_view(struct si_context *sctx, unsigned shader, unsigned slot,
491 struct pipe_sampler_view *view, bool disallow_early_out)
492 {
493 struct si_samplers *samplers = &sctx->samplers[shader];
494 struct si_sampler_view *sview = (struct si_sampler_view *)view;
495 struct si_descriptors *descs = si_sampler_and_image_descriptors(sctx, shader);
496 unsigned desc_slot = si_get_sampler_slot(slot);
497 uint32_t *desc = descs->list + desc_slot * 16;
498
499 if (samplers->views[slot] == view && !disallow_early_out)
500 return;
501
502 if (view) {
503 struct si_texture *tex = (struct si_texture *)view->texture;
504
505 si_set_sampler_view_desc(sctx, sview, samplers->sampler_states[slot], desc);
506
507 if (tex->buffer.b.b.target == PIPE_BUFFER) {
508 tex->buffer.bind_history |= PIPE_BIND_SAMPLER_VIEW;
509 samplers->needs_depth_decompress_mask &= ~(1u << slot);
510 samplers->needs_color_decompress_mask &= ~(1u << slot);
511 } else {
512 if (depth_needs_decompression(tex)) {
513 samplers->needs_depth_decompress_mask |= 1u << slot;
514 } else {
515 samplers->needs_depth_decompress_mask &= ~(1u << slot);
516 }
517 if (color_needs_decompression(tex)) {
518 samplers->needs_color_decompress_mask |= 1u << slot;
519 } else {
520 samplers->needs_color_decompress_mask &= ~(1u << slot);
521 }
522
523 if (vi_dcc_enabled(tex, view->u.tex.first_level) &&
524 p_atomic_read(&tex->framebuffers_bound))
525 sctx->need_check_render_feedback = true;
526 }
527
528 pipe_sampler_view_reference(&samplers->views[slot], view);
529 samplers->enabled_mask |= 1u << slot;
530
531 /* Since this can flush, it must be done after enabled_mask is
532 * updated. */
533 si_sampler_view_add_buffer(sctx, view->texture, RADEON_USAGE_READ, sview->is_stencil_sampler,
534 true);
535 } else {
536 pipe_sampler_view_reference(&samplers->views[slot], NULL);
537 memcpy(desc, null_texture_descriptor, 8 * 4);
538 /* Only clear the lower dwords of FMASK. */
539 memcpy(desc + 8, null_texture_descriptor, 4 * 4);
540 /* Re-set the sampler state if we are transitioning from FMASK. */
541 if (samplers->sampler_states[slot])
542 si_set_sampler_state_desc(samplers->sampler_states[slot], NULL, NULL, desc + 12);
543
544 samplers->enabled_mask &= ~(1u << slot);
545 samplers->needs_depth_decompress_mask &= ~(1u << slot);
546 samplers->needs_color_decompress_mask &= ~(1u << slot);
547 }
548
549 sctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
550 }
551
552 static void si_update_shader_needs_decompress_mask(struct si_context *sctx, unsigned shader)
553 {
554 struct si_samplers *samplers = &sctx->samplers[shader];
555 unsigned shader_bit = 1 << shader;
556
557 if (samplers->needs_depth_decompress_mask || samplers->needs_color_decompress_mask ||
558 sctx->images[shader].needs_color_decompress_mask)
559 sctx->shader_needs_decompress_mask |= shader_bit;
560 else
561 sctx->shader_needs_decompress_mask &= ~shader_bit;
562 }
563
564 static void si_set_sampler_views(struct pipe_context *ctx, enum pipe_shader_type shader,
565 unsigned start, unsigned count, struct pipe_sampler_view **views)
566 {
567 struct si_context *sctx = (struct si_context *)ctx;
568 int i;
569
570 if (!count || shader >= SI_NUM_SHADERS)
571 return;
572
573 if (views) {
574 for (i = 0; i < count; i++)
575 si_set_sampler_view(sctx, shader, start + i, views[i], false);
576 } else {
577 for (i = 0; i < count; i++)
578 si_set_sampler_view(sctx, shader, start + i, NULL, false);
579 }
580
581 si_update_shader_needs_decompress_mask(sctx, shader);
582 }
583
584 static void si_samplers_update_needs_color_decompress_mask(struct si_samplers *samplers)
585 {
586 unsigned mask = samplers->enabled_mask;
587
588 while (mask) {
589 int i = u_bit_scan(&mask);
590 struct pipe_resource *res = samplers->views[i]->texture;
591
592 if (res && res->target != PIPE_BUFFER) {
593 struct si_texture *tex = (struct si_texture *)res;
594
595 if (color_needs_decompression(tex)) {
596 samplers->needs_color_decompress_mask |= 1u << i;
597 } else {
598 samplers->needs_color_decompress_mask &= ~(1u << i);
599 }
600 }
601 }
602 }
603
604 /* IMAGE VIEWS */
605
606 static void si_release_image_views(struct si_images *images)
607 {
608 unsigned i;
609
610 for (i = 0; i < SI_NUM_IMAGES; ++i) {
611 struct pipe_image_view *view = &images->views[i];
612
613 pipe_resource_reference(&view->resource, NULL);
614 }
615 }
616
617 static void si_image_views_begin_new_cs(struct si_context *sctx, struct si_images *images)
618 {
619 uint mask = images->enabled_mask;
620
621 /* Add buffers to the CS. */
622 while (mask) {
623 int i = u_bit_scan(&mask);
624 struct pipe_image_view *view = &images->views[i];
625
626 assert(view->resource);
627
628 si_sampler_view_add_buffer(sctx, view->resource, RADEON_USAGE_READWRITE, false, false);
629 }
630 }
631
632 static bool si_image_views_check_encrypted(struct si_context *sctx, struct si_images *images,
633 unsigned images_declared)
634 {
635 uint mask = images->enabled_mask & images_declared;
636
637 while (mask) {
638 int i = u_bit_scan(&mask);
639 struct pipe_image_view *view = &images->views[i];
640
641 assert(view->resource);
642
643 struct si_texture *tex = (struct si_texture *)view->resource;
644 if (tex->buffer.flags & RADEON_FLAG_ENCRYPTED)
645 return true;
646 }
647 return false;
648 }
649
650 static void si_disable_shader_image(struct si_context *ctx, unsigned shader, unsigned slot)
651 {
652 struct si_images *images = &ctx->images[shader];
653
654 if (images->enabled_mask & (1u << slot)) {
655 struct si_descriptors *descs = si_sampler_and_image_descriptors(ctx, shader);
656 unsigned desc_slot = si_get_image_slot(slot);
657
658 pipe_resource_reference(&images->views[slot].resource, NULL);
659 images->needs_color_decompress_mask &= ~(1 << slot);
660
661 memcpy(descs->list + desc_slot * 8, null_image_descriptor, 8 * 4);
662 images->enabled_mask &= ~(1u << slot);
663 ctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
664 }
665 }
666
667 static void si_mark_image_range_valid(const struct pipe_image_view *view)
668 {
669 struct si_resource *res = si_resource(view->resource);
670
671 if (res->b.b.target != PIPE_BUFFER)
672 return;
673
674 util_range_add(&res->b.b, &res->valid_buffer_range, view->u.buf.offset,
675 view->u.buf.offset + view->u.buf.size);
676 }
677
678 static void si_set_shader_image_desc(struct si_context *ctx, const struct pipe_image_view *view,
679 bool skip_decompress, uint32_t *desc, uint32_t *fmask_desc)
680 {
681 struct si_screen *screen = ctx->screen;
682 struct si_resource *res;
683
684 res = si_resource(view->resource);
685
686 if (res->b.b.target == PIPE_BUFFER || view->shader_access & SI_IMAGE_ACCESS_AS_BUFFER) {
687 if (view->access & PIPE_IMAGE_ACCESS_WRITE)
688 si_mark_image_range_valid(view);
689
690 si_make_buffer_descriptor(screen, res, view->format, view->u.buf.offset, view->u.buf.size,
691 desc);
692 si_set_buf_desc_address(res, view->u.buf.offset, desc + 4);
693 } else {
694 static const unsigned char swizzle[4] = {0, 1, 2, 3};
695 struct si_texture *tex = (struct si_texture *)res;
696 unsigned level = view->u.tex.level;
697 unsigned width, height, depth, hw_level;
698 bool uses_dcc = vi_dcc_enabled(tex, level);
699 unsigned access = view->access;
700
701 assert(!tex->is_depth);
702 assert(fmask_desc || tex->surface.fmask_offset == 0);
703
704 if (uses_dcc && !skip_decompress &&
705 !(access & SI_IMAGE_ACCESS_DCC_OFF) &&
706 (access & PIPE_IMAGE_ACCESS_WRITE ||
707 !vi_dcc_formats_compatible(screen, res->b.b.format, view->format))) {
708 /* If DCC can't be disabled, at least decompress it.
709 * The decompression is relatively cheap if the surface
710 * has been decompressed already.
711 */
712 if (!si_texture_disable_dcc(ctx, tex))
713 si_decompress_dcc(ctx, tex);
714 }
715
716 if (ctx->chip_class >= GFX9) {
717 /* Always set the base address. The swizzle modes don't
718 * allow setting mipmap level offsets as the base.
719 */
720 width = res->b.b.width0;
721 height = res->b.b.height0;
722 depth = res->b.b.depth0;
723 hw_level = level;
724 } else {
725 /* Always force the base level to the selected level.
726 *
727 * This is required for 3D textures, where otherwise
728 * selecting a single slice for non-layered bindings
729 * fails. It doesn't hurt the other targets.
730 */
731 width = u_minify(res->b.b.width0, level);
732 height = u_minify(res->b.b.height0, level);
733 depth = u_minify(res->b.b.depth0, level);
734 hw_level = 0;
735 }
736
737 screen->make_texture_descriptor(
738 screen, tex, false, res->b.b.target, view->format, swizzle, hw_level, hw_level,
739 view->u.tex.first_layer, view->u.tex.last_layer, width, height, depth, desc, fmask_desc);
740 si_set_mutable_tex_desc_fields(screen, tex, &tex->surface.u.legacy.level[level], level, level,
741 util_format_get_blockwidth(view->format), false,
742 view->access & SI_IMAGE_ACCESS_DCC_OFF, desc);
743 }
744 }
745
746 static void si_set_shader_image(struct si_context *ctx, unsigned shader, unsigned slot,
747 const struct pipe_image_view *view, bool skip_decompress)
748 {
749 struct si_images *images = &ctx->images[shader];
750 struct si_descriptors *descs = si_sampler_and_image_descriptors(ctx, shader);
751 struct si_resource *res;
752
753 if (!view || !view->resource) {
754 si_disable_shader_image(ctx, shader, slot);
755 return;
756 }
757
758 res = si_resource(view->resource);
759
760 si_set_shader_image_desc(ctx, view, skip_decompress, descs->list + si_get_image_slot(slot) * 8,
761 descs->list + si_get_image_slot(slot + SI_NUM_IMAGES) * 8);
762
763 if (&images->views[slot] != view)
764 util_copy_image_view(&images->views[slot], view);
765
766 if (res->b.b.target == PIPE_BUFFER || view->shader_access & SI_IMAGE_ACCESS_AS_BUFFER) {
767 images->needs_color_decompress_mask &= ~(1 << slot);
768 res->bind_history |= PIPE_BIND_SHADER_IMAGE;
769 } else {
770 struct si_texture *tex = (struct si_texture *)res;
771 unsigned level = view->u.tex.level;
772
773 if (color_needs_decompression(tex)) {
774 images->needs_color_decompress_mask |= 1 << slot;
775 } else {
776 images->needs_color_decompress_mask &= ~(1 << slot);
777 }
778
779 if (vi_dcc_enabled(tex, level) && p_atomic_read(&tex->framebuffers_bound))
780 ctx->need_check_render_feedback = true;
781 }
782
783 images->enabled_mask |= 1u << slot;
784 ctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
785
786 /* Since this can flush, it must be done after enabled_mask is updated. */
787 si_sampler_view_add_buffer(
788 ctx, &res->b.b,
789 (view->access & PIPE_IMAGE_ACCESS_WRITE) ? RADEON_USAGE_READWRITE : RADEON_USAGE_READ, false,
790 true);
791 }
792
793 static void si_set_shader_images(struct pipe_context *pipe, enum pipe_shader_type shader,
794 unsigned start_slot, unsigned count,
795 const struct pipe_image_view *views)
796 {
797 struct si_context *ctx = (struct si_context *)pipe;
798 unsigned i, slot;
799
800 assert(shader < SI_NUM_SHADERS);
801
802 if (!count)
803 return;
804
805 assert(start_slot + count <= SI_NUM_IMAGES);
806
807 if (views) {
808 for (i = 0, slot = start_slot; i < count; ++i, ++slot)
809 si_set_shader_image(ctx, shader, slot, &views[i], false);
810 } else {
811 for (i = 0, slot = start_slot; i < count; ++i, ++slot)
812 si_set_shader_image(ctx, shader, slot, NULL, false);
813 }
814
815 if (shader == PIPE_SHADER_COMPUTE &&
816 ctx->cs_shader_state.program &&
817 start_slot < ctx->cs_shader_state.program->sel.cs_num_images_in_user_sgprs)
818 ctx->compute_image_sgprs_dirty = true;
819
820 si_update_shader_needs_decompress_mask(ctx, shader);
821 }
822
823 static void si_images_update_needs_color_decompress_mask(struct si_images *images)
824 {
825 unsigned mask = images->enabled_mask;
826
827 while (mask) {
828 int i = u_bit_scan(&mask);
829 struct pipe_resource *res = images->views[i].resource;
830
831 if (res && res->target != PIPE_BUFFER) {
832 struct si_texture *tex = (struct si_texture *)res;
833
834 if (color_needs_decompression(tex)) {
835 images->needs_color_decompress_mask |= 1 << i;
836 } else {
837 images->needs_color_decompress_mask &= ~(1 << i);
838 }
839 }
840 }
841 }
842
843 void si_update_ps_colorbuf0_slot(struct si_context *sctx)
844 {
845 struct si_buffer_resources *buffers = &sctx->rw_buffers;
846 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
847 unsigned slot = SI_PS_IMAGE_COLORBUF0;
848 struct pipe_surface *surf = NULL;
849
850 /* si_texture_disable_dcc can get us here again. */
851 if (sctx->blitter->running)
852 return;
853
854 /* See whether FBFETCH is used and color buffer 0 is set. */
855 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_fbfetch &&
856 sctx->framebuffer.state.nr_cbufs && sctx->framebuffer.state.cbufs[0])
857 surf = sctx->framebuffer.state.cbufs[0];
858
859 /* Return if FBFETCH transitions from disabled to disabled. */
860 if (!buffers->buffers[slot] && !surf)
861 return;
862
863 sctx->ps_uses_fbfetch = surf != NULL;
864 si_update_ps_iter_samples(sctx);
865
866 if (surf) {
867 struct si_texture *tex = (struct si_texture *)surf->texture;
868 struct pipe_image_view view = {0};
869
870 assert(tex);
871 assert(!tex->is_depth);
872
873 /* Disable DCC, because the texture is used as both a sampler
874 * and color buffer.
875 */
876 si_texture_disable_dcc(sctx, tex);
877
878 if (tex->buffer.b.b.nr_samples <= 1 && tex->cmask_buffer) {
879 /* Disable CMASK. */
880 assert(tex->cmask_buffer != &tex->buffer);
881 si_eliminate_fast_color_clear(sctx, tex, NULL);
882 si_texture_discard_cmask(sctx->screen, tex);
883 }
884
885 view.resource = surf->texture;
886 view.format = surf->format;
887 view.access = PIPE_IMAGE_ACCESS_READ;
888 view.u.tex.first_layer = surf->u.tex.first_layer;
889 view.u.tex.last_layer = surf->u.tex.last_layer;
890 view.u.tex.level = surf->u.tex.level;
891
892 /* Set the descriptor. */
893 uint32_t *desc = descs->list + slot * 4;
894 memset(desc, 0, 16 * 4);
895 si_set_shader_image_desc(sctx, &view, true, desc, desc + 8);
896
897 pipe_resource_reference(&buffers->buffers[slot], &tex->buffer.b.b);
898 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READ,
899 RADEON_PRIO_SHADER_RW_IMAGE);
900 buffers->enabled_mask |= 1u << slot;
901 } else {
902 /* Clear the descriptor. */
903 memset(descs->list + slot * 4, 0, 8 * 4);
904 pipe_resource_reference(&buffers->buffers[slot], NULL);
905 buffers->enabled_mask &= ~(1u << slot);
906 }
907
908 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
909 }
910
911 /* SAMPLER STATES */
912
913 static void si_bind_sampler_states(struct pipe_context *ctx, enum pipe_shader_type shader,
914 unsigned start, unsigned count, void **states)
915 {
916 struct si_context *sctx = (struct si_context *)ctx;
917 struct si_samplers *samplers = &sctx->samplers[shader];
918 struct si_descriptors *desc = si_sampler_and_image_descriptors(sctx, shader);
919 struct si_sampler_state **sstates = (struct si_sampler_state **)states;
920 int i;
921
922 if (!count || shader >= SI_NUM_SHADERS || !sstates)
923 return;
924
925 for (i = 0; i < count; i++) {
926 unsigned slot = start + i;
927 unsigned desc_slot = si_get_sampler_slot(slot);
928
929 if (!sstates[i] || sstates[i] == samplers->sampler_states[slot])
930 continue;
931
932 #ifndef NDEBUG
933 assert(sstates[i]->magic == SI_SAMPLER_STATE_MAGIC);
934 #endif
935 samplers->sampler_states[slot] = sstates[i];
936
937 /* If FMASK is bound, don't overwrite it.
938 * The sampler state will be set after FMASK is unbound.
939 */
940 struct si_sampler_view *sview = (struct si_sampler_view *)samplers->views[slot];
941
942 struct si_texture *tex = NULL;
943
944 if (sview && sview->base.texture && sview->base.texture->target != PIPE_BUFFER)
945 tex = (struct si_texture *)sview->base.texture;
946
947 if (tex && tex->surface.fmask_size)
948 continue;
949
950 si_set_sampler_state_desc(sstates[i], sview, tex, desc->list + desc_slot * 16 + 12);
951
952 sctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
953 }
954 }
955
956 /* BUFFER RESOURCES */
957
958 static void si_init_buffer_resources(struct si_buffer_resources *buffers,
959 struct si_descriptors *descs, unsigned num_buffers,
960 short shader_userdata_rel_index,
961 enum radeon_bo_priority priority,
962 enum radeon_bo_priority priority_constbuf)
963 {
964 buffers->priority = priority;
965 buffers->priority_constbuf = priority_constbuf;
966 buffers->buffers = CALLOC(num_buffers, sizeof(struct pipe_resource *));
967 buffers->offsets = CALLOC(num_buffers, sizeof(buffers->offsets[0]));
968
969 si_init_descriptors(descs, shader_userdata_rel_index, 4, num_buffers);
970 }
971
972 static void si_release_buffer_resources(struct si_buffer_resources *buffers,
973 struct si_descriptors *descs)
974 {
975 int i;
976
977 for (i = 0; i < descs->num_elements; i++) {
978 pipe_resource_reference(&buffers->buffers[i], NULL);
979 }
980
981 FREE(buffers->buffers);
982 FREE(buffers->offsets);
983 }
984
985 static void si_buffer_resources_begin_new_cs(struct si_context *sctx,
986 struct si_buffer_resources *buffers)
987 {
988 unsigned mask = buffers->enabled_mask;
989
990 /* Add buffers to the CS. */
991 while (mask) {
992 int i = u_bit_scan(&mask);
993
994 radeon_add_to_buffer_list(
995 sctx, sctx->gfx_cs, si_resource(buffers->buffers[i]),
996 buffers->writable_mask & (1u << i) ? RADEON_USAGE_READWRITE : RADEON_USAGE_READ,
997 i < SI_NUM_SHADER_BUFFERS ? buffers->priority : buffers->priority_constbuf);
998 }
999 }
1000
1001 static bool si_buffer_resources_check_encrypted(struct si_context *sctx,
1002 struct si_buffer_resources *buffers)
1003 {
1004 unsigned mask = buffers->enabled_mask;
1005
1006 while (mask) {
1007 int i = u_bit_scan(&mask);
1008
1009 /* only check for reads */
1010 if ((buffers->writable_mask & (1u << i)) == 0 &&
1011 (si_resource(buffers->buffers[i])->flags & RADEON_FLAG_ENCRYPTED))
1012 return true;
1013 }
1014
1015 return false;
1016 }
1017
1018 static void si_get_buffer_from_descriptors(struct si_buffer_resources *buffers,
1019 struct si_descriptors *descs, unsigned idx,
1020 struct pipe_resource **buf, unsigned *offset,
1021 unsigned *size)
1022 {
1023 pipe_resource_reference(buf, buffers->buffers[idx]);
1024 if (*buf) {
1025 struct si_resource *res = si_resource(*buf);
1026 const uint32_t *desc = descs->list + idx * 4;
1027 uint64_t va;
1028
1029 *size = desc[2];
1030
1031 assert(G_008F04_STRIDE(desc[1]) == 0);
1032 va = si_desc_extract_buffer_address(desc);
1033
1034 assert(va >= res->gpu_address && va + *size <= res->gpu_address + res->bo_size);
1035 *offset = va - res->gpu_address;
1036 }
1037 }
1038
1039 /* VERTEX BUFFERS */
1040
1041 static void si_vertex_buffers_begin_new_cs(struct si_context *sctx)
1042 {
1043 int count = sctx->num_vertex_elements;
1044 int i;
1045
1046 for (i = 0; i < count; i++) {
1047 int vb = sctx->vertex_elements->vertex_buffer_index[i];
1048
1049 if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
1050 continue;
1051 if (!sctx->vertex_buffer[vb].buffer.resource)
1052 continue;
1053
1054 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
1055 si_resource(sctx->vertex_buffer[vb].buffer.resource),
1056 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
1057 }
1058
1059 if (!sctx->vb_descriptors_buffer)
1060 return;
1061 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, sctx->vb_descriptors_buffer, RADEON_USAGE_READ,
1062 RADEON_PRIO_DESCRIPTORS);
1063 }
1064
1065 bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
1066 {
1067 unsigned i, count = sctx->num_vertex_elements;
1068 uint32_t *ptr;
1069
1070 if (!sctx->vertex_buffers_dirty || !count)
1071 return true;
1072
1073 struct si_vertex_elements *velems = sctx->vertex_elements;
1074 unsigned alloc_size = velems->vb_desc_list_alloc_size;
1075
1076 if (alloc_size) {
1077 /* Vertex buffer descriptors are the only ones which are uploaded
1078 * directly through a staging buffer and don't go through
1079 * the fine-grained upload path.
1080 */
1081 u_upload_alloc(sctx->b.const_uploader, 0, alloc_size,
1082 si_optimal_tcc_alignment(sctx, alloc_size), &sctx->vb_descriptors_offset,
1083 (struct pipe_resource **)&sctx->vb_descriptors_buffer, (void **)&ptr);
1084 if (!sctx->vb_descriptors_buffer) {
1085 sctx->vb_descriptors_offset = 0;
1086 sctx->vb_descriptors_gpu_list = NULL;
1087 return false;
1088 }
1089
1090 sctx->vb_descriptors_gpu_list = ptr;
1091 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, sctx->vb_descriptors_buffer, RADEON_USAGE_READ,
1092 RADEON_PRIO_DESCRIPTORS);
1093 sctx->vertex_buffer_pointer_dirty = true;
1094 sctx->prefetch_L2_mask |= SI_PREFETCH_VBO_DESCRIPTORS;
1095 } else {
1096 si_resource_reference(&sctx->vb_descriptors_buffer, NULL);
1097 sctx->vertex_buffer_pointer_dirty = false;
1098 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VBO_DESCRIPTORS;
1099 }
1100
1101 assert(count <= SI_MAX_ATTRIBS);
1102
1103 unsigned first_vb_use_mask = velems->first_vb_use_mask;
1104 unsigned num_vbos_in_user_sgprs = sctx->screen->num_vbos_in_user_sgprs;
1105
1106 for (i = 0; i < count; i++) {
1107 struct pipe_vertex_buffer *vb;
1108 struct si_resource *buf;
1109 unsigned vbo_index = velems->vertex_buffer_index[i];
1110 uint32_t *desc = i < num_vbos_in_user_sgprs ? &sctx->vb_descriptor_user_sgprs[i * 4]
1111 : &ptr[(i - num_vbos_in_user_sgprs) * 4];
1112
1113 vb = &sctx->vertex_buffer[vbo_index];
1114 buf = si_resource(vb->buffer.resource);
1115 if (!buf) {
1116 memset(desc, 0, 16);
1117 continue;
1118 }
1119
1120 int64_t offset = (int64_t)((int)vb->buffer_offset) + velems->src_offset[i];
1121
1122 if (offset >= buf->b.b.width0) {
1123 assert(offset < buf->b.b.width0);
1124 memset(desc, 0, 16);
1125 continue;
1126 }
1127
1128 uint64_t va = buf->gpu_address + offset;
1129
1130 int64_t num_records = (int64_t)buf->b.b.width0 - offset;
1131 if (sctx->chip_class != GFX8 && vb->stride) {
1132 /* Round up by rounding down and adding 1 */
1133 num_records = (num_records - velems->format_size[i]) / vb->stride + 1;
1134 }
1135 assert(num_records >= 0 && num_records <= UINT_MAX);
1136
1137 uint32_t rsrc_word3 = velems->rsrc_word3[i];
1138
1139 /* OOB_SELECT chooses the out-of-bounds check:
1140 * - 1: index >= NUM_RECORDS (Structured)
1141 * - 3: offset >= NUM_RECORDS (Raw)
1142 */
1143 if (sctx->chip_class >= GFX10)
1144 rsrc_word3 |= S_008F0C_OOB_SELECT(vb->stride ? V_008F0C_OOB_SELECT_STRUCTURED
1145 : V_008F0C_OOB_SELECT_RAW);
1146
1147 desc[0] = va;
1148 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(vb->stride);
1149 desc[2] = num_records;
1150 desc[3] = rsrc_word3;
1151
1152 if (first_vb_use_mask & (1 << i)) {
1153 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, si_resource(vb->buffer.resource),
1154 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
1155 }
1156 }
1157
1158 /* Don't flush the const cache. It would have a very negative effect
1159 * on performance (confirmed by testing). New descriptors are always
1160 * uploaded to a fresh new buffer, so I don't think flushing the const
1161 * cache is needed. */
1162 si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
1163 sctx->vertex_buffer_user_sgprs_dirty = num_vbos_in_user_sgprs > 0;
1164 sctx->vertex_buffers_dirty = false;
1165 return true;
1166 }
1167
1168 /* CONSTANT BUFFERS */
1169
1170 static struct si_descriptors *si_const_and_shader_buffer_descriptors(struct si_context *sctx,
1171 unsigned shader)
1172 {
1173 return &sctx->descriptors[si_const_and_shader_buffer_descriptors_idx(shader)];
1174 }
1175
1176 void si_upload_const_buffer(struct si_context *sctx, struct si_resource **buf, const uint8_t *ptr,
1177 unsigned size, uint32_t *const_offset)
1178 {
1179 void *tmp;
1180
1181 u_upload_alloc(sctx->b.const_uploader, 0, size, si_optimal_tcc_alignment(sctx, size),
1182 const_offset, (struct pipe_resource **)buf, &tmp);
1183 if (*buf)
1184 util_memcpy_cpu_to_le32(tmp, ptr, size);
1185 }
1186
1187 static void si_set_constant_buffer(struct si_context *sctx, struct si_buffer_resources *buffers,
1188 unsigned descriptors_idx, uint slot,
1189 const struct pipe_constant_buffer *input)
1190 {
1191 struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
1192 assert(slot < descs->num_elements);
1193 pipe_resource_reference(&buffers->buffers[slot], NULL);
1194
1195 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1196 * with a NULL buffer). We need to use a dummy buffer instead. */
1197 if (sctx->chip_class == GFX7 && (!input || (!input->buffer && !input->user_buffer)))
1198 input = &sctx->null_const_buf;
1199
1200 if (input && (input->buffer || input->user_buffer)) {
1201 struct pipe_resource *buffer = NULL;
1202 uint64_t va;
1203 unsigned buffer_offset;
1204
1205 /* Upload the user buffer if needed. */
1206 if (input->user_buffer) {
1207 si_upload_const_buffer(sctx, (struct si_resource **)&buffer, input->user_buffer,
1208 input->buffer_size, &buffer_offset);
1209 if (!buffer) {
1210 /* Just unbind on failure. */
1211 si_set_constant_buffer(sctx, buffers, descriptors_idx, slot, NULL);
1212 return;
1213 }
1214 } else {
1215 pipe_resource_reference(&buffer, input->buffer);
1216 buffer_offset = input->buffer_offset;
1217 }
1218
1219 va = si_resource(buffer)->gpu_address + buffer_offset;
1220
1221 /* Set the descriptor. */
1222 uint32_t *desc = descs->list + slot * 4;
1223 desc[0] = va;
1224 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(0);
1225 desc[2] = input->buffer_size;
1226 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1227 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
1228
1229 if (sctx->chip_class >= GFX10) {
1230 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
1231 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | S_008F0C_RESOURCE_LEVEL(1);
1232 } else {
1233 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1234 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1235 }
1236
1237 buffers->buffers[slot] = buffer;
1238 buffers->offsets[slot] = buffer_offset;
1239 radeon_add_to_gfx_buffer_list_check_mem(sctx, si_resource(buffer), RADEON_USAGE_READ,
1240 buffers->priority_constbuf, true);
1241 buffers->enabled_mask |= 1u << slot;
1242 } else {
1243 /* Clear the descriptor. */
1244 memset(descs->list + slot * 4, 0, sizeof(uint32_t) * 4);
1245 buffers->enabled_mask &= ~(1u << slot);
1246 }
1247
1248 sctx->descriptors_dirty |= 1u << descriptors_idx;
1249 }
1250
1251 static void si_pipe_set_constant_buffer(struct pipe_context *ctx, enum pipe_shader_type shader,
1252 uint slot, const struct pipe_constant_buffer *input)
1253 {
1254 struct si_context *sctx = (struct si_context *)ctx;
1255
1256 if (shader >= SI_NUM_SHADERS)
1257 return;
1258
1259 if (slot == 0 && input && input->buffer &&
1260 !(si_resource(input->buffer)->flags & RADEON_FLAG_32BIT)) {
1261 assert(!"constant buffer 0 must have a 32-bit VM address, use const_uploader");
1262 return;
1263 }
1264
1265 if (input && input->buffer)
1266 si_resource(input->buffer)->bind_history |= PIPE_BIND_CONSTANT_BUFFER;
1267
1268 slot = si_get_constbuf_slot(slot);
1269 si_set_constant_buffer(sctx, &sctx->const_and_shader_buffers[shader],
1270 si_const_and_shader_buffer_descriptors_idx(shader), slot, input);
1271 }
1272
1273 void si_get_pipe_constant_buffer(struct si_context *sctx, uint shader, uint slot,
1274 struct pipe_constant_buffer *cbuf)
1275 {
1276 cbuf->user_buffer = NULL;
1277 si_get_buffer_from_descriptors(
1278 &sctx->const_and_shader_buffers[shader], si_const_and_shader_buffer_descriptors(sctx, shader),
1279 si_get_constbuf_slot(slot), &cbuf->buffer, &cbuf->buffer_offset, &cbuf->buffer_size);
1280 }
1281
1282 /* SHADER BUFFERS */
1283
1284 static void si_set_shader_buffer(struct si_context *sctx, struct si_buffer_resources *buffers,
1285 unsigned descriptors_idx, uint slot,
1286 const struct pipe_shader_buffer *sbuffer, bool writable,
1287 enum radeon_bo_priority priority)
1288 {
1289 struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
1290 uint32_t *desc = descs->list + slot * 4;
1291
1292 if (!sbuffer || !sbuffer->buffer) {
1293 pipe_resource_reference(&buffers->buffers[slot], NULL);
1294 memset(desc, 0, sizeof(uint32_t) * 4);
1295 buffers->enabled_mask &= ~(1u << slot);
1296 buffers->writable_mask &= ~(1u << slot);
1297 sctx->descriptors_dirty |= 1u << descriptors_idx;
1298 return;
1299 }
1300
1301 struct si_resource *buf = si_resource(sbuffer->buffer);
1302 uint64_t va = buf->gpu_address + sbuffer->buffer_offset;
1303
1304 desc[0] = va;
1305 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(0);
1306 desc[2] = sbuffer->buffer_size;
1307 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1308 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
1309
1310 if (sctx->chip_class >= GFX10) {
1311 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
1312 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | S_008F0C_RESOURCE_LEVEL(1);
1313 } else {
1314 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1315 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1316 }
1317
1318 pipe_resource_reference(&buffers->buffers[slot], &buf->b.b);
1319 buffers->offsets[slot] = sbuffer->buffer_offset;
1320 radeon_add_to_gfx_buffer_list_check_mem(
1321 sctx, buf, writable ? RADEON_USAGE_READWRITE : RADEON_USAGE_READ, priority, true);
1322 if (writable)
1323 buffers->writable_mask |= 1u << slot;
1324 else
1325 buffers->writable_mask &= ~(1u << slot);
1326
1327 buffers->enabled_mask |= 1u << slot;
1328 sctx->descriptors_dirty |= 1u << descriptors_idx;
1329
1330 util_range_add(&buf->b.b, &buf->valid_buffer_range, sbuffer->buffer_offset,
1331 sbuffer->buffer_offset + sbuffer->buffer_size);
1332 }
1333
1334 static void si_set_shader_buffers(struct pipe_context *ctx, enum pipe_shader_type shader,
1335 unsigned start_slot, unsigned count,
1336 const struct pipe_shader_buffer *sbuffers,
1337 unsigned writable_bitmask)
1338 {
1339 struct si_context *sctx = (struct si_context *)ctx;
1340 struct si_buffer_resources *buffers = &sctx->const_and_shader_buffers[shader];
1341 unsigned descriptors_idx = si_const_and_shader_buffer_descriptors_idx(shader);
1342 unsigned i;
1343
1344 assert(start_slot + count <= SI_NUM_SHADER_BUFFERS);
1345
1346 if (shader == PIPE_SHADER_COMPUTE &&
1347 sctx->cs_shader_state.program &&
1348 start_slot < sctx->cs_shader_state.program->sel.cs_num_shaderbufs_in_user_sgprs)
1349 sctx->compute_shaderbuf_sgprs_dirty = true;
1350
1351 for (i = 0; i < count; ++i) {
1352 const struct pipe_shader_buffer *sbuffer = sbuffers ? &sbuffers[i] : NULL;
1353 unsigned slot = si_get_shaderbuf_slot(start_slot + i);
1354
1355 if (sbuffer && sbuffer->buffer)
1356 si_resource(sbuffer->buffer)->bind_history |= PIPE_BIND_SHADER_BUFFER;
1357
1358 si_set_shader_buffer(sctx, buffers, descriptors_idx, slot, sbuffer,
1359 !!(writable_bitmask & (1u << i)), buffers->priority);
1360 }
1361 }
1362
1363 void si_get_shader_buffers(struct si_context *sctx, enum pipe_shader_type shader, uint start_slot,
1364 uint count, struct pipe_shader_buffer *sbuf)
1365 {
1366 struct si_buffer_resources *buffers = &sctx->const_and_shader_buffers[shader];
1367 struct si_descriptors *descs = si_const_and_shader_buffer_descriptors(sctx, shader);
1368
1369 for (unsigned i = 0; i < count; ++i) {
1370 si_get_buffer_from_descriptors(buffers, descs, si_get_shaderbuf_slot(start_slot + i),
1371 &sbuf[i].buffer, &sbuf[i].buffer_offset, &sbuf[i].buffer_size);
1372 }
1373 }
1374
1375 /* RING BUFFERS */
1376
1377 void si_set_rw_buffer(struct si_context *sctx, uint slot, const struct pipe_constant_buffer *input)
1378 {
1379 si_set_constant_buffer(sctx, &sctx->rw_buffers, SI_DESCS_RW_BUFFERS, slot, input);
1380 }
1381
1382 void si_set_rw_shader_buffer(struct si_context *sctx, uint slot,
1383 const struct pipe_shader_buffer *sbuffer)
1384 {
1385 si_set_shader_buffer(sctx, &sctx->rw_buffers, SI_DESCS_RW_BUFFERS, slot, sbuffer, true,
1386 RADEON_PRIO_SHADER_RW_BUFFER);
1387 }
1388
1389 void si_set_ring_buffer(struct si_context *sctx, uint slot, struct pipe_resource *buffer,
1390 unsigned stride, unsigned num_records, bool add_tid, bool swizzle,
1391 unsigned element_size, unsigned index_stride, uint64_t offset)
1392 {
1393 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1394 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1395
1396 /* The stride field in the resource descriptor has 14 bits */
1397 assert(stride < (1 << 14));
1398
1399 assert(slot < descs->num_elements);
1400 pipe_resource_reference(&buffers->buffers[slot], NULL);
1401
1402 if (buffer) {
1403 uint64_t va;
1404
1405 va = si_resource(buffer)->gpu_address + offset;
1406
1407 switch (element_size) {
1408 default:
1409 assert(!"Unsupported ring buffer element size");
1410 case 0:
1411 case 2:
1412 element_size = 0;
1413 break;
1414 case 4:
1415 element_size = 1;
1416 break;
1417 case 8:
1418 element_size = 2;
1419 break;
1420 case 16:
1421 element_size = 3;
1422 break;
1423 }
1424
1425 switch (index_stride) {
1426 default:
1427 assert(!"Unsupported ring buffer index stride");
1428 case 0:
1429 case 8:
1430 index_stride = 0;
1431 break;
1432 case 16:
1433 index_stride = 1;
1434 break;
1435 case 32:
1436 index_stride = 2;
1437 break;
1438 case 64:
1439 index_stride = 3;
1440 break;
1441 }
1442
1443 if (sctx->chip_class >= GFX8 && stride)
1444 num_records *= stride;
1445
1446 /* Set the descriptor. */
1447 uint32_t *desc = descs->list + slot * 4;
1448 desc[0] = va;
1449 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride) |
1450 S_008F04_SWIZZLE_ENABLE(swizzle);
1451 desc[2] = num_records;
1452 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1453 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1454 S_008F0C_INDEX_STRIDE(index_stride) | S_008F0C_ADD_TID_ENABLE(add_tid);
1455
1456 if (sctx->chip_class >= GFX9)
1457 assert(!swizzle || element_size == 1); /* always 4 bytes on GFX9 */
1458 else
1459 desc[3] |= S_008F0C_ELEMENT_SIZE(element_size);
1460
1461 if (sctx->chip_class >= GFX10) {
1462 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
1463 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) | S_008F0C_RESOURCE_LEVEL(1);
1464 } else {
1465 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1466 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1467 }
1468
1469 pipe_resource_reference(&buffers->buffers[slot], buffer);
1470 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, si_resource(buffer), RADEON_USAGE_READWRITE,
1471 buffers->priority);
1472 buffers->enabled_mask |= 1u << slot;
1473 } else {
1474 /* Clear the descriptor. */
1475 memset(descs->list + slot * 4, 0, sizeof(uint32_t) * 4);
1476 buffers->enabled_mask &= ~(1u << slot);
1477 }
1478
1479 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
1480 }
1481
1482 /* INTERNAL CONST BUFFERS */
1483
1484 static void si_set_polygon_stipple(struct pipe_context *ctx, const struct pipe_poly_stipple *state)
1485 {
1486 struct si_context *sctx = (struct si_context *)ctx;
1487 struct pipe_constant_buffer cb = {};
1488 unsigned stipple[32];
1489 int i;
1490
1491 for (i = 0; i < 32; i++)
1492 stipple[i] = util_bitreverse(state->stipple[i]);
1493
1494 cb.user_buffer = stipple;
1495 cb.buffer_size = sizeof(stipple);
1496
1497 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE, &cb);
1498 }
1499
1500 /* TEXTURE METADATA ENABLE/DISABLE */
1501
1502 static void si_resident_handles_update_needs_color_decompress(struct si_context *sctx)
1503 {
1504 util_dynarray_clear(&sctx->resident_tex_needs_color_decompress);
1505 util_dynarray_clear(&sctx->resident_img_needs_color_decompress);
1506
1507 util_dynarray_foreach (&sctx->resident_tex_handles, struct si_texture_handle *, tex_handle) {
1508 struct pipe_resource *res = (*tex_handle)->view->texture;
1509 struct si_texture *tex;
1510
1511 if (!res || res->target == PIPE_BUFFER)
1512 continue;
1513
1514 tex = (struct si_texture *)res;
1515 if (!color_needs_decompression(tex))
1516 continue;
1517
1518 util_dynarray_append(&sctx->resident_tex_needs_color_decompress, struct si_texture_handle *,
1519 *tex_handle);
1520 }
1521
1522 util_dynarray_foreach (&sctx->resident_img_handles, struct si_image_handle *, img_handle) {
1523 struct pipe_image_view *view = &(*img_handle)->view;
1524 struct pipe_resource *res = view->resource;
1525 struct si_texture *tex;
1526
1527 if (!res || res->target == PIPE_BUFFER)
1528 continue;
1529
1530 tex = (struct si_texture *)res;
1531 if (!color_needs_decompression(tex))
1532 continue;
1533
1534 util_dynarray_append(&sctx->resident_img_needs_color_decompress, struct si_image_handle *,
1535 *img_handle);
1536 }
1537 }
1538
1539 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1540 * while the texture is bound, possibly by a different context. In that case,
1541 * call this function to update needs_*_decompress_masks.
1542 */
1543 void si_update_needs_color_decompress_masks(struct si_context *sctx)
1544 {
1545 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
1546 si_samplers_update_needs_color_decompress_mask(&sctx->samplers[i]);
1547 si_images_update_needs_color_decompress_mask(&sctx->images[i]);
1548 si_update_shader_needs_decompress_mask(sctx, i);
1549 }
1550
1551 si_resident_handles_update_needs_color_decompress(sctx);
1552 }
1553
1554 /* BUFFER DISCARD/INVALIDATION */
1555
1556 /* Reset descriptors of buffer resources after \p buf has been invalidated.
1557 * If buf == NULL, reset all descriptors.
1558 */
1559 static void si_reset_buffer_resources(struct si_context *sctx, struct si_buffer_resources *buffers,
1560 unsigned descriptors_idx, unsigned slot_mask,
1561 struct pipe_resource *buf, enum radeon_bo_priority priority)
1562 {
1563 struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
1564 unsigned mask = buffers->enabled_mask & slot_mask;
1565
1566 while (mask) {
1567 unsigned i = u_bit_scan(&mask);
1568 struct pipe_resource *buffer = buffers->buffers[i];
1569
1570 if (buffer && (!buf || buffer == buf)) {
1571 si_set_buf_desc_address(si_resource(buffer), buffers->offsets[i], descs->list + i * 4);
1572 sctx->descriptors_dirty |= 1u << descriptors_idx;
1573
1574 radeon_add_to_gfx_buffer_list_check_mem(
1575 sctx, si_resource(buffer),
1576 buffers->writable_mask & (1u << i) ? RADEON_USAGE_READWRITE : RADEON_USAGE_READ,
1577 priority, true);
1578 }
1579 }
1580 }
1581
1582 /* Update all buffer bindings where the buffer is bound, including
1583 * all resource descriptors. This is invalidate_buffer without
1584 * the invalidation.
1585 *
1586 * If buf == NULL, update all buffer bindings.
1587 */
1588 void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf)
1589 {
1590 struct si_resource *buffer = si_resource(buf);
1591 unsigned i, shader;
1592 unsigned num_elems = sctx->num_vertex_elements;
1593
1594 /* We changed the buffer, now we need to bind it where the old one
1595 * was bound. This consists of 2 things:
1596 * 1) Updating the resource descriptor and dirtying it.
1597 * 2) Adding a relocation to the CS, so that it's usable.
1598 */
1599
1600 /* Vertex buffers. */
1601 if (!buffer) {
1602 if (num_elems)
1603 sctx->vertex_buffers_dirty = true;
1604 } else if (buffer->bind_history & PIPE_BIND_VERTEX_BUFFER) {
1605 for (i = 0; i < num_elems; i++) {
1606 int vb = sctx->vertex_elements->vertex_buffer_index[i];
1607
1608 if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
1609 continue;
1610 if (!sctx->vertex_buffer[vb].buffer.resource)
1611 continue;
1612
1613 if (sctx->vertex_buffer[vb].buffer.resource == buf) {
1614 sctx->vertex_buffers_dirty = true;
1615 break;
1616 }
1617 }
1618 }
1619
1620 /* Streamout buffers. (other internal buffers can't be invalidated) */
1621 if (!buffer || buffer->bind_history & PIPE_BIND_STREAM_OUTPUT) {
1622 for (i = SI_VS_STREAMOUT_BUF0; i <= SI_VS_STREAMOUT_BUF3; i++) {
1623 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1624 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1625 struct pipe_resource *buffer = buffers->buffers[i];
1626
1627 if (!buffer || (buf && buffer != buf))
1628 continue;
1629
1630 si_set_buf_desc_address(si_resource(buffer), buffers->offsets[i], descs->list + i * 4);
1631 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
1632
1633 radeon_add_to_gfx_buffer_list_check_mem(sctx, si_resource(buffer), RADEON_USAGE_WRITE,
1634 RADEON_PRIO_SHADER_RW_BUFFER, true);
1635
1636 /* Update the streamout state. */
1637 if (sctx->streamout.begin_emitted)
1638 si_emit_streamout_end(sctx);
1639 sctx->streamout.append_bitmask = sctx->streamout.enabled_mask;
1640 si_streamout_buffers_dirty(sctx);
1641 }
1642 }
1643
1644 /* Constant and shader buffers. */
1645 if (!buffer || buffer->bind_history & PIPE_BIND_CONSTANT_BUFFER) {
1646 for (shader = 0; shader < SI_NUM_SHADERS; shader++)
1647 si_reset_buffer_resources(sctx, &sctx->const_and_shader_buffers[shader],
1648 si_const_and_shader_buffer_descriptors_idx(shader),
1649 u_bit_consecutive(SI_NUM_SHADER_BUFFERS, SI_NUM_CONST_BUFFERS),
1650 buf, sctx->const_and_shader_buffers[shader].priority_constbuf);
1651 }
1652
1653 if (!buffer || buffer->bind_history & PIPE_BIND_SHADER_BUFFER) {
1654 for (shader = 0; shader < SI_NUM_SHADERS; shader++)
1655 si_reset_buffer_resources(sctx, &sctx->const_and_shader_buffers[shader],
1656 si_const_and_shader_buffer_descriptors_idx(shader),
1657 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS), buf,
1658 sctx->const_and_shader_buffers[shader].priority);
1659 }
1660
1661 if (!buffer || buffer->bind_history & PIPE_BIND_SAMPLER_VIEW) {
1662 /* Texture buffers - update bindings. */
1663 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1664 struct si_samplers *samplers = &sctx->samplers[shader];
1665 struct si_descriptors *descs = si_sampler_and_image_descriptors(sctx, shader);
1666 unsigned mask = samplers->enabled_mask;
1667
1668 while (mask) {
1669 unsigned i = u_bit_scan(&mask);
1670 struct pipe_resource *buffer = samplers->views[i]->texture;
1671
1672 if (buffer && buffer->target == PIPE_BUFFER && (!buf || buffer == buf)) {
1673 unsigned desc_slot = si_get_sampler_slot(i);
1674
1675 si_set_buf_desc_address(si_resource(buffer), samplers->views[i]->u.buf.offset,
1676 descs->list + desc_slot * 16 + 4);
1677 sctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
1678
1679 radeon_add_to_gfx_buffer_list_check_mem(sctx, si_resource(buffer), RADEON_USAGE_READ,
1680 RADEON_PRIO_SAMPLER_BUFFER, true);
1681 }
1682 }
1683 }
1684 }
1685
1686 /* Shader images */
1687 if (!buffer || buffer->bind_history & PIPE_BIND_SHADER_IMAGE) {
1688 for (shader = 0; shader < SI_NUM_SHADERS; ++shader) {
1689 struct si_images *images = &sctx->images[shader];
1690 struct si_descriptors *descs = si_sampler_and_image_descriptors(sctx, shader);
1691 unsigned mask = images->enabled_mask;
1692
1693 while (mask) {
1694 unsigned i = u_bit_scan(&mask);
1695 struct pipe_resource *buffer = images->views[i].resource;
1696
1697 if (buffer && buffer->target == PIPE_BUFFER && (!buf || buffer == buf)) {
1698 unsigned desc_slot = si_get_image_slot(i);
1699
1700 if (images->views[i].access & PIPE_IMAGE_ACCESS_WRITE)
1701 si_mark_image_range_valid(&images->views[i]);
1702
1703 si_set_buf_desc_address(si_resource(buffer), images->views[i].u.buf.offset,
1704 descs->list + desc_slot * 8 + 4);
1705 sctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
1706
1707 radeon_add_to_gfx_buffer_list_check_mem(sctx, si_resource(buffer),
1708 RADEON_USAGE_READWRITE,
1709 RADEON_PRIO_SAMPLER_BUFFER, true);
1710 }
1711 }
1712 }
1713 }
1714
1715 /* Bindless texture handles */
1716 if (!buffer || buffer->texture_handle_allocated) {
1717 struct si_descriptors *descs = &sctx->bindless_descriptors;
1718
1719 util_dynarray_foreach (&sctx->resident_tex_handles, struct si_texture_handle *, tex_handle) {
1720 struct pipe_sampler_view *view = (*tex_handle)->view;
1721 unsigned desc_slot = (*tex_handle)->desc_slot;
1722 struct pipe_resource *buffer = view->texture;
1723
1724 if (buffer && buffer->target == PIPE_BUFFER && (!buf || buffer == buf)) {
1725 si_set_buf_desc_address(si_resource(buffer), view->u.buf.offset,
1726 descs->list + desc_slot * 16 + 4);
1727
1728 (*tex_handle)->desc_dirty = true;
1729 sctx->bindless_descriptors_dirty = true;
1730
1731 radeon_add_to_gfx_buffer_list_check_mem(sctx, si_resource(buffer), RADEON_USAGE_READ,
1732 RADEON_PRIO_SAMPLER_BUFFER, true);
1733 }
1734 }
1735 }
1736
1737 /* Bindless image handles */
1738 if (!buffer || buffer->image_handle_allocated) {
1739 struct si_descriptors *descs = &sctx->bindless_descriptors;
1740
1741 util_dynarray_foreach (&sctx->resident_img_handles, struct si_image_handle *, img_handle) {
1742 struct pipe_image_view *view = &(*img_handle)->view;
1743 unsigned desc_slot = (*img_handle)->desc_slot;
1744 struct pipe_resource *buffer = view->resource;
1745
1746 if (buffer && buffer->target == PIPE_BUFFER && (!buf || buffer == buf)) {
1747 if (view->access & PIPE_IMAGE_ACCESS_WRITE)
1748 si_mark_image_range_valid(view);
1749
1750 si_set_buf_desc_address(si_resource(buffer), view->u.buf.offset,
1751 descs->list + desc_slot * 16 + 4);
1752
1753 (*img_handle)->desc_dirty = true;
1754 sctx->bindless_descriptors_dirty = true;
1755
1756 radeon_add_to_gfx_buffer_list_check_mem(
1757 sctx, si_resource(buffer), RADEON_USAGE_READWRITE, RADEON_PRIO_SAMPLER_BUFFER, true);
1758 }
1759 }
1760 }
1761
1762 if (buffer) {
1763 /* Do the same for other contexts. They will invoke this function
1764 * with buffer == NULL.
1765 */
1766 unsigned new_counter = p_atomic_inc_return(&sctx->screen->dirty_buf_counter);
1767
1768 /* Skip the update for the current context, because we have already updated
1769 * the buffer bindings.
1770 */
1771 if (new_counter == sctx->last_dirty_buf_counter + 1)
1772 sctx->last_dirty_buf_counter = new_counter;
1773 }
1774 }
1775
1776 static void si_upload_bindless_descriptor(struct si_context *sctx, unsigned desc_slot,
1777 unsigned num_dwords)
1778 {
1779 struct si_descriptors *desc = &sctx->bindless_descriptors;
1780 unsigned desc_slot_offset = desc_slot * 16;
1781 uint32_t *data;
1782 uint64_t va;
1783
1784 data = desc->list + desc_slot_offset;
1785 va = desc->gpu_address + desc_slot_offset * 4;
1786
1787 si_cp_write_data(sctx, desc->buffer, va - desc->buffer->gpu_address, num_dwords * 4, V_370_TC_L2,
1788 V_370_ME, data);
1789 }
1790
1791 static void si_upload_bindless_descriptors(struct si_context *sctx)
1792 {
1793 if (!sctx->bindless_descriptors_dirty)
1794 return;
1795
1796 /* Wait for graphics/compute to be idle before updating the resident
1797 * descriptors directly in memory, in case the GPU is using them.
1798 */
1799 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH;
1800 sctx->emit_cache_flush(sctx);
1801
1802 util_dynarray_foreach (&sctx->resident_tex_handles, struct si_texture_handle *, tex_handle) {
1803 unsigned desc_slot = (*tex_handle)->desc_slot;
1804
1805 if (!(*tex_handle)->desc_dirty)
1806 continue;
1807
1808 si_upload_bindless_descriptor(sctx, desc_slot, 16);
1809 (*tex_handle)->desc_dirty = false;
1810 }
1811
1812 util_dynarray_foreach (&sctx->resident_img_handles, struct si_image_handle *, img_handle) {
1813 unsigned desc_slot = (*img_handle)->desc_slot;
1814
1815 if (!(*img_handle)->desc_dirty)
1816 continue;
1817
1818 si_upload_bindless_descriptor(sctx, desc_slot, 8);
1819 (*img_handle)->desc_dirty = false;
1820 }
1821
1822 /* Invalidate L1 because it doesn't know that L2 changed. */
1823 sctx->flags |= SI_CONTEXT_INV_SCACHE;
1824 sctx->emit_cache_flush(sctx);
1825
1826 sctx->bindless_descriptors_dirty = false;
1827 }
1828
1829 /* Update mutable image descriptor fields of all resident textures. */
1830 static void si_update_bindless_texture_descriptor(struct si_context *sctx,
1831 struct si_texture_handle *tex_handle)
1832 {
1833 struct si_sampler_view *sview = (struct si_sampler_view *)tex_handle->view;
1834 struct si_descriptors *desc = &sctx->bindless_descriptors;
1835 unsigned desc_slot_offset = tex_handle->desc_slot * 16;
1836 uint32_t desc_list[16];
1837
1838 if (sview->base.texture->target == PIPE_BUFFER)
1839 return;
1840
1841 memcpy(desc_list, desc->list + desc_slot_offset, sizeof(desc_list));
1842 si_set_sampler_view_desc(sctx, sview, &tex_handle->sstate, desc->list + desc_slot_offset);
1843
1844 if (memcmp(desc_list, desc->list + desc_slot_offset, sizeof(desc_list))) {
1845 tex_handle->desc_dirty = true;
1846 sctx->bindless_descriptors_dirty = true;
1847 }
1848 }
1849
1850 static void si_update_bindless_image_descriptor(struct si_context *sctx,
1851 struct si_image_handle *img_handle)
1852 {
1853 struct si_descriptors *desc = &sctx->bindless_descriptors;
1854 unsigned desc_slot_offset = img_handle->desc_slot * 16;
1855 struct pipe_image_view *view = &img_handle->view;
1856 struct pipe_resource *res = view->resource;
1857 uint32_t image_desc[16];
1858 unsigned desc_size = (res->nr_samples >= 2 ? 16 : 8) * 4;
1859
1860 if (res->target == PIPE_BUFFER)
1861 return;
1862
1863 memcpy(image_desc, desc->list + desc_slot_offset, desc_size);
1864 si_set_shader_image_desc(sctx, view, true, desc->list + desc_slot_offset,
1865 desc->list + desc_slot_offset + 8);
1866
1867 if (memcmp(image_desc, desc->list + desc_slot_offset, desc_size)) {
1868 img_handle->desc_dirty = true;
1869 sctx->bindless_descriptors_dirty = true;
1870 }
1871 }
1872
1873 static void si_update_all_resident_texture_descriptors(struct si_context *sctx)
1874 {
1875 util_dynarray_foreach (&sctx->resident_tex_handles, struct si_texture_handle *, tex_handle) {
1876 si_update_bindless_texture_descriptor(sctx, *tex_handle);
1877 }
1878
1879 util_dynarray_foreach (&sctx->resident_img_handles, struct si_image_handle *, img_handle) {
1880 si_update_bindless_image_descriptor(sctx, *img_handle);
1881 }
1882
1883 si_upload_bindless_descriptors(sctx);
1884 }
1885
1886 /* Update mutable image descriptor fields of all bound textures. */
1887 void si_update_all_texture_descriptors(struct si_context *sctx)
1888 {
1889 unsigned shader;
1890
1891 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1892 struct si_samplers *samplers = &sctx->samplers[shader];
1893 struct si_images *images = &sctx->images[shader];
1894 unsigned mask;
1895
1896 /* Images. */
1897 mask = images->enabled_mask;
1898 while (mask) {
1899 unsigned i = u_bit_scan(&mask);
1900 struct pipe_image_view *view = &images->views[i];
1901
1902 if (!view->resource || view->resource->target == PIPE_BUFFER)
1903 continue;
1904
1905 si_set_shader_image(sctx, shader, i, view, true);
1906 }
1907
1908 /* Sampler views. */
1909 mask = samplers->enabled_mask;
1910 while (mask) {
1911 unsigned i = u_bit_scan(&mask);
1912 struct pipe_sampler_view *view = samplers->views[i];
1913
1914 if (!view || !view->texture || view->texture->target == PIPE_BUFFER)
1915 continue;
1916
1917 si_set_sampler_view(sctx, shader, i, samplers->views[i], true);
1918 }
1919
1920 si_update_shader_needs_decompress_mask(sctx, shader);
1921 }
1922
1923 si_update_all_resident_texture_descriptors(sctx);
1924 si_update_ps_colorbuf0_slot(sctx);
1925 }
1926
1927 /* SHADER USER DATA */
1928
1929 static void si_mark_shader_pointers_dirty(struct si_context *sctx, unsigned shader)
1930 {
1931 sctx->shader_pointers_dirty |=
1932 u_bit_consecutive(SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS, SI_NUM_SHADER_DESCS);
1933
1934 if (shader == PIPE_SHADER_VERTEX) {
1935 sctx->vertex_buffer_pointer_dirty = sctx->vb_descriptors_buffer != NULL;
1936 sctx->vertex_buffer_user_sgprs_dirty =
1937 sctx->num_vertex_elements > 0 && sctx->screen->num_vbos_in_user_sgprs;
1938 }
1939
1940 si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
1941 }
1942
1943 void si_shader_pointers_mark_dirty(struct si_context *sctx)
1944 {
1945 sctx->shader_pointers_dirty = u_bit_consecutive(0, SI_NUM_DESCS);
1946 sctx->vertex_buffer_pointer_dirty = sctx->vb_descriptors_buffer != NULL;
1947 sctx->vertex_buffer_user_sgprs_dirty =
1948 sctx->num_vertex_elements > 0 && sctx->screen->num_vbos_in_user_sgprs;
1949 si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
1950 sctx->graphics_bindless_pointer_dirty = sctx->bindless_descriptors.buffer != NULL;
1951 sctx->compute_bindless_pointer_dirty = sctx->bindless_descriptors.buffer != NULL;
1952 sctx->compute_shaderbuf_sgprs_dirty = true;
1953 sctx->compute_image_sgprs_dirty = true;
1954 }
1955
1956 /* Set a base register address for user data constants in the given shader.
1957 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
1958 */
1959 static void si_set_user_data_base(struct si_context *sctx, unsigned shader, uint32_t new_base)
1960 {
1961 uint32_t *base = &sctx->shader_pointers.sh_base[shader];
1962
1963 if (*base != new_base) {
1964 *base = new_base;
1965
1966 if (new_base)
1967 si_mark_shader_pointers_dirty(sctx, shader);
1968
1969 /* Any change in enabled shader stages requires re-emitting
1970 * the VS state SGPR, because it contains the clamp_vertex_color
1971 * state, which can be done in VS, TES, and GS.
1972 */
1973 sctx->last_vs_state = ~0;
1974 }
1975 }
1976
1977 /* This must be called when these are changed between enabled and disabled
1978 * - geometry shader
1979 * - tessellation evaluation shader
1980 * - NGG
1981 */
1982 void si_shader_change_notify(struct si_context *sctx)
1983 {
1984 /* VS can be bound as VS, ES, or LS. */
1985 if (sctx->tes_shader.cso) {
1986 if (sctx->chip_class >= GFX10) {
1987 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B430_SPI_SHADER_USER_DATA_HS_0);
1988 } else if (sctx->chip_class == GFX9) {
1989 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B430_SPI_SHADER_USER_DATA_LS_0);
1990 } else {
1991 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B530_SPI_SHADER_USER_DATA_LS_0);
1992 }
1993 } else if (sctx->chip_class >= GFX10) {
1994 if (sctx->ngg || sctx->gs_shader.cso) {
1995 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B230_SPI_SHADER_USER_DATA_GS_0);
1996 } else {
1997 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0);
1998 }
1999 } else if (sctx->gs_shader.cso) {
2000 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B330_SPI_SHADER_USER_DATA_ES_0);
2001 } else {
2002 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0);
2003 }
2004
2005 /* TES can be bound as ES, VS, or not bound. */
2006 if (sctx->tes_shader.cso) {
2007 if (sctx->chip_class >= GFX10) {
2008 if (sctx->ngg || sctx->gs_shader.cso) {
2009 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, R_00B230_SPI_SHADER_USER_DATA_GS_0);
2010 } else {
2011 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, R_00B130_SPI_SHADER_USER_DATA_VS_0);
2012 }
2013 } else if (sctx->gs_shader.cso) {
2014 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, R_00B330_SPI_SHADER_USER_DATA_ES_0);
2015 } else {
2016 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, R_00B130_SPI_SHADER_USER_DATA_VS_0);
2017 }
2018 } else {
2019 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, 0);
2020 }
2021 }
2022
2023 static void si_emit_shader_pointer_head(struct radeon_cmdbuf *cs, unsigned sh_offset,
2024 unsigned pointer_count)
2025 {
2026 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count, 0));
2027 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
2028 }
2029
2030 static void si_emit_shader_pointer_body(struct si_screen *sscreen, struct radeon_cmdbuf *cs,
2031 uint64_t va)
2032 {
2033 radeon_emit(cs, va);
2034
2035 assert(va == 0 || (va >> 32) == sscreen->info.address32_hi);
2036 }
2037
2038 static void si_emit_shader_pointer(struct si_context *sctx, struct si_descriptors *desc,
2039 unsigned sh_base)
2040 {
2041 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2042 unsigned sh_offset = sh_base + desc->shader_userdata_offset;
2043
2044 si_emit_shader_pointer_head(cs, sh_offset, 1);
2045 si_emit_shader_pointer_body(sctx->screen, cs, desc->gpu_address);
2046 }
2047
2048 static void si_emit_consecutive_shader_pointers(struct si_context *sctx, unsigned pointer_mask,
2049 unsigned sh_base)
2050 {
2051 if (!sh_base)
2052 return;
2053
2054 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2055 unsigned mask = sctx->shader_pointers_dirty & pointer_mask;
2056
2057 while (mask) {
2058 int start, count;
2059 u_bit_scan_consecutive_range(&mask, &start, &count);
2060
2061 struct si_descriptors *descs = &sctx->descriptors[start];
2062 unsigned sh_offset = sh_base + descs->shader_userdata_offset;
2063
2064 si_emit_shader_pointer_head(cs, sh_offset, count);
2065 for (int i = 0; i < count; i++)
2066 si_emit_shader_pointer_body(sctx->screen, cs, descs[i].gpu_address);
2067 }
2068 }
2069
2070 static void si_emit_global_shader_pointers(struct si_context *sctx, struct si_descriptors *descs)
2071 {
2072 if (sctx->chip_class >= GFX10) {
2073 si_emit_shader_pointer(sctx, descs, R_00B030_SPI_SHADER_USER_DATA_PS_0);
2074 /* HW VS stage only used in non-NGG mode. */
2075 si_emit_shader_pointer(sctx, descs, R_00B130_SPI_SHADER_USER_DATA_VS_0);
2076 si_emit_shader_pointer(sctx, descs, R_00B230_SPI_SHADER_USER_DATA_GS_0);
2077 si_emit_shader_pointer(sctx, descs, R_00B430_SPI_SHADER_USER_DATA_HS_0);
2078 return;
2079 } else if (sctx->chip_class == GFX9) {
2080 /* Broadcast it to all shader stages. */
2081 si_emit_shader_pointer(sctx, descs, R_00B530_SPI_SHADER_USER_DATA_COMMON_0);
2082 return;
2083 }
2084
2085 si_emit_shader_pointer(sctx, descs, R_00B030_SPI_SHADER_USER_DATA_PS_0);
2086 si_emit_shader_pointer(sctx, descs, R_00B130_SPI_SHADER_USER_DATA_VS_0);
2087 si_emit_shader_pointer(sctx, descs, R_00B330_SPI_SHADER_USER_DATA_ES_0);
2088 si_emit_shader_pointer(sctx, descs, R_00B230_SPI_SHADER_USER_DATA_GS_0);
2089 si_emit_shader_pointer(sctx, descs, R_00B430_SPI_SHADER_USER_DATA_HS_0);
2090 si_emit_shader_pointer(sctx, descs, R_00B530_SPI_SHADER_USER_DATA_LS_0);
2091 }
2092
2093 void si_emit_graphics_shader_pointers(struct si_context *sctx)
2094 {
2095 uint32_t *sh_base = sctx->shader_pointers.sh_base;
2096
2097 if (sctx->shader_pointers_dirty & (1 << SI_DESCS_RW_BUFFERS)) {
2098 si_emit_global_shader_pointers(sctx, &sctx->descriptors[SI_DESCS_RW_BUFFERS]);
2099 }
2100
2101 si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(VERTEX),
2102 sh_base[PIPE_SHADER_VERTEX]);
2103 si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(TESS_EVAL),
2104 sh_base[PIPE_SHADER_TESS_EVAL]);
2105 si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(FRAGMENT),
2106 sh_base[PIPE_SHADER_FRAGMENT]);
2107 si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(TESS_CTRL),
2108 sh_base[PIPE_SHADER_TESS_CTRL]);
2109 si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(GEOMETRY),
2110 sh_base[PIPE_SHADER_GEOMETRY]);
2111
2112 sctx->shader_pointers_dirty &= ~u_bit_consecutive(SI_DESCS_RW_BUFFERS, SI_DESCS_FIRST_COMPUTE);
2113
2114 if (sctx->vertex_buffer_pointer_dirty && sctx->num_vertex_elements) {
2115 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2116
2117 /* Find the location of the VB descriptor pointer. */
2118 unsigned sh_dw_offset = SI_VS_NUM_USER_SGPR;
2119 if (sctx->chip_class >= GFX9) {
2120 if (sctx->tes_shader.cso)
2121 sh_dw_offset = GFX9_TCS_NUM_USER_SGPR;
2122 else if (sctx->gs_shader.cso)
2123 sh_dw_offset = GFX9_VSGS_NUM_USER_SGPR;
2124 }
2125
2126 unsigned sh_offset = sh_base[PIPE_SHADER_VERTEX] + sh_dw_offset * 4;
2127 si_emit_shader_pointer_head(cs, sh_offset, 1);
2128 si_emit_shader_pointer_body(
2129 sctx->screen, cs, sctx->vb_descriptors_buffer->gpu_address + sctx->vb_descriptors_offset);
2130 sctx->vertex_buffer_pointer_dirty = false;
2131 }
2132
2133 if (sctx->vertex_buffer_user_sgprs_dirty && sctx->num_vertex_elements &&
2134 sctx->screen->num_vbos_in_user_sgprs) {
2135 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2136 unsigned num_desc = MIN2(sctx->num_vertex_elements, sctx->screen->num_vbos_in_user_sgprs);
2137 unsigned sh_offset = sh_base[PIPE_SHADER_VERTEX] + SI_SGPR_VS_VB_DESCRIPTOR_FIRST * 4;
2138
2139 si_emit_shader_pointer_head(cs, sh_offset, num_desc * 4);
2140 radeon_emit_array(cs, sctx->vb_descriptor_user_sgprs, num_desc * 4);
2141 sctx->vertex_buffer_user_sgprs_dirty = false;
2142 }
2143
2144 if (sctx->graphics_bindless_pointer_dirty) {
2145 si_emit_global_shader_pointers(sctx, &sctx->bindless_descriptors);
2146 sctx->graphics_bindless_pointer_dirty = false;
2147 }
2148 }
2149
2150 void si_emit_compute_shader_pointers(struct si_context *sctx)
2151 {
2152 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2153 struct si_shader_selector *shader = &sctx->cs_shader_state.program->sel;
2154 unsigned base = R_00B900_COMPUTE_USER_DATA_0;
2155
2156 si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(COMPUTE),
2157 R_00B900_COMPUTE_USER_DATA_0);
2158 sctx->shader_pointers_dirty &= ~SI_DESCS_SHADER_MASK(COMPUTE);
2159
2160 if (sctx->compute_bindless_pointer_dirty) {
2161 si_emit_shader_pointer(sctx, &sctx->bindless_descriptors, base);
2162 sctx->compute_bindless_pointer_dirty = false;
2163 }
2164
2165 /* Set shader buffer descriptors in user SGPRs. */
2166 unsigned num_shaderbufs = shader->cs_num_shaderbufs_in_user_sgprs;
2167 if (num_shaderbufs && sctx->compute_shaderbuf_sgprs_dirty) {
2168 struct si_descriptors *desc = si_const_and_shader_buffer_descriptors(sctx, PIPE_SHADER_COMPUTE);
2169
2170 si_emit_shader_pointer_head(cs, R_00B900_COMPUTE_USER_DATA_0 +
2171 shader->cs_shaderbufs_sgpr_index * 4,
2172 num_shaderbufs * 4);
2173
2174 for (unsigned i = 0; i < num_shaderbufs; i++)
2175 radeon_emit_array(cs, &desc->list[si_get_shaderbuf_slot(i) * 4], 4);
2176
2177 sctx->compute_shaderbuf_sgprs_dirty = false;
2178 }
2179
2180 /* Set image descriptors in user SGPRs. */
2181 unsigned num_images = shader->cs_num_images_in_user_sgprs;
2182 if (num_images && sctx->compute_image_sgprs_dirty) {
2183 struct si_descriptors *desc = si_sampler_and_image_descriptors(sctx, PIPE_SHADER_COMPUTE);
2184
2185 si_emit_shader_pointer_head(cs, R_00B900_COMPUTE_USER_DATA_0 +
2186 shader->cs_images_sgpr_index * 4,
2187 shader->cs_images_num_sgprs);
2188
2189 for (unsigned i = 0; i < num_images; i++) {
2190 unsigned desc_offset = si_get_image_slot(i) * 8;
2191 unsigned num_sgprs = 8;
2192
2193 /* Image buffers are in desc[4..7]. */
2194 if (shader->info.image_buffers & (1 << i)) {
2195 desc_offset += 4;
2196 num_sgprs = 4;
2197 }
2198
2199 radeon_emit_array(cs, &desc->list[desc_offset], num_sgprs);
2200 }
2201
2202 sctx->compute_image_sgprs_dirty = false;
2203 }
2204 }
2205
2206 /* BINDLESS */
2207
2208 static void si_init_bindless_descriptors(struct si_context *sctx, struct si_descriptors *desc,
2209 short shader_userdata_rel_index, unsigned num_elements)
2210 {
2211 ASSERTED unsigned desc_slot;
2212
2213 si_init_descriptors(desc, shader_userdata_rel_index, 16, num_elements);
2214 sctx->bindless_descriptors.num_active_slots = num_elements;
2215
2216 /* The first bindless descriptor is stored at slot 1, because 0 is not
2217 * considered to be a valid handle.
2218 */
2219 sctx->num_bindless_descriptors = 1;
2220
2221 /* Track which bindless slots are used (or not). */
2222 util_idalloc_init(&sctx->bindless_used_slots);
2223 util_idalloc_resize(&sctx->bindless_used_slots, num_elements);
2224
2225 /* Reserve slot 0 because it's an invalid handle for bindless. */
2226 desc_slot = util_idalloc_alloc(&sctx->bindless_used_slots);
2227 assert(desc_slot == 0);
2228 }
2229
2230 static void si_release_bindless_descriptors(struct si_context *sctx)
2231 {
2232 si_release_descriptors(&sctx->bindless_descriptors);
2233 util_idalloc_fini(&sctx->bindless_used_slots);
2234 }
2235
2236 static unsigned si_get_first_free_bindless_slot(struct si_context *sctx)
2237 {
2238 struct si_descriptors *desc = &sctx->bindless_descriptors;
2239 unsigned desc_slot;
2240
2241 desc_slot = util_idalloc_alloc(&sctx->bindless_used_slots);
2242 if (desc_slot >= desc->num_elements) {
2243 /* The array of bindless descriptors is full, resize it. */
2244 unsigned slot_size = desc->element_dw_size * 4;
2245 unsigned new_num_elements = desc->num_elements * 2;
2246
2247 desc->list =
2248 REALLOC(desc->list, desc->num_elements * slot_size, new_num_elements * slot_size);
2249 desc->num_elements = new_num_elements;
2250 desc->num_active_slots = new_num_elements;
2251 }
2252
2253 assert(desc_slot);
2254 return desc_slot;
2255 }
2256
2257 static unsigned si_create_bindless_descriptor(struct si_context *sctx, uint32_t *desc_list,
2258 unsigned size)
2259 {
2260 struct si_descriptors *desc = &sctx->bindless_descriptors;
2261 unsigned desc_slot, desc_slot_offset;
2262
2263 /* Find a free slot. */
2264 desc_slot = si_get_first_free_bindless_slot(sctx);
2265
2266 /* For simplicity, sampler and image bindless descriptors use fixed
2267 * 16-dword slots for now. Image descriptors only need 8-dword but this
2268 * doesn't really matter because no real apps use image handles.
2269 */
2270 desc_slot_offset = desc_slot * 16;
2271
2272 /* Copy the descriptor into the array. */
2273 memcpy(desc->list + desc_slot_offset, desc_list, size);
2274
2275 /* Re-upload the whole array of bindless descriptors into a new buffer.
2276 */
2277 if (!si_upload_descriptors(sctx, desc))
2278 return 0;
2279
2280 /* Make sure to re-emit the shader pointers for all stages. */
2281 sctx->graphics_bindless_pointer_dirty = true;
2282 sctx->compute_bindless_pointer_dirty = true;
2283
2284 return desc_slot;
2285 }
2286
2287 static void si_update_bindless_buffer_descriptor(struct si_context *sctx, unsigned desc_slot,
2288 struct pipe_resource *resource, uint64_t offset,
2289 bool *desc_dirty)
2290 {
2291 struct si_descriptors *desc = &sctx->bindless_descriptors;
2292 struct si_resource *buf = si_resource(resource);
2293 unsigned desc_slot_offset = desc_slot * 16;
2294 uint32_t *desc_list = desc->list + desc_slot_offset + 4;
2295 uint64_t old_desc_va;
2296
2297 assert(resource->target == PIPE_BUFFER);
2298
2299 /* Retrieve the old buffer addr from the descriptor. */
2300 old_desc_va = si_desc_extract_buffer_address(desc_list);
2301
2302 if (old_desc_va != buf->gpu_address + offset) {
2303 /* The buffer has been invalidated when the handle wasn't
2304 * resident, update the descriptor and the dirty flag.
2305 */
2306 si_set_buf_desc_address(buf, offset, &desc_list[0]);
2307
2308 *desc_dirty = true;
2309 }
2310 }
2311
2312 static uint64_t si_create_texture_handle(struct pipe_context *ctx, struct pipe_sampler_view *view,
2313 const struct pipe_sampler_state *state)
2314 {
2315 struct si_sampler_view *sview = (struct si_sampler_view *)view;
2316 struct si_context *sctx = (struct si_context *)ctx;
2317 struct si_texture_handle *tex_handle;
2318 struct si_sampler_state *sstate;
2319 uint32_t desc_list[16];
2320 uint64_t handle;
2321
2322 tex_handle = CALLOC_STRUCT(si_texture_handle);
2323 if (!tex_handle)
2324 return 0;
2325
2326 memset(desc_list, 0, sizeof(desc_list));
2327 si_init_descriptor_list(&desc_list[0], 16, 1, null_texture_descriptor);
2328
2329 sstate = ctx->create_sampler_state(ctx, state);
2330 if (!sstate) {
2331 FREE(tex_handle);
2332 return 0;
2333 }
2334
2335 si_set_sampler_view_desc(sctx, sview, sstate, &desc_list[0]);
2336 memcpy(&tex_handle->sstate, sstate, sizeof(*sstate));
2337 ctx->delete_sampler_state(ctx, sstate);
2338
2339 tex_handle->desc_slot = si_create_bindless_descriptor(sctx, desc_list, sizeof(desc_list));
2340 if (!tex_handle->desc_slot) {
2341 FREE(tex_handle);
2342 return 0;
2343 }
2344
2345 handle = tex_handle->desc_slot;
2346
2347 if (!_mesa_hash_table_insert(sctx->tex_handles, (void *)(uintptr_t)handle, tex_handle)) {
2348 FREE(tex_handle);
2349 return 0;
2350 }
2351
2352 pipe_sampler_view_reference(&tex_handle->view, view);
2353
2354 si_resource(sview->base.texture)->texture_handle_allocated = true;
2355
2356 return handle;
2357 }
2358
2359 static void si_delete_texture_handle(struct pipe_context *ctx, uint64_t handle)
2360 {
2361 struct si_context *sctx = (struct si_context *)ctx;
2362 struct si_texture_handle *tex_handle;
2363 struct hash_entry *entry;
2364
2365 entry = _mesa_hash_table_search(sctx->tex_handles, (void *)(uintptr_t)handle);
2366 if (!entry)
2367 return;
2368
2369 tex_handle = (struct si_texture_handle *)entry->data;
2370
2371 /* Allow this descriptor slot to be re-used. */
2372 util_idalloc_free(&sctx->bindless_used_slots, tex_handle->desc_slot);
2373
2374 pipe_sampler_view_reference(&tex_handle->view, NULL);
2375 _mesa_hash_table_remove(sctx->tex_handles, entry);
2376 FREE(tex_handle);
2377 }
2378
2379 static void si_make_texture_handle_resident(struct pipe_context *ctx, uint64_t handle,
2380 bool resident)
2381 {
2382 struct si_context *sctx = (struct si_context *)ctx;
2383 struct si_texture_handle *tex_handle;
2384 struct si_sampler_view *sview;
2385 struct hash_entry *entry;
2386
2387 entry = _mesa_hash_table_search(sctx->tex_handles, (void *)(uintptr_t)handle);
2388 if (!entry)
2389 return;
2390
2391 tex_handle = (struct si_texture_handle *)entry->data;
2392 sview = (struct si_sampler_view *)tex_handle->view;
2393
2394 if (resident) {
2395 if (sview->base.texture->target != PIPE_BUFFER) {
2396 struct si_texture *tex = (struct si_texture *)sview->base.texture;
2397
2398 if (depth_needs_decompression(tex)) {
2399 util_dynarray_append(&sctx->resident_tex_needs_depth_decompress,
2400 struct si_texture_handle *, tex_handle);
2401 }
2402
2403 if (color_needs_decompression(tex)) {
2404 util_dynarray_append(&sctx->resident_tex_needs_color_decompress,
2405 struct si_texture_handle *, tex_handle);
2406 }
2407
2408 if (vi_dcc_enabled(tex, sview->base.u.tex.first_level) &&
2409 p_atomic_read(&tex->framebuffers_bound))
2410 sctx->need_check_render_feedback = true;
2411
2412 si_update_bindless_texture_descriptor(sctx, tex_handle);
2413 } else {
2414 si_update_bindless_buffer_descriptor(sctx, tex_handle->desc_slot, sview->base.texture,
2415 sview->base.u.buf.offset, &tex_handle->desc_dirty);
2416 }
2417
2418 /* Re-upload the descriptor if it has been updated while it
2419 * wasn't resident.
2420 */
2421 if (tex_handle->desc_dirty)
2422 sctx->bindless_descriptors_dirty = true;
2423
2424 /* Add the texture handle to the per-context list. */
2425 util_dynarray_append(&sctx->resident_tex_handles, struct si_texture_handle *, tex_handle);
2426
2427 /* Add the buffers to the current CS in case si_begin_new_cs()
2428 * is not going to be called.
2429 */
2430 si_sampler_view_add_buffer(sctx, sview->base.texture, RADEON_USAGE_READ,
2431 sview->is_stencil_sampler, false);
2432 } else {
2433 /* Remove the texture handle from the per-context list. */
2434 util_dynarray_delete_unordered(&sctx->resident_tex_handles, struct si_texture_handle *,
2435 tex_handle);
2436
2437 if (sview->base.texture->target != PIPE_BUFFER) {
2438 util_dynarray_delete_unordered(&sctx->resident_tex_needs_depth_decompress,
2439 struct si_texture_handle *, tex_handle);
2440
2441 util_dynarray_delete_unordered(&sctx->resident_tex_needs_color_decompress,
2442 struct si_texture_handle *, tex_handle);
2443 }
2444 }
2445 }
2446
2447 static uint64_t si_create_image_handle(struct pipe_context *ctx, const struct pipe_image_view *view)
2448 {
2449 struct si_context *sctx = (struct si_context *)ctx;
2450 struct si_image_handle *img_handle;
2451 uint32_t desc_list[16];
2452 uint64_t handle;
2453
2454 if (!view || !view->resource)
2455 return 0;
2456
2457 img_handle = CALLOC_STRUCT(si_image_handle);
2458 if (!img_handle)
2459 return 0;
2460
2461 memset(desc_list, 0, sizeof(desc_list));
2462 si_init_descriptor_list(&desc_list[0], 8, 2, null_image_descriptor);
2463
2464 si_set_shader_image_desc(sctx, view, false, &desc_list[0], &desc_list[8]);
2465
2466 img_handle->desc_slot = si_create_bindless_descriptor(sctx, desc_list, sizeof(desc_list));
2467 if (!img_handle->desc_slot) {
2468 FREE(img_handle);
2469 return 0;
2470 }
2471
2472 handle = img_handle->desc_slot;
2473
2474 if (!_mesa_hash_table_insert(sctx->img_handles, (void *)(uintptr_t)handle, img_handle)) {
2475 FREE(img_handle);
2476 return 0;
2477 }
2478
2479 util_copy_image_view(&img_handle->view, view);
2480
2481 si_resource(view->resource)->image_handle_allocated = true;
2482
2483 return handle;
2484 }
2485
2486 static void si_delete_image_handle(struct pipe_context *ctx, uint64_t handle)
2487 {
2488 struct si_context *sctx = (struct si_context *)ctx;
2489 struct si_image_handle *img_handle;
2490 struct hash_entry *entry;
2491
2492 entry = _mesa_hash_table_search(sctx->img_handles, (void *)(uintptr_t)handle);
2493 if (!entry)
2494 return;
2495
2496 img_handle = (struct si_image_handle *)entry->data;
2497
2498 util_copy_image_view(&img_handle->view, NULL);
2499 _mesa_hash_table_remove(sctx->img_handles, entry);
2500 FREE(img_handle);
2501 }
2502
2503 static void si_make_image_handle_resident(struct pipe_context *ctx, uint64_t handle,
2504 unsigned access, bool resident)
2505 {
2506 struct si_context *sctx = (struct si_context *)ctx;
2507 struct si_image_handle *img_handle;
2508 struct pipe_image_view *view;
2509 struct si_resource *res;
2510 struct hash_entry *entry;
2511
2512 entry = _mesa_hash_table_search(sctx->img_handles, (void *)(uintptr_t)handle);
2513 if (!entry)
2514 return;
2515
2516 img_handle = (struct si_image_handle *)entry->data;
2517 view = &img_handle->view;
2518 res = si_resource(view->resource);
2519
2520 if (resident) {
2521 if (res->b.b.target != PIPE_BUFFER) {
2522 struct si_texture *tex = (struct si_texture *)res;
2523 unsigned level = view->u.tex.level;
2524
2525 if (color_needs_decompression(tex)) {
2526 util_dynarray_append(&sctx->resident_img_needs_color_decompress,
2527 struct si_image_handle *, img_handle);
2528 }
2529
2530 if (vi_dcc_enabled(tex, level) && p_atomic_read(&tex->framebuffers_bound))
2531 sctx->need_check_render_feedback = true;
2532
2533 si_update_bindless_image_descriptor(sctx, img_handle);
2534 } else {
2535 si_update_bindless_buffer_descriptor(sctx, img_handle->desc_slot, view->resource,
2536 view->u.buf.offset, &img_handle->desc_dirty);
2537 }
2538
2539 /* Re-upload the descriptor if it has been updated while it
2540 * wasn't resident.
2541 */
2542 if (img_handle->desc_dirty)
2543 sctx->bindless_descriptors_dirty = true;
2544
2545 /* Add the image handle to the per-context list. */
2546 util_dynarray_append(&sctx->resident_img_handles, struct si_image_handle *, img_handle);
2547
2548 /* Add the buffers to the current CS in case si_begin_new_cs()
2549 * is not going to be called.
2550 */
2551 si_sampler_view_add_buffer(
2552 sctx, view->resource,
2553 (access & PIPE_IMAGE_ACCESS_WRITE) ? RADEON_USAGE_READWRITE : RADEON_USAGE_READ, false,
2554 false);
2555 } else {
2556 /* Remove the image handle from the per-context list. */
2557 util_dynarray_delete_unordered(&sctx->resident_img_handles, struct si_image_handle *,
2558 img_handle);
2559
2560 if (res->b.b.target != PIPE_BUFFER) {
2561 util_dynarray_delete_unordered(&sctx->resident_img_needs_color_decompress,
2562 struct si_image_handle *, img_handle);
2563 }
2564 }
2565 }
2566
2567 static void si_resident_buffers_add_all_to_bo_list(struct si_context *sctx)
2568 {
2569 unsigned num_resident_tex_handles, num_resident_img_handles;
2570
2571 num_resident_tex_handles = sctx->resident_tex_handles.size / sizeof(struct si_texture_handle *);
2572 num_resident_img_handles = sctx->resident_img_handles.size / sizeof(struct si_image_handle *);
2573
2574 /* Add all resident texture handles. */
2575 util_dynarray_foreach (&sctx->resident_tex_handles, struct si_texture_handle *, tex_handle) {
2576 struct si_sampler_view *sview = (struct si_sampler_view *)(*tex_handle)->view;
2577
2578 si_sampler_view_add_buffer(sctx, sview->base.texture, RADEON_USAGE_READ,
2579 sview->is_stencil_sampler, false);
2580 }
2581
2582 /* Add all resident image handles. */
2583 util_dynarray_foreach (&sctx->resident_img_handles, struct si_image_handle *, img_handle) {
2584 struct pipe_image_view *view = &(*img_handle)->view;
2585
2586 si_sampler_view_add_buffer(sctx, view->resource, RADEON_USAGE_READWRITE, false, false);
2587 }
2588
2589 sctx->num_resident_handles += num_resident_tex_handles + num_resident_img_handles;
2590 assert(sctx->bo_list_add_all_resident_resources);
2591 sctx->bo_list_add_all_resident_resources = false;
2592 }
2593
2594 /* INIT/DEINIT/UPLOAD */
2595
2596 void si_init_all_descriptors(struct si_context *sctx)
2597 {
2598 int i;
2599 unsigned first_shader = sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE;
2600
2601 for (i = first_shader; i < SI_NUM_SHADERS; i++) {
2602 bool is_2nd =
2603 sctx->chip_class >= GFX9 && (i == PIPE_SHADER_TESS_CTRL || i == PIPE_SHADER_GEOMETRY);
2604 unsigned num_sampler_slots = SI_NUM_IMAGE_SLOTS / 2 + SI_NUM_SAMPLERS;
2605 unsigned num_buffer_slots = SI_NUM_SHADER_BUFFERS + SI_NUM_CONST_BUFFERS;
2606 int rel_dw_offset;
2607 struct si_descriptors *desc;
2608
2609 if (is_2nd) {
2610 if (i == PIPE_SHADER_TESS_CTRL) {
2611 rel_dw_offset =
2612 (R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS - R_00B430_SPI_SHADER_USER_DATA_LS_0) / 4;
2613 } else if (sctx->chip_class >= GFX10) { /* PIPE_SHADER_GEOMETRY */
2614 rel_dw_offset =
2615 (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS - R_00B230_SPI_SHADER_USER_DATA_GS_0) / 4;
2616 } else {
2617 rel_dw_offset =
2618 (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS - R_00B330_SPI_SHADER_USER_DATA_ES_0) / 4;
2619 }
2620 } else {
2621 rel_dw_offset = SI_SGPR_CONST_AND_SHADER_BUFFERS;
2622 }
2623 desc = si_const_and_shader_buffer_descriptors(sctx, i);
2624 si_init_buffer_resources(&sctx->const_and_shader_buffers[i], desc, num_buffer_slots,
2625 rel_dw_offset, RADEON_PRIO_SHADER_RW_BUFFER,
2626 RADEON_PRIO_CONST_BUFFER);
2627 desc->slot_index_to_bind_directly = si_get_constbuf_slot(0);
2628
2629 if (is_2nd) {
2630 if (i == PIPE_SHADER_TESS_CTRL) {
2631 rel_dw_offset =
2632 (R_00B40C_SPI_SHADER_USER_DATA_ADDR_HI_HS - R_00B430_SPI_SHADER_USER_DATA_LS_0) / 4;
2633 } else if (sctx->chip_class >= GFX10) { /* PIPE_SHADER_GEOMETRY */
2634 rel_dw_offset =
2635 (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS - R_00B230_SPI_SHADER_USER_DATA_GS_0) / 4;
2636 } else {
2637 rel_dw_offset =
2638 (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS - R_00B330_SPI_SHADER_USER_DATA_ES_0) / 4;
2639 }
2640 } else {
2641 rel_dw_offset = SI_SGPR_SAMPLERS_AND_IMAGES;
2642 }
2643
2644 desc = si_sampler_and_image_descriptors(sctx, i);
2645 si_init_descriptors(desc, rel_dw_offset, 16, num_sampler_slots);
2646
2647 int j;
2648 for (j = 0; j < SI_NUM_IMAGE_SLOTS; j++)
2649 memcpy(desc->list + j * 8, null_image_descriptor, 8 * 4);
2650 for (; j < SI_NUM_IMAGE_SLOTS + SI_NUM_SAMPLERS * 2; j++)
2651 memcpy(desc->list + j * 8, null_texture_descriptor, 8 * 4);
2652 }
2653
2654 si_init_buffer_resources(&sctx->rw_buffers, &sctx->descriptors[SI_DESCS_RW_BUFFERS],
2655 SI_NUM_RW_BUFFERS, SI_SGPR_RW_BUFFERS,
2656 /* The second priority is used by
2657 * const buffers in RW buffer slots. */
2658 RADEON_PRIO_SHADER_RINGS, RADEON_PRIO_CONST_BUFFER);
2659 sctx->descriptors[SI_DESCS_RW_BUFFERS].num_active_slots = SI_NUM_RW_BUFFERS;
2660
2661 /* Initialize an array of 1024 bindless descriptors, when the limit is
2662 * reached, just make it larger and re-upload the whole array.
2663 */
2664 si_init_bindless_descriptors(sctx, &sctx->bindless_descriptors,
2665 SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES, 1024);
2666
2667 sctx->descriptors_dirty = u_bit_consecutive(0, SI_NUM_DESCS);
2668
2669 /* Set pipe_context functions. */
2670 sctx->b.bind_sampler_states = si_bind_sampler_states;
2671 sctx->b.set_shader_images = si_set_shader_images;
2672 sctx->b.set_constant_buffer = si_pipe_set_constant_buffer;
2673 sctx->b.set_shader_buffers = si_set_shader_buffers;
2674 sctx->b.set_sampler_views = si_set_sampler_views;
2675 sctx->b.create_texture_handle = si_create_texture_handle;
2676 sctx->b.delete_texture_handle = si_delete_texture_handle;
2677 sctx->b.make_texture_handle_resident = si_make_texture_handle_resident;
2678 sctx->b.create_image_handle = si_create_image_handle;
2679 sctx->b.delete_image_handle = si_delete_image_handle;
2680 sctx->b.make_image_handle_resident = si_make_image_handle_resident;
2681
2682 if (!sctx->has_graphics)
2683 return;
2684
2685 sctx->b.set_polygon_stipple = si_set_polygon_stipple;
2686
2687 /* Shader user data. */
2688 sctx->atoms.s.shader_pointers.emit = si_emit_graphics_shader_pointers;
2689
2690 /* Set default and immutable mappings. */
2691 if (sctx->ngg) {
2692 assert(sctx->chip_class >= GFX10);
2693 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B230_SPI_SHADER_USER_DATA_GS_0);
2694 } else {
2695 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0);
2696 }
2697
2698 if (sctx->chip_class == GFX9) {
2699 si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL, R_00B430_SPI_SHADER_USER_DATA_LS_0);
2700 si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY, R_00B330_SPI_SHADER_USER_DATA_ES_0);
2701 } else {
2702 si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL, R_00B430_SPI_SHADER_USER_DATA_HS_0);
2703 si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY, R_00B230_SPI_SHADER_USER_DATA_GS_0);
2704 }
2705 si_set_user_data_base(sctx, PIPE_SHADER_FRAGMENT, R_00B030_SPI_SHADER_USER_DATA_PS_0);
2706 }
2707
2708 static bool si_upload_shader_descriptors(struct si_context *sctx, unsigned mask)
2709 {
2710 unsigned dirty = sctx->descriptors_dirty & mask;
2711
2712 /* Assume nothing will go wrong: */
2713 sctx->shader_pointers_dirty |= dirty;
2714
2715 while (dirty) {
2716 unsigned i = u_bit_scan(&dirty);
2717
2718 if (!si_upload_descriptors(sctx, &sctx->descriptors[i]))
2719 return false;
2720 }
2721
2722 sctx->descriptors_dirty &= ~mask;
2723
2724 si_upload_bindless_descriptors(sctx);
2725
2726 return true;
2727 }
2728
2729 bool si_upload_graphics_shader_descriptors(struct si_context *sctx)
2730 {
2731 const unsigned mask = u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE);
2732 return si_upload_shader_descriptors(sctx, mask);
2733 }
2734
2735 bool si_upload_compute_shader_descriptors(struct si_context *sctx)
2736 {
2737 /* Does not update rw_buffers as that is not needed for compute shaders
2738 * and the input buffer is using the same SGPR's anyway.
2739 */
2740 const unsigned mask =
2741 u_bit_consecutive(SI_DESCS_FIRST_COMPUTE, SI_NUM_DESCS - SI_DESCS_FIRST_COMPUTE);
2742 return si_upload_shader_descriptors(sctx, mask);
2743 }
2744
2745 void si_release_all_descriptors(struct si_context *sctx)
2746 {
2747 int i;
2748
2749 for (i = 0; i < SI_NUM_SHADERS; i++) {
2750 si_release_buffer_resources(&sctx->const_and_shader_buffers[i],
2751 si_const_and_shader_buffer_descriptors(sctx, i));
2752 si_release_sampler_views(&sctx->samplers[i]);
2753 si_release_image_views(&sctx->images[i]);
2754 }
2755 si_release_buffer_resources(&sctx->rw_buffers, &sctx->descriptors[SI_DESCS_RW_BUFFERS]);
2756 for (i = 0; i < SI_NUM_VERTEX_BUFFERS; i++)
2757 pipe_vertex_buffer_unreference(&sctx->vertex_buffer[i]);
2758
2759 for (i = 0; i < SI_NUM_DESCS; ++i)
2760 si_release_descriptors(&sctx->descriptors[i]);
2761
2762 si_resource_reference(&sctx->vb_descriptors_buffer, NULL);
2763 sctx->vb_descriptors_gpu_list = NULL; /* points into a mapped buffer */
2764
2765 si_release_bindless_descriptors(sctx);
2766 }
2767
2768 bool si_gfx_resources_check_encrypted(struct si_context *sctx)
2769 {
2770 bool use_encrypted_bo = false;
2771 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
2772 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
2773 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
2774 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
2775 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
2776 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
2777 };
2778
2779 for (unsigned i = 0; i < SI_NUM_GRAPHICS_SHADERS && !use_encrypted_bo; i++) {
2780 if (!current_shader[i]->cso)
2781 continue;
2782
2783 use_encrypted_bo |=
2784 si_buffer_resources_check_encrypted(sctx, &sctx->const_and_shader_buffers[i]);
2785 use_encrypted_bo |=
2786 si_sampler_views_check_encrypted(sctx, &sctx->samplers[i],
2787 current_shader[i]->cso->info.samplers_declared);
2788 use_encrypted_bo |= si_image_views_check_encrypted(sctx, &sctx->images[i],
2789 current_shader[i]->cso->info.images_declared);
2790 }
2791 use_encrypted_bo |= si_buffer_resources_check_encrypted(sctx, &sctx->rw_buffers);
2792
2793 struct si_state_blend *blend = sctx->queued.named.blend;
2794 for (int i = 0; i < sctx->framebuffer.state.nr_cbufs && !use_encrypted_bo; i++) {
2795 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2796 if (surf && surf->texture) {
2797 struct si_texture *tex = (struct si_texture *)surf->texture;
2798 if (!(tex->buffer.flags & RADEON_FLAG_ENCRYPTED))
2799 continue;
2800 /* Are we reading from this framebuffer (blend) */
2801 if ((blend->blend_enable_4bit >> (4 * i)) & 0xf) {
2802 /* TODO: blend op */
2803 use_encrypted_bo = true;
2804 }
2805 }
2806 }
2807
2808 /* TODO: we should assert that either use_encrypted_bo is false,
2809 * or all writable buffers are encrypted.
2810 */
2811 return use_encrypted_bo;
2812 }
2813
2814 void si_gfx_resources_add_all_to_bo_list(struct si_context *sctx)
2815 {
2816 for (unsigned i = 0; i < SI_NUM_GRAPHICS_SHADERS; i++) {
2817 si_buffer_resources_begin_new_cs(sctx, &sctx->const_and_shader_buffers[i]);
2818 si_sampler_views_begin_new_cs(sctx, &sctx->samplers[i]);
2819 si_image_views_begin_new_cs(sctx, &sctx->images[i]);
2820 }
2821 si_buffer_resources_begin_new_cs(sctx, &sctx->rw_buffers);
2822 si_vertex_buffers_begin_new_cs(sctx);
2823
2824 if (sctx->bo_list_add_all_resident_resources)
2825 si_resident_buffers_add_all_to_bo_list(sctx);
2826
2827 assert(sctx->bo_list_add_all_gfx_resources);
2828 sctx->bo_list_add_all_gfx_resources = false;
2829 }
2830
2831 bool si_compute_resources_check_encrypted(struct si_context *sctx)
2832 {
2833 unsigned sh = PIPE_SHADER_COMPUTE;
2834
2835 struct si_shader_info* info = &sctx->cs_shader_state.program->sel.info;
2836
2837 /* TODO: we should assert that either use_encrypted_bo is false,
2838 * or all writable buffers are encrypted.
2839 */
2840 return si_buffer_resources_check_encrypted(sctx, &sctx->const_and_shader_buffers[sh]) ||
2841 si_sampler_views_check_encrypted(sctx, &sctx->samplers[sh], info->samplers_declared) ||
2842 si_image_views_check_encrypted(sctx, &sctx->images[sh], info->images_declared) ||
2843 si_buffer_resources_check_encrypted(sctx, &sctx->rw_buffers);
2844 }
2845
2846 void si_compute_resources_add_all_to_bo_list(struct si_context *sctx)
2847 {
2848 unsigned sh = PIPE_SHADER_COMPUTE;
2849
2850 si_buffer_resources_begin_new_cs(sctx, &sctx->const_and_shader_buffers[sh]);
2851 si_sampler_views_begin_new_cs(sctx, &sctx->samplers[sh]);
2852 si_image_views_begin_new_cs(sctx, &sctx->images[sh]);
2853 si_buffer_resources_begin_new_cs(sctx, &sctx->rw_buffers);
2854
2855 if (sctx->bo_list_add_all_resident_resources)
2856 si_resident_buffers_add_all_to_bo_list(sctx);
2857
2858 assert(sctx->bo_list_add_all_compute_resources);
2859 sctx->bo_list_add_all_compute_resources = false;
2860 }
2861
2862 void si_add_all_descriptors_to_bo_list(struct si_context *sctx)
2863 {
2864 for (unsigned i = 0; i < SI_NUM_DESCS; ++i)
2865 si_add_descriptors_to_bo_list(sctx, &sctx->descriptors[i]);
2866 si_add_descriptors_to_bo_list(sctx, &sctx->bindless_descriptors);
2867
2868 sctx->bo_list_add_all_resident_resources = true;
2869 sctx->bo_list_add_all_gfx_resources = true;
2870 sctx->bo_list_add_all_compute_resources = true;
2871 }
2872
2873 void si_set_active_descriptors(struct si_context *sctx, unsigned desc_idx, uint64_t new_active_mask)
2874 {
2875 struct si_descriptors *desc = &sctx->descriptors[desc_idx];
2876
2877 /* Ignore no-op updates and updates that disable all slots. */
2878 if (!new_active_mask ||
2879 new_active_mask == u_bit_consecutive64(desc->first_active_slot, desc->num_active_slots))
2880 return;
2881
2882 int first, count;
2883 u_bit_scan_consecutive_range64(&new_active_mask, &first, &count);
2884 assert(new_active_mask == 0);
2885
2886 /* Upload/dump descriptors if slots are being enabled. */
2887 if (first < desc->first_active_slot ||
2888 first + count > desc->first_active_slot + desc->num_active_slots)
2889 sctx->descriptors_dirty |= 1u << desc_idx;
2890
2891 desc->first_active_slot = first;
2892 desc->num_active_slots = count;
2893 }
2894
2895 void si_set_active_descriptors_for_shader(struct si_context *sctx, struct si_shader_selector *sel)
2896 {
2897 if (!sel)
2898 return;
2899
2900 si_set_active_descriptors(sctx, si_const_and_shader_buffer_descriptors_idx(sel->type),
2901 sel->active_const_and_shader_buffers);
2902 si_set_active_descriptors(sctx, si_sampler_and_image_descriptors_idx(sel<