ce5eba575b77c8c06d7618f9bc83d0bc076e9ef6
[mesa.git] / src / gallium / drivers / radeonsi / si_descriptors.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 /* Resource binding slots and sampler states (each described with 8 or
26 * 4 dwords) are stored in lists in memory which is accessed by shaders
27 * using scalar load instructions.
28 *
29 * This file is responsible for managing such lists. It keeps a copy of all
30 * descriptors in CPU memory and re-uploads a whole list if some slots have
31 * been changed.
32 *
33 * This code is also reponsible for updating shader pointers to those lists.
34 *
35 * Note that CP DMA can't be used for updating the lists, because a GPU hang
36 * could leave the list in a mid-IB state and the next IB would get wrong
37 * descriptors and the whole context would be unusable at that point.
38 * (Note: The register shadowing can't be used due to the same reason)
39 *
40 * Also, uploading descriptors to newly allocated memory doesn't require
41 * a KCACHE flush.
42 *
43 *
44 * Possible scenarios for one 16 dword image+sampler slot:
45 *
46 * | Image | w/ FMASK | Buffer | NULL
47 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
48 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
49 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
50 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
51 *
52 * FMASK implies MSAA, therefore no sampler state.
53 * Sampler states are never unbound except when FMASK is bound.
54 */
55
56 #include "si_pipe.h"
57 #include "si_compute.h"
58 #include "sid.h"
59 #include "util/format/u_format.h"
60 #include "util/hash_table.h"
61 #include "util/u_idalloc.h"
62 #include "util/u_memory.h"
63 #include "util/u_upload_mgr.h"
64
65 /* NULL image and buffer descriptor for textures (alpha = 1) and images
66 * (alpha = 0).
67 *
68 * For images, all fields must be zero except for the swizzle, which
69 * supports arbitrary combinations of 0s and 1s. The texture type must be
70 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
71 *
72 * For buffers, all fields must be zero. If they are not, the hw hangs.
73 *
74 * This is the only reason why the buffer descriptor must be in words [4:7].
75 */
76 static uint32_t null_texture_descriptor[8] = {
77 0, 0, 0, S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1) | S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D)
78 /* the rest must contain zeros, which is also used by the buffer
79 * descriptor */
80 };
81
82 static uint32_t null_image_descriptor[8] = {
83 0, 0, 0, S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D)
84 /* the rest must contain zeros, which is also used by the buffer
85 * descriptor */
86 };
87
88 static uint64_t si_desc_extract_buffer_address(const uint32_t *desc)
89 {
90 uint64_t va = desc[0] | ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc[1]) << 32);
91
92 /* Sign-extend the 48-bit address. */
93 va <<= 16;
94 va = (int64_t)va >> 16;
95 return va;
96 }
97
98 static void si_init_descriptor_list(uint32_t *desc_list, unsigned element_dw_size,
99 unsigned num_elements, const uint32_t *null_descriptor)
100 {
101 int i;
102
103 /* Initialize the array to NULL descriptors if the element size is 8. */
104 if (null_descriptor) {
105 assert(element_dw_size % 8 == 0);
106 for (i = 0; i < num_elements * element_dw_size / 8; i++)
107 memcpy(desc_list + i * 8, null_descriptor, 8 * 4);
108 }
109 }
110
111 static void si_init_descriptors(struct si_descriptors *desc, short shader_userdata_rel_index,
112 unsigned element_dw_size, unsigned num_elements)
113 {
114 desc->list = CALLOC(num_elements, element_dw_size * 4);
115 desc->element_dw_size = element_dw_size;
116 desc->num_elements = num_elements;
117 desc->shader_userdata_offset = shader_userdata_rel_index * 4;
118 desc->slot_index_to_bind_directly = -1;
119 }
120
121 static void si_release_descriptors(struct si_descriptors *desc)
122 {
123 si_resource_reference(&desc->buffer, NULL);
124 FREE(desc->list);
125 }
126
127 static bool si_upload_descriptors(struct si_context *sctx, struct si_descriptors *desc)
128 {
129 unsigned slot_size = desc->element_dw_size * 4;
130 unsigned first_slot_offset = desc->first_active_slot * slot_size;
131 unsigned upload_size = desc->num_active_slots * slot_size;
132
133 /* Skip the upload if no shader is using the descriptors. dirty_mask
134 * will stay dirty and the descriptors will be uploaded when there is
135 * a shader using them.
136 */
137 if (!upload_size)
138 return true;
139
140 /* If there is just one active descriptor, bind it directly. */
141 if ((int)desc->first_active_slot == desc->slot_index_to_bind_directly &&
142 desc->num_active_slots == 1) {
143 uint32_t *descriptor = &desc->list[desc->slot_index_to_bind_directly * desc->element_dw_size];
144
145 /* The buffer is already in the buffer list. */
146 si_resource_reference(&desc->buffer, NULL);
147 desc->gpu_list = NULL;
148 desc->gpu_address = si_desc_extract_buffer_address(descriptor);
149 si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
150 return true;
151 }
152
153 uint32_t *ptr;
154 unsigned buffer_offset;
155 u_upload_alloc(sctx->b.const_uploader, first_slot_offset, upload_size,
156 si_optimal_tcc_alignment(sctx, upload_size), &buffer_offset,
157 (struct pipe_resource **)&desc->buffer, (void **)&ptr);
158 if (!desc->buffer) {
159 desc->gpu_address = 0;
160 return false; /* skip the draw call */
161 }
162
163 util_memcpy_cpu_to_le32(ptr, (char *)desc->list + first_slot_offset, upload_size);
164 desc->gpu_list = ptr - first_slot_offset / 4;
165
166 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, desc->buffer, RADEON_USAGE_READ,
167 RADEON_PRIO_DESCRIPTORS);
168
169 /* The shader pointer should point to slot 0. */
170 buffer_offset -= first_slot_offset;
171 desc->gpu_address = desc->buffer->gpu_address + buffer_offset;
172
173 assert(desc->buffer->flags & RADEON_FLAG_32BIT);
174 assert((desc->buffer->gpu_address >> 32) == sctx->screen->info.address32_hi);
175 assert((desc->gpu_address >> 32) == sctx->screen->info.address32_hi);
176
177 si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
178 return true;
179 }
180
181 static void
182 si_add_descriptors_to_bo_list(struct si_context *sctx, struct si_descriptors *desc)
183 {
184 if (!desc->buffer)
185 return;
186
187 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, desc->buffer, RADEON_USAGE_READ,
188 RADEON_PRIO_DESCRIPTORS);
189 }
190
191 /* SAMPLER VIEWS */
192
193 static inline enum radeon_bo_priority si_get_sampler_view_priority(struct si_resource *res)
194 {
195 if (res->b.b.target == PIPE_BUFFER)
196 return RADEON_PRIO_SAMPLER_BUFFER;
197
198 if (res->b.b.nr_samples > 1)
199 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
200
201 return RADEON_PRIO_SAMPLER_TEXTURE;
202 }
203
204 static struct si_descriptors *si_sampler_and_image_descriptors(struct si_context *sctx,
205 unsigned shader)
206 {
207 return &sctx->descriptors[si_sampler_and_image_descriptors_idx(shader)];
208 }
209
210 static void si_release_sampler_views(struct si_samplers *samplers)
211 {
212 int i;
213
214 for (i = 0; i < ARRAY_SIZE(samplers->views); i++) {
215 pipe_sampler_view_reference(&samplers->views[i], NULL);
216 }
217 }
218
219 static void si_sampler_view_add_buffer(struct si_context *sctx, struct pipe_resource *resource,
220 enum radeon_bo_usage usage, bool is_stencil_sampler,
221 bool check_mem)
222 {
223 struct si_texture *tex = (struct si_texture *)resource;
224 enum radeon_bo_priority priority;
225
226 if (!resource)
227 return;
228
229 /* Use the flushed depth texture if direct sampling is unsupported. */
230 if (resource->target != PIPE_BUFFER && tex->is_depth &&
231 !si_can_sample_zs(tex, is_stencil_sampler))
232 tex = tex->flushed_depth_texture;
233
234 priority = si_get_sampler_view_priority(&tex->buffer);
235 radeon_add_to_gfx_buffer_list_check_mem(sctx, &tex->buffer, usage, priority, check_mem);
236
237 if (resource->target == PIPE_BUFFER)
238 return;
239
240 /* Add separate DCC. */
241 if (tex->dcc_separate_buffer) {
242 radeon_add_to_gfx_buffer_list_check_mem(sctx, tex->dcc_separate_buffer, usage,
243 RADEON_PRIO_SEPARATE_META, check_mem);
244 }
245 }
246
247 static void si_sampler_views_begin_new_cs(struct si_context *sctx, struct si_samplers *samplers)
248 {
249 unsigned mask = samplers->enabled_mask;
250
251 /* Add buffers to the CS. */
252 while (mask) {
253 int i = u_bit_scan(&mask);
254 struct si_sampler_view *sview = (struct si_sampler_view *)samplers->views[i];
255
256 si_sampler_view_add_buffer(sctx, sview->base.texture, RADEON_USAGE_READ,
257 sview->is_stencil_sampler, false);
258 }
259 }
260
261 static bool si_sampler_views_check_encrypted(struct si_context *sctx, struct si_samplers *samplers,
262 unsigned samplers_declared)
263 {
264 unsigned mask = samplers->enabled_mask & samplers_declared;
265
266 /* Verify if a samplers uses an encrypted resource */
267 while (mask) {
268 int i = u_bit_scan(&mask);
269 struct si_sampler_view *sview = (struct si_sampler_view *)samplers->views[i];
270
271 struct si_resource *res = si_resource(sview->base.texture);
272 if (res->flags & RADEON_FLAG_ENCRYPTED)
273 return true;
274 }
275 return false;
276 }
277
278 /* Set buffer descriptor fields that can be changed by reallocations. */
279 static void si_set_buf_desc_address(struct si_resource *buf, uint64_t offset, uint32_t *state)
280 {
281 uint64_t va = buf->gpu_address + offset;
282
283 state[0] = va;
284 state[1] &= C_008F04_BASE_ADDRESS_HI;
285 state[1] |= S_008F04_BASE_ADDRESS_HI(va >> 32);
286 }
287
288 /* Set texture descriptor fields that can be changed by reallocations.
289 *
290 * \param tex texture
291 * \param base_level_info information of the level of BASE_ADDRESS
292 * \param base_level the level of BASE_ADDRESS
293 * \param first_level pipe_sampler_view.u.tex.first_level
294 * \param block_width util_format_get_blockwidth()
295 * \param is_stencil select between separate Z & Stencil
296 * \param state descriptor to update
297 */
298 void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture *tex,
299 const struct legacy_surf_level *base_level_info,
300 unsigned base_level, unsigned first_level, unsigned block_width,
301 bool is_stencil, bool force_dcc_off, uint32_t *state)
302 {
303 uint64_t va, meta_va = 0;
304
305 if (tex->is_depth && !si_can_sample_zs(tex, is_stencil)) {
306 tex = tex->flushed_depth_texture;
307 is_stencil = false;
308 }
309
310 va = tex->buffer.gpu_address;
311
312 if (sscreen->info.chip_class >= GFX9) {
313 /* Only stencil_offset needs to be added here. */
314 if (is_stencil)
315 va += tex->surface.u.gfx9.stencil_offset;
316 else
317 va += tex->surface.u.gfx9.surf_offset;
318 } else {
319 va += base_level_info->offset;
320 }
321
322 state[0] = va >> 8;
323 state[1] &= C_008F14_BASE_ADDRESS_HI;
324 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
325
326 /* Only macrotiled modes can set tile swizzle.
327 * GFX9 doesn't use (legacy) base_level_info.
328 */
329 if (sscreen->info.chip_class >= GFX9 || base_level_info->mode == RADEON_SURF_MODE_2D)
330 state[0] |= tex->surface.tile_swizzle;
331
332 if (sscreen->info.chip_class >= GFX8) {
333 state[6] &= C_008F28_COMPRESSION_EN;
334
335 if (!force_dcc_off && vi_dcc_enabled(tex, first_level)) {
336 meta_va =
337 (!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) + tex->surface.dcc_offset;
338
339 if (sscreen->info.chip_class == GFX8) {
340 meta_va += base_level_info->dcc_offset;
341 assert(base_level_info->mode == RADEON_SURF_MODE_2D);
342 }
343
344 unsigned dcc_tile_swizzle = tex->surface.tile_swizzle << 8;
345 dcc_tile_swizzle &= tex->surface.dcc_alignment - 1;
346 meta_va |= dcc_tile_swizzle;
347 } else if (vi_tc_compat_htile_enabled(tex, first_level,
348 is_stencil ? PIPE_MASK_S : PIPE_MASK_Z)) {
349 meta_va = tex->buffer.gpu_address + tex->surface.htile_offset;
350 }
351
352 if (meta_va)
353 state[6] |= S_008F28_COMPRESSION_EN(1);
354 }
355
356 if (sscreen->info.chip_class >= GFX8 && sscreen->info.chip_class <= GFX9)
357 state[7] = meta_va >> 8;
358
359 if (sscreen->info.chip_class >= GFX10) {
360 state[3] &= C_00A00C_SW_MODE;
361
362 if (is_stencil) {
363 state[3] |= S_00A00C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
364 } else {
365 state[3] |= S_00A00C_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode);
366 }
367
368 state[6] &= C_00A018_META_DATA_ADDRESS_LO & C_00A018_META_PIPE_ALIGNED;
369
370 if (meta_va) {
371 struct gfx9_surf_meta_flags meta = {
372 .rb_aligned = 1,
373 .pipe_aligned = 1,
374 };
375
376 if (tex->surface.dcc_offset)
377 meta = tex->surface.u.gfx9.dcc;
378
379 state[6] |= S_00A018_META_PIPE_ALIGNED(meta.pipe_aligned) |
380 S_00A018_META_DATA_ADDRESS_LO(meta_va >> 8);
381 }
382
383 state[7] = meta_va >> 16;
384 } else if (sscreen->info.chip_class == GFX9) {
385 state[3] &= C_008F1C_SW_MODE;
386 state[4] &= C_008F20_PITCH;
387
388 if (is_stencil) {
389 state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
390 state[4] |= S_008F20_PITCH(tex->surface.u.gfx9.stencil.epitch);
391 } else {
392 uint16_t epitch = tex->surface.u.gfx9.surf.epitch;
393 if (tex->buffer.b.b.format == PIPE_FORMAT_R8G8_R8B8_UNORM &&
394 block_width == 1) {
395 /* epitch is patched in ac_surface for sdma/vcn blocks to get
396 * a value expressed in elements unit.
397 * But here the texture is used with block_width == 1 so we
398 * need epitch in pixel units.
399 */
400 epitch = (epitch + 1) / tex->surface.blk_w - 1;
401 }
402 state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode);
403 state[4] |= S_008F20_PITCH(epitch);
404 }
405
406 state[5] &=
407 C_008F24_META_DATA_ADDRESS & C_008F24_META_PIPE_ALIGNED & C_008F24_META_RB_ALIGNED;
408 if (meta_va) {
409 struct gfx9_surf_meta_flags meta = {
410 .rb_aligned = 1,
411 .pipe_aligned = 1,
412 };
413
414 if (tex->surface.dcc_offset)
415 meta = tex->surface.u.gfx9.dcc;
416
417 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
418 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
419 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
420 }
421 } else {
422 /* GFX6-GFX8 */
423 unsigned pitch = base_level_info->nblk_x * block_width;
424 unsigned index = si_tile_mode_index(tex, base_level, is_stencil);
425
426 state[3] &= C_008F1C_TILING_INDEX;
427 state[3] |= S_008F1C_TILING_INDEX(index);
428 state[4] &= C_008F20_PITCH;
429 state[4] |= S_008F20_PITCH(pitch - 1);
430 }
431 }
432
433 static void si_set_sampler_state_desc(struct si_sampler_state *sstate,
434 struct si_sampler_view *sview, struct si_texture *tex,
435 uint32_t *desc)
436 {
437 if (sview && sview->is_integer)
438 memcpy(desc, sstate->integer_val, 4 * 4);
439 else if (tex && tex->upgraded_depth && (!sview || !sview->is_stencil_sampler))
440 memcpy(desc, sstate->upgraded_depth_val, 4 * 4);
441 else
442 memcpy(desc, sstate->val, 4 * 4);
443 }
444
445 static void si_set_sampler_view_desc(struct si_context *sctx, struct si_sampler_view *sview,
446 struct si_sampler_state *sstate, uint32_t *desc)
447 {
448 struct pipe_sampler_view *view = &sview->base;
449 struct si_texture *tex = (struct si_texture *)view->texture;
450 bool is_buffer = tex->buffer.b.b.target == PIPE_BUFFER;
451
452 if (unlikely(!is_buffer && sview->dcc_incompatible)) {
453 if (vi_dcc_enabled(tex, view->u.tex.first_level))
454 if (!si_texture_disable_dcc(sctx, tex))
455 si_decompress_dcc(sctx, tex);
456
457 sview->dcc_incompatible = false;
458 }
459
460 assert(tex); /* views with texture == NULL aren't supported */
461 memcpy(desc, sview->state, 8 * 4);
462
463 if (is_buffer) {
464 si_set_buf_desc_address(&tex->buffer, sview->base.u.buf.offset, desc + 4);
465 } else {
466 bool is_separate_stencil = tex->db_compatible && sview->is_stencil_sampler;
467
468 si_set_mutable_tex_desc_fields(sctx->screen, tex, sview->base_level_info, sview->base_level,
469 sview->base.u.tex.first_level, sview->block_width,
470 is_separate_stencil, false, desc);
471 }
472
473 if (!is_buffer && tex->surface.fmask_size) {
474 memcpy(desc + 8, sview->fmask_state, 8 * 4);
475 } else {
476 /* Disable FMASK and bind sampler state in [12:15]. */
477 memcpy(desc + 8, null_texture_descriptor, 4 * 4);
478
479 if (sstate)
480 si_set_sampler_state_desc(sstate, sview, is_buffer ? NULL : tex, desc + 12);
481 }
482 }
483
484 static bool color_needs_decompression(struct si_texture *tex)
485 {
486 return tex->surface.fmask_size ||
487 (tex->dirty_level_mask && (tex->cmask_buffer || tex->surface.dcc_offset));
488 }
489
490 static bool depth_needs_decompression(struct si_texture *tex)
491 {
492 /* If the depth/stencil texture is TC-compatible, no decompression
493 * will be done. The decompression function will only flush DB caches
494 * to make it coherent with shaders. That's necessary because the driver
495 * doesn't flush DB caches in any other case.
496 */
497 return tex->db_compatible;
498 }
499
500 static void si_set_sampler_view(struct si_context *sctx, unsigned shader, unsigned slot,
501 struct pipe_sampler_view *view, bool disallow_early_out)
502 {
503 struct si_samplers *samplers = &sctx->samplers[shader];
504 struct si_sampler_view *sview = (struct si_sampler_view *)view;
505 struct si_descriptors *descs = si_sampler_and_image_descriptors(sctx, shader);
506 unsigned desc_slot = si_get_sampler_slot(slot);
507 uint32_t *desc = descs->list + desc_slot * 16;
508
509 if (samplers->views[slot] == view && !disallow_early_out)
510 return;
511
512 if (view) {
513 struct si_texture *tex = (struct si_texture *)view->texture;
514
515 si_set_sampler_view_desc(sctx, sview, samplers->sampler_states[slot], desc);
516
517 if (tex->buffer.b.b.target == PIPE_BUFFER) {
518 tex->buffer.bind_history |= PIPE_BIND_SAMPLER_VIEW;
519 samplers->needs_depth_decompress_mask &= ~(1u << slot);
520 samplers->needs_color_decompress_mask &= ~(1u << slot);
521 } else {
522 if (depth_needs_decompression(tex)) {
523 samplers->needs_depth_decompress_mask |= 1u << slot;
524 } else {
525 samplers->needs_depth_decompress_mask &= ~(1u << slot);
526 }
527 if (color_needs_decompression(tex)) {
528 samplers->needs_color_decompress_mask |= 1u << slot;
529 } else {
530 samplers->needs_color_decompress_mask &= ~(1u << slot);
531 }
532
533 if (vi_dcc_enabled(tex, view->u.tex.first_level) &&
534 p_atomic_read(&tex->framebuffers_bound))
535 sctx->need_check_render_feedback = true;
536 }
537
538 pipe_sampler_view_reference(&samplers->views[slot], view);
539 samplers->enabled_mask |= 1u << slot;
540
541 /* Since this can flush, it must be done after enabled_mask is
542 * updated. */
543 si_sampler_view_add_buffer(sctx, view->texture, RADEON_USAGE_READ, sview->is_stencil_sampler,
544 true);
545 } else {
546 pipe_sampler_view_reference(&samplers->views[slot], NULL);
547 memcpy(desc, null_texture_descriptor, 8 * 4);
548 /* Only clear the lower dwords of FMASK. */
549 memcpy(desc + 8, null_texture_descriptor, 4 * 4);
550 /* Re-set the sampler state if we are transitioning from FMASK. */
551 if (samplers->sampler_states[slot])
552 si_set_sampler_state_desc(samplers->sampler_states[slot], NULL, NULL, desc + 12);
553
554 samplers->enabled_mask &= ~(1u << slot);
555 samplers->needs_depth_decompress_mask &= ~(1u << slot);
556 samplers->needs_color_decompress_mask &= ~(1u << slot);
557 }
558
559 sctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
560 }
561
562 static void si_update_shader_needs_decompress_mask(struct si_context *sctx, unsigned shader)
563 {
564 struct si_samplers *samplers = &sctx->samplers[shader];
565 unsigned shader_bit = 1 << shader;
566
567 if (samplers->needs_depth_decompress_mask || samplers->needs_color_decompress_mask ||
568 sctx->images[shader].needs_color_decompress_mask)
569 sctx->shader_needs_decompress_mask |= shader_bit;
570 else
571 sctx->shader_needs_decompress_mask &= ~shader_bit;
572 }
573
574 static void si_set_sampler_views(struct pipe_context *ctx, enum pipe_shader_type shader,
575 unsigned start, unsigned count, struct pipe_sampler_view **views)
576 {
577 struct si_context *sctx = (struct si_context *)ctx;
578 int i;
579
580 if (!count || shader >= SI_NUM_SHADERS)
581 return;
582
583 if (views) {
584 for (i = 0; i < count; i++)
585 si_set_sampler_view(sctx, shader, start + i, views[i], false);
586 } else {
587 for (i = 0; i < count; i++)
588 si_set_sampler_view(sctx, shader, start + i, NULL, false);
589 }
590
591 si_update_shader_needs_decompress_mask(sctx, shader);
592 }
593
594 static void si_samplers_update_needs_color_decompress_mask(struct si_samplers *samplers)
595 {
596 unsigned mask = samplers->enabled_mask;
597
598 while (mask) {
599 int i = u_bit_scan(&mask);
600 struct pipe_resource *res = samplers->views[i]->texture;
601
602 if (res && res->target != PIPE_BUFFER) {
603 struct si_texture *tex = (struct si_texture *)res;
604
605 if (color_needs_decompression(tex)) {
606 samplers->needs_color_decompress_mask |= 1u << i;
607 } else {
608 samplers->needs_color_decompress_mask &= ~(1u << i);
609 }
610 }
611 }
612 }
613
614 /* IMAGE VIEWS */
615
616 static void si_release_image_views(struct si_images *images)
617 {
618 unsigned i;
619
620 for (i = 0; i < SI_NUM_IMAGES; ++i) {
621 struct pipe_image_view *view = &images->views[i];
622
623 pipe_resource_reference(&view->resource, NULL);
624 }
625 }
626
627 static void si_image_views_begin_new_cs(struct si_context *sctx, struct si_images *images)
628 {
629 uint mask = images->enabled_mask;
630
631 /* Add buffers to the CS. */
632 while (mask) {
633 int i = u_bit_scan(&mask);
634 struct pipe_image_view *view = &images->views[i];
635
636 assert(view->resource);
637
638 si_sampler_view_add_buffer(sctx, view->resource, RADEON_USAGE_READWRITE, false, false);
639 }
640 }
641
642 static bool si_image_views_check_encrypted(struct si_context *sctx, struct si_images *images,
643 unsigned images_declared)
644 {
645 uint mask = images->enabled_mask & images_declared;
646
647 while (mask) {
648 int i = u_bit_scan(&mask);
649 struct pipe_image_view *view = &images->views[i];
650
651 assert(view->resource);
652
653 struct si_texture *tex = (struct si_texture *)view->resource;
654 if (tex->buffer.flags & RADEON_FLAG_ENCRYPTED)
655 return true;
656 }
657 return false;
658 }
659
660 static void si_disable_shader_image(struct si_context *ctx, unsigned shader, unsigned slot)
661 {
662 struct si_images *images = &ctx->images[shader];
663
664 if (images->enabled_mask & (1u << slot)) {
665 struct si_descriptors *descs = si_sampler_and_image_descriptors(ctx, shader);
666 unsigned desc_slot = si_get_image_slot(slot);
667
668 pipe_resource_reference(&images->views[slot].resource, NULL);
669 images->needs_color_decompress_mask &= ~(1 << slot);
670
671 memcpy(descs->list + desc_slot * 8, null_image_descriptor, 8 * 4);
672 images->enabled_mask &= ~(1u << slot);
673 ctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
674 }
675 }
676
677 static void si_mark_image_range_valid(const struct pipe_image_view *view)
678 {
679 struct si_resource *res = si_resource(view->resource);
680
681 if (res->b.b.target != PIPE_BUFFER)
682 return;
683
684 util_range_add(&res->b.b, &res->valid_buffer_range, view->u.buf.offset,
685 view->u.buf.offset + view->u.buf.size);
686 }
687
688 static void si_set_shader_image_desc(struct si_context *ctx, const struct pipe_image_view *view,
689 bool skip_decompress, uint32_t *desc, uint32_t *fmask_desc)
690 {
691 struct si_screen *screen = ctx->screen;
692 struct si_resource *res;
693
694 res = si_resource(view->resource);
695
696 if (res->b.b.target == PIPE_BUFFER || view->shader_access & SI_IMAGE_ACCESS_AS_BUFFER) {
697 if (view->access & PIPE_IMAGE_ACCESS_WRITE)
698 si_mark_image_range_valid(view);
699
700 si_make_buffer_descriptor(screen, res, view->format, view->u.buf.offset, view->u.buf.size,
701 desc);
702 si_set_buf_desc_address(res, view->u.buf.offset, desc + 4);
703 } else {
704 static const unsigned char swizzle[4] = {0, 1, 2, 3};
705 struct si_texture *tex = (struct si_texture *)res;
706 unsigned level = view->u.tex.level;
707 unsigned width, height, depth, hw_level;
708 bool uses_dcc = vi_dcc_enabled(tex, level);
709 unsigned access = view->access;
710
711 assert(!tex->is_depth);
712 assert(fmask_desc || tex->surface.fmask_offset == 0);
713
714 if (uses_dcc && !skip_decompress &&
715 !(access & SI_IMAGE_ACCESS_DCC_OFF) &&
716 (access & PIPE_IMAGE_ACCESS_WRITE ||
717 !vi_dcc_formats_compatible(screen, res->b.b.format, view->format))) {
718 /* If DCC can't be disabled, at least decompress it.
719 * The decompression is relatively cheap if the surface
720 * has been decompressed already.
721 */
722 if (!si_texture_disable_dcc(ctx, tex))
723 si_decompress_dcc(ctx, tex);
724 }
725
726 if (ctx->chip_class >= GFX9) {
727 /* Always set the base address. The swizzle modes don't
728 * allow setting mipmap level offsets as the base.
729 */
730 width = res->b.b.width0;
731 height = res->b.b.height0;
732 depth = res->b.b.depth0;
733 hw_level = level;
734 } else {
735 /* Always force the base level to the selected level.
736 *
737 * This is required for 3D textures, where otherwise
738 * selecting a single slice for non-layered bindings
739 * fails. It doesn't hurt the other targets.
740 */
741 width = u_minify(res->b.b.width0, level);
742 height = u_minify(res->b.b.height0, level);
743 depth = u_minify(res->b.b.depth0, level);
744 hw_level = 0;
745 }
746
747 screen->make_texture_descriptor(
748 screen, tex, false, res->b.b.target, view->format, swizzle, hw_level, hw_level,
749 view->u.tex.first_layer, view->u.tex.last_layer, width, height, depth, desc, fmask_desc);
750 si_set_mutable_tex_desc_fields(screen, tex, &tex->surface.u.legacy.level[level], level, level,
751 util_format_get_blockwidth(view->format), false,
752 view->access & SI_IMAGE_ACCESS_DCC_OFF, desc);
753 }
754 }
755
756 static void si_set_shader_image(struct si_context *ctx, unsigned shader, unsigned slot,
757 const struct pipe_image_view *view, bool skip_decompress)
758 {
759 struct si_images *images = &ctx->images[shader];
760 struct si_descriptors *descs = si_sampler_and_image_descriptors(ctx, shader);
761 struct si_resource *res;
762
763 if (!view || !view->resource) {
764 si_disable_shader_image(ctx, shader, slot);
765 return;
766 }
767
768 res = si_resource(view->resource);
769
770 si_set_shader_image_desc(ctx, view, skip_decompress, descs->list + si_get_image_slot(slot) * 8,
771 descs->list + si_get_image_slot(slot + SI_NUM_IMAGES) * 8);
772
773 if (&images->views[slot] != view)
774 util_copy_image_view(&images->views[slot], view);
775
776 if (res->b.b.target == PIPE_BUFFER || view->shader_access & SI_IMAGE_ACCESS_AS_BUFFER) {
777 images->needs_color_decompress_mask &= ~(1 << slot);
778 res->bind_history |= PIPE_BIND_SHADER_IMAGE;
779 } else {
780 struct si_texture *tex = (struct si_texture *)res;
781 unsigned level = view->u.tex.level;
782
783 if (color_needs_decompression(tex)) {
784 images->needs_color_decompress_mask |= 1 << slot;
785 } else {
786 images->needs_color_decompress_mask &= ~(1 << slot);
787 }
788
789 if (vi_dcc_enabled(tex, level) && p_atomic_read(&tex->framebuffers_bound))
790 ctx->need_check_render_feedback = true;
791 }
792
793 images->enabled_mask |= 1u << slot;
794 ctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
795
796 /* Since this can flush, it must be done after enabled_mask is updated. */
797 si_sampler_view_add_buffer(
798 ctx, &res->b.b,
799 (view->access & PIPE_IMAGE_ACCESS_WRITE) ? RADEON_USAGE_READWRITE : RADEON_USAGE_READ, false,
800 true);
801 }
802
803 static void si_set_shader_images(struct pipe_context *pipe, enum pipe_shader_type shader,
804 unsigned start_slot, unsigned count,
805 const struct pipe_image_view *views)
806 {
807 struct si_context *ctx = (struct si_context *)pipe;
808 unsigned i, slot;
809
810 assert(shader < SI_NUM_SHADERS);
811
812 if (!count)
813 return;
814
815 assert(start_slot + count <= SI_NUM_IMAGES);
816
817 if (views) {
818 for (i = 0, slot = start_slot; i < count; ++i, ++slot)
819 si_set_shader_image(ctx, shader, slot, &views[i], false);
820 } else {
821 for (i = 0, slot = start_slot; i < count; ++i, ++slot)
822 si_set_shader_image(ctx, shader, slot, NULL, false);
823 }
824
825 if (shader == PIPE_SHADER_COMPUTE &&
826 ctx->cs_shader_state.program &&
827 start_slot < ctx->cs_shader_state.program->sel.cs_num_images_in_user_sgprs)
828 ctx->compute_image_sgprs_dirty = true;
829
830 si_update_shader_needs_decompress_mask(ctx, shader);
831 }
832
833 static void si_images_update_needs_color_decompress_mask(struct si_images *images)
834 {
835 unsigned mask = images->enabled_mask;
836
837 while (mask) {
838 int i = u_bit_scan(&mask);
839 struct pipe_resource *res = images->views[i].resource;
840
841 if (res && res->target != PIPE_BUFFER) {
842 struct si_texture *tex = (struct si_texture *)res;
843
844 if (color_needs_decompression(tex)) {
845 images->needs_color_decompress_mask |= 1 << i;
846 } else {
847 images->needs_color_decompress_mask &= ~(1 << i);
848 }
849 }
850 }
851 }
852
853 void si_update_ps_colorbuf0_slot(struct si_context *sctx)
854 {
855 struct si_buffer_resources *buffers = &sctx->rw_buffers;
856 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
857 unsigned slot = SI_PS_IMAGE_COLORBUF0;
858 struct pipe_surface *surf = NULL;
859
860 /* si_texture_disable_dcc can get us here again. */
861 if (sctx->blitter->running)
862 return;
863
864 /* See whether FBFETCH is used and color buffer 0 is set. */
865 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_fbfetch &&
866 sctx->framebuffer.state.nr_cbufs && sctx->framebuffer.state.cbufs[0])
867 surf = sctx->framebuffer.state.cbufs[0];
868
869 /* Return if FBFETCH transitions from disabled to disabled. */
870 if (!buffers->buffers[slot] && !surf)
871 return;
872
873 sctx->ps_uses_fbfetch = surf != NULL;
874 si_update_ps_iter_samples(sctx);
875
876 if (surf) {
877 struct si_texture *tex = (struct si_texture *)surf->texture;
878 struct pipe_image_view view = {0};
879
880 assert(tex);
881 assert(!tex->is_depth);
882
883 /* Disable DCC, because the texture is used as both a sampler
884 * and color buffer.
885 */
886 si_texture_disable_dcc(sctx, tex);
887
888 if (tex->buffer.b.b.nr_samples <= 1 && tex->cmask_buffer) {
889 /* Disable CMASK. */
890 assert(tex->cmask_buffer != &tex->buffer);
891 si_eliminate_fast_color_clear(sctx, tex, NULL);
892 si_texture_discard_cmask(sctx->screen, tex);
893 }
894
895 view.resource = surf->texture;
896 view.format = surf->format;
897 view.access = PIPE_IMAGE_ACCESS_READ;
898 view.u.tex.first_layer = surf->u.tex.first_layer;
899 view.u.tex.last_layer = surf->u.tex.last_layer;
900 view.u.tex.level = surf->u.tex.level;
901
902 /* Set the descriptor. */
903 uint32_t *desc = descs->list + slot * 4;
904 memset(desc, 0, 16 * 4);
905 si_set_shader_image_desc(sctx, &view, true, desc, desc + 8);
906
907 pipe_resource_reference(&buffers->buffers[slot], &tex->buffer.b.b);
908 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READ,
909 RADEON_PRIO_SHADER_RW_IMAGE);
910 buffers->enabled_mask |= 1llu << slot;
911 } else {
912 /* Clear the descriptor. */
913 memset(descs->list + slot * 4, 0, 8 * 4);
914 pipe_resource_reference(&buffers->buffers[slot], NULL);
915 buffers->enabled_mask &= ~(1llu << slot);
916 }
917
918 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
919 }
920
921 /* SAMPLER STATES */
922
923 static void si_bind_sampler_states(struct pipe_context *ctx, enum pipe_shader_type shader,
924 unsigned start, unsigned count, void **states)
925 {
926 struct si_context *sctx = (struct si_context *)ctx;
927 struct si_samplers *samplers = &sctx->samplers[shader];
928 struct si_descriptors *desc = si_sampler_and_image_descriptors(sctx, shader);
929 struct si_sampler_state **sstates = (struct si_sampler_state **)states;
930 int i;
931
932 if (!count || shader >= SI_NUM_SHADERS || !sstates)
933 return;
934
935 for (i = 0; i < count; i++) {
936 unsigned slot = start + i;
937 unsigned desc_slot = si_get_sampler_slot(slot);
938
939 if (!sstates[i] || sstates[i] == samplers->sampler_states[slot])
940 continue;
941
942 #ifndef NDEBUG
943 assert(sstates[i]->magic == SI_SAMPLER_STATE_MAGIC);
944 #endif
945 samplers->sampler_states[slot] = sstates[i];
946
947 /* If FMASK is bound, don't overwrite it.
948 * The sampler state will be set after FMASK is unbound.
949 */
950 struct si_sampler_view *sview = (struct si_sampler_view *)samplers->views[slot];
951
952 struct si_texture *tex = NULL;
953
954 if (sview && sview->base.texture && sview->base.texture->target != PIPE_BUFFER)
955 tex = (struct si_texture *)sview->base.texture;
956
957 if (tex && tex->surface.fmask_size)
958 continue;
959
960 si_set_sampler_state_desc(sstates[i], sview, tex, desc->list + desc_slot * 16 + 12);
961
962 sctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
963 }
964 }
965
966 /* BUFFER RESOURCES */
967
968 static void si_init_buffer_resources(struct si_buffer_resources *buffers,
969 struct si_descriptors *descs, unsigned num_buffers,
970 short shader_userdata_rel_index,
971 enum radeon_bo_priority priority,
972 enum radeon_bo_priority priority_constbuf)
973 {
974 buffers->priority = priority;
975 buffers->priority_constbuf = priority_constbuf;
976 buffers->buffers = CALLOC(num_buffers, sizeof(struct pipe_resource *));
977 buffers->offsets = CALLOC(num_buffers, sizeof(buffers->offsets[0]));
978
979 si_init_descriptors(descs, shader_userdata_rel_index, 4, num_buffers);
980 }
981
982 static void si_release_buffer_resources(struct si_buffer_resources *buffers,
983 struct si_descriptors *descs)
984 {
985 int i;
986
987 for (i = 0; i < descs->num_elements; i++) {
988 pipe_resource_reference(&buffers->buffers[i], NULL);
989 }
990
991 FREE(buffers->buffers);
992 FREE(buffers->offsets);
993 }
994
995 static void si_buffer_resources_begin_new_cs(struct si_context *sctx,
996 struct si_buffer_resources *buffers)
997 {
998 uint64_t mask = buffers->enabled_mask;
999
1000 /* Add buffers to the CS. */
1001 while (mask) {
1002 int i = u_bit_scan64(&mask);
1003
1004 radeon_add_to_buffer_list(
1005 sctx, sctx->gfx_cs, si_resource(buffers->buffers[i]),
1006 buffers->writable_mask & (1llu << i) ? RADEON_USAGE_READWRITE : RADEON_USAGE_READ,
1007 i < SI_NUM_SHADER_BUFFERS ? buffers->priority : buffers->priority_constbuf);
1008 }
1009 }
1010
1011 static bool si_buffer_resources_check_encrypted(struct si_context *sctx,
1012 struct si_buffer_resources *buffers)
1013 {
1014 uint64_t mask = buffers->enabled_mask;
1015
1016 while (mask) {
1017 int i = u_bit_scan64(&mask);
1018
1019 /* only check for reads */
1020 if ((buffers->writable_mask & (1llu << i)) == 0 &&
1021 (si_resource(buffers->buffers[i])->flags & RADEON_FLAG_ENCRYPTED))
1022 return true;
1023 }
1024
1025 return false;
1026 }
1027
1028 static void si_get_buffer_from_descriptors(struct si_buffer_resources *buffers,
1029 struct si_descriptors *descs, unsigned idx,
1030 struct pipe_resource **buf, unsigned *offset,
1031 unsigned *size)
1032 {
1033 pipe_resource_reference(buf, buffers->buffers[idx]);
1034 if (*buf) {
1035 struct si_resource *res = si_resource(*buf);
1036 const uint32_t *desc = descs->list + idx * 4;
1037 uint64_t va;
1038
1039 *size = desc[2];
1040
1041 assert(G_008F04_STRIDE(desc[1]) == 0);
1042 va = si_desc_extract_buffer_address(desc);
1043
1044 assert(va >= res->gpu_address && va + *size <= res->gpu_address + res->bo_size);
1045 *offset = va - res->gpu_address;
1046 }
1047 }
1048
1049 /* VERTEX BUFFERS */
1050
1051 static void si_vertex_buffers_begin_new_cs(struct si_context *sctx)
1052 {
1053 int count = sctx->num_vertex_elements;
1054 int i;
1055
1056 for (i = 0; i < count; i++) {
1057 int vb = sctx->vertex_elements->vertex_buffer_index[i];
1058
1059 if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
1060 continue;
1061 if (!sctx->vertex_buffer[vb].buffer.resource)
1062 continue;
1063
1064 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
1065 si_resource(sctx->vertex_buffer[vb].buffer.resource),
1066 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
1067 }
1068
1069 if (!sctx->vb_descriptors_buffer)
1070 return;
1071 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, sctx->vb_descriptors_buffer, RADEON_USAGE_READ,
1072 RADEON_PRIO_DESCRIPTORS);
1073 }
1074
1075 bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
1076 {
1077 unsigned i, count = sctx->num_vertex_elements;
1078 uint32_t *ptr;
1079
1080 if (!sctx->vertex_buffers_dirty || !count)
1081 return true;
1082
1083 struct si_vertex_elements *velems = sctx->vertex_elements;
1084 unsigned alloc_size = velems->vb_desc_list_alloc_size;
1085
1086 if (alloc_size) {
1087 /* Vertex buffer descriptors are the only ones which are uploaded
1088 * directly through a staging buffer and don't go through
1089 * the fine-grained upload path.
1090 */
1091 u_upload_alloc(sctx->b.const_uploader, 0, alloc_size,
1092 si_optimal_tcc_alignment(sctx, alloc_size), &sctx->vb_descriptors_offset,
1093 (struct pipe_resource **)&sctx->vb_descriptors_buffer, (void **)&ptr);
1094 if (!sctx->vb_descriptors_buffer) {
1095 sctx->vb_descriptors_offset = 0;
1096 sctx->vb_descriptors_gpu_list = NULL;
1097 return false;
1098 }
1099
1100 sctx->vb_descriptors_gpu_list = ptr;
1101 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, sctx->vb_descriptors_buffer, RADEON_USAGE_READ,
1102 RADEON_PRIO_DESCRIPTORS);
1103 sctx->vertex_buffer_pointer_dirty = true;
1104 sctx->prefetch_L2_mask |= SI_PREFETCH_VBO_DESCRIPTORS;
1105 } else {
1106 si_resource_reference(&sctx->vb_descriptors_buffer, NULL);
1107 sctx->vertex_buffer_pointer_dirty = false;
1108 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VBO_DESCRIPTORS;
1109 }
1110
1111 assert(count <= SI_MAX_ATTRIBS);
1112
1113 unsigned first_vb_use_mask = velems->first_vb_use_mask;
1114 unsigned num_vbos_in_user_sgprs = sctx->screen->num_vbos_in_user_sgprs;
1115
1116 for (i = 0; i < count; i++) {
1117 struct pipe_vertex_buffer *vb;
1118 struct si_resource *buf;
1119 unsigned vbo_index = velems->vertex_buffer_index[i];
1120 uint32_t *desc = i < num_vbos_in_user_sgprs ? &sctx->vb_descriptor_user_sgprs[i * 4]
1121 : &ptr[(i - num_vbos_in_user_sgprs) * 4];
1122
1123 vb = &sctx->vertex_buffer[vbo_index];
1124 buf = si_resource(vb->buffer.resource);
1125 if (!buf) {
1126 memset(desc, 0, 16);
1127 continue;
1128 }
1129
1130 int64_t offset = (int64_t)((int)vb->buffer_offset) + velems->src_offset[i];
1131
1132 if (offset >= buf->b.b.width0) {
1133 assert(offset < buf->b.b.width0);
1134 memset(desc, 0, 16);
1135 continue;
1136 }
1137
1138 uint64_t va = buf->gpu_address + offset;
1139
1140 int64_t num_records = (int64_t)buf->b.b.width0 - offset;
1141 if (sctx->chip_class != GFX8 && vb->stride) {
1142 /* Round up by rounding down and adding 1 */
1143 num_records = (num_records - velems->format_size[i]) / vb->stride + 1;
1144 }
1145 assert(num_records >= 0 && num_records <= UINT_MAX);
1146
1147 uint32_t rsrc_word3 = velems->rsrc_word3[i];
1148
1149 /* OOB_SELECT chooses the out-of-bounds check:
1150 * - 1: index >= NUM_RECORDS (Structured)
1151 * - 3: offset >= NUM_RECORDS (Raw)
1152 */
1153 if (sctx->chip_class >= GFX10)
1154 rsrc_word3 |= S_008F0C_OOB_SELECT(vb->stride ? V_008F0C_OOB_SELECT_STRUCTURED
1155 : V_008F0C_OOB_SELECT_RAW);
1156
1157 desc[0] = va;
1158 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(vb->stride);
1159 desc[2] = num_records;
1160 desc[3] = rsrc_word3;
1161
1162 if (first_vb_use_mask & (1 << i)) {
1163 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, si_resource(vb->buffer.resource),
1164 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
1165 }
1166 }
1167
1168 /* Don't flush the const cache. It would have a very negative effect
1169 * on performance (confirmed by testing). New descriptors are always
1170 * uploaded to a fresh new buffer, so I don't think flushing the const
1171 * cache is needed. */
1172 si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
1173 sctx->vertex_buffer_user_sgprs_dirty = num_vbos_in_user_sgprs > 0;
1174 sctx->vertex_buffers_dirty = false;
1175 return true;
1176 }
1177
1178 /* CONSTANT BUFFERS */
1179
1180 static struct si_descriptors *si_const_and_shader_buffer_descriptors(struct si_context *sctx,
1181 unsigned shader)
1182 {
1183 return &sctx->descriptors[si_const_and_shader_buffer_descriptors_idx(shader)];
1184 }
1185
1186 void si_upload_const_buffer(struct si_context *sctx, struct si_resource **buf, const uint8_t *ptr,
1187 unsigned size, uint32_t *const_offset)
1188 {
1189 void *tmp;
1190
1191 u_upload_alloc(sctx->b.const_uploader, 0, size, si_optimal_tcc_alignment(sctx, size),
1192 const_offset, (struct pipe_resource **)buf, &tmp);
1193 if (*buf)
1194 util_memcpy_cpu_to_le32(tmp, ptr, size);
1195 }
1196
1197 static void si_set_constant_buffer(struct si_context *sctx, struct si_buffer_resources *buffers,
1198 unsigned descriptors_idx, uint slot,
1199 const struct pipe_constant_buffer *input)
1200 {
1201 struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
1202 assert(slot < descs->num_elements);
1203 pipe_resource_reference(&buffers->buffers[slot], NULL);
1204
1205 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1206 * with a NULL buffer). We need to use a dummy buffer instead. */
1207 if (sctx->chip_class == GFX7 && (!input || (!input->buffer && !input->user_buffer)))
1208 input = &sctx->null_const_buf;
1209
1210 if (input && (input->buffer || input->user_buffer)) {
1211 struct pipe_resource *buffer = NULL;
1212 uint64_t va;
1213 unsigned buffer_offset;
1214
1215 /* Upload the user buffer if needed. */
1216 if (input->user_buffer) {
1217 si_upload_const_buffer(sctx, (struct si_resource **)&buffer, input->user_buffer,
1218 input->buffer_size, &buffer_offset);
1219 if (!buffer) {
1220 /* Just unbind on failure. */
1221 si_set_constant_buffer(sctx, buffers, descriptors_idx, slot, NULL);
1222 return;
1223 }
1224 } else {
1225 pipe_resource_reference(&buffer, input->buffer);
1226 buffer_offset = input->buffer_offset;
1227 }
1228
1229 va = si_resource(buffer)->gpu_address + buffer_offset;
1230
1231 /* Set the descriptor. */
1232 uint32_t *desc = descs->list + slot * 4;
1233 desc[0] = va;
1234 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(0);
1235 desc[2] = input->buffer_size;
1236 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1237 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
1238
1239 if (sctx->chip_class >= GFX10) {
1240 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
1241 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | S_008F0C_RESOURCE_LEVEL(1);
1242 } else {
1243 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1244 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1245 }
1246
1247 buffers->buffers[slot] = buffer;
1248 buffers->offsets[slot] = buffer_offset;
1249 radeon_add_to_gfx_buffer_list_check_mem(sctx, si_resource(buffer), RADEON_USAGE_READ,
1250 buffers->priority_constbuf, true);
1251 buffers->enabled_mask |= 1llu << slot;
1252 } else {
1253 /* Clear the descriptor. */
1254 memset(descs->list + slot * 4, 0, sizeof(uint32_t) * 4);
1255 buffers->enabled_mask &= ~(1llu << slot);
1256 }
1257
1258 sctx->descriptors_dirty |= 1u << descriptors_idx;
1259 }
1260
1261 static void si_pipe_set_constant_buffer(struct pipe_context *ctx, enum pipe_shader_type shader,
1262 uint slot, const struct pipe_constant_buffer *input)
1263 {
1264 struct si_context *sctx = (struct si_context *)ctx;
1265
1266 if (shader >= SI_NUM_SHADERS)
1267 return;
1268
1269 if (slot == 0 && input && input->buffer &&
1270 !(si_resource(input->buffer)->flags & RADEON_FLAG_32BIT)) {
1271 assert(!"constant buffer 0 must have a 32-bit VM address, use const_uploader");
1272 return;
1273 }
1274
1275 if (input && input->buffer)
1276 si_resource(input->buffer)->bind_history |= PIPE_BIND_CONSTANT_BUFFER;
1277
1278 slot = si_get_constbuf_slot(slot);
1279 si_set_constant_buffer(sctx, &sctx->const_and_shader_buffers[shader],
1280 si_const_and_shader_buffer_descriptors_idx(shader), slot, input);
1281 }
1282
1283 void si_get_pipe_constant_buffer(struct si_context *sctx, uint shader, uint slot,
1284 struct pipe_constant_buffer *cbuf)
1285 {
1286 cbuf->user_buffer = NULL;
1287 si_get_buffer_from_descriptors(
1288 &sctx->const_and_shader_buffers[shader], si_const_and_shader_buffer_descriptors(sctx, shader),
1289 si_get_constbuf_slot(slot), &cbuf->buffer, &cbuf->buffer_offset, &cbuf->buffer_size);
1290 }
1291
1292 /* SHADER BUFFERS */
1293
1294 static void si_set_shader_buffer(struct si_context *sctx, struct si_buffer_resources *buffers,
1295 unsigned descriptors_idx, uint slot,
1296 const struct pipe_shader_buffer *sbuffer, bool writable,
1297 enum radeon_bo_priority priority)
1298 {
1299 struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
1300 uint32_t *desc = descs->list + slot * 4;
1301
1302 if (!sbuffer || !sbuffer->buffer) {
1303 pipe_resource_reference(&buffers->buffers[slot], NULL);
1304 memset(desc, 0, sizeof(uint32_t) * 4);
1305 buffers->enabled_mask &= ~(1llu << slot);
1306 buffers->writable_mask &= ~(1llu << slot);
1307 sctx->descriptors_dirty |= 1u << descriptors_idx;
1308 return;
1309 }
1310
1311 struct si_resource *buf = si_resource(sbuffer->buffer);
1312 uint64_t va = buf->gpu_address + sbuffer->buffer_offset;
1313
1314 desc[0] = va;
1315 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(0);
1316 desc[2] = sbuffer->buffer_size;
1317 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1318 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
1319
1320 if (sctx->chip_class >= GFX10) {
1321 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
1322 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | S_008F0C_RESOURCE_LEVEL(1);
1323 } else {
1324 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1325 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1326 }
1327
1328 pipe_resource_reference(&buffers->buffers[slot], &buf->b.b);
1329 buffers->offsets[slot] = sbuffer->buffer_offset;
1330 radeon_add_to_gfx_buffer_list_check_mem(
1331 sctx, buf, writable ? RADEON_USAGE_READWRITE : RADEON_USAGE_READ, priority, true);
1332 if (writable)
1333 buffers->writable_mask |= 1llu << slot;
1334 else
1335 buffers->writable_mask &= ~(1llu << slot);
1336
1337 buffers->enabled_mask |= 1llu << slot;
1338 sctx->descriptors_dirty |= 1lu << descriptors_idx;
1339
1340 util_range_add(&buf->b.b, &buf->valid_buffer_range, sbuffer->buffer_offset,
1341 sbuffer->buffer_offset + sbuffer->buffer_size);
1342 }
1343
1344 static void si_set_shader_buffers(struct pipe_context *ctx, enum pipe_shader_type shader,
1345 unsigned start_slot, unsigned count,
1346 const struct pipe_shader_buffer *sbuffers,
1347 unsigned writable_bitmask)
1348 {
1349 struct si_context *sctx = (struct si_context *)ctx;
1350 struct si_buffer_resources *buffers = &sctx->const_and_shader_buffers[shader];
1351 unsigned descriptors_idx = si_const_and_shader_buffer_descriptors_idx(shader);
1352 unsigned i;
1353
1354 assert(start_slot + count <= SI_NUM_SHADER_BUFFERS);
1355
1356 if (shader == PIPE_SHADER_COMPUTE &&
1357 sctx->cs_shader_state.program &&
1358 start_slot < sctx->cs_shader_state.program->sel.cs_num_shaderbufs_in_user_sgprs)
1359 sctx->compute_shaderbuf_sgprs_dirty = true;
1360
1361 for (i = 0; i < count; ++i) {
1362 const struct pipe_shader_buffer *sbuffer = sbuffers ? &sbuffers[i] : NULL;
1363 unsigned slot = si_get_shaderbuf_slot(start_slot + i);
1364
1365 if (sbuffer && sbuffer->buffer)
1366 si_resource(sbuffer->buffer)->bind_history |= PIPE_BIND_SHADER_BUFFER;
1367
1368 si_set_shader_buffer(sctx, buffers, descriptors_idx, slot, sbuffer,
1369 !!(writable_bitmask & (1u << i)), buffers->priority);
1370 }
1371 }
1372
1373 void si_get_shader_buffers(struct si_context *sctx, enum pipe_shader_type shader, uint start_slot,
1374 uint count, struct pipe_shader_buffer *sbuf)
1375 {
1376 struct si_buffer_resources *buffers = &sctx->const_and_shader_buffers[shader];
1377 struct si_descriptors *descs = si_const_and_shader_buffer_descriptors(sctx, shader);
1378
1379 for (unsigned i = 0; i < count; ++i) {
1380 si_get_buffer_from_descriptors(buffers, descs, si_get_shaderbuf_slot(start_slot + i),
1381 &sbuf[i].buffer, &sbuf[i].buffer_offset, &sbuf[i].buffer_size);
1382 }
1383 }
1384
1385 /* RING BUFFERS */
1386
1387 void si_set_rw_buffer(struct si_context *sctx, uint slot, const struct pipe_constant_buffer *input)
1388 {
1389 si_set_constant_buffer(sctx, &sctx->rw_buffers, SI_DESCS_RW_BUFFERS, slot, input);
1390 }
1391
1392 void si_set_rw_shader_buffer(struct si_context *sctx, uint slot,
1393 const struct pipe_shader_buffer *sbuffer)
1394 {
1395 si_set_shader_buffer(sctx, &sctx->rw_buffers, SI_DESCS_RW_BUFFERS, slot, sbuffer, true,
1396 RADEON_PRIO_SHADER_RW_BUFFER);
1397 }
1398
1399 void si_set_ring_buffer(struct si_context *sctx, uint slot, struct pipe_resource *buffer,
1400 unsigned stride, unsigned num_records, bool add_tid, bool swizzle,
1401 unsigned element_size, unsigned index_stride, uint64_t offset)
1402 {
1403 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1404 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1405
1406 /* The stride field in the resource descriptor has 14 bits */
1407 assert(stride < (1 << 14));
1408
1409 assert(slot < descs->num_elements);
1410 pipe_resource_reference(&buffers->buffers[slot], NULL);
1411
1412 if (buffer) {
1413 uint64_t va;
1414
1415 va = si_resource(buffer)->gpu_address + offset;
1416
1417 switch (element_size) {
1418 default:
1419 assert(!"Unsupported ring buffer element size");
1420 case 0:
1421 case 2:
1422 element_size = 0;
1423 break;
1424 case 4:
1425 element_size = 1;
1426 break;
1427 case 8:
1428 element_size = 2;
1429 break;
1430 case 16:
1431 element_size = 3;
1432 break;
1433 }
1434
1435 switch (index_stride) {
1436 default:
1437 assert(!"Unsupported ring buffer index stride");
1438 case 0:
1439 case 8:
1440 index_stride = 0;
1441 break;
1442 case 16:
1443 index_stride = 1;
1444 break;
1445 case 32:
1446 index_stride = 2;
1447 break;
1448 case 64:
1449 index_stride = 3;
1450 break;
1451 }
1452
1453 if (sctx->chip_class >= GFX8 && stride)
1454 num_records *= stride;
1455
1456 /* Set the descriptor. */
1457 uint32_t *desc = descs->list + slot * 4;
1458 desc[0] = va;
1459 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride) |
1460 S_008F04_SWIZZLE_ENABLE(swizzle);
1461 desc[2] = num_records;
1462 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1463 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1464 S_008F0C_INDEX_STRIDE(index_stride) | S_008F0C_ADD_TID_ENABLE(add_tid);
1465
1466 if (sctx->chip_class >= GFX9)
1467 assert(!swizzle || element_size == 1); /* always 4 bytes on GFX9 */
1468 else
1469 desc[3] |= S_008F0C_ELEMENT_SIZE(element_size);
1470
1471 if (sctx->chip_class >= GFX10) {
1472 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
1473 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) | S_008F0C_RESOURCE_LEVEL(1);
1474 } else {
1475 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1476 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1477 }
1478
1479 pipe_resource_reference(&buffers->buffers[slot], buffer);
1480 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, si_resource(buffer), RADEON_USAGE_READWRITE,
1481 buffers->priority);
1482 buffers->enabled_mask |= 1llu << slot;
1483 } else {
1484 /* Clear the descriptor. */
1485 memset(descs->list + slot * 4, 0, sizeof(uint32_t) * 4);
1486 buffers->enabled_mask &= ~(1llu << slot);
1487 }
1488
1489 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
1490 }
1491
1492 /* INTERNAL CONST BUFFERS */
1493
1494 static void si_set_polygon_stipple(struct pipe_context *ctx, const struct pipe_poly_stipple *state)
1495 {
1496 struct si_context *sctx = (struct si_context *)ctx;
1497 struct pipe_constant_buffer cb = {};
1498 unsigned stipple[32];
1499 int i;
1500
1501 for (i = 0; i < 32; i++)
1502 stipple[i] = util_bitreverse(state->stipple[i]);
1503
1504 cb.user_buffer = stipple;
1505 cb.buffer_size = sizeof(stipple);
1506
1507 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE, &cb);
1508 }
1509
1510 /* TEXTURE METADATA ENABLE/DISABLE */
1511
1512 static void si_resident_handles_update_needs_color_decompress(struct si_context *sctx)
1513 {
1514 util_dynarray_clear(&sctx->resident_tex_needs_color_decompress);
1515 util_dynarray_clear(&sctx->resident_img_needs_color_decompress);
1516
1517 util_dynarray_foreach (&sctx->resident_tex_handles, struct si_texture_handle *, tex_handle) {
1518 struct pipe_resource *res = (*tex_handle)->view->texture;
1519 struct si_texture *tex;
1520
1521 if (!res || res->target == PIPE_BUFFER)
1522 continue;
1523
1524 tex = (struct si_texture *)res;
1525 if (!color_needs_decompression(tex))
1526 continue;
1527
1528 util_dynarray_append(&sctx->resident_tex_needs_color_decompress, struct si_texture_handle *,
1529 *tex_handle);
1530 }
1531
1532 util_dynarray_foreach (&sctx->resident_img_handles, struct si_image_handle *, img_handle) {
1533 struct pipe_image_view *view = &(*img_handle)->view;
1534 struct pipe_resource *res = view->resource;
1535 struct si_texture *tex;
1536
1537 if (!res || res->target == PIPE_BUFFER)
1538 continue;
1539
1540 tex = (struct si_texture *)res;
1541 if (!color_needs_decompression(tex))
1542 continue;
1543
1544 util_dynarray_append(&sctx->resident_img_needs_color_decompress, struct si_image_handle *,
1545 *img_handle);
1546 }
1547 }
1548
1549 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1550 * while the texture is bound, possibly by a different context. In that case,
1551 * call this function to update needs_*_decompress_masks.
1552 */
1553 void si_update_needs_color_decompress_masks(struct si_context *sctx)
1554 {
1555 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
1556 si_samplers_update_needs_color_decompress_mask(&sctx->samplers[i]);
1557 si_images_update_needs_color_decompress_mask(&sctx->images[i]);
1558 si_update_shader_needs_decompress_mask(sctx, i);
1559 }
1560
1561 si_resident_handles_update_needs_color_decompress(sctx);
1562 }
1563
1564 /* BUFFER DISCARD/INVALIDATION */
1565
1566 /* Reset descriptors of buffer resources after \p buf has been invalidated.
1567 * If buf == NULL, reset all descriptors.
1568 */
1569 static void si_reset_buffer_resources(struct si_context *sctx, struct si_buffer_resources *buffers,
1570 unsigned descriptors_idx, uint64_t slot_mask,
1571 struct pipe_resource *buf, enum radeon_bo_priority priority)
1572 {
1573 struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
1574 uint64_t mask = buffers->enabled_mask & slot_mask;
1575
1576 while (mask) {
1577 unsigned i = u_bit_scan64(&mask);
1578 struct pipe_resource *buffer = buffers->buffers[i];
1579
1580 if (buffer && (!buf || buffer == buf)) {
1581 si_set_buf_desc_address(si_resource(buffer), buffers->offsets[i], descs->list + i * 4);
1582 sctx->descriptors_dirty |= 1u << descriptors_idx;
1583
1584 radeon_add_to_gfx_buffer_list_check_mem(
1585 sctx, si_resource(buffer),
1586 buffers->writable_mask & (1llu << i) ? RADEON_USAGE_READWRITE : RADEON_USAGE_READ,
1587 priority, true);
1588 }
1589 }
1590 }
1591
1592 /* Update all buffer bindings where the buffer is bound, including
1593 * all resource descriptors. This is invalidate_buffer without
1594 * the invalidation.
1595 *
1596 * If buf == NULL, update all buffer bindings.
1597 */
1598 void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf)
1599 {
1600 struct si_resource *buffer = si_resource(buf);
1601 unsigned i, shader;
1602 unsigned num_elems = sctx->num_vertex_elements;
1603
1604 /* We changed the buffer, now we need to bind it where the old one
1605 * was bound. This consists of 2 things:
1606 * 1) Updating the resource descriptor and dirtying it.
1607 * 2) Adding a relocation to the CS, so that it's usable.
1608 */
1609
1610 /* Vertex buffers. */
1611 if (!buffer) {
1612 if (num_elems)
1613 sctx->vertex_buffers_dirty = true;
1614 } else if (buffer->bind_history & PIPE_BIND_VERTEX_BUFFER) {
1615 for (i = 0; i < num_elems; i++) {
1616 int vb = sctx->vertex_elements->vertex_buffer_index[i];
1617
1618 if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
1619 continue;
1620 if (!sctx->vertex_buffer[vb].buffer.resource)
1621 continue;
1622
1623 if (sctx->vertex_buffer[vb].buffer.resource == buf) {
1624 sctx->vertex_buffers_dirty = true;
1625 break;
1626 }
1627 }
1628 }
1629
1630 /* Streamout buffers. (other internal buffers can't be invalidated) */
1631 if (!buffer || buffer->bind_history & PIPE_BIND_STREAM_OUTPUT) {
1632 for (i = SI_VS_STREAMOUT_BUF0; i <= SI_VS_STREAMOUT_BUF3; i++) {
1633 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1634 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1635 struct pipe_resource *buffer = buffers->buffers[i];
1636
1637 if (!buffer || (buf && buffer != buf))
1638 continue;
1639
1640 si_set_buf_desc_address(si_resource(buffer), buffers->offsets[i], descs->list + i * 4);
1641 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
1642
1643 radeon_add_to_gfx_buffer_list_check_mem(sctx, si_resource(buffer), RADEON_USAGE_WRITE,
1644 RADEON_PRIO_SHADER_RW_BUFFER, true);
1645
1646 /* Update the streamout state. */
1647 if (sctx->streamout.begin_emitted)
1648 si_emit_streamout_end(sctx);
1649 sctx->streamout.append_bitmask = sctx->streamout.enabled_mask;
1650 si_streamout_buffers_dirty(sctx);
1651 }
1652 }
1653
1654 /* Constant and shader buffers. */
1655 if (!buffer || buffer->bind_history & PIPE_BIND_CONSTANT_BUFFER) {
1656 for (shader = 0; shader < SI_NUM_SHADERS; shader++)
1657 si_reset_buffer_resources(sctx, &sctx->const_and_shader_buffers[shader],
1658 si_const_and_shader_buffer_descriptors_idx(shader),
1659 u_bit_consecutive64(SI_NUM_SHADER_BUFFERS, SI_NUM_CONST_BUFFERS),
1660 buf, sctx->const_and_shader_buffers[shader].priority_constbuf);
1661 }
1662
1663 if (!buffer || buffer->bind_history & PIPE_BIND_SHADER_BUFFER) {
1664 for (shader = 0; shader < SI_NUM_SHADERS; shader++)
1665 si_reset_buffer_resources(sctx, &sctx->const_and_shader_buffers[shader],
1666 si_const_and_shader_buffer_descriptors_idx(shader),
1667 u_bit_consecutive64(0, SI_NUM_SHADER_BUFFERS), buf,
1668 sctx->const_and_shader_buffers[shader].priority);
1669 }
1670
1671 if (!buffer || buffer->bind_history & PIPE_BIND_SAMPLER_VIEW) {
1672 /* Texture buffers - update bindings. */
1673 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1674 struct si_samplers *samplers = &sctx->samplers[shader];
1675 struct si_descriptors *descs = si_sampler_and_image_descriptors(sctx, shader);
1676 unsigned mask = samplers->enabled_mask;
1677
1678 while (mask) {
1679 unsigned i = u_bit_scan(&mask);
1680 struct pipe_resource *buffer = samplers->views[i]->texture;
1681
1682 if (buffer && buffer->target == PIPE_BUFFER && (!buf || buffer == buf)) {
1683 unsigned desc_slot = si_get_sampler_slot(i);
1684
1685 si_set_buf_desc_address(si_resource(buffer), samplers->views[i]->u.buf.offset,
1686 descs->list + desc_slot * 16 + 4);
1687 sctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
1688
1689 radeon_add_to_gfx_buffer_list_check_mem(sctx, si_resource(buffer), RADEON_USAGE_READ,
1690 RADEON_PRIO_SAMPLER_BUFFER, true);
1691 }
1692 }
1693 }
1694 }
1695
1696 /* Shader images */
1697 if (!buffer || buffer->bind_history & PIPE_BIND_SHADER_IMAGE) {
1698 for (shader = 0; shader < SI_NUM_SHADERS; ++shader) {
1699 struct si_images *images = &sctx->images[shader];
1700 struct si_descriptors *descs = si_sampler_and_image_descriptors(sctx, shader);
1701 unsigned mask = images->enabled_mask;
1702
1703 while (mask) {
1704 unsigned i = u_bit_scan(&mask);
1705 struct pipe_resource *buffer = images->views[i].resource;
1706
1707 if (buffer && buffer->target == PIPE_BUFFER && (!buf || buffer == buf)) {
1708 unsigned desc_slot = si_get_image_slot(i);
1709
1710 if (images->views[i].access & PIPE_IMAGE_ACCESS_WRITE)
1711 si_mark_image_range_valid(&images->views[i]);
1712
1713 si_set_buf_desc_address(si_resource(buffer), images->views[i].u.buf.offset,
1714 descs->list + desc_slot * 8 + 4);
1715 sctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
1716
1717 radeon_add_to_gfx_buffer_list_check_mem(sctx, si_resource(buffer),
1718 RADEON_USAGE_READWRITE,
1719 RADEON_PRIO_SAMPLER_BUFFER, true);
1720 }
1721 }
1722 }
1723 }
1724
1725 /* Bindless texture handles */
1726 if (!buffer || buffer->texture_handle_allocated) {
1727 struct si_descriptors *descs = &sctx->bindless_descriptors;
1728
1729 util_dynarray_foreach (&sctx->resident_tex_handles, struct si_texture_handle *, tex_handle) {
1730 struct pipe_sampler_view *view = (*tex_handle)->view;
1731 unsigned desc_slot = (*tex_handle)->desc_slot;
1732 struct pipe_resource *buffer = view->texture;
1733
1734 if (buffer && buffer->target == PIPE_BUFFER && (!buf || buffer == buf)) {
1735 si_set_buf_desc_address(si_resource(buffer), view->u.buf.offset,
1736 descs->list + desc_slot * 16 + 4);
1737
1738 (*tex_handle)->desc_dirty = true;
1739 sctx->bindless_descriptors_dirty = true;
1740
1741 radeon_add_to_gfx_buffer_list_check_mem(sctx, si_resource(buffer), RADEON_USAGE_READ,
1742 RADEON_PRIO_SAMPLER_BUFFER, true);
1743 }
1744 }
1745 }
1746
1747 /* Bindless image handles */
1748 if (!buffer || buffer->image_handle_allocated) {
1749 struct si_descriptors *descs = &sctx->bindless_descriptors;
1750
1751 util_dynarray_foreach (&sctx->resident_img_handles, struct si_image_handle *, img_handle) {
1752 struct pipe_image_view *view = &(*img_handle)->view;
1753 unsigned desc_slot = (*img_handle)->desc_slot;
1754 struct pipe_resource *buffer = view->resource;
1755
1756 if (buffer && buffer->target == PIPE_BUFFER && (!buf || buffer == buf)) {
1757 if (view->access & PIPE_IMAGE_ACCESS_WRITE)
1758 si_mark_image_range_valid(view);
1759
1760 si_set_buf_desc_address(si_resource(buffer), view->u.buf.offset,
1761 descs->list + desc_slot * 16 + 4);
1762
1763 (*img_handle)->desc_dirty = true;
1764 sctx->bindless_descriptors_dirty = true;
1765
1766 radeon_add_to_gfx_buffer_list_check_mem(
1767 sctx, si_resource(buffer), RADEON_USAGE_READWRITE, RADEON_PRIO_SAMPLER_BUFFER, true);
1768 }
1769 }
1770 }
1771
1772 if (buffer) {
1773 /* Do the same for other contexts. They will invoke this function
1774 * with buffer == NULL.
1775 */
1776 unsigned new_counter = p_atomic_inc_return(&sctx->screen->dirty_buf_counter);
1777
1778 /* Skip the update for the current context, because we have already updated
1779 * the buffer bindings.
1780 */
1781 if (new_counter == sctx->last_dirty_buf_counter + 1)
1782 sctx->last_dirty_buf_counter = new_counter;
1783 }
1784 }
1785
1786 static void si_upload_bindless_descriptor(struct si_context *sctx, unsigned desc_slot,
1787 unsigned num_dwords)
1788 {
1789 struct si_descriptors *desc = &sctx->bindless_descriptors;
1790 unsigned desc_slot_offset = desc_slot * 16;
1791 uint32_t *data;
1792 uint64_t va;
1793
1794 data = desc->list + desc_slot_offset;
1795 va = desc->gpu_address + desc_slot_offset * 4;
1796
1797 si_cp_write_data(sctx, desc->buffer, va - desc->buffer->gpu_address, num_dwords * 4, V_370_TC_L2,
1798 V_370_ME, data);
1799 }
1800
1801 static void si_upload_bindless_descriptors(struct si_context *sctx)
1802 {
1803 if (!sctx->bindless_descriptors_dirty)
1804 return;
1805
1806 /* Wait for graphics/compute to be idle before updating the resident
1807 * descriptors directly in memory, in case the GPU is using them.
1808 */
1809 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH;
1810 sctx->emit_cache_flush(sctx);
1811
1812 util_dynarray_foreach (&sctx->resident_tex_handles, struct si_texture_handle *, tex_handle) {
1813 unsigned desc_slot = (*tex_handle)->desc_slot;
1814
1815 if (!(*tex_handle)->desc_dirty)
1816 continue;
1817
1818 si_upload_bindless_descriptor(sctx, desc_slot, 16);
1819 (*tex_handle)->desc_dirty = false;
1820 }
1821
1822 util_dynarray_foreach (&sctx->resident_img_handles, struct si_image_handle *, img_handle) {
1823 unsigned desc_slot = (*img_handle)->desc_slot;
1824
1825 if (!(*img_handle)->desc_dirty)
1826 continue;
1827
1828 si_upload_bindless_descriptor(sctx, desc_slot, 8);
1829 (*img_handle)->desc_dirty = false;
1830 }
1831
1832 /* Invalidate L1 because it doesn't know that L2 changed. */
1833 sctx->flags |= SI_CONTEXT_INV_SCACHE;
1834 sctx->emit_cache_flush(sctx);
1835
1836 sctx->bindless_descriptors_dirty = false;
1837 }
1838
1839 /* Update mutable image descriptor fields of all resident textures. */
1840 static void si_update_bindless_texture_descriptor(struct si_context *sctx,
1841 struct si_texture_handle *tex_handle)
1842 {
1843 struct si_sampler_view *sview = (struct si_sampler_view *)tex_handle->view;
1844 struct si_descriptors *desc = &sctx->bindless_descriptors;
1845 unsigned desc_slot_offset = tex_handle->desc_slot * 16;
1846 uint32_t desc_list[16];
1847
1848 if (sview->base.texture->target == PIPE_BUFFER)
1849 return;
1850
1851 memcpy(desc_list, desc->list + desc_slot_offset, sizeof(desc_list));
1852 si_set_sampler_view_desc(sctx, sview, &tex_handle->sstate, desc->list + desc_slot_offset);
1853
1854 if (memcmp(desc_list, desc->list + desc_slot_offset, sizeof(desc_list))) {
1855 tex_handle->desc_dirty = true;
1856 sctx->bindless_descriptors_dirty = true;
1857 }
1858 }
1859
1860 static void si_update_bindless_image_descriptor(struct si_context *sctx,
1861 struct si_image_handle *img_handle)
1862 {
1863 struct si_descriptors *desc = &sctx->bindless_descriptors;
1864 unsigned desc_slot_offset = img_handle->desc_slot * 16;
1865 struct pipe_image_view *view = &img_handle->view;
1866 struct pipe_resource *res = view->resource;
1867 uint32_t image_desc[16];
1868 unsigned desc_size = (res->nr_samples >= 2 ? 16 : 8) * 4;
1869
1870 if (res->target == PIPE_BUFFER)
1871 return;
1872
1873 memcpy(image_desc, desc->list + desc_slot_offset, desc_size);
1874 si_set_shader_image_desc(sctx, view, true, desc->list + desc_slot_offset,
1875 desc->list + desc_slot_offset + 8);
1876
1877 if (memcmp(image_desc, desc->list + desc_slot_offset, desc_size)) {
1878 img_handle->desc_dirty = true;
1879 sctx->bindless_descriptors_dirty = true;
1880 }
1881 }
1882
1883 static void si_update_all_resident_texture_descriptors(struct si_context *sctx)
1884 {
1885 util_dynarray_foreach (&sctx->resident_tex_handles, struct si_texture_handle *, tex_handle) {
1886 si_update_bindless_texture_descriptor(sctx, *tex_handle);
1887 }
1888
1889 util_dynarray_foreach (&sctx->resident_img_handles, struct si_image_handle *, img_handle) {
1890 si_update_bindless_image_descriptor(sctx, *img_handle);
1891 }
1892
1893 si_upload_bindless_descriptors(sctx);
1894 }
1895
1896 /* Update mutable image descriptor fields of all bound textures. */
1897 void si_update_all_texture_descriptors(struct si_context *sctx)
1898 {
1899 unsigned shader;
1900
1901 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1902 struct si_samplers *samplers = &sctx->samplers[shader];
1903 struct si_images *images = &sctx->images[shader];
1904 unsigned mask;
1905
1906 /* Images. */
1907 mask = images->enabled_mask;
1908 while (mask) {
1909 unsigned i = u_bit_scan(&mask);
1910 struct pipe_image_view *view = &images->views[i];
1911
1912 if (!view->resource || view->resource->target == PIPE_BUFFER)
1913 continue;
1914
1915 si_set_shader_image(sctx, shader, i, view, true);
1916 }
1917
1918 /* Sampler views. */
1919 mask = samplers->enabled_mask;
1920 while (mask) {
1921 unsigned i = u_bit_scan(&mask);
1922 struct pipe_sampler_view *view = samplers->views[i];
1923
1924 if (!view || !view->texture || view->texture->target == PIPE_BUFFER)
1925 continue;
1926
1927 si_set_sampler_view(sctx, shader, i, samplers->views[i], true);
1928 }
1929
1930 si_update_shader_needs_decompress_mask(sctx, shader);
1931 }
1932
1933 si_update_all_resident_texture_descriptors(sctx);
1934 si_update_ps_colorbuf0_slot(sctx);
1935 }
1936
1937 /* SHADER USER DATA */
1938
1939 static void si_mark_shader_pointers_dirty(struct si_context *sctx, unsigned shader)
1940 {
1941 sctx->shader_pointers_dirty |=
1942 u_bit_consecutive(SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS, SI_NUM_SHADER_DESCS);
1943
1944 if (shader == PIPE_SHADER_VERTEX) {
1945 sctx->vertex_buffer_pointer_dirty = sctx->vb_descriptors_buffer != NULL;
1946 sctx->vertex_buffer_user_sgprs_dirty =
1947 sctx->num_vertex_elements > 0 && sctx->screen->num_vbos_in_user_sgprs;
1948 }
1949
1950 si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
1951 }
1952
1953 void si_shader_pointers_mark_dirty(struct si_context *sctx)
1954 {
1955 sctx->shader_pointers_dirty = u_bit_consecutive(0, SI_NUM_DESCS);
1956 sctx->vertex_buffer_pointer_dirty = sctx->vb_descriptors_buffer != NULL;
1957 sctx->vertex_buffer_user_sgprs_dirty =
1958 sctx->num_vertex_elements > 0 && sctx->screen->num_vbos_in_user_sgprs;
1959 si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
1960 sctx->graphics_bindless_pointer_dirty = sctx->bindless_descriptors.buffer != NULL;
1961 sctx->compute_bindless_pointer_dirty = sctx->bindless_descriptors.buffer != NULL;
1962 sctx->compute_shaderbuf_sgprs_dirty = true;
1963 sctx->compute_image_sgprs_dirty = true;
1964 }
1965
1966 /* Set a base register address for user data constants in the given shader.
1967 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
1968 */
1969 static void si_set_user_data_base(struct si_context *sctx, unsigned shader, uint32_t new_base)
1970 {
1971 uint32_t *base = &sctx->shader_pointers.sh_base[shader];
1972
1973 if (*base != new_base) {
1974 *base = new_base;
1975
1976 if (new_base)
1977 si_mark_shader_pointers_dirty(sctx, shader);
1978
1979 /* Any change in enabled shader stages requires re-emitting
1980 * the VS state SGPR, because it contains the clamp_vertex_color
1981 * state, which can be done in VS, TES, and GS.
1982 */
1983 sctx->last_vs_state = ~0;
1984 }
1985 }
1986
1987 /* This must be called when these are changed between enabled and disabled
1988 * - geometry shader
1989 * - tessellation evaluation shader
1990 * - NGG
1991 */
1992 void si_shader_change_notify(struct si_context *sctx)
1993 {
1994 /* VS can be bound as VS, ES, or LS. */
1995 if (sctx->tes_shader.cso) {
1996 if (sctx->chip_class >= GFX10) {
1997 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B430_SPI_SHADER_USER_DATA_HS_0);
1998 } else if (sctx->chip_class == GFX9) {
1999 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B430_SPI_SHADER_USER_DATA_LS_0);
2000 } else {
2001 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B530_SPI_SHADER_USER_DATA_LS_0);
2002 }
2003 } else if (sctx->chip_class >= GFX10) {
2004 if (sctx->ngg || sctx->gs_shader.cso) {
2005 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B230_SPI_SHADER_USER_DATA_GS_0);
2006 } else {
2007 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0);
2008 }
2009 } else if (sctx->gs_shader.cso) {
2010 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B330_SPI_SHADER_USER_DATA_ES_0);
2011 } else {
2012 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0);
2013 }
2014
2015 /* TES can be bound as ES, VS, or not bound. */
2016 if (sctx->tes_shader.cso) {
2017 if (sctx->chip_class >= GFX10) {
2018 if (sctx->ngg || sctx->gs_shader.cso) {
2019 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, R_00B230_SPI_SHADER_USER_DATA_GS_0);
2020 } else {
2021 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, R_00B130_SPI_SHADER_USER_DATA_VS_0);
2022 }
2023 } else if (sctx->gs_shader.cso) {
2024 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, R_00B330_SPI_SHADER_USER_DATA_ES_0);
2025 } else {
2026 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, R_00B130_SPI_SHADER_USER_DATA_VS_0);
2027 }
2028 } else {
2029 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, 0);
2030 }
2031 }
2032
2033 static void si_emit_shader_pointer_head(struct radeon_cmdbuf *cs, unsigned sh_offset,
2034 unsigned pointer_count)
2035 {
2036 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count, 0));
2037 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
2038 }
2039
2040 static void si_emit_shader_pointer_body(struct si_screen *sscreen, struct radeon_cmdbuf *cs,
2041 uint64_t va)
2042 {
2043 radeon_emit(cs, va);
2044
2045 assert(va == 0 || (va >> 32) == sscreen->info.address32_hi);
2046 }
2047
2048 static void si_emit_shader_pointer(struct si_context *sctx, struct si_descriptors *desc,
2049 unsigned sh_base)
2050 {
2051 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2052 unsigned sh_offset = sh_base + desc->shader_userdata_offset;
2053
2054 si_emit_shader_pointer_head(cs, sh_offset, 1);
2055 si_emit_shader_pointer_body(sctx->screen, cs, desc->gpu_address);
2056 }
2057
2058 static void si_emit_consecutive_shader_pointers(struct si_context *sctx, unsigned pointer_mask,
2059 unsigned sh_base)
2060 {
2061 if (!sh_base)
2062 return;
2063
2064 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2065 unsigned mask = sctx->shader_pointers_dirty & pointer_mask;
2066
2067 while (mask) {
2068 int start, count;
2069 u_bit_scan_consecutive_range(&mask, &start, &count);
2070
2071 struct si_descriptors *descs = &sctx->descriptors[start];
2072 unsigned sh_offset = sh_base + descs->shader_userdata_offset;
2073
2074 si_emit_shader_pointer_head(cs, sh_offset, count);
2075 for (int i = 0; i < count; i++)
2076 si_emit_shader_pointer_body(sctx->screen, cs, descs[i].gpu_address);
2077 }
2078 }
2079
2080 static void si_emit_global_shader_pointers(struct si_context *sctx, struct si_descriptors *descs)
2081 {
2082 if (sctx->chip_class >= GFX10) {
2083 si_emit_shader_pointer(sctx, descs, R_00B030_SPI_SHADER_USER_DATA_PS_0);
2084 /* HW VS stage only used in non-NGG mode. */
2085 si_emit_shader_pointer(sctx, descs, R_00B130_SPI_SHADER_USER_DATA_VS_0);
2086 si_emit_shader_pointer(sctx, descs, R_00B230_SPI_SHADER_USER_DATA_GS_0);
2087 si_emit_shader_pointer(sctx, descs, R_00B430_SPI_SHADER_USER_DATA_HS_0);
2088 return;
2089 } else if (sctx->chip_class == GFX9 && sctx->shadowed_regs) {
2090 /* We can't use the COMMON registers with register shadowing. */
2091 si_emit_shader_pointer(sctx, descs, R_00B030_SPI_SHADER_USER_DATA_PS_0);
2092 si_emit_shader_pointer(sctx, descs, R_00B130_SPI_SHADER_USER_DATA_VS_0);
2093 si_emit_shader_pointer(sctx, descs, R_00B330_SPI_SHADER_USER_DATA_ES_0);
2094 si_emit_shader_pointer(sctx, descs, R_00B430_SPI_SHADER_USER_DATA_LS_0);
2095 return;
2096 } else if (sctx->chip_class == GFX9) {
2097 /* Broadcast it to all shader stages. */
2098 si_emit_shader_pointer(sctx, descs, R_00B530_SPI_SHADER_USER_DATA_COMMON_0);
2099 return;
2100 }
2101
2102 si_emit_shader_pointer(sctx, descs, R_00B030_SPI_SHADER_USER_DATA_PS_0);
2103 si_emit_shader_pointer(sctx, descs, R_00B130_SPI_SHADER_USER_DATA_VS_0);
2104 si_emit_shader_pointer(sctx, descs, R_00B330_SPI_SHADER_USER_DATA_ES_0);
2105 si_emit_shader_pointer(sctx, descs, R_00B230_SPI_SHADER_USER_DATA_GS_0);
2106 si_emit_shader_pointer(sctx, descs, R_00B430_SPI_SHADER_USER_DATA_HS_0);
2107 si_emit_shader_pointer(sctx, descs, R_00B530_SPI_SHADER_USER_DATA_LS_0);
2108 }
2109
2110 void si_emit_graphics_shader_pointers(struct si_context *sctx)
2111 {
2112 uint32_t *sh_base = sctx->shader_pointers.sh_base;
2113
2114 if (sctx->shader_pointers_dirty & (1 << SI_DESCS_RW_BUFFERS)) {
2115 si_emit_global_shader_pointers(sctx, &sctx->descriptors[SI_DESCS_RW_BUFFERS]);
2116 }
2117
2118 si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(VERTEX),
2119 sh_base[PIPE_SHADER_VERTEX]);
2120 si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(TESS_EVAL),
2121 sh_base[PIPE_SHADER_TESS_EVAL]);
2122 si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(FRAGMENT),
2123 sh_base[PIPE_SHADER_FRAGMENT]);
2124 si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(TESS_CTRL),
2125 sh_base[PIPE_SHADER_TESS_CTRL]);
2126 si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(GEOMETRY),
2127 sh_base[PIPE_SHADER_GEOMETRY]);
2128
2129 sctx->shader_pointers_dirty &= ~u_bit_consecutive(SI_DESCS_RW_BUFFERS, SI_DESCS_FIRST_COMPUTE);
2130
2131 if (sctx->vertex_buffer_pointer_dirty && sctx->num_vertex_elements) {
2132 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2133
2134 /* Find the location of the VB descriptor pointer. */
2135 unsigned sh_dw_offset = SI_VS_NUM_USER_SGPR;
2136 if (sctx->chip_class >= GFX9) {
2137 if (sctx->tes_shader.cso)
2138 sh_dw_offset = GFX9_TCS_NUM_USER_SGPR;
2139 else if (sctx->gs_shader.cso)
2140 sh_dw_offset = GFX9_VSGS_NUM_USER_SGPR;
2141 }
2142
2143 unsigned sh_offset = sh_base[PIPE_SHADER_VERTEX] + sh_dw_offset * 4;
2144 si_emit_shader_pointer_head(cs, sh_offset, 1);
2145 si_emit_shader_pointer_body(
2146 sctx->screen, cs, sctx->vb_descriptors_buffer->gpu_address + sctx->vb_descriptors_offset);
2147 sctx->vertex_buffer_pointer_dirty = false;
2148 }
2149
2150 if (sctx->vertex_buffer_user_sgprs_dirty && sctx->num_vertex_elements &&
2151 sctx->screen->num_vbos_in_user_sgprs) {
2152 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2153 unsigned num_desc = MIN2(sctx->num_vertex_elements, sctx->screen->num_vbos_in_user_sgprs);
2154 unsigned sh_offset = sh_base[PIPE_SHADER_VERTEX] + SI_SGPR_VS_VB_DESCRIPTOR_FIRST * 4;
2155
2156 si_emit_shader_pointer_head(cs, sh_offset, num_desc * 4);
2157 radeon_emit_array(cs, sctx->vb_descriptor_user_sgprs, num_desc * 4);
2158 sctx->vertex_buffer_user_sgprs_dirty = false;
2159 }
2160
2161 if (sctx->graphics_bindless_pointer_dirty) {
2162 si_emit_global_shader_pointers(sctx, &sctx->bindless_descriptors);
2163 sctx->graphics_bindless_pointer_dirty = false;
2164 }
2165 }
2166
2167 void si_emit_compute_shader_pointers(struct si_context *sctx)
2168 {
2169 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2170 struct si_shader_selector *shader = &sctx->cs_shader_state.program->sel;
2171 unsigned base = R_00B900_COMPUTE_USER_DATA_0;
2172
2173 si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(COMPUTE),
2174 R_00B900_COMPUTE_USER_DATA_0);
2175 sctx->shader_pointers_dirty &= ~SI_DESCS_SHADER_MASK(COMPUTE);
2176
2177 if (sctx->compute_bindless_pointer_dirty) {
2178 si_emit_shader_pointer(sctx, &sctx->bindless_descriptors, base);
2179 sctx->compute_bindless_pointer_dirty = false;
2180 }
2181
2182 /* Set shader buffer descriptors in user SGPRs. */
2183 unsigned num_shaderbufs = shader->cs_num_shaderbufs_in_user_sgprs;
2184 if (num_shaderbufs && sctx->compute_shaderbuf_sgprs_dirty) {
2185 struct si_descriptors *desc = si_const_and_shader_buffer_descriptors(sctx, PIPE_SHADER_COMPUTE);
2186
2187 si_emit_shader_pointer_head(cs, R_00B900_COMPUTE_USER_DATA_0 +
2188 shader->cs_shaderbufs_sgpr_index * 4,
2189 num_shaderbufs * 4);
2190
2191 for (unsigned i = 0; i < num_shaderbufs; i++)
2192 radeon_emit_array(cs, &desc->list[si_get_shaderbuf_slot(i) * 4], 4);
2193
2194 sctx->compute_shaderbuf_sgprs_dirty = false;
2195 }
2196
2197 /* Set image descriptors in user SGPRs. */
2198 unsigned num_images = shader->cs_num_images_in_user_sgprs;
2199 if (num_images && sctx->compute_image_sgprs_dirty) {
2200 struct si_descriptors *desc = si_sampler_and_image_descriptors(sctx, PIPE_SHADER_COMPUTE);
2201
2202 si_emit_shader_pointer_head(cs, R_00B900_COMPUTE_USER_DATA_0 +
2203 shader->cs_images_sgpr_index * 4,
2204 shader->cs_images_num_sgprs);
2205
2206 for (unsigned i = 0; i < num_images; i++) {
2207 unsigned desc_offset = si_get_image_slot(i) * 8;
2208 unsigned num_sgprs = 8;
2209
2210 /* Image buffers are in desc[4..7]. */
2211 if (shader->info.image_buffers & (1 << i)) {
2212 desc_offset += 4;
2213 num_sgprs = 4;
2214 }
2215
2216 radeon_emit_array(cs, &desc->list[desc_offset], num_sgprs);
2217 }
2218
2219 sctx->compute_image_sgprs_dirty = false;
2220 }
2221 }
2222
2223 /* BINDLESS */
2224
2225 static void si_init_bindless_descriptors(struct si_context *sctx, struct si_descriptors *desc,
2226 short shader_userdata_rel_index, unsigned num_elements)
2227 {
2228 ASSERTED unsigned desc_slot;
2229
2230 si_init_descriptors(desc, shader_userdata_rel_index, 16, num_elements);
2231 sctx->bindless_descriptors.num_active_slots = num_elements;
2232
2233 /* The first bindless descriptor is stored at slot 1, because 0 is not
2234 * considered to be a valid handle.
2235 */
2236 sctx->num_bindless_descriptors = 1;
2237
2238 /* Track which bindless slots are used (or not). */
2239 util_idalloc_init(&sctx->bindless_used_slots);
2240 util_idalloc_resize(&sctx->bindless_used_slots, num_elements);
2241
2242 /* Reserve slot 0 because it's an invalid handle for bindless. */
2243 desc_slot = util_idalloc_alloc(&sctx->bindless_used_slots);
2244 assert(desc_slot == 0);
2245 }
2246
2247 static void si_release_bindless_descriptors(struct si_context *sctx)
2248 {
2249 si_release_descriptors(&sctx->bindless_descriptors);
2250 util_idalloc_fini(&sctx->bindless_used_slots);
2251 }
2252
2253 static unsigned si_get_first_free_bindless_slot(struct si_context *sctx)
2254 {
2255 struct si_descriptors *desc = &sctx->bindless_descriptors;
2256 unsigned desc_slot;
2257
2258 desc_slot = util_idalloc_alloc(&sctx->bindless_used_slots);
2259 if (desc_slot >= desc->num_elements) {
2260 /* The array of bindless descriptors is full, resize it. */
2261 unsigned slot_size = desc->element_dw_size * 4;
2262 unsigned new_num_elements = desc->num_elements * 2;
2263
2264 desc->list =
2265 REALLOC(desc->list, desc->num_elements * slot_size, new_num_elements * slot_size);
2266 desc->num_elements = new_num_elements;
2267 desc->num_active_slots = new_num_elements;
2268 }
2269
2270 assert(desc_slot);
2271 return desc_slot;
2272 }
2273
2274 static unsigned si_create_bindless_descriptor(struct si_context *sctx, uint32_t *desc_list,
2275 unsigned size)
2276 {
2277 struct si_descriptors *desc = &sctx->bindless_descriptors;
2278 unsigned desc_slot, desc_slot_offset;
2279
2280 /* Find a free slot. */
2281 desc_slot = si_get_first_free_bindless_slot(sctx);
2282
2283 /* For simplicity, sampler and image bindless descriptors use fixed
2284 * 16-dword slots for now. Image descriptors only need 8-dword but this
2285 * doesn't really matter because no real apps use image handles.
2286 */
2287 desc_slot_offset = desc_slot * 16;
2288
2289 /* Copy the descriptor into the array. */
2290 memcpy(desc->list + desc_slot_offset, desc_list, size);
2291
2292 /* Re-upload the whole array of bindless descriptors into a new buffer.
2293 */
2294 if (!si_upload_descriptors(sctx, desc))
2295 return 0;
2296
2297 /* Make sure to re-emit the shader pointers for all stages. */
2298 sctx->graphics_bindless_pointer_dirty = true;
2299 sctx->compute_bindless_pointer_dirty = true;
2300
2301 return desc_slot;
2302 }
2303
2304 static void si_update_bindless_buffer_descriptor(struct si_context *sctx, unsigned desc_slot,
2305 struct pipe_resource *resource, uint64_t offset,
2306 bool *desc_dirty)
2307 {
2308 struct si_descriptors *desc = &sctx->bindless_descriptors;
2309 struct si_resource *buf = si_resource(resource);
2310 unsigned desc_slot_offset = desc_slot * 16;
2311 uint32_t *desc_list = desc->list + desc_slot_offset + 4;
2312 uint64_t old_desc_va;
2313
2314 assert(resource->target == PIPE_BUFFER);
2315
2316 /* Retrieve the old buffer addr from the descriptor. */
2317 old_desc_va = si_desc_extract_buffer_address(desc_list);
2318
2319 if (old_desc_va != buf->gpu_address + offset) {
2320 /* The buffer has been invalidated when the handle wasn't
2321 * resident, update the descriptor and the dirty flag.
2322 */
2323 si_set_buf_desc_address(buf, offset, &desc_list[0]);
2324
2325 *desc_dirty = true;
2326 }
2327 }
2328
2329 static uint64_t si_create_texture_handle(struct pipe_context *ctx, struct pipe_sampler_view *view,
2330 const struct pipe_sampler_state *state)
2331 {
2332 struct si_sampler_view *sview = (struct si_sampler_view *)view;
2333 struct si_context *sctx = (struct si_context *)ctx;
2334 struct si_texture_handle *tex_handle;
2335 struct si_sampler_state *sstate;
2336 uint32_t desc_list[16];
2337 uint64_t handle;
2338
2339 tex_handle = CALLOC_STRUCT(si_texture_handle);
2340 if (!tex_handle)
2341 return 0;
2342
2343 memset(desc_list, 0, sizeof(desc_list));
2344 si_init_descriptor_list(&desc_list[0], 16, 1, null_texture_descriptor);
2345
2346 sstate = ctx->create_sampler_state(ctx, state);
2347 if (!sstate) {
2348 FREE(tex_handle);
2349 return 0;
2350 }
2351
2352 si_set_sampler_view_desc(sctx, sview, sstate, &desc_list[0]);
2353 memcpy(&tex_handle->sstate, sstate, sizeof(*sstate));
2354 ctx->delete_sampler_state(ctx, sstate);
2355
2356 tex_handle->desc_slot = si_create_bindless_descriptor(sctx, desc_list, sizeof(desc_list));
2357 if (!tex_handle->desc_slot) {
2358 FREE(tex_handle);
2359 return 0;
2360 }
2361
2362 handle = tex_handle->desc_slot;
2363
2364 if (!_mesa_hash_table_insert(sctx->tex_handles, (void *)(uintptr_t)handle, tex_handle)) {
2365 FREE(tex_handle);
2366 return 0;
2367 }
2368
2369 pipe_sampler_view_reference(&tex_handle->view, view);
2370
2371 si_resource(sview->base.texture)->texture_handle_allocated = true;
2372
2373 return handle;
2374 }
2375
2376 static void si_delete_texture_handle(struct pipe_context *ctx, uint64_t handle)
2377 {
2378 struct si_context *sctx = (struct si_context *)ctx;
2379 struct si_texture_handle *tex_handle;
2380 struct hash_entry *entry;
2381
2382 entry = _mesa_hash_table_search(sctx->tex_handles, (void *)(uintptr_t)handle);
2383 if (!entry)
2384 return;
2385
2386 tex_handle = (struct si_texture_handle *)entry->data;
2387
2388 /* Allow this descriptor slot to be re-used. */
2389 util_idalloc_free(&sctx->bindless_used_slots, tex_handle->desc_slot);
2390
2391 pipe_sampler_view_reference(&tex_handle->view, NULL);
2392 _mesa_hash_table_remove(sctx->tex_handles, entry);
2393 FREE(tex_handle);
2394 }
2395
2396 static void si_make_texture_handle_resident(struct pipe_context *ctx, uint64_t handle,
2397 bool resident)
2398 {
2399 struct si_context *sctx = (struct si_context *)ctx;
2400 struct si_texture_handle *tex_handle;
2401 struct si_sampler_view *sview;
2402 struct hash_entry *entry;
2403
2404 entry = _mesa_hash_table_search(sctx->tex_handles, (void *)(uintptr_t)handle);
2405 if (!entry)
2406 return;
2407
2408 tex_handle = (struct si_texture_handle *)entry->data;
2409 sview = (struct si_sampler_view *)tex_handle->view;
2410
2411 if (resident) {
2412 if (sview->base.texture->target != PIPE_BUFFER) {
2413 struct si_texture *tex = (struct si_texture *)sview->base.texture;
2414
2415 if (depth_needs_decompression(tex)) {
2416 util_dynarray_append(&sctx->resident_tex_needs_depth_decompress,
2417 struct si_texture_handle *, tex_handle);
2418 }
2419
2420 if (color_needs_decompression(tex)) {
2421 util_dynarray_append(&sctx->resident_tex_needs_color_decompress,
2422 struct si_texture_handle *, tex_handle);
2423 }
2424
2425 if (vi_dcc_enabled(tex, sview->base.u.tex.first_level) &&
2426 p_atomic_read(&tex->framebuffers_bound))
2427 sctx->need_check_render_feedback = true;
2428
2429 si_update_bindless_texture_descriptor(sctx, tex_handle);
2430 } else {
2431 si_update_bindless_buffer_descriptor(sctx, tex_handle->desc_slot, sview->base.texture,
2432 sview->base.u.buf.offset, &tex_handle->desc_dirty);
2433 }
2434
2435 /* Re-upload the descriptor if it has been updated while it
2436 * wasn't resident.
2437 */
2438 if (tex_handle->desc_dirty)
2439 sctx->bindless_descriptors_dirty = true;
2440
2441 /* Add the texture handle to the per-context list. */
2442 util_dynarray_append(&sctx->resident_tex_handles, struct si_texture_handle *, tex_handle);
2443
2444 /* Add the buffers to the current CS in case si_begin_new_cs()
2445 * is not going to be called.
2446 */
2447 si_sampler_view_add_buffer(sctx, sview->base.texture, RADEON_USAGE_READ,
2448 sview->is_stencil_sampler, false);
2449 } else {
2450 /* Remove the texture handle from the per-context list. */
2451 util_dynarray_delete_unordered(&sctx->resident_tex_handles, struct si_texture_handle *,
2452 tex_handle);
2453
2454 if (sview->base.texture->target != PIPE_BUFFER) {
2455 util_dynarray_delete_unordered(&sctx->resident_tex_needs_depth_decompress,
2456 struct si_texture_handle *, tex_handle);
2457
2458 util_dynarray_delete_unordered(&sctx->resident_tex_needs_color_decompress,
2459 struct si_texture_handle *, tex_handle);
2460 }
2461 }
2462 }
2463
2464 static uint64_t si_create_image_handle(struct pipe_context *ctx, const struct pipe_image_view *view)
2465 {
2466 struct si_context *sctx = (struct si_context *)ctx;
2467 struct si_image_handle *img_handle;
2468 uint32_t desc_list[16];
2469 uint64_t handle;
2470
2471 if (!view || !view->resource)
2472 return 0;
2473
2474 img_handle = CALLOC_STRUCT(si_image_handle);
2475 if (!img_handle)
2476 return 0;
2477
2478 memset(desc_list, 0, sizeof(desc_list));
2479 si_init_descriptor_list(&desc_list[0], 8, 2, null_image_descriptor);
2480
2481 si_set_shader_image_desc(sctx, view, false, &desc_list[0], &desc_list[8]);
2482
2483 img_handle->desc_slot = si_create_bindless_descriptor(sctx, desc_list, sizeof(desc_list));
2484 if (!img_handle->desc_slot) {
2485 FREE(img_handle);
2486 return 0;
2487 }
2488
2489 handle = img_handle->desc_slot;
2490
2491 if (!_mesa_hash_table_insert(sctx->img_handles, (void *)(uintptr_t)handle, img_handle)) {
2492 FREE(img_handle);
2493 return 0;
2494 }
2495
2496 util_copy_image_view(&img_handle->view, view);
2497
2498 si_resource(view->resource)->image_handle_allocated = true;
2499
2500 return handle;
2501 }
2502
2503 static void si_delete_image_handle(struct pipe_context *ctx, uint64_t handle)
2504 {
2505 struct si_context *sctx = (struct si_context *)ctx;
2506 struct si_image_handle *img_handle;
2507 struct hash_entry *entry;
2508
2509 entry = _mesa_hash_table_search(sctx->img_handles, (void *)(uintptr_t)handle);
2510 if (!entry)
2511 return;
2512
2513 img_handle = (struct si_image_handle *)entry->data;
2514
2515 util_copy_image_view(&img_handle->view, NULL);
2516 _mesa_hash_table_remove(sctx->img_handles, entry);
2517 FREE(img_handle);
2518 }
2519
2520 static void si_make_image_handle_resident(struct pipe_context *ctx, uint64_t handle,
2521 unsigned access, bool resident)
2522 {
2523 struct si_context *sctx = (struct si_context *)ctx;
2524 struct si_image_handle *img_handle;
2525 struct pipe_image_view *view;
2526 struct si_resource *res;
2527 struct hash_entry *entry;
2528
2529 entry = _mesa_hash_table_search(sctx->img_handles, (void *)(uintptr_t)handle);
2530 if (!entry)
2531 return;
2532
2533 img_handle = (struct si_image_handle *)entry->data;
2534 view = &img_handle->view;
2535 res = si_resource(view->resource);
2536
2537 if (resident) {
2538 if (res->b.b.target != PIPE_BUFFER) {
2539 struct si_texture *tex = (struct si_texture *)res;
2540 unsigned level = view->u.tex.level;
2541
2542 if (color_needs_decompression(tex)) {
2543 util_dynarray_append(&sctx->resident_img_needs_color_decompress,
2544 struct si_image_handle *, img_handle);
2545 }
2546
2547 if (vi_dcc_enabled(tex, level) && p_atomic_read(&tex->framebuffers_bound))
2548 sctx->need_check_render_feedback = true;
2549
2550 si_update_bindless_image_descriptor(sctx, img_handle);
2551 } else {
2552 si_update_bindless_buffer_descriptor(sctx, img_handle->desc_slot, view->resource,
2553 view->u.buf.offset, &img_handle->desc_dirty);
2554 }
2555
2556 /* Re-upload the descriptor if it has been updated while it
2557 * wasn't resident.
2558 */
2559 if (img_handle->desc_dirty)
2560 sctx->bindless_descriptors_dirty = true;
2561
2562 /* Add the image handle to the per-context list. */
2563 util_dynarray_append(&sctx->resident_img_handles, struct si_image_handle *, img_handle);
2564
2565 /* Add the buffers to the current CS in case si_begin_new_cs()
2566 * is not going to be called.
2567 */
2568 si_sampler_view_add_buffer(
2569 sctx, view->resource,
2570 (access & PIPE_IMAGE_ACCESS_WRITE) ? RADEON_USAGE_READWRITE : RADEON_USAGE_READ, false,
2571 false);
2572 } else {
2573 /* Remove the image handle from the per-context list. */
2574 util_dynarray_delete_unordered(&sctx->resident_img_handles, struct si_image_handle *,
2575 img_handle);
2576
2577 if (res->b.b.target != PIPE_BUFFER) {
2578 util_dynarray_delete_unordered(&sctx->resident_img_needs_color_decompress,
2579 struct si_image_handle *, img_handle);
2580 }
2581 }
2582 }
2583
2584 static void si_resident_buffers_add_all_to_bo_list(struct si_context *sctx)
2585 {
2586 unsigned num_resident_tex_handles, num_resident_img_handles;
2587
2588 num_resident_tex_handles = sctx->resident_tex_handles.size / sizeof(struct si_texture_handle *);
2589 num_resident_img_handles = sctx->resident_img_handles.size / sizeof(struct si_image_handle *);
2590
2591 /* Add all resident texture handles. */
2592 util_dynarray_foreach (&sctx->resident_tex_handles, struct si_texture_handle *, tex_handle) {
2593 struct si_sampler_view *sview = (struct si_sampler_view *)(*tex_handle)->view;
2594
2595 si_sampler_view_add_buffer(sctx, sview->base.texture, RADEON_USAGE_READ,
2596 sview->is_stencil_sampler, false);
2597 }
2598
2599 /* Add all resident image handles. */
2600 util_dynarray_foreach (&sctx->resident_img_handles, struct si_image_handle *, img_handle) {
2601 struct pipe_image_view *view = &(*img_handle)->view;
2602
2603 si_sampler_view_add_buffer(sctx, view->resource, RADEON_USAGE_READWRITE, false, false);
2604 }
2605
2606 sctx->num_resident_handles += num_resident_tex_handles + num_resident_img_handles;
2607 assert(sctx->bo_list_add_all_resident_resources);
2608 sctx->bo_list_add_all_resident_resources = false;
2609 }
2610
2611 /* INIT/DEINIT/UPLOAD */
2612
2613 void si_init_all_descriptors(struct si_context *sctx)
2614 {
2615 int i;
2616 unsigned first_shader = sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE;
2617
2618 for (i = first_shader; i < SI_NUM_SHADERS; i++) {
2619 bool is_2nd =
2620 sctx->chip_class >= GFX9 && (i == PIPE_SHADER_TESS_CTRL || i == PIPE_SHADER_GEOMETRY);
2621 unsigned num_sampler_slots = SI_NUM_IMAGE_SLOTS / 2 + SI_NUM_SAMPLERS;
2622 unsigned num_buffer_slots = SI_NUM_SHADER_BUFFERS + SI_NUM_CONST_BUFFERS;
2623 int rel_dw_offset;
2624 struct si_descriptors *desc;
2625
2626 if (is_2nd) {
2627 if (i == PIPE_SHADER_TESS_CTRL) {
2628 rel_dw_offset =
2629 (R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS - R_00B430_SPI_SHADER_USER_DATA_LS_0) / 4;
2630 } else if (sctx->chip_class >= GFX10) { /* PIPE_SHADER_GEOMETRY */
2631 rel_dw_offset =
2632 (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS - R_00B230_SPI_SHADER_USER_DATA_GS_0) / 4;
2633 } else {
2634 rel_dw_offset =
2635 (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS - R_00B330_SPI_SHADER_USER_DATA_ES_0) / 4;
2636 }
2637 } else {
2638 rel_dw_offset = SI_SGPR_CONST_AND_SHADER_BUFFERS;
2639 }
2640 desc = si_const_and_shader_buffer_descriptors(sctx, i);
2641 si_init_buffer_resources(&sctx->const_and_shader_buffers[i], desc, num_buffer_slots,
2642 rel_dw_offset, RADEON_PRIO_SHADER_RW_BUFFER,
2643 RADEON_PRIO_CONST_BUFFER);
2644 desc->slot_index_to_bind_directly = si_get_constbuf_slot(0);
2645
2646 if (is_2nd) {
2647 if (i == PIPE_SHADER_TESS_CTRL) {
2648 rel_dw_offset =
2649 (R_00B40C_SPI_SHADER_USER_DATA_ADDR_HI_HS - R_00B430_SPI_SHADER_USER_DATA_LS_0) / 4;
2650 } else if (sctx->chip_class >= GFX10) { /* PIPE_SHADER_GEOMETRY */
2651 rel_dw_offset =
2652 (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS - R_00B230_SPI_SHADER_USER_DATA_GS_0) / 4;
2653 } else {
2654 rel_dw_offset =
2655 (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS - R_00B330_SPI_SHADER_USER_DATA_ES_0) / 4;
2656 }
2657 } else {
2658 rel_dw_offset = SI_SGPR_SAMPLERS_AND_IMAGES;
2659 }
2660
2661 desc = si_sampler_and_image_descriptors(sctx, i);
2662 si_init_descriptors(desc, rel_dw_offset, 16, num_sampler_slots);
2663
2664 int j;
2665 for (j = 0; j < SI_NUM_IMAGE_SLOTS; j++)
2666 memcpy(desc->list + j * 8, null_image_descriptor, 8 * 4);
2667 for (; j < SI_NUM_IMAGE_SLOTS + SI_NUM_SAMPLERS * 2; j++)
2668 memcpy(desc->list + j * 8, null_texture_descriptor, 8 * 4);
2669 }
2670
2671 si_init_buffer_resources(&sctx->rw_buffers, &sctx->descriptors[SI_DESCS_RW_BUFFERS],
2672 SI_NUM_RW_BUFFERS, SI_SGPR_RW_BUFFERS,
2673 /* The second priority is used by
2674 * const buffers in RW buffer slots. */
2675 RADEON_PRIO_SHADER_RINGS, RADEON_PRIO_CONST_BUFFER);
2676 sctx->descriptors[SI_DESCS_RW_BUFFERS].num_active_slots = SI_NUM_RW_BUFFERS;
2677
2678 /* Initialize an array of 1024 bindless descriptors, when the limit is
2679 * reached, just make it larger and re-upload the whole array.
2680 */
2681 si_init_bindless_descriptors(sctx, &sctx->bindless_descriptors,
2682 SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES, 1024);
2683
2684 sctx->descriptors_dirty = u_bit_consecutive(0, SI_NUM_DESCS);
2685
2686 /* Set pipe_context functions. */
2687 sctx->b.bind_sampler_states = si_bind_sampler_states;
2688 sctx->b.set_shader_images = si_set_shader_images;
2689 sctx->b.set_constant_buffer = si_pipe_set_constant_buffer;
2690 sctx->b.set_shader_buffers = si_set_shader_buffers;
2691 sctx->b.set_sampler_views = si_set_sampler_views;
2692 sctx->b.create_texture_handle = si_create_texture_handle;
2693 sctx->b.delete_texture_handle = si_delete_texture_handle;
2694 sctx->b.make_texture_handle_resident = si_make_texture_handle_resident;
2695 sctx->b.create_image_handle = si_create_image_handle;
2696 sctx->b.delete_image_handle = si_delete_image_handle;
2697 sctx->b.make_image_handle_resident = si_make_image_handle_resident;
2698
2699 if (!sctx->has_graphics)
2700 return;
2701
2702 sctx->b.set_polygon_stipple = si_set_polygon_stipple;
2703
2704 /* Shader user data. */
2705 sctx->atoms.s.shader_pointers.emit = si_emit_graphics_shader_pointers;
2706
2707 /* Set default and immutable mappings. */
2708 if (sctx->ngg) {
2709 assert(sctx->chip_class >= GFX10);
2710 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B230_SPI_SHADER_USER_DATA_GS_0);
2711 } else {
2712 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0);
2713 }
2714
2715 if (sctx->chip_class == GFX9) {
2716 si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL, R_00B430_SPI_SHADER_USER_DATA_LS_0);
2717 si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY, R_00B330_SPI_SHADER_USER_DATA_ES_0);
2718 } else {
2719 si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL, R_00B430_SPI_SHADER_USER_DATA_HS_0);
2720 si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY, R_00B230_SPI_SHADER_USER_DATA_GS_0);
2721 }
2722 si_set_user_data_base(sctx, PIPE_SHADER_FRAGMENT, R_00B030_SPI_SHADER_USER_DATA_PS_0);
2723 }
2724
2725 static bool si_upload_shader_descriptors(struct si_context *sctx, unsigned mask)
2726 {
2727 unsigned dirty = sctx->descriptors_dirty & mask;
2728
2729 /* Assume nothing will go wrong: */
2730 sctx->shader_pointers_dirty |= dirty;
2731
2732 while (dirty) {
2733 unsigned i = u_bit_scan(&dirty);
2734
2735 if (!si_upload_descriptors(sctx, &sctx->descriptors[i]))
2736 return false;
2737 }
2738
2739 sctx->descriptors_dirty &= ~mask;
2740
2741 si_upload_bindless_descriptors(sctx);
2742
2743 return true;
2744 }
2745
2746 bool si_upload_graphics_shader_descriptors(struct si_context *sctx)
2747 {
2748 const unsigned mask = u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE);
2749 return si_upload_shader_descriptors(sctx, mask);
2750 }
2751
2752 bool si_upload_compute_shader_descriptors(struct si_context *sctx)
2753 {
2754 /* Does not update rw_buffers as that is not needed for compute shaders
2755 * and the input buffer is using the same SGPR's anyway.
2756 */
2757 const unsigned mask =
2758 u_bit_consecutive(SI_DESCS_FIRST_COMPUTE, SI_NUM_DESCS - SI_DESCS_FIRST_COMPUTE);
2759 return si_upload_shader_descriptors(sctx, mask);
2760 }
2761
2762 void si_release_all_descriptors(struct si_context *sctx)
2763 {
2764 int i;
2765
2766 for (i = 0; i < SI_NUM_SHADERS; i++) {
2767 si_release_buffer_resources(&sctx->const_and_shader_buffers[i],
2768 si_const_and_shader_buffer_descriptors(sctx, i));
2769 si_release_sampler_views(&sctx->samplers[i]);
2770 si_release_image_views(&sctx->images[i]);
2771 }
2772 si_release_buffer_resources(&sctx->rw_buffers, &sctx->descriptors[SI_DESCS_RW_BUFFERS]);
2773 for (i = 0; i < SI_NUM_VERTEX_BUFFERS; i++)
2774 pipe_vertex_buffer_unreference(&sctx->vertex_buffer[i]);
2775
2776 for (i = 0; i < SI_NUM_DESCS; ++i)
2777 si_release_descriptors(&sctx->descriptors[i]);
2778
2779 si_resource_reference(&sctx->vb_descriptors_buffer, NULL);
2780 sctx->vb_descriptors_gpu_list = NULL; /* points into a mapped buffer */
2781
2782 si_release_bindless_descriptors(sctx);
2783 }
2784
2785 bool si_gfx_resources_check_encrypted(struct si_context *sctx)
2786 {
2787 bool use_encrypted_bo = false;
2788 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
2789 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
2790 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
2791 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
2792 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
2793 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
2794 };
2795
2796 for (unsigned i = 0; i < SI_NUM_GRAPHICS_SHADERS && !use_encrypted_bo; i++) {
2797 if (!current_shader[i]->cso)
2798 continue;
2799
2800 use_encrypted_bo |=
2801 si_buffer_resources_check_encrypted(sctx, &sctx->const_and_shader_buffers[i]);
2802 use_encrypted_bo |=
2803 si_sampler_views_check_encrypted(sctx, &sctx->samplers[i],
2804 current_shader[i]->cso->info.samplers_declared);
2805 use_encrypted_bo |= si_image_views_check_encrypted(sctx, &sctx->images[i],
2806 current_shader[i]->cso->info.images_declared);
2807 }
2808 use_encrypted_bo |= si_buffer_resources_check_encrypted(sctx, &sctx->rw_buffers);
2809
2810 struct si_state_blend *blend = sctx->queued.named.blend;
2811 for (int i = 0; i < sctx->framebuffer.state.nr_cbufs && !use_encrypted_bo; i++) {
2812 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2813 if (surf && surf->texture) {
2814 struct si_texture *tex = (struct si_texture *)surf->texture;
2815 if (!(tex->buffer.flags & RADEON_FLAG_ENCRYPTED))
2816 continue;
2817 /* Are we reading from this framebuffer (blend) */
2818 if ((blend->blend_enable_4bit >> (4 * i)) & 0xf) {
2819 /* TODO: blend op */
2820 use_encrypted_bo = true;
2821 }
2822 }
2823 }
2824
2825 /* TODO: we should assert that either use_encrypted_bo is false,
2826 * or all writable buffers are encrypted.
2827 */
2828 return use_encrypted_bo;
2829 }
2830
2831 void si_gfx_resources_add_all_to_bo_list(struct si_context *sctx)
2832 {
2833 for (unsigned i = 0; i < SI_NUM_GRAPHICS_SHADERS; i++) {
2834 si_buffer_resources_begin_new_cs(sctx, &sctx->const_and_shader_buffers[i]);
2835 si_sampler_views_begin_new_cs(sctx, &sctx->samplers[i]);
2836 si_image_views_begin_new_cs(sctx, &sctx->images[i]);
2837 }
2838 si_buffer_resources_begin_new_cs(sctx, &sctx->rw_buffers);
2839 si_vertex_buffers_begin_new_cs(sctx);
2840
2841 if (sctx->bo_list_add_all_resident_resources)
2842 si_resident_buffers_add_all_to_bo_list(sctx);
2843
2844 assert(sctx->bo_list_add_all_gfx_resources);
2845 sctx->bo_list_add_all_gfx_resources = false;
2846 }
2847
2848 bool si_compute_resources_check_encrypted(struct si_context *sctx)
2849 {
2850 unsigned sh = PIPE_SHADER_COMPUTE;
2851
2852 struct si_shader_info* info = &sctx->cs_shader_state.program->sel.info;
2853
2854 /* TODO: we should assert that either use_encrypted_bo is false,
2855 * or all writable buffers are encrypted.
2856 */
2857 return si_buffer_resources_check_encrypted(sctx, &sctx->const_and_shader_buffers[sh]) ||
2858 si_sampler_views_check_encrypted(sctx, &sctx->samplers[sh], info->samplers_declared) ||
2859 si_image_views_check_encrypted(sctx, &sctx->images[sh], info->images_declared) ||
2860 si_buffer_resources_check_encrypted(sctx, &sctx->rw_buffers);
2861 }
2862
2863 void si_compute_resources_add_all_to_bo_list(struct si_context *sctx)
2864 {
2865 unsigned sh = PIPE_SHADER_COMPUTE;
2866
2867 si_buffer_resources_begin_new_cs(sctx, &sctx->const_and_shader_buffers[sh]);
2868 si_sampler_views_begin_new_cs(sctx, &sctx->samplers[sh]);
2869 si_image_views_begin_new_cs(sctx, &sctx->images[sh]);
2870 si_buffer_resources_begin_new_cs(sctx, &sctx->rw_buffers);
2871
2872 if (sctx->bo_list_add_all_resident_resources)
2873 si_resident_buffers_add_all_to_bo_list(sctx);
2874
2875 assert(sctx->bo_list_add_all_compute_resources);
2876 sctx->bo_list_add_all_compute_resources = false;
2877 }
2878
2879 void si_add_all_descriptors_to_bo_list(struct si_context *sctx)
2880 {
2881 for (unsigned i = 0; i < SI_NUM_DESCS; ++i)
2882 si_add_descriptors_to_bo_list(sctx, &sctx->descriptors[i]);
2883 si_add_descriptors_to_bo_list(sctx, &sctx->bindless_descriptors);
2884
2885 sctx->bo_list_add_all_resident_resources = true;
2886 sctx->bo_list_add_all_gfx_resources = true;
2887 sctx->bo_list_add_all_compute_resources = true;
2888 }
2889
2890 void si_set_active_descriptors(struct si_context *sctx, unsigned desc_idx, uint64_t new_active_mask)
2891 {
2892 struct si_descriptors *desc = &sctx->descriptors[desc_idx];
2893
2894 /* Ignore no-op updates and updates that disable all slots. */
2895 if (!new_active_mask ||
2896 new_active_mask == u_bit_consecutive64(desc->first_active_slot, desc->num_active_slots))
2897 return;
2898
2899 int first, count;
2900 u_bit_scan_consecutive_range64(&new_active_mask, &first, &count);
2901 assert(new_active_mask == 0);
2902
2903 /* Upload/dump descriptors if slots are being enabled. */
2904 if (first < desc->first_active_slot ||
2905 first + count > desc->first_active_slot + desc->num_active_slots)
2906 sctx->descriptors_dirty |= 1u << desc_idx;
2907
2908 desc->first_active_slot = first;
2909 desc->num_active_slots = count;
2910 }
2911
2912 void si_set_active_descriptors_for_shader(struct si_context *sctx, struct si_shader_selector *sel)
2913 {
2914 if (!sel)
2915 return;
2916
2917 si_set_active_descriptors(sctx, si_const_and_shader_buffer_descriptors_idx(sel->type),
2918 sel->active_const_and_shader_buffers);
2919 si_set_active_descriptors(sctx, si_sampler_and_image_descriptors_idx(sel->type),
2920 sel->active_samplers_and_images);
2921 }