2 * Copyright 2013 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 /* Resource binding slots and sampler states (each described with 8 or
26 * 4 dwords) are stored in lists in memory which is accessed by shaders
27 * using scalar load instructions.
29 * This file is responsible for managing such lists. It keeps a copy of all
30 * descriptors in CPU memory and re-uploads a whole list if some slots have
33 * This code is also reponsible for updating shader pointers to those lists.
35 * Note that CP DMA can't be used for updating the lists, because a GPU hang
36 * could leave the list in a mid-IB state and the next IB would get wrong
37 * descriptors and the whole context would be unusable at that point.
38 * (Note: The register shadowing can't be used due to the same reason)
40 * Also, uploading descriptors to newly allocated memory doesn't require
44 * Possible scenarios for one 16 dword image+sampler slot:
46 * | Image | w/ FMASK | Buffer | NULL
47 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
48 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
49 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
50 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
52 * FMASK implies MSAA, therefore no sampler state.
53 * Sampler states are never unbound except when FMASK is bound.
59 #include "util/hash_table.h"
60 #include "util/u_idalloc.h"
61 #include "util/format/u_format.h"
62 #include "util/u_memory.h"
63 #include "util/u_upload_mgr.h"
66 /* NULL image and buffer descriptor for textures (alpha = 1) and images
69 * For images, all fields must be zero except for the swizzle, which
70 * supports arbitrary combinations of 0s and 1s. The texture type must be
71 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
73 * For buffers, all fields must be zero. If they are not, the hw hangs.
75 * This is the only reason why the buffer descriptor must be in words [4:7].
77 static uint32_t null_texture_descriptor
[8] = {
81 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1
) |
82 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
83 /* the rest must contain zeros, which is also used by the buffer
87 static uint32_t null_image_descriptor
[8] = {
91 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
92 /* the rest must contain zeros, which is also used by the buffer
96 static uint64_t si_desc_extract_buffer_address(const uint32_t *desc
)
98 uint64_t va
= desc
[0] |
99 ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc
[1]) << 32);
101 /* Sign-extend the 48-bit address. */
103 va
= (int64_t)va
>> 16;
107 static void si_init_descriptor_list(uint32_t *desc_list
,
108 unsigned element_dw_size
,
109 unsigned num_elements
,
110 const uint32_t *null_descriptor
)
114 /* Initialize the array to NULL descriptors if the element size is 8. */
115 if (null_descriptor
) {
116 assert(element_dw_size
% 8 == 0);
117 for (i
= 0; i
< num_elements
* element_dw_size
/ 8; i
++)
118 memcpy(desc_list
+ i
* 8, null_descriptor
, 8 * 4);
122 static void si_init_descriptors(struct si_descriptors
*desc
,
123 short shader_userdata_rel_index
,
124 unsigned element_dw_size
,
125 unsigned num_elements
)
127 desc
->list
= CALLOC(num_elements
, element_dw_size
* 4);
128 desc
->element_dw_size
= element_dw_size
;
129 desc
->num_elements
= num_elements
;
130 desc
->shader_userdata_offset
= shader_userdata_rel_index
* 4;
131 desc
->slot_index_to_bind_directly
= -1;
134 static void si_release_descriptors(struct si_descriptors
*desc
)
136 si_resource_reference(&desc
->buffer
, NULL
);
140 static bool si_upload_descriptors(struct si_context
*sctx
,
141 struct si_descriptors
*desc
)
143 unsigned slot_size
= desc
->element_dw_size
* 4;
144 unsigned first_slot_offset
= desc
->first_active_slot
* slot_size
;
145 unsigned upload_size
= desc
->num_active_slots
* slot_size
;
147 /* Skip the upload if no shader is using the descriptors. dirty_mask
148 * will stay dirty and the descriptors will be uploaded when there is
149 * a shader using them.
154 /* If there is just one active descriptor, bind it directly. */
155 if ((int)desc
->first_active_slot
== desc
->slot_index_to_bind_directly
&&
156 desc
->num_active_slots
== 1) {
157 uint32_t *descriptor
= &desc
->list
[desc
->slot_index_to_bind_directly
*
158 desc
->element_dw_size
];
160 /* The buffer is already in the buffer list. */
161 si_resource_reference(&desc
->buffer
, NULL
);
162 desc
->gpu_list
= NULL
;
163 desc
->gpu_address
= si_desc_extract_buffer_address(descriptor
);
164 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
169 unsigned buffer_offset
;
170 u_upload_alloc(sctx
->b
.const_uploader
, first_slot_offset
, upload_size
,
171 si_optimal_tcc_alignment(sctx
, upload_size
),
172 &buffer_offset
, (struct pipe_resource
**)&desc
->buffer
,
175 desc
->gpu_address
= 0;
176 return false; /* skip the draw call */
179 util_memcpy_cpu_to_le32(ptr
, (char*)desc
->list
+ first_slot_offset
,
181 desc
->gpu_list
= ptr
- first_slot_offset
/ 4;
183 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, desc
->buffer
,
184 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
186 /* The shader pointer should point to slot 0. */
187 buffer_offset
-= first_slot_offset
;
188 desc
->gpu_address
= desc
->buffer
->gpu_address
+ buffer_offset
;
190 assert(desc
->buffer
->flags
& RADEON_FLAG_32BIT
);
191 assert((desc
->buffer
->gpu_address
>> 32) == sctx
->screen
->info
.address32_hi
);
192 assert((desc
->gpu_address
>> 32) == sctx
->screen
->info
.address32_hi
);
194 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
199 si_descriptors_begin_new_cs(struct si_context
*sctx
, struct si_descriptors
*desc
)
204 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, desc
->buffer
,
205 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
210 static inline enum radeon_bo_priority
211 si_get_sampler_view_priority(struct si_resource
*res
)
213 if (res
->b
.b
.target
== PIPE_BUFFER
)
214 return RADEON_PRIO_SAMPLER_BUFFER
;
216 if (res
->b
.b
.nr_samples
> 1)
217 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA
;
219 return RADEON_PRIO_SAMPLER_TEXTURE
;
222 static struct si_descriptors
*
223 si_sampler_and_image_descriptors(struct si_context
*sctx
, unsigned shader
)
225 return &sctx
->descriptors
[si_sampler_and_image_descriptors_idx(shader
)];
228 static void si_release_sampler_views(struct si_samplers
*samplers
)
232 for (i
= 0; i
< ARRAY_SIZE(samplers
->views
); i
++) {
233 pipe_sampler_view_reference(&samplers
->views
[i
], NULL
);
237 static void si_sampler_view_add_buffer(struct si_context
*sctx
,
238 struct pipe_resource
*resource
,
239 enum radeon_bo_usage usage
,
240 bool is_stencil_sampler
,
243 struct si_texture
*tex
= (struct si_texture
*)resource
;
244 enum radeon_bo_priority priority
;
249 /* Use the flushed depth texture if direct sampling is unsupported. */
250 if (resource
->target
!= PIPE_BUFFER
&&
251 tex
->is_depth
&& !si_can_sample_zs(tex
, is_stencil_sampler
))
252 tex
= tex
->flushed_depth_texture
;
254 priority
= si_get_sampler_view_priority(&tex
->buffer
);
255 radeon_add_to_gfx_buffer_list_check_mem(sctx
, &tex
->buffer
, usage
, priority
,
258 if (resource
->target
== PIPE_BUFFER
)
261 /* Add separate DCC. */
262 if (tex
->dcc_separate_buffer
) {
263 radeon_add_to_gfx_buffer_list_check_mem(sctx
, tex
->dcc_separate_buffer
,
264 usage
, RADEON_PRIO_SEPARATE_META
, check_mem
);
268 static void si_sampler_views_begin_new_cs(struct si_context
*sctx
,
269 struct si_samplers
*samplers
)
271 unsigned mask
= samplers
->enabled_mask
;
273 /* Add buffers to the CS. */
275 int i
= u_bit_scan(&mask
);
276 struct si_sampler_view
*sview
= (struct si_sampler_view
*)samplers
->views
[i
];
278 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
280 sview
->is_stencil_sampler
, false);
284 /* Set buffer descriptor fields that can be changed by reallocations. */
285 static void si_set_buf_desc_address(struct si_resource
*buf
,
286 uint64_t offset
, uint32_t *state
)
288 uint64_t va
= buf
->gpu_address
+ offset
;
291 state
[1] &= C_008F04_BASE_ADDRESS_HI
;
292 state
[1] |= S_008F04_BASE_ADDRESS_HI(va
>> 32);
295 /* Set texture descriptor fields that can be changed by reallocations.
298 * \param base_level_info information of the level of BASE_ADDRESS
299 * \param base_level the level of BASE_ADDRESS
300 * \param first_level pipe_sampler_view.u.tex.first_level
301 * \param block_width util_format_get_blockwidth()
302 * \param is_stencil select between separate Z & Stencil
303 * \param state descriptor to update
305 void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen
,
306 struct si_texture
*tex
,
307 const struct legacy_surf_level
*base_level_info
,
308 unsigned base_level
, unsigned first_level
,
309 unsigned block_width
, bool is_stencil
,
312 uint64_t va
, meta_va
= 0;
314 if (tex
->is_depth
&& !si_can_sample_zs(tex
, is_stencil
)) {
315 tex
= tex
->flushed_depth_texture
;
319 va
= tex
->buffer
.gpu_address
;
321 if (sscreen
->info
.chip_class
>= GFX9
) {
322 /* Only stencil_offset needs to be added here. */
324 va
+= tex
->surface
.u
.gfx9
.stencil_offset
;
326 va
+= tex
->surface
.u
.gfx9
.surf_offset
;
328 va
+= base_level_info
->offset
;
332 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
333 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
335 /* Only macrotiled modes can set tile swizzle.
336 * GFX9 doesn't use (legacy) base_level_info.
338 if (sscreen
->info
.chip_class
>= GFX9
||
339 base_level_info
->mode
== RADEON_SURF_MODE_2D
)
340 state
[0] |= tex
->surface
.tile_swizzle
;
342 if (sscreen
->info
.chip_class
>= GFX8
) {
343 state
[6] &= C_008F28_COMPRESSION_EN
;
345 if (vi_dcc_enabled(tex
, first_level
)) {
346 meta_va
= (!tex
->dcc_separate_buffer
? tex
->buffer
.gpu_address
: 0) +
347 tex
->surface
.dcc_offset
;
349 if (sscreen
->info
.chip_class
== GFX8
) {
350 meta_va
+= base_level_info
->dcc_offset
;
351 assert(base_level_info
->mode
== RADEON_SURF_MODE_2D
);
354 unsigned dcc_tile_swizzle
= tex
->surface
.tile_swizzle
<< 8;
355 dcc_tile_swizzle
&= tex
->surface
.dcc_alignment
- 1;
356 meta_va
|= dcc_tile_swizzle
;
357 } else if (vi_tc_compat_htile_enabled(tex
, first_level
,
358 is_stencil
? PIPE_MASK_S
: PIPE_MASK_Z
)) {
359 meta_va
= tex
->buffer
.gpu_address
+ tex
->surface
.htile_offset
;
363 state
[6] |= S_008F28_COMPRESSION_EN(1);
366 if (sscreen
->info
.chip_class
>= GFX8
&& sscreen
->info
.chip_class
<= GFX9
)
367 state
[7] = meta_va
>> 8;
369 if (sscreen
->info
.chip_class
>= GFX10
) {
370 state
[3] &= C_00A00C_SW_MODE
;
373 state
[3] |= S_00A00C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
375 state
[3] |= S_00A00C_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
);
378 state
[6] &= C_00A018_META_DATA_ADDRESS_LO
&
379 C_00A018_META_PIPE_ALIGNED
;
382 struct gfx9_surf_meta_flags meta
;
384 if (tex
->surface
.dcc_offset
)
385 meta
= tex
->surface
.u
.gfx9
.dcc
;
387 meta
= tex
->surface
.u
.gfx9
.htile
;
389 state
[6] |= S_00A018_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
390 S_00A018_META_DATA_ADDRESS_LO(meta_va
>> 8);
393 state
[7] = meta_va
>> 16;
394 } else if (sscreen
->info
.chip_class
== GFX9
) {
395 state
[3] &= C_008F1C_SW_MODE
;
396 state
[4] &= C_008F20_PITCH
;
399 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
400 state
[4] |= S_008F20_PITCH(tex
->surface
.u
.gfx9
.stencil
.epitch
);
402 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
);
403 state
[4] |= S_008F20_PITCH(tex
->surface
.u
.gfx9
.surf
.epitch
);
406 state
[5] &= C_008F24_META_DATA_ADDRESS
&
407 C_008F24_META_PIPE_ALIGNED
&
408 C_008F24_META_RB_ALIGNED
;
410 struct gfx9_surf_meta_flags meta
;
412 if (tex
->surface
.dcc_offset
)
413 meta
= tex
->surface
.u
.gfx9
.dcc
;
415 meta
= tex
->surface
.u
.gfx9
.htile
;
417 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
418 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
419 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
423 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
424 unsigned index
= si_tile_mode_index(tex
, base_level
, is_stencil
);
426 state
[3] &= C_008F1C_TILING_INDEX
;
427 state
[3] |= S_008F1C_TILING_INDEX(index
);
428 state
[4] &= C_008F20_PITCH
;
429 state
[4] |= S_008F20_PITCH(pitch
- 1);
433 static void si_set_sampler_state_desc(struct si_sampler_state
*sstate
,
434 struct si_sampler_view
*sview
,
435 struct si_texture
*tex
,
438 if (sview
&& sview
->is_integer
)
439 memcpy(desc
, sstate
->integer_val
, 4*4);
440 else if (tex
&& tex
->upgraded_depth
&&
441 (!sview
|| !sview
->is_stencil_sampler
))
442 memcpy(desc
, sstate
->upgraded_depth_val
, 4*4);
444 memcpy(desc
, sstate
->val
, 4*4);
447 static void si_set_sampler_view_desc(struct si_context
*sctx
,
448 struct si_sampler_view
*sview
,
449 struct si_sampler_state
*sstate
,
452 struct pipe_sampler_view
*view
= &sview
->base
;
453 struct si_texture
*tex
= (struct si_texture
*)view
->texture
;
454 bool is_buffer
= tex
->buffer
.b
.b
.target
== PIPE_BUFFER
;
456 if (unlikely(!is_buffer
&& sview
->dcc_incompatible
)) {
457 if (vi_dcc_enabled(tex
, view
->u
.tex
.first_level
))
458 if (!si_texture_disable_dcc(sctx
, tex
))
459 si_decompress_dcc(sctx
, tex
);
461 sview
->dcc_incompatible
= false;
464 assert(tex
); /* views with texture == NULL aren't supported */
465 memcpy(desc
, sview
->state
, 8*4);
468 si_set_buf_desc_address(&tex
->buffer
,
469 sview
->base
.u
.buf
.offset
,
472 bool is_separate_stencil
= tex
->db_compatible
&&
473 sview
->is_stencil_sampler
;
475 si_set_mutable_tex_desc_fields(sctx
->screen
, tex
,
476 sview
->base_level_info
,
478 sview
->base
.u
.tex
.first_level
,
484 if (!is_buffer
&& tex
->surface
.fmask_size
) {
485 memcpy(desc
+ 8, sview
->fmask_state
, 8*4);
487 /* Disable FMASK and bind sampler state in [12:15]. */
488 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
491 si_set_sampler_state_desc(sstate
, sview
,
492 is_buffer
? NULL
: tex
,
497 static bool color_needs_decompression(struct si_texture
*tex
)
499 return tex
->surface
.fmask_size
||
500 (tex
->dirty_level_mask
&&
501 (tex
->cmask_buffer
|| tex
->surface
.dcc_offset
));
504 static bool depth_needs_decompression(struct si_texture
*tex
)
506 /* If the depth/stencil texture is TC-compatible, no decompression
507 * will be done. The decompression function will only flush DB caches
508 * to make it coherent with shaders. That's necessary because the driver
509 * doesn't flush DB caches in any other case.
511 return tex
->db_compatible
;
514 static void si_set_sampler_view(struct si_context
*sctx
,
516 unsigned slot
, struct pipe_sampler_view
*view
,
517 bool disallow_early_out
)
519 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
520 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
521 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(sctx
, shader
);
522 unsigned desc_slot
= si_get_sampler_slot(slot
);
523 uint32_t *desc
= descs
->list
+ desc_slot
* 16;
525 if (samplers
->views
[slot
] == view
&& !disallow_early_out
)
529 struct si_texture
*tex
= (struct si_texture
*)view
->texture
;
531 si_set_sampler_view_desc(sctx
, sview
,
532 samplers
->sampler_states
[slot
], desc
);
534 if (tex
->buffer
.b
.b
.target
== PIPE_BUFFER
) {
535 tex
->buffer
.bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
536 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
537 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
539 if (depth_needs_decompression(tex
)) {
540 samplers
->needs_depth_decompress_mask
|= 1u << slot
;
542 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
544 if (color_needs_decompression(tex
)) {
545 samplers
->needs_color_decompress_mask
|= 1u << slot
;
547 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
550 if (tex
->surface
.dcc_offset
&&
551 p_atomic_read(&tex
->framebuffers_bound
))
552 sctx
->need_check_render_feedback
= true;
555 pipe_sampler_view_reference(&samplers
->views
[slot
], view
);
556 samplers
->enabled_mask
|= 1u << slot
;
558 /* Since this can flush, it must be done after enabled_mask is
560 si_sampler_view_add_buffer(sctx
, view
->texture
,
562 sview
->is_stencil_sampler
, true);
564 pipe_sampler_view_reference(&samplers
->views
[slot
], NULL
);
565 memcpy(desc
, null_texture_descriptor
, 8*4);
566 /* Only clear the lower dwords of FMASK. */
567 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
568 /* Re-set the sampler state if we are transitioning from FMASK. */
569 if (samplers
->sampler_states
[slot
])
570 si_set_sampler_state_desc(samplers
->sampler_states
[slot
], NULL
, NULL
,
573 samplers
->enabled_mask
&= ~(1u << slot
);
574 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
575 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
578 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
581 static void si_update_shader_needs_decompress_mask(struct si_context
*sctx
,
584 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
585 unsigned shader_bit
= 1 << shader
;
587 if (samplers
->needs_depth_decompress_mask
||
588 samplers
->needs_color_decompress_mask
||
589 sctx
->images
[shader
].needs_color_decompress_mask
)
590 sctx
->shader_needs_decompress_mask
|= shader_bit
;
592 sctx
->shader_needs_decompress_mask
&= ~shader_bit
;
595 static void si_set_sampler_views(struct pipe_context
*ctx
,
596 enum pipe_shader_type shader
, unsigned start
,
598 struct pipe_sampler_view
**views
)
600 struct si_context
*sctx
= (struct si_context
*)ctx
;
603 if (!count
|| shader
>= SI_NUM_SHADERS
)
607 for (i
= 0; i
< count
; i
++)
608 si_set_sampler_view(sctx
, shader
, start
+ i
, views
[i
], false);
610 for (i
= 0; i
< count
; i
++)
611 si_set_sampler_view(sctx
, shader
, start
+ i
, NULL
, false);
614 si_update_shader_needs_decompress_mask(sctx
, shader
);
618 si_samplers_update_needs_color_decompress_mask(struct si_samplers
*samplers
)
620 unsigned mask
= samplers
->enabled_mask
;
623 int i
= u_bit_scan(&mask
);
624 struct pipe_resource
*res
= samplers
->views
[i
]->texture
;
626 if (res
&& res
->target
!= PIPE_BUFFER
) {
627 struct si_texture
*tex
= (struct si_texture
*)res
;
629 if (color_needs_decompression(tex
)) {
630 samplers
->needs_color_decompress_mask
|= 1u << i
;
632 samplers
->needs_color_decompress_mask
&= ~(1u << i
);
641 si_release_image_views(struct si_images
*images
)
645 for (i
= 0; i
< SI_NUM_IMAGES
; ++i
) {
646 struct pipe_image_view
*view
= &images
->views
[i
];
648 pipe_resource_reference(&view
->resource
, NULL
);
653 si_image_views_begin_new_cs(struct si_context
*sctx
, struct si_images
*images
)
655 uint mask
= images
->enabled_mask
;
657 /* Add buffers to the CS. */
659 int i
= u_bit_scan(&mask
);
660 struct pipe_image_view
*view
= &images
->views
[i
];
662 assert(view
->resource
);
664 si_sampler_view_add_buffer(sctx
, view
->resource
,
665 RADEON_USAGE_READWRITE
, false, false);
670 si_disable_shader_image(struct si_context
*ctx
, unsigned shader
, unsigned slot
)
672 struct si_images
*images
= &ctx
->images
[shader
];
674 if (images
->enabled_mask
& (1u << slot
)) {
675 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
676 unsigned desc_slot
= si_get_image_slot(slot
);
678 pipe_resource_reference(&images
->views
[slot
].resource
, NULL
);
679 images
->needs_color_decompress_mask
&= ~(1 << slot
);
681 memcpy(descs
->list
+ desc_slot
*8, null_image_descriptor
, 8*4);
682 images
->enabled_mask
&= ~(1u << slot
);
683 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
688 si_mark_image_range_valid(const struct pipe_image_view
*view
)
690 struct si_resource
*res
= si_resource(view
->resource
);
692 if (res
->b
.b
.target
!= PIPE_BUFFER
)
695 util_range_add(&res
->b
.b
, &res
->valid_buffer_range
,
697 view
->u
.buf
.offset
+ view
->u
.buf
.size
);
700 static void si_set_shader_image_desc(struct si_context
*ctx
,
701 const struct pipe_image_view
*view
,
702 bool skip_decompress
,
703 uint32_t *desc
, uint32_t *fmask_desc
)
705 struct si_screen
*screen
= ctx
->screen
;
706 struct si_resource
*res
;
708 res
= si_resource(view
->resource
);
710 if (res
->b
.b
.target
== PIPE_BUFFER
||
711 view
->shader_access
& SI_IMAGE_ACCESS_AS_BUFFER
) {
712 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
713 si_mark_image_range_valid(view
);
715 si_make_buffer_descriptor(screen
, res
,
718 view
->u
.buf
.size
, desc
);
719 si_set_buf_desc_address(res
, view
->u
.buf
.offset
, desc
+ 4);
721 static const unsigned char swizzle
[4] = { 0, 1, 2, 3 };
722 struct si_texture
*tex
= (struct si_texture
*)res
;
723 unsigned level
= view
->u
.tex
.level
;
724 unsigned width
, height
, depth
, hw_level
;
725 bool uses_dcc
= vi_dcc_enabled(tex
, level
);
726 unsigned access
= view
->access
;
728 assert(!tex
->is_depth
);
729 assert(fmask_desc
|| tex
->surface
.fmask_offset
== 0);
731 if (uses_dcc
&& !skip_decompress
&&
732 (access
& PIPE_IMAGE_ACCESS_WRITE
||
733 !vi_dcc_formats_compatible(screen
, res
->b
.b
.format
, view
->format
))) {
734 /* If DCC can't be disabled, at least decompress it.
735 * The decompression is relatively cheap if the surface
736 * has been decompressed already.
738 if (!si_texture_disable_dcc(ctx
, tex
))
739 si_decompress_dcc(ctx
, tex
);
742 if (ctx
->chip_class
>= GFX9
) {
743 /* Always set the base address. The swizzle modes don't
744 * allow setting mipmap level offsets as the base.
746 width
= res
->b
.b
.width0
;
747 height
= res
->b
.b
.height0
;
748 depth
= res
->b
.b
.depth0
;
751 /* Always force the base level to the selected level.
753 * This is required for 3D textures, where otherwise
754 * selecting a single slice for non-layered bindings
755 * fails. It doesn't hurt the other targets.
757 width
= u_minify(res
->b
.b
.width0
, level
);
758 height
= u_minify(res
->b
.b
.height0
, level
);
759 depth
= u_minify(res
->b
.b
.depth0
, level
);
763 screen
->make_texture_descriptor(screen
, tex
,
764 false, res
->b
.b
.target
,
765 view
->format
, swizzle
,
767 view
->u
.tex
.first_layer
,
768 view
->u
.tex
.last_layer
,
769 width
, height
, depth
,
771 si_set_mutable_tex_desc_fields(screen
, tex
,
772 &tex
->surface
.u
.legacy
.level
[level
],
774 util_format_get_blockwidth(view
->format
),
779 static void si_set_shader_image(struct si_context
*ctx
,
781 unsigned slot
, const struct pipe_image_view
*view
,
782 bool skip_decompress
)
784 struct si_images
*images
= &ctx
->images
[shader
];
785 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
786 struct si_resource
*res
;
788 if (!view
|| !view
->resource
) {
789 si_disable_shader_image(ctx
, shader
, slot
);
793 res
= si_resource(view
->resource
);
795 if (&images
->views
[slot
] != view
)
796 util_copy_image_view(&images
->views
[slot
], view
);
798 si_set_shader_image_desc(ctx
, view
, skip_decompress
,
799 descs
->list
+ si_get_image_slot(slot
) * 8,
800 descs
->list
+ si_get_image_slot(slot
+ SI_NUM_IMAGES
) * 8);
802 if (res
->b
.b
.target
== PIPE_BUFFER
||
803 view
->shader_access
& SI_IMAGE_ACCESS_AS_BUFFER
) {
804 images
->needs_color_decompress_mask
&= ~(1 << slot
);
805 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
807 struct si_texture
*tex
= (struct si_texture
*)res
;
808 unsigned level
= view
->u
.tex
.level
;
810 if (color_needs_decompression(tex
)) {
811 images
->needs_color_decompress_mask
|= 1 << slot
;
813 images
->needs_color_decompress_mask
&= ~(1 << slot
);
816 if (vi_dcc_enabled(tex
, level
) &&
817 p_atomic_read(&tex
->framebuffers_bound
))
818 ctx
->need_check_render_feedback
= true;
821 images
->enabled_mask
|= 1u << slot
;
822 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
824 /* Since this can flush, it must be done after enabled_mask is updated. */
825 si_sampler_view_add_buffer(ctx
, &res
->b
.b
,
826 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
) ?
827 RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
,
832 si_set_shader_images(struct pipe_context
*pipe
,
833 enum pipe_shader_type shader
,
834 unsigned start_slot
, unsigned count
,
835 const struct pipe_image_view
*views
)
837 struct si_context
*ctx
= (struct si_context
*)pipe
;
840 assert(shader
< SI_NUM_SHADERS
);
845 assert(start_slot
+ count
<= SI_NUM_IMAGES
);
848 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
849 si_set_shader_image(ctx
, shader
, slot
, &views
[i
], false);
851 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
852 si_set_shader_image(ctx
, shader
, slot
, NULL
, false);
855 si_update_shader_needs_decompress_mask(ctx
, shader
);
859 si_images_update_needs_color_decompress_mask(struct si_images
*images
)
861 unsigned mask
= images
->enabled_mask
;
864 int i
= u_bit_scan(&mask
);
865 struct pipe_resource
*res
= images
->views
[i
].resource
;
867 if (res
&& res
->target
!= PIPE_BUFFER
) {
868 struct si_texture
*tex
= (struct si_texture
*)res
;
870 if (color_needs_decompression(tex
)) {
871 images
->needs_color_decompress_mask
|= 1 << i
;
873 images
->needs_color_decompress_mask
&= ~(1 << i
);
879 void si_update_ps_colorbuf0_slot(struct si_context
*sctx
)
881 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
882 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
883 unsigned slot
= SI_PS_IMAGE_COLORBUF0
;
884 struct pipe_surface
*surf
= NULL
;
886 /* si_texture_disable_dcc can get us here again. */
887 if (sctx
->blitter
->running
)
890 /* See whether FBFETCH is used and color buffer 0 is set. */
891 if (sctx
->ps_shader
.cso
&&
892 sctx
->ps_shader
.cso
->info
.uses_fbfetch
&&
893 sctx
->framebuffer
.state
.nr_cbufs
&&
894 sctx
->framebuffer
.state
.cbufs
[0])
895 surf
= sctx
->framebuffer
.state
.cbufs
[0];
897 /* Return if FBFETCH transitions from disabled to disabled. */
898 if (!buffers
->buffers
[slot
] && !surf
)
901 sctx
->ps_uses_fbfetch
= surf
!= NULL
;
902 si_update_ps_iter_samples(sctx
);
905 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
906 struct pipe_image_view view
= {0};
909 assert(!tex
->is_depth
);
911 /* Disable DCC, because the texture is used as both a sampler
914 si_texture_disable_dcc(sctx
, tex
);
916 if (tex
->buffer
.b
.b
.nr_samples
<= 1 && tex
->cmask_buffer
) {
918 assert(tex
->cmask_buffer
!= &tex
->buffer
);
919 si_eliminate_fast_color_clear(sctx
, tex
);
920 si_texture_discard_cmask(sctx
->screen
, tex
);
923 view
.resource
= surf
->texture
;
924 view
.format
= surf
->format
;
925 view
.access
= PIPE_IMAGE_ACCESS_READ
;
926 view
.u
.tex
.first_layer
= surf
->u
.tex
.first_layer
;
927 view
.u
.tex
.last_layer
= surf
->u
.tex
.last_layer
;
928 view
.u
.tex
.level
= surf
->u
.tex
.level
;
930 /* Set the descriptor. */
931 uint32_t *desc
= descs
->list
+ slot
*4;
932 memset(desc
, 0, 16 * 4);
933 si_set_shader_image_desc(sctx
, &view
, true, desc
, desc
+ 8);
935 pipe_resource_reference(&buffers
->buffers
[slot
], &tex
->buffer
.b
.b
);
936 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
937 &tex
->buffer
, RADEON_USAGE_READ
,
938 RADEON_PRIO_SHADER_RW_IMAGE
);
939 buffers
->enabled_mask
|= 1u << slot
;
941 /* Clear the descriptor. */
942 memset(descs
->list
+ slot
*4, 0, 8*4);
943 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
944 buffers
->enabled_mask
&= ~(1u << slot
);
947 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
952 static void si_bind_sampler_states(struct pipe_context
*ctx
,
953 enum pipe_shader_type shader
,
954 unsigned start
, unsigned count
, void **states
)
956 struct si_context
*sctx
= (struct si_context
*)ctx
;
957 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
958 struct si_descriptors
*desc
= si_sampler_and_image_descriptors(sctx
, shader
);
959 struct si_sampler_state
**sstates
= (struct si_sampler_state
**)states
;
962 if (!count
|| shader
>= SI_NUM_SHADERS
|| !sstates
)
965 for (i
= 0; i
< count
; i
++) {
966 unsigned slot
= start
+ i
;
967 unsigned desc_slot
= si_get_sampler_slot(slot
);
970 sstates
[i
] == samplers
->sampler_states
[slot
])
974 assert(sstates
[i
]->magic
== SI_SAMPLER_STATE_MAGIC
);
976 samplers
->sampler_states
[slot
] = sstates
[i
];
978 /* If FMASK is bound, don't overwrite it.
979 * The sampler state will be set after FMASK is unbound.
981 struct si_sampler_view
*sview
=
982 (struct si_sampler_view
*)samplers
->views
[slot
];
984 struct si_texture
*tex
= NULL
;
986 if (sview
&& sview
->base
.texture
&&
987 sview
->base
.texture
->target
!= PIPE_BUFFER
)
988 tex
= (struct si_texture
*)sview
->base
.texture
;
990 if (tex
&& tex
->surface
.fmask_size
)
993 si_set_sampler_state_desc(sstates
[i
], sview
, tex
,
994 desc
->list
+ desc_slot
* 16 + 12);
996 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
1000 /* BUFFER RESOURCES */
1002 static void si_init_buffer_resources(struct si_buffer_resources
*buffers
,
1003 struct si_descriptors
*descs
,
1004 unsigned num_buffers
,
1005 short shader_userdata_rel_index
,
1006 enum radeon_bo_priority priority
,
1007 enum radeon_bo_priority priority_constbuf
)
1009 buffers
->priority
= priority
;
1010 buffers
->priority_constbuf
= priority_constbuf
;
1011 buffers
->buffers
= CALLOC(num_buffers
, sizeof(struct pipe_resource
*));
1012 buffers
->offsets
= CALLOC(num_buffers
, sizeof(buffers
->offsets
[0]));
1014 si_init_descriptors(descs
, shader_userdata_rel_index
, 4, num_buffers
);
1017 static void si_release_buffer_resources(struct si_buffer_resources
*buffers
,
1018 struct si_descriptors
*descs
)
1022 for (i
= 0; i
< descs
->num_elements
; i
++) {
1023 pipe_resource_reference(&buffers
->buffers
[i
], NULL
);
1026 FREE(buffers
->buffers
);
1027 FREE(buffers
->offsets
);
1030 static void si_buffer_resources_begin_new_cs(struct si_context
*sctx
,
1031 struct si_buffer_resources
*buffers
)
1033 unsigned mask
= buffers
->enabled_mask
;
1035 /* Add buffers to the CS. */
1037 int i
= u_bit_scan(&mask
);
1039 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1040 si_resource(buffers
->buffers
[i
]),
1041 buffers
->writable_mask
& (1u << i
) ? RADEON_USAGE_READWRITE
:
1043 i
< SI_NUM_SHADER_BUFFERS
? buffers
->priority
:
1044 buffers
->priority_constbuf
);
1048 static void si_get_buffer_from_descriptors(struct si_buffer_resources
*buffers
,
1049 struct si_descriptors
*descs
,
1050 unsigned idx
, struct pipe_resource
**buf
,
1051 unsigned *offset
, unsigned *size
)
1053 pipe_resource_reference(buf
, buffers
->buffers
[idx
]);
1055 struct si_resource
*res
= si_resource(*buf
);
1056 const uint32_t *desc
= descs
->list
+ idx
* 4;
1061 assert(G_008F04_STRIDE(desc
[1]) == 0);
1062 va
= si_desc_extract_buffer_address(desc
);
1064 assert(va
>= res
->gpu_address
&& va
+ *size
<= res
->gpu_address
+ res
->bo_size
);
1065 *offset
= va
- res
->gpu_address
;
1069 /* VERTEX BUFFERS */
1071 static void si_vertex_buffers_begin_new_cs(struct si_context
*sctx
)
1073 int count
= sctx
->num_vertex_elements
;
1076 for (i
= 0; i
< count
; i
++) {
1077 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1079 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1081 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1084 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1085 si_resource(sctx
->vertex_buffer
[vb
].buffer
.resource
),
1086 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1089 if (!sctx
->vb_descriptors_buffer
)
1091 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1092 sctx
->vb_descriptors_buffer
, RADEON_USAGE_READ
,
1093 RADEON_PRIO_DESCRIPTORS
);
1096 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
)
1098 unsigned i
, count
= sctx
->num_vertex_elements
;
1101 if (!sctx
->vertex_buffers_dirty
|| !count
)
1104 struct si_vertex_elements
*velems
= sctx
->vertex_elements
;
1105 unsigned alloc_size
= velems
->vb_desc_list_alloc_size
;
1108 /* Vertex buffer descriptors are the only ones which are uploaded
1109 * directly through a staging buffer and don't go through
1110 * the fine-grained upload path.
1112 u_upload_alloc(sctx
->b
.const_uploader
, 0,
1114 si_optimal_tcc_alignment(sctx
, alloc_size
),
1115 &sctx
->vb_descriptors_offset
,
1116 (struct pipe_resource
**)&sctx
->vb_descriptors_buffer
,
1118 if (!sctx
->vb_descriptors_buffer
) {
1119 sctx
->vb_descriptors_offset
= 0;
1120 sctx
->vb_descriptors_gpu_list
= NULL
;
1124 sctx
->vb_descriptors_gpu_list
= ptr
;
1125 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1126 sctx
->vb_descriptors_buffer
, RADEON_USAGE_READ
,
1127 RADEON_PRIO_DESCRIPTORS
);
1128 sctx
->vertex_buffer_pointer_dirty
= true;
1129 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VBO_DESCRIPTORS
;
1131 si_resource_reference(&sctx
->vb_descriptors_buffer
, NULL
);
1132 sctx
->vertex_buffer_pointer_dirty
= false;
1133 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_VBO_DESCRIPTORS
;
1136 assert(count
<= SI_MAX_ATTRIBS
);
1138 unsigned first_vb_use_mask
= velems
->first_vb_use_mask
;
1139 unsigned num_vbos_in_user_sgprs
= sctx
->screen
->num_vbos_in_user_sgprs
;
1141 for (i
= 0; i
< count
; i
++) {
1142 struct pipe_vertex_buffer
*vb
;
1143 struct si_resource
*buf
;
1144 unsigned vbo_index
= velems
->vertex_buffer_index
[i
];
1145 uint32_t *desc
= i
< num_vbos_in_user_sgprs
?
1146 &sctx
->vb_descriptor_user_sgprs
[i
* 4] :
1147 &ptr
[(i
- num_vbos_in_user_sgprs
) * 4];
1149 vb
= &sctx
->vertex_buffer
[vbo_index
];
1150 buf
= si_resource(vb
->buffer
.resource
);
1152 memset(desc
, 0, 16);
1156 int64_t offset
= (int64_t)((int)vb
->buffer_offset
) +
1157 velems
->src_offset
[i
];
1159 if (offset
>= buf
->b
.b
.width0
) {
1160 assert(offset
< buf
->b
.b
.width0
);
1161 memset(desc
, 0, 16);
1165 uint64_t va
= buf
->gpu_address
+ offset
;
1167 int64_t num_records
= (int64_t)buf
->b
.b
.width0
- offset
;
1168 if (sctx
->chip_class
!= GFX8
&& vb
->stride
) {
1169 /* Round up by rounding down and adding 1 */
1170 num_records
= (num_records
- velems
->format_size
[i
]) /
1173 assert(num_records
>= 0 && num_records
<= UINT_MAX
);
1175 uint32_t rsrc_word3
= velems
->rsrc_word3
[i
];
1177 /* OOB_SELECT chooses the out-of-bounds check:
1178 * - 1: index >= NUM_RECORDS (Structured)
1179 * - 3: offset >= NUM_RECORDS (Raw)
1181 if (sctx
->chip_class
>= GFX10
)
1182 rsrc_word3
|= S_008F0C_OOB_SELECT(vb
->stride
? V_008F0C_OOB_SELECT_STRUCTURED
: V_008F0C_OOB_SELECT_RAW
);
1185 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1186 S_008F04_STRIDE(vb
->stride
);
1187 desc
[2] = num_records
;
1188 desc
[3] = rsrc_word3
;
1190 if (first_vb_use_mask
& (1 << i
)) {
1191 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1192 si_resource(vb
->buffer
.resource
),
1193 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1197 /* Don't flush the const cache. It would have a very negative effect
1198 * on performance (confirmed by testing). New descriptors are always
1199 * uploaded to a fresh new buffer, so I don't think flushing the const
1200 * cache is needed. */
1201 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
1202 sctx
->vertex_buffer_user_sgprs_dirty
= num_vbos_in_user_sgprs
> 0;
1203 sctx
->vertex_buffers_dirty
= false;
1208 /* CONSTANT BUFFERS */
1210 static struct si_descriptors
*
1211 si_const_and_shader_buffer_descriptors(struct si_context
*sctx
, unsigned shader
)
1213 return &sctx
->descriptors
[si_const_and_shader_buffer_descriptors_idx(shader
)];
1216 void si_upload_const_buffer(struct si_context
*sctx
, struct si_resource
**buf
,
1217 const uint8_t *ptr
, unsigned size
, uint32_t *const_offset
)
1221 u_upload_alloc(sctx
->b
.const_uploader
, 0, size
,
1222 si_optimal_tcc_alignment(sctx
, size
),
1224 (struct pipe_resource
**)buf
, &tmp
);
1226 util_memcpy_cpu_to_le32(tmp
, ptr
, size
);
1229 static void si_set_constant_buffer(struct si_context
*sctx
,
1230 struct si_buffer_resources
*buffers
,
1231 unsigned descriptors_idx
,
1232 uint slot
, const struct pipe_constant_buffer
*input
)
1234 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1235 assert(slot
< descs
->num_elements
);
1236 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1238 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1239 * with a NULL buffer). We need to use a dummy buffer instead. */
1240 if (sctx
->chip_class
== GFX7
&&
1241 (!input
|| (!input
->buffer
&& !input
->user_buffer
)))
1242 input
= &sctx
->null_const_buf
;
1244 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
1245 struct pipe_resource
*buffer
= NULL
;
1247 unsigned buffer_offset
;
1249 /* Upload the user buffer if needed. */
1250 if (input
->user_buffer
) {
1251 si_upload_const_buffer(sctx
,
1252 (struct si_resource
**)&buffer
, input
->user_buffer
,
1253 input
->buffer_size
, &buffer_offset
);
1255 /* Just unbind on failure. */
1256 si_set_constant_buffer(sctx
, buffers
, descriptors_idx
, slot
, NULL
);
1260 pipe_resource_reference(&buffer
, input
->buffer
);
1261 buffer_offset
= input
->buffer_offset
;
1264 va
= si_resource(buffer
)->gpu_address
+ buffer_offset
;
1266 /* Set the descriptor. */
1267 uint32_t *desc
= descs
->list
+ slot
*4;
1269 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1271 desc
[2] = input
->buffer_size
;
1272 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1273 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1274 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1275 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
1277 if (sctx
->chip_class
>= GFX10
) {
1278 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
1279 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
1280 S_008F0C_RESOURCE_LEVEL(1);
1282 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1283 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1286 buffers
->buffers
[slot
] = buffer
;
1287 buffers
->offsets
[slot
] = buffer_offset
;
1288 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1289 si_resource(buffer
),
1291 buffers
->priority_constbuf
, true);
1292 buffers
->enabled_mask
|= 1u << slot
;
1294 /* Clear the descriptor. */
1295 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1296 buffers
->enabled_mask
&= ~(1u << slot
);
1299 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1302 static void si_pipe_set_constant_buffer(struct pipe_context
*ctx
,
1303 enum pipe_shader_type shader
, uint slot
,
1304 const struct pipe_constant_buffer
*input
)
1306 struct si_context
*sctx
= (struct si_context
*)ctx
;
1308 if (shader
>= SI_NUM_SHADERS
)
1311 if (slot
== 0 && input
&& input
->buffer
&&
1312 !(si_resource(input
->buffer
)->flags
& RADEON_FLAG_32BIT
)) {
1313 assert(!"constant buffer 0 must have a 32-bit VM address, use const_uploader");
1317 if (input
&& input
->buffer
)
1318 si_resource(input
->buffer
)->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
1320 slot
= si_get_constbuf_slot(slot
);
1321 si_set_constant_buffer(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1322 si_const_and_shader_buffer_descriptors_idx(shader
),
1326 void si_get_pipe_constant_buffer(struct si_context
*sctx
, uint shader
,
1327 uint slot
, struct pipe_constant_buffer
*cbuf
)
1329 cbuf
->user_buffer
= NULL
;
1330 si_get_buffer_from_descriptors(
1331 &sctx
->const_and_shader_buffers
[shader
],
1332 si_const_and_shader_buffer_descriptors(sctx
, shader
),
1333 si_get_constbuf_slot(slot
),
1334 &cbuf
->buffer
, &cbuf
->buffer_offset
, &cbuf
->buffer_size
);
1337 /* SHADER BUFFERS */
1339 static void si_set_shader_buffer(struct si_context
*sctx
,
1340 struct si_buffer_resources
*buffers
,
1341 unsigned descriptors_idx
,
1342 uint slot
, const struct pipe_shader_buffer
*sbuffer
,
1343 bool writable
, enum radeon_bo_priority priority
)
1345 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1346 uint32_t *desc
= descs
->list
+ slot
* 4;
1348 if (!sbuffer
|| !sbuffer
->buffer
) {
1349 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1350 memset(desc
, 0, sizeof(uint32_t) * 4);
1351 buffers
->enabled_mask
&= ~(1u << slot
);
1352 buffers
->writable_mask
&= ~(1u << slot
);
1353 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1357 struct si_resource
*buf
= si_resource(sbuffer
->buffer
);
1358 uint64_t va
= buf
->gpu_address
+ sbuffer
->buffer_offset
;
1361 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1363 desc
[2] = sbuffer
->buffer_size
;
1364 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1365 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1366 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1367 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
1369 if (sctx
->chip_class
>= GFX10
) {
1370 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
1371 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
1372 S_008F0C_RESOURCE_LEVEL(1);
1374 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1375 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1378 pipe_resource_reference(&buffers
->buffers
[slot
], &buf
->b
.b
);
1379 buffers
->offsets
[slot
] = sbuffer
->buffer_offset
;
1380 radeon_add_to_gfx_buffer_list_check_mem(sctx
, buf
,
1381 writable
? RADEON_USAGE_READWRITE
:
1385 buffers
->writable_mask
|= 1u << slot
;
1387 buffers
->writable_mask
&= ~(1u << slot
);
1389 buffers
->enabled_mask
|= 1u << slot
;
1390 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1392 util_range_add(&buf
->b
.b
, &buf
->valid_buffer_range
, sbuffer
->buffer_offset
,
1393 sbuffer
->buffer_offset
+ sbuffer
->buffer_size
);
1396 static void si_set_shader_buffers(struct pipe_context
*ctx
,
1397 enum pipe_shader_type shader
,
1398 unsigned start_slot
, unsigned count
,
1399 const struct pipe_shader_buffer
*sbuffers
,
1400 unsigned writable_bitmask
)
1402 struct si_context
*sctx
= (struct si_context
*)ctx
;
1403 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1404 unsigned descriptors_idx
= si_const_and_shader_buffer_descriptors_idx(shader
);
1407 assert(start_slot
+ count
<= SI_NUM_SHADER_BUFFERS
);
1409 for (i
= 0; i
< count
; ++i
) {
1410 const struct pipe_shader_buffer
*sbuffer
= sbuffers
? &sbuffers
[i
] : NULL
;
1411 unsigned slot
= si_get_shaderbuf_slot(start_slot
+ i
);
1413 if (sbuffer
&& sbuffer
->buffer
)
1414 si_resource(sbuffer
->buffer
)->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
1416 si_set_shader_buffer(sctx
, buffers
, descriptors_idx
, slot
, sbuffer
,
1417 !!(writable_bitmask
& (1u << i
)),
1422 void si_get_shader_buffers(struct si_context
*sctx
,
1423 enum pipe_shader_type shader
,
1424 uint start_slot
, uint count
,
1425 struct pipe_shader_buffer
*sbuf
)
1427 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1428 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1430 for (unsigned i
= 0; i
< count
; ++i
) {
1431 si_get_buffer_from_descriptors(
1433 si_get_shaderbuf_slot(start_slot
+ i
),
1434 &sbuf
[i
].buffer
, &sbuf
[i
].buffer_offset
,
1435 &sbuf
[i
].buffer_size
);
1441 void si_set_rw_buffer(struct si_context
*sctx
,
1442 uint slot
, const struct pipe_constant_buffer
*input
)
1444 si_set_constant_buffer(sctx
, &sctx
->rw_buffers
, SI_DESCS_RW_BUFFERS
,
1448 void si_set_rw_shader_buffer(struct si_context
*sctx
, uint slot
,
1449 const struct pipe_shader_buffer
*sbuffer
)
1451 si_set_shader_buffer(sctx
, &sctx
->rw_buffers
, SI_DESCS_RW_BUFFERS
,
1452 slot
, sbuffer
, true, RADEON_PRIO_SHADER_RW_BUFFER
);
1455 void si_set_ring_buffer(struct si_context
*sctx
, uint slot
,
1456 struct pipe_resource
*buffer
,
1457 unsigned stride
, unsigned num_records
,
1458 bool add_tid
, bool swizzle
,
1459 unsigned element_size
, unsigned index_stride
, uint64_t offset
)
1461 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1462 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1464 /* The stride field in the resource descriptor has 14 bits */
1465 assert(stride
< (1 << 14));
1467 assert(slot
< descs
->num_elements
);
1468 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1473 va
= si_resource(buffer
)->gpu_address
+ offset
;
1475 switch (element_size
) {
1477 assert(!"Unsupported ring buffer element size");
1493 switch (index_stride
) {
1495 assert(!"Unsupported ring buffer index stride");
1511 if (sctx
->chip_class
>= GFX8
&& stride
)
1512 num_records
*= stride
;
1514 /* Set the descriptor. */
1515 uint32_t *desc
= descs
->list
+ slot
*4;
1517 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1518 S_008F04_STRIDE(stride
) |
1519 S_008F04_SWIZZLE_ENABLE(swizzle
);
1520 desc
[2] = num_records
;
1521 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1522 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1523 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1524 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1525 S_008F0C_INDEX_STRIDE(index_stride
) |
1526 S_008F0C_ADD_TID_ENABLE(add_tid
);
1528 if (sctx
->chip_class
>= GFX9
)
1529 assert(!swizzle
|| element_size
== 1); /* always 4 bytes on GFX9 */
1531 desc
[3] |= S_008F0C_ELEMENT_SIZE(element_size
);
1533 if (sctx
->chip_class
>= GFX10
) {
1534 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
1535 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
1536 S_008F0C_RESOURCE_LEVEL(1);
1538 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1539 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1542 pipe_resource_reference(&buffers
->buffers
[slot
], buffer
);
1543 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1544 si_resource(buffer
),
1545 RADEON_USAGE_READWRITE
, buffers
->priority
);
1546 buffers
->enabled_mask
|= 1u << slot
;
1548 /* Clear the descriptor. */
1549 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1550 buffers
->enabled_mask
&= ~(1u << slot
);
1553 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1556 /* INTERNAL CONST BUFFERS */
1558 static void si_set_polygon_stipple(struct pipe_context
*ctx
,
1559 const struct pipe_poly_stipple
*state
)
1561 struct si_context
*sctx
= (struct si_context
*)ctx
;
1562 struct pipe_constant_buffer cb
= {};
1563 unsigned stipple
[32];
1566 for (i
= 0; i
< 32; i
++)
1567 stipple
[i
] = util_bitreverse(state
->stipple
[i
]);
1569 cb
.user_buffer
= stipple
;
1570 cb
.buffer_size
= sizeof(stipple
);
1572 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
, &cb
);
1575 /* TEXTURE METADATA ENABLE/DISABLE */
1578 si_resident_handles_update_needs_color_decompress(struct si_context
*sctx
)
1580 util_dynarray_clear(&sctx
->resident_tex_needs_color_decompress
);
1581 util_dynarray_clear(&sctx
->resident_img_needs_color_decompress
);
1583 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1584 struct si_texture_handle
*, tex_handle
) {
1585 struct pipe_resource
*res
= (*tex_handle
)->view
->texture
;
1586 struct si_texture
*tex
;
1588 if (!res
|| res
->target
== PIPE_BUFFER
)
1591 tex
= (struct si_texture
*)res
;
1592 if (!color_needs_decompression(tex
))
1595 util_dynarray_append(&sctx
->resident_tex_needs_color_decompress
,
1596 struct si_texture_handle
*, *tex_handle
);
1599 util_dynarray_foreach(&sctx
->resident_img_handles
,
1600 struct si_image_handle
*, img_handle
) {
1601 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1602 struct pipe_resource
*res
= view
->resource
;
1603 struct si_texture
*tex
;
1605 if (!res
|| res
->target
== PIPE_BUFFER
)
1608 tex
= (struct si_texture
*)res
;
1609 if (!color_needs_decompression(tex
))
1612 util_dynarray_append(&sctx
->resident_img_needs_color_decompress
,
1613 struct si_image_handle
*, *img_handle
);
1617 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1618 * while the texture is bound, possibly by a different context. In that case,
1619 * call this function to update needs_*_decompress_masks.
1621 void si_update_needs_color_decompress_masks(struct si_context
*sctx
)
1623 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
1624 si_samplers_update_needs_color_decompress_mask(&sctx
->samplers
[i
]);
1625 si_images_update_needs_color_decompress_mask(&sctx
->images
[i
]);
1626 si_update_shader_needs_decompress_mask(sctx
, i
);
1629 si_resident_handles_update_needs_color_decompress(sctx
);
1632 /* BUFFER DISCARD/INVALIDATION */
1634 /* Reset descriptors of buffer resources after \p buf has been invalidated.
1635 * If buf == NULL, reset all descriptors.
1637 static void si_reset_buffer_resources(struct si_context
*sctx
,
1638 struct si_buffer_resources
*buffers
,
1639 unsigned descriptors_idx
,
1641 struct pipe_resource
*buf
,
1642 enum radeon_bo_priority priority
)
1644 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1645 unsigned mask
= buffers
->enabled_mask
& slot_mask
;
1648 unsigned i
= u_bit_scan(&mask
);
1649 struct pipe_resource
*buffer
= buffers
->buffers
[i
];
1651 if (buffer
&& (!buf
|| buffer
== buf
)) {
1652 si_set_buf_desc_address(si_resource(buffer
), buffers
->offsets
[i
],
1654 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1656 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1657 si_resource(buffer
),
1658 buffers
->writable_mask
& (1u << i
) ?
1659 RADEON_USAGE_READWRITE
:
1666 /* Update all buffer bindings where the buffer is bound, including
1667 * all resource descriptors. This is invalidate_buffer without
1670 * If buf == NULL, update all buffer bindings.
1672 void si_rebind_buffer(struct si_context
*sctx
, struct pipe_resource
*buf
)
1674 struct si_resource
*buffer
= si_resource(buf
);
1676 unsigned num_elems
= sctx
->num_vertex_elements
;
1678 /* We changed the buffer, now we need to bind it where the old one
1679 * was bound. This consists of 2 things:
1680 * 1) Updating the resource descriptor and dirtying it.
1681 * 2) Adding a relocation to the CS, so that it's usable.
1684 /* Vertex buffers. */
1687 sctx
->vertex_buffers_dirty
= true;
1688 } else if (buffer
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
1689 for (i
= 0; i
< num_elems
; i
++) {
1690 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1692 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1694 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1697 if (sctx
->vertex_buffer
[vb
].buffer
.resource
== buf
) {
1698 sctx
->vertex_buffers_dirty
= true;
1704 /* Streamout buffers. (other internal buffers can't be invalidated) */
1705 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
1706 for (i
= SI_VS_STREAMOUT_BUF0
; i
<= SI_VS_STREAMOUT_BUF3
; i
++) {
1707 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1708 struct si_descriptors
*descs
=
1709 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1710 struct pipe_resource
*buffer
= buffers
->buffers
[i
];
1712 if (!buffer
|| (buf
&& buffer
!= buf
))
1715 si_set_buf_desc_address(si_resource(buffer
), buffers
->offsets
[i
],
1717 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1719 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1720 si_resource(buffer
),
1722 RADEON_PRIO_SHADER_RW_BUFFER
,
1725 /* Update the streamout state. */
1726 if (sctx
->streamout
.begin_emitted
)
1727 si_emit_streamout_end(sctx
);
1728 sctx
->streamout
.append_bitmask
=
1729 sctx
->streamout
.enabled_mask
;
1730 si_streamout_buffers_dirty(sctx
);
1734 /* Constant and shader buffers. */
1735 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1736 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1737 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1738 si_const_and_shader_buffer_descriptors_idx(shader
),
1739 u_bit_consecutive(SI_NUM_SHADER_BUFFERS
, SI_NUM_CONST_BUFFERS
),
1741 sctx
->const_and_shader_buffers
[shader
].priority_constbuf
);
1744 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
1745 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1746 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1747 si_const_and_shader_buffer_descriptors_idx(shader
),
1748 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS
),
1750 sctx
->const_and_shader_buffers
[shader
].priority
);
1753 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
1754 /* Texture buffers - update bindings. */
1755 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1756 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1757 struct si_descriptors
*descs
=
1758 si_sampler_and_image_descriptors(sctx
, shader
);
1759 unsigned mask
= samplers
->enabled_mask
;
1762 unsigned i
= u_bit_scan(&mask
);
1763 struct pipe_resource
*buffer
= samplers
->views
[i
]->texture
;
1765 if (buffer
&& buffer
->target
== PIPE_BUFFER
&&
1766 (!buf
|| buffer
== buf
)) {
1767 unsigned desc_slot
= si_get_sampler_slot(i
);
1769 si_set_buf_desc_address(si_resource(buffer
),
1770 samplers
->views
[i
]->u
.buf
.offset
,
1771 descs
->list
+ desc_slot
* 16 + 4);
1772 sctx
->descriptors_dirty
|=
1773 1u << si_sampler_and_image_descriptors_idx(shader
);
1775 radeon_add_to_gfx_buffer_list_check_mem(
1776 sctx
, si_resource(buffer
),
1778 RADEON_PRIO_SAMPLER_BUFFER
, true);
1785 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
1786 for (shader
= 0; shader
< SI_NUM_SHADERS
; ++shader
) {
1787 struct si_images
*images
= &sctx
->images
[shader
];
1788 struct si_descriptors
*descs
=
1789 si_sampler_and_image_descriptors(sctx
, shader
);
1790 unsigned mask
= images
->enabled_mask
;
1793 unsigned i
= u_bit_scan(&mask
);
1794 struct pipe_resource
*buffer
= images
->views
[i
].resource
;
1796 if (buffer
&& buffer
->target
== PIPE_BUFFER
&&
1797 (!buf
|| buffer
== buf
)) {
1798 unsigned desc_slot
= si_get_image_slot(i
);
1800 if (images
->views
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
)
1801 si_mark_image_range_valid(&images
->views
[i
]);
1803 si_set_buf_desc_address(si_resource(buffer
),
1804 images
->views
[i
].u
.buf
.offset
,
1805 descs
->list
+ desc_slot
* 8 + 4);
1806 sctx
->descriptors_dirty
|=
1807 1u << si_sampler_and_image_descriptors_idx(shader
);
1809 radeon_add_to_gfx_buffer_list_check_mem(
1810 sctx
, si_resource(buffer
),
1811 RADEON_USAGE_READWRITE
,
1812 RADEON_PRIO_SAMPLER_BUFFER
, true);
1818 /* Bindless texture handles */
1819 if (!buffer
|| buffer
->texture_handle_allocated
) {
1820 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1822 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1823 struct si_texture_handle
*, tex_handle
) {
1824 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
1825 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1826 struct pipe_resource
*buffer
= view
->texture
;
1828 if (buffer
&& buffer
->target
== PIPE_BUFFER
&&
1829 (!buf
|| buffer
== buf
)) {
1830 si_set_buf_desc_address(si_resource(buffer
),
1833 desc_slot
* 16 + 4);
1835 (*tex_handle
)->desc_dirty
= true;
1836 sctx
->bindless_descriptors_dirty
= true;
1838 radeon_add_to_gfx_buffer_list_check_mem(
1839 sctx
, si_resource(buffer
),
1841 RADEON_PRIO_SAMPLER_BUFFER
, true);
1846 /* Bindless image handles */
1847 if (!buffer
|| buffer
->image_handle_allocated
) {
1848 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1850 util_dynarray_foreach(&sctx
->resident_img_handles
,
1851 struct si_image_handle
*, img_handle
) {
1852 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1853 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1854 struct pipe_resource
*buffer
= view
->resource
;
1856 if (buffer
&& buffer
->target
== PIPE_BUFFER
&&
1857 (!buf
|| buffer
== buf
)) {
1858 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
1859 si_mark_image_range_valid(view
);
1861 si_set_buf_desc_address(si_resource(buffer
),
1864 desc_slot
* 16 + 4);
1866 (*img_handle
)->desc_dirty
= true;
1867 sctx
->bindless_descriptors_dirty
= true;
1869 radeon_add_to_gfx_buffer_list_check_mem(
1870 sctx
, si_resource(buffer
),
1871 RADEON_USAGE_READWRITE
,
1872 RADEON_PRIO_SAMPLER_BUFFER
, true);
1878 /* Do the same for other contexts. They will invoke this function
1879 * with buffer == NULL.
1881 unsigned new_counter
= p_atomic_inc_return(&sctx
->screen
->dirty_buf_counter
);
1883 /* Skip the update for the current context, because we have already updated
1884 * the buffer bindings.
1886 if (new_counter
== sctx
->last_dirty_buf_counter
+ 1)
1887 sctx
->last_dirty_buf_counter
= new_counter
;
1891 static void si_upload_bindless_descriptor(struct si_context
*sctx
,
1893 unsigned num_dwords
)
1895 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1896 unsigned desc_slot_offset
= desc_slot
* 16;
1900 data
= desc
->list
+ desc_slot_offset
;
1901 va
= desc
->gpu_address
+ desc_slot_offset
* 4;
1903 si_cp_write_data(sctx
, desc
->buffer
, va
- desc
->buffer
->gpu_address
,
1904 num_dwords
* 4, V_370_TC_L2
, V_370_ME
, data
);
1907 static void si_upload_bindless_descriptors(struct si_context
*sctx
)
1909 if (!sctx
->bindless_descriptors_dirty
)
1912 /* Wait for graphics/compute to be idle before updating the resident
1913 * descriptors directly in memory, in case the GPU is using them.
1915 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
1916 SI_CONTEXT_CS_PARTIAL_FLUSH
;
1917 sctx
->emit_cache_flush(sctx
);
1919 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1920 struct si_texture_handle
*, tex_handle
) {
1921 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1923 if (!(*tex_handle
)->desc_dirty
)
1926 si_upload_bindless_descriptor(sctx
, desc_slot
, 16);
1927 (*tex_handle
)->desc_dirty
= false;
1930 util_dynarray_foreach(&sctx
->resident_img_handles
,
1931 struct si_image_handle
*, img_handle
) {
1932 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1934 if (!(*img_handle
)->desc_dirty
)
1937 si_upload_bindless_descriptor(sctx
, desc_slot
, 8);
1938 (*img_handle
)->desc_dirty
= false;
1941 /* Invalidate L1 because it doesn't know that L2 changed. */
1942 sctx
->flags
|= SI_CONTEXT_INV_SCACHE
;
1943 sctx
->emit_cache_flush(sctx
);
1945 sctx
->bindless_descriptors_dirty
= false;
1948 /* Update mutable image descriptor fields of all resident textures. */
1949 static void si_update_bindless_texture_descriptor(struct si_context
*sctx
,
1950 struct si_texture_handle
*tex_handle
)
1952 struct si_sampler_view
*sview
= (struct si_sampler_view
*)tex_handle
->view
;
1953 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1954 unsigned desc_slot_offset
= tex_handle
->desc_slot
* 16;
1955 uint32_t desc_list
[16];
1957 if (sview
->base
.texture
->target
== PIPE_BUFFER
)
1960 memcpy(desc_list
, desc
->list
+ desc_slot_offset
, sizeof(desc_list
));
1961 si_set_sampler_view_desc(sctx
, sview
, &tex_handle
->sstate
,
1962 desc
->list
+ desc_slot_offset
);
1964 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1965 sizeof(desc_list
))) {
1966 tex_handle
->desc_dirty
= true;
1967 sctx
->bindless_descriptors_dirty
= true;
1971 static void si_update_bindless_image_descriptor(struct si_context
*sctx
,
1972 struct si_image_handle
*img_handle
)
1974 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1975 unsigned desc_slot_offset
= img_handle
->desc_slot
* 16;
1976 struct pipe_image_view
*view
= &img_handle
->view
;
1977 struct pipe_resource
*res
= view
->resource
;
1978 uint32_t image_desc
[16];
1979 unsigned desc_size
= (res
->nr_samples
>= 2 ? 16 : 8) * 4;
1981 if (res
->target
== PIPE_BUFFER
)
1984 memcpy(image_desc
, desc
->list
+ desc_slot_offset
, desc_size
);
1985 si_set_shader_image_desc(sctx
, view
, true,
1986 desc
->list
+ desc_slot_offset
,
1987 desc
->list
+ desc_slot_offset
+ 8);
1989 if (memcmp(image_desc
, desc
->list
+ desc_slot_offset
, desc_size
)) {
1990 img_handle
->desc_dirty
= true;
1991 sctx
->bindless_descriptors_dirty
= true;
1995 static void si_update_all_resident_texture_descriptors(struct si_context
*sctx
)
1997 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1998 struct si_texture_handle
*, tex_handle
) {
1999 si_update_bindless_texture_descriptor(sctx
, *tex_handle
);
2002 util_dynarray_foreach(&sctx
->resident_img_handles
,
2003 struct si_image_handle
*, img_handle
) {
2004 si_update_bindless_image_descriptor(sctx
, *img_handle
);
2007 si_upload_bindless_descriptors(sctx
);
2010 /* Update mutable image descriptor fields of all bound textures. */
2011 void si_update_all_texture_descriptors(struct si_context
*sctx
)
2015 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
2016 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
2017 struct si_images
*images
= &sctx
->images
[shader
];
2021 mask
= images
->enabled_mask
;
2023 unsigned i
= u_bit_scan(&mask
);
2024 struct pipe_image_view
*view
= &images
->views
[i
];
2026 if (!view
->resource
||
2027 view
->resource
->target
== PIPE_BUFFER
)
2030 si_set_shader_image(sctx
, shader
, i
, view
, true);
2033 /* Sampler views. */
2034 mask
= samplers
->enabled_mask
;
2036 unsigned i
= u_bit_scan(&mask
);
2037 struct pipe_sampler_view
*view
= samplers
->views
[i
];
2041 view
->texture
->target
== PIPE_BUFFER
)
2044 si_set_sampler_view(sctx
, shader
, i
,
2045 samplers
->views
[i
], true);
2048 si_update_shader_needs_decompress_mask(sctx
, shader
);
2051 si_update_all_resident_texture_descriptors(sctx
);
2052 si_update_ps_colorbuf0_slot(sctx
);
2055 /* SHADER USER DATA */
2057 static void si_mark_shader_pointers_dirty(struct si_context
*sctx
,
2060 sctx
->shader_pointers_dirty
|=
2061 u_bit_consecutive(SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
,
2062 SI_NUM_SHADER_DESCS
);
2064 if (shader
== PIPE_SHADER_VERTEX
) {
2065 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
2066 sctx
->vertex_buffer_user_sgprs_dirty
= sctx
->num_vertex_elements
> 0 &&
2067 sctx
->screen
->num_vbos_in_user_sgprs
;
2070 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
2073 static void si_shader_pointers_begin_new_cs(struct si_context
*sctx
)
2075 sctx
->shader_pointers_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2076 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
2077 sctx
->vertex_buffer_user_sgprs_dirty
= sctx
->num_vertex_elements
> 0 &&
2078 sctx
->screen
->num_vbos_in_user_sgprs
;
2079 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
2080 sctx
->graphics_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
2081 sctx
->compute_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
2084 /* Set a base register address for user data constants in the given shader.
2085 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
2087 static void si_set_user_data_base(struct si_context
*sctx
,
2088 unsigned shader
, uint32_t new_base
)
2090 uint32_t *base
= &sctx
->shader_pointers
.sh_base
[shader
];
2092 if (*base
!= new_base
) {
2096 si_mark_shader_pointers_dirty(sctx
, shader
);
2098 /* Any change in enabled shader stages requires re-emitting
2099 * the VS state SGPR, because it contains the clamp_vertex_color
2100 * state, which can be done in VS, TES, and GS.
2102 sctx
->last_vs_state
= ~0;
2106 /* This must be called when these are changed between enabled and disabled
2108 * - tessellation evaluation shader
2111 void si_shader_change_notify(struct si_context
*sctx
)
2113 /* VS can be bound as VS, ES, or LS. */
2114 if (sctx
->tes_shader
.cso
) {
2115 if (sctx
->chip_class
>= GFX10
) {
2116 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2117 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2118 } else if (sctx
->chip_class
== GFX9
) {
2119 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2120 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2122 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2123 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2125 } else if (sctx
->chip_class
>= GFX10
) {
2126 if (sctx
->ngg
|| sctx
->gs_shader
.cso
) {
2127 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2128 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2130 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2131 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2133 } else if (sctx
->gs_shader
.cso
) {
2134 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2135 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2137 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2138 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2141 /* TES can be bound as ES, VS, or not bound. */
2142 if (sctx
->tes_shader
.cso
) {
2143 if (sctx
->chip_class
>= GFX10
) {
2144 if (sctx
->ngg
|| sctx
->gs_shader
.cso
) {
2145 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
2146 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2148 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
2149 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2151 } else if (sctx
->gs_shader
.cso
) {
2152 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
2153 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2155 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
2156 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2159 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, 0);
2163 static void si_emit_shader_pointer_head(struct radeon_cmdbuf
*cs
,
2165 unsigned pointer_count
)
2167 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
, 0));
2168 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
2171 static void si_emit_shader_pointer_body(struct si_screen
*sscreen
,
2172 struct radeon_cmdbuf
*cs
,
2175 radeon_emit(cs
, va
);
2177 assert(va
== 0 || (va
>> 32) == sscreen
->info
.address32_hi
);
2180 static void si_emit_shader_pointer(struct si_context
*sctx
,
2181 struct si_descriptors
*desc
,
2184 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2185 unsigned sh_offset
= sh_base
+ desc
->shader_userdata_offset
;
2187 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2188 si_emit_shader_pointer_body(sctx
->screen
, cs
, desc
->gpu_address
);
2191 static void si_emit_consecutive_shader_pointers(struct si_context
*sctx
,
2192 unsigned pointer_mask
,
2198 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2199 unsigned mask
= sctx
->shader_pointers_dirty
& pointer_mask
;
2203 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
2205 struct si_descriptors
*descs
= &sctx
->descriptors
[start
];
2206 unsigned sh_offset
= sh_base
+ descs
->shader_userdata_offset
;
2208 si_emit_shader_pointer_head(cs
, sh_offset
, count
);
2209 for (int i
= 0; i
< count
; i
++)
2210 si_emit_shader_pointer_body(sctx
->screen
, cs
,
2211 descs
[i
].gpu_address
);
2215 static void si_emit_global_shader_pointers(struct si_context
*sctx
,
2216 struct si_descriptors
*descs
)
2218 if (sctx
->chip_class
>= GFX10
) {
2219 si_emit_shader_pointer(sctx
, descs
,
2220 R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2221 /* HW VS stage only used in non-NGG mode. */
2222 si_emit_shader_pointer(sctx
, descs
,
2223 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2224 si_emit_shader_pointer(sctx
, descs
,
2225 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2226 si_emit_shader_pointer(sctx
, descs
,
2227 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2229 } else if (sctx
->chip_class
== GFX9
) {
2230 /* Broadcast it to all shader stages. */
2231 si_emit_shader_pointer(sctx
, descs
,
2232 R_00B530_SPI_SHADER_USER_DATA_COMMON_0
);
2236 si_emit_shader_pointer(sctx
, descs
,
2237 R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2238 si_emit_shader_pointer(sctx
, descs
,
2239 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2240 si_emit_shader_pointer(sctx
, descs
,
2241 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2242 si_emit_shader_pointer(sctx
, descs
,
2243 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2244 si_emit_shader_pointer(sctx
, descs
,
2245 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2246 si_emit_shader_pointer(sctx
, descs
,
2247 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2250 void si_emit_graphics_shader_pointers(struct si_context
*sctx
)
2252 uint32_t *sh_base
= sctx
->shader_pointers
.sh_base
;
2254 if (sctx
->shader_pointers_dirty
& (1 << SI_DESCS_RW_BUFFERS
)) {
2255 si_emit_global_shader_pointers(sctx
,
2256 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2259 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(VERTEX
),
2260 sh_base
[PIPE_SHADER_VERTEX
]);
2261 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_EVAL
),
2262 sh_base
[PIPE_SHADER_TESS_EVAL
]);
2263 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(FRAGMENT
),
2264 sh_base
[PIPE_SHADER_FRAGMENT
]);
2265 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_CTRL
),
2266 sh_base
[PIPE_SHADER_TESS_CTRL
]);
2267 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(GEOMETRY
),
2268 sh_base
[PIPE_SHADER_GEOMETRY
]);
2270 sctx
->shader_pointers_dirty
&=
2271 ~u_bit_consecutive(SI_DESCS_RW_BUFFERS
, SI_DESCS_FIRST_COMPUTE
);
2273 if (sctx
->vertex_buffer_pointer_dirty
&& sctx
->num_vertex_elements
) {
2274 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2276 /* Find the location of the VB descriptor pointer. */
2277 unsigned sh_dw_offset
= SI_VS_NUM_USER_SGPR
;
2278 if (sctx
->chip_class
>= GFX9
) {
2279 if (sctx
->tes_shader
.cso
)
2280 sh_dw_offset
= GFX9_TCS_NUM_USER_SGPR
;
2281 else if (sctx
->gs_shader
.cso
)
2282 sh_dw_offset
= GFX9_VSGS_NUM_USER_SGPR
;
2285 unsigned sh_offset
= sh_base
[PIPE_SHADER_VERTEX
] + sh_dw_offset
* 4;
2286 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2287 si_emit_shader_pointer_body(sctx
->screen
, cs
,
2288 sctx
->vb_descriptors_buffer
->gpu_address
+
2289 sctx
->vb_descriptors_offset
);
2290 sctx
->vertex_buffer_pointer_dirty
= false;
2293 if (sctx
->vertex_buffer_user_sgprs_dirty
&&
2294 sctx
->num_vertex_elements
&&
2295 sctx
->screen
->num_vbos_in_user_sgprs
) {
2296 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2297 unsigned num_desc
= MIN2(sctx
->num_vertex_elements
,
2298 sctx
->screen
->num_vbos_in_user_sgprs
);
2299 unsigned sh_offset
= sh_base
[PIPE_SHADER_VERTEX
] + SI_SGPR_VS_VB_DESCRIPTOR_FIRST
* 4;
2301 si_emit_shader_pointer_head(cs
, sh_offset
, num_desc
* 4);
2302 radeon_emit_array(cs
, sctx
->vb_descriptor_user_sgprs
, num_desc
* 4);
2303 sctx
->vertex_buffer_user_sgprs_dirty
= false;
2306 if (sctx
->graphics_bindless_pointer_dirty
) {
2307 si_emit_global_shader_pointers(sctx
,
2308 &sctx
->bindless_descriptors
);
2309 sctx
->graphics_bindless_pointer_dirty
= false;
2313 void si_emit_compute_shader_pointers(struct si_context
*sctx
)
2315 unsigned base
= R_00B900_COMPUTE_USER_DATA_0
;
2317 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(COMPUTE
),
2318 R_00B900_COMPUTE_USER_DATA_0
);
2319 sctx
->shader_pointers_dirty
&= ~SI_DESCS_SHADER_MASK(COMPUTE
);
2321 if (sctx
->compute_bindless_pointer_dirty
) {
2322 si_emit_shader_pointer(sctx
, &sctx
->bindless_descriptors
, base
);
2323 sctx
->compute_bindless_pointer_dirty
= false;
2329 static void si_init_bindless_descriptors(struct si_context
*sctx
,
2330 struct si_descriptors
*desc
,
2331 short shader_userdata_rel_index
,
2332 unsigned num_elements
)
2334 ASSERTED
unsigned desc_slot
;
2336 si_init_descriptors(desc
, shader_userdata_rel_index
, 16, num_elements
);
2337 sctx
->bindless_descriptors
.num_active_slots
= num_elements
;
2339 /* The first bindless descriptor is stored at slot 1, because 0 is not
2340 * considered to be a valid handle.
2342 sctx
->num_bindless_descriptors
= 1;
2344 /* Track which bindless slots are used (or not). */
2345 util_idalloc_init(&sctx
->bindless_used_slots
);
2346 util_idalloc_resize(&sctx
->bindless_used_slots
, num_elements
);
2348 /* Reserve slot 0 because it's an invalid handle for bindless. */
2349 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2350 assert(desc_slot
== 0);
2353 static void si_release_bindless_descriptors(struct si_context
*sctx
)
2355 si_release_descriptors(&sctx
->bindless_descriptors
);
2356 util_idalloc_fini(&sctx
->bindless_used_slots
);
2359 static unsigned si_get_first_free_bindless_slot(struct si_context
*sctx
)
2361 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2364 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2365 if (desc_slot
>= desc
->num_elements
) {
2366 /* The array of bindless descriptors is full, resize it. */
2367 unsigned slot_size
= desc
->element_dw_size
* 4;
2368 unsigned new_num_elements
= desc
->num_elements
* 2;
2370 desc
->list
= REALLOC(desc
->list
, desc
->num_elements
* slot_size
,
2371 new_num_elements
* slot_size
);
2372 desc
->num_elements
= new_num_elements
;
2373 desc
->num_active_slots
= new_num_elements
;
2381 si_create_bindless_descriptor(struct si_context
*sctx
, uint32_t *desc_list
,
2384 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2385 unsigned desc_slot
, desc_slot_offset
;
2387 /* Find a free slot. */
2388 desc_slot
= si_get_first_free_bindless_slot(sctx
);
2390 /* For simplicity, sampler and image bindless descriptors use fixed
2391 * 16-dword slots for now. Image descriptors only need 8-dword but this
2392 * doesn't really matter because no real apps use image handles.
2394 desc_slot_offset
= desc_slot
* 16;
2396 /* Copy the descriptor into the array. */
2397 memcpy(desc
->list
+ desc_slot_offset
, desc_list
, size
);
2399 /* Re-upload the whole array of bindless descriptors into a new buffer.
2401 if (!si_upload_descriptors(sctx
, desc
))
2404 /* Make sure to re-emit the shader pointers for all stages. */
2405 sctx
->graphics_bindless_pointer_dirty
= true;
2406 sctx
->compute_bindless_pointer_dirty
= true;
2411 static void si_update_bindless_buffer_descriptor(struct si_context
*sctx
,
2413 struct pipe_resource
*resource
,
2417 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2418 struct si_resource
*buf
= si_resource(resource
);
2419 unsigned desc_slot_offset
= desc_slot
* 16;
2420 uint32_t *desc_list
= desc
->list
+ desc_slot_offset
+ 4;
2421 uint64_t old_desc_va
;
2423 assert(resource
->target
== PIPE_BUFFER
);
2425 /* Retrieve the old buffer addr from the descriptor. */
2426 old_desc_va
= si_desc_extract_buffer_address(desc_list
);
2428 if (old_desc_va
!= buf
->gpu_address
+ offset
) {
2429 /* The buffer has been invalidated when the handle wasn't
2430 * resident, update the descriptor and the dirty flag.
2432 si_set_buf_desc_address(buf
, offset
, &desc_list
[0]);
2438 static uint64_t si_create_texture_handle(struct pipe_context
*ctx
,
2439 struct pipe_sampler_view
*view
,
2440 const struct pipe_sampler_state
*state
)
2442 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
2443 struct si_context
*sctx
= (struct si_context
*)ctx
;
2444 struct si_texture_handle
*tex_handle
;
2445 struct si_sampler_state
*sstate
;
2446 uint32_t desc_list
[16];
2449 tex_handle
= CALLOC_STRUCT(si_texture_handle
);
2453 memset(desc_list
, 0, sizeof(desc_list
));
2454 si_init_descriptor_list(&desc_list
[0], 16, 1, null_texture_descriptor
);
2456 sstate
= ctx
->create_sampler_state(ctx
, state
);
2462 si_set_sampler_view_desc(sctx
, sview
, sstate
, &desc_list
[0]);
2463 memcpy(&tex_handle
->sstate
, sstate
, sizeof(*sstate
));
2464 ctx
->delete_sampler_state(ctx
, sstate
);
2466 tex_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2468 if (!tex_handle
->desc_slot
) {
2473 handle
= tex_handle
->desc_slot
;
2475 if (!_mesa_hash_table_insert(sctx
->tex_handles
,
2476 (void *)(uintptr_t)handle
,
2482 pipe_sampler_view_reference(&tex_handle
->view
, view
);
2484 si_resource(sview
->base
.texture
)->texture_handle_allocated
= true;
2489 static void si_delete_texture_handle(struct pipe_context
*ctx
, uint64_t handle
)
2491 struct si_context
*sctx
= (struct si_context
*)ctx
;
2492 struct si_texture_handle
*tex_handle
;
2493 struct hash_entry
*entry
;
2495 entry
= _mesa_hash_table_search(sctx
->tex_handles
,
2496 (void *)(uintptr_t)handle
);
2500 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2502 /* Allow this descriptor slot to be re-used. */
2503 util_idalloc_free(&sctx
->bindless_used_slots
, tex_handle
->desc_slot
);
2505 pipe_sampler_view_reference(&tex_handle
->view
, NULL
);
2506 _mesa_hash_table_remove(sctx
->tex_handles
, entry
);
2510 static void si_make_texture_handle_resident(struct pipe_context
*ctx
,
2511 uint64_t handle
, bool resident
)
2513 struct si_context
*sctx
= (struct si_context
*)ctx
;
2514 struct si_texture_handle
*tex_handle
;
2515 struct si_sampler_view
*sview
;
2516 struct hash_entry
*entry
;
2518 entry
= _mesa_hash_table_search(sctx
->tex_handles
,
2519 (void *)(uintptr_t)handle
);
2523 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2524 sview
= (struct si_sampler_view
*)tex_handle
->view
;
2527 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2528 struct si_texture
*tex
=
2529 (struct si_texture
*)sview
->base
.texture
;
2531 if (depth_needs_decompression(tex
)) {
2532 util_dynarray_append(
2533 &sctx
->resident_tex_needs_depth_decompress
,
2534 struct si_texture_handle
*,
2538 if (color_needs_decompression(tex
)) {
2539 util_dynarray_append(
2540 &sctx
->resident_tex_needs_color_decompress
,
2541 struct si_texture_handle
*,
2545 if (tex
->surface
.dcc_offset
&&
2546 p_atomic_read(&tex
->framebuffers_bound
))
2547 sctx
->need_check_render_feedback
= true;
2549 si_update_bindless_texture_descriptor(sctx
, tex_handle
);
2551 si_update_bindless_buffer_descriptor(sctx
,
2552 tex_handle
->desc_slot
,
2553 sview
->base
.texture
,
2554 sview
->base
.u
.buf
.offset
,
2555 &tex_handle
->desc_dirty
);
2558 /* Re-upload the descriptor if it has been updated while it
2561 if (tex_handle
->desc_dirty
)
2562 sctx
->bindless_descriptors_dirty
= true;
2564 /* Add the texture handle to the per-context list. */
2565 util_dynarray_append(&sctx
->resident_tex_handles
,
2566 struct si_texture_handle
*, tex_handle
);
2568 /* Add the buffers to the current CS in case si_begin_new_cs()
2569 * is not going to be called.
2571 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2573 sview
->is_stencil_sampler
, false);
2575 /* Remove the texture handle from the per-context list. */
2576 util_dynarray_delete_unordered(&sctx
->resident_tex_handles
,
2577 struct si_texture_handle
*,
2580 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2581 util_dynarray_delete_unordered(
2582 &sctx
->resident_tex_needs_depth_decompress
,
2583 struct si_texture_handle
*, tex_handle
);
2585 util_dynarray_delete_unordered(
2586 &sctx
->resident_tex_needs_color_decompress
,
2587 struct si_texture_handle
*, tex_handle
);
2592 static uint64_t si_create_image_handle(struct pipe_context
*ctx
,
2593 const struct pipe_image_view
*view
)
2595 struct si_context
*sctx
= (struct si_context
*)ctx
;
2596 struct si_image_handle
*img_handle
;
2597 uint32_t desc_list
[16];
2600 if (!view
|| !view
->resource
)
2603 img_handle
= CALLOC_STRUCT(si_image_handle
);
2607 memset(desc_list
, 0, sizeof(desc_list
));
2608 si_init_descriptor_list(&desc_list
[0], 8, 2, null_image_descriptor
);
2610 si_set_shader_image_desc(sctx
, view
, false, &desc_list
[0], &desc_list
[8]);
2612 img_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2614 if (!img_handle
->desc_slot
) {
2619 handle
= img_handle
->desc_slot
;
2621 if (!_mesa_hash_table_insert(sctx
->img_handles
,
2622 (void *)(uintptr_t)handle
,
2628 util_copy_image_view(&img_handle
->view
, view
);
2630 si_resource(view
->resource
)->image_handle_allocated
= true;
2635 static void si_delete_image_handle(struct pipe_context
*ctx
, uint64_t handle
)
2637 struct si_context
*sctx
= (struct si_context
*)ctx
;
2638 struct si_image_handle
*img_handle
;
2639 struct hash_entry
*entry
;
2641 entry
= _mesa_hash_table_search(sctx
->img_handles
,
2642 (void *)(uintptr_t)handle
);
2646 img_handle
= (struct si_image_handle
*)entry
->data
;
2648 util_copy_image_view(&img_handle
->view
, NULL
);
2649 _mesa_hash_table_remove(sctx
->img_handles
, entry
);
2653 static void si_make_image_handle_resident(struct pipe_context
*ctx
,
2654 uint64_t handle
, unsigned access
,
2657 struct si_context
*sctx
= (struct si_context
*)ctx
;
2658 struct si_image_handle
*img_handle
;
2659 struct pipe_image_view
*view
;
2660 struct si_resource
*res
;
2661 struct hash_entry
*entry
;
2663 entry
= _mesa_hash_table_search(sctx
->img_handles
,
2664 (void *)(uintptr_t)handle
);
2668 img_handle
= (struct si_image_handle
*)entry
->data
;
2669 view
= &img_handle
->view
;
2670 res
= si_resource(view
->resource
);
2673 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2674 struct si_texture
*tex
= (struct si_texture
*)res
;
2675 unsigned level
= view
->u
.tex
.level
;
2677 if (color_needs_decompression(tex
)) {
2678 util_dynarray_append(
2679 &sctx
->resident_img_needs_color_decompress
,
2680 struct si_image_handle
*,
2684 if (vi_dcc_enabled(tex
, level
) &&
2685 p_atomic_read(&tex
->framebuffers_bound
))
2686 sctx
->need_check_render_feedback
= true;
2688 si_update_bindless_image_descriptor(sctx
, img_handle
);
2690 si_update_bindless_buffer_descriptor(sctx
,
2691 img_handle
->desc_slot
,
2694 &img_handle
->desc_dirty
);
2697 /* Re-upload the descriptor if it has been updated while it
2700 if (img_handle
->desc_dirty
)
2701 sctx
->bindless_descriptors_dirty
= true;
2703 /* Add the image handle to the per-context list. */
2704 util_dynarray_append(&sctx
->resident_img_handles
,
2705 struct si_image_handle
*, img_handle
);
2707 /* Add the buffers to the current CS in case si_begin_new_cs()
2708 * is not going to be called.
2710 si_sampler_view_add_buffer(sctx
, view
->resource
,
2711 (access
& PIPE_IMAGE_ACCESS_WRITE
) ?
2712 RADEON_USAGE_READWRITE
:
2713 RADEON_USAGE_READ
, false, false);
2715 /* Remove the image handle from the per-context list. */
2716 util_dynarray_delete_unordered(&sctx
->resident_img_handles
,
2717 struct si_image_handle
*,
2720 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2721 util_dynarray_delete_unordered(
2722 &sctx
->resident_img_needs_color_decompress
,
2723 struct si_image_handle
*,
2729 static void si_resident_buffers_add_all_to_bo_list(struct si_context
*sctx
)
2731 unsigned num_resident_tex_handles
, num_resident_img_handles
;
2733 num_resident_tex_handles
= sctx
->resident_tex_handles
.size
/
2734 sizeof(struct si_texture_handle
*);
2735 num_resident_img_handles
= sctx
->resident_img_handles
.size
/
2736 sizeof(struct si_image_handle
*);
2738 /* Add all resident texture handles. */
2739 util_dynarray_foreach(&sctx
->resident_tex_handles
,
2740 struct si_texture_handle
*, tex_handle
) {
2741 struct si_sampler_view
*sview
=
2742 (struct si_sampler_view
*)(*tex_handle
)->view
;
2744 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2746 sview
->is_stencil_sampler
, false);
2749 /* Add all resident image handles. */
2750 util_dynarray_foreach(&sctx
->resident_img_handles
,
2751 struct si_image_handle
*, img_handle
) {
2752 struct pipe_image_view
*view
= &(*img_handle
)->view
;
2754 si_sampler_view_add_buffer(sctx
, view
->resource
,
2755 RADEON_USAGE_READWRITE
,
2759 sctx
->num_resident_handles
+= num_resident_tex_handles
+
2760 num_resident_img_handles
;
2761 assert(sctx
->bo_list_add_all_resident_resources
);
2762 sctx
->bo_list_add_all_resident_resources
= false;
2765 /* INIT/DEINIT/UPLOAD */
2767 void si_init_all_descriptors(struct si_context
*sctx
)
2770 unsigned first_shader
=
2771 sctx
->has_graphics
? 0 : PIPE_SHADER_COMPUTE
;
2773 for (i
= first_shader
; i
< SI_NUM_SHADERS
; i
++) {
2774 bool is_2nd
= sctx
->chip_class
>= GFX9
&&
2775 (i
== PIPE_SHADER_TESS_CTRL
||
2776 i
== PIPE_SHADER_GEOMETRY
);
2777 unsigned num_sampler_slots
= SI_NUM_IMAGE_SLOTS
/ 2 + SI_NUM_SAMPLERS
;
2778 unsigned num_buffer_slots
= SI_NUM_SHADER_BUFFERS
+ SI_NUM_CONST_BUFFERS
;
2780 struct si_descriptors
*desc
;
2783 if (i
== PIPE_SHADER_TESS_CTRL
) {
2784 rel_dw_offset
= (R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
-
2785 R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2786 } else if (sctx
->chip_class
>= GFX10
) { /* PIPE_SHADER_GEOMETRY */
2787 rel_dw_offset
= (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
-
2788 R_00B230_SPI_SHADER_USER_DATA_GS_0
) / 4;
2790 rel_dw_offset
= (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
-
2791 R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2794 rel_dw_offset
= SI_SGPR_CONST_AND_SHADER_BUFFERS
;
2796 desc
= si_const_and_shader_buffer_descriptors(sctx
, i
);
2797 si_init_buffer_resources(&sctx
->const_and_shader_buffers
[i
], desc
,
2798 num_buffer_slots
, rel_dw_offset
,
2799 RADEON_PRIO_SHADER_RW_BUFFER
,
2800 RADEON_PRIO_CONST_BUFFER
);
2801 desc
->slot_index_to_bind_directly
= si_get_constbuf_slot(0);
2804 if (i
== PIPE_SHADER_TESS_CTRL
) {
2805 rel_dw_offset
= (R_00B40C_SPI_SHADER_USER_DATA_ADDR_HI_HS
-
2806 R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2807 } else if (sctx
->chip_class
>= GFX10
) { /* PIPE_SHADER_GEOMETRY */
2808 rel_dw_offset
= (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS
-
2809 R_00B230_SPI_SHADER_USER_DATA_GS_0
) / 4;
2811 rel_dw_offset
= (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS
-
2812 R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2815 rel_dw_offset
= SI_SGPR_SAMPLERS_AND_IMAGES
;
2818 desc
= si_sampler_and_image_descriptors(sctx
, i
);
2819 si_init_descriptors(desc
, rel_dw_offset
, 16, num_sampler_slots
);
2822 for (j
= 0; j
< SI_NUM_IMAGE_SLOTS
; j
++)
2823 memcpy(desc
->list
+ j
* 8, null_image_descriptor
, 8 * 4);
2824 for (; j
< SI_NUM_IMAGE_SLOTS
+ SI_NUM_SAMPLERS
* 2; j
++)
2825 memcpy(desc
->list
+ j
* 8, null_texture_descriptor
, 8 * 4);
2828 si_init_buffer_resources(&sctx
->rw_buffers
,
2829 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
],
2830 SI_NUM_RW_BUFFERS
, SI_SGPR_RW_BUFFERS
,
2831 /* The second priority is used by
2832 * const buffers in RW buffer slots. */
2833 RADEON_PRIO_SHADER_RINGS
, RADEON_PRIO_CONST_BUFFER
);
2834 sctx
->descriptors
[SI_DESCS_RW_BUFFERS
].num_active_slots
= SI_NUM_RW_BUFFERS
;
2836 /* Initialize an array of 1024 bindless descriptors, when the limit is
2837 * reached, just make it larger and re-upload the whole array.
2839 si_init_bindless_descriptors(sctx
, &sctx
->bindless_descriptors
,
2840 SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES
,
2843 sctx
->descriptors_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2845 /* Set pipe_context functions. */
2846 sctx
->b
.bind_sampler_states
= si_bind_sampler_states
;
2847 sctx
->b
.set_shader_images
= si_set_shader_images
;
2848 sctx
->b
.set_constant_buffer
= si_pipe_set_constant_buffer
;
2849 sctx
->b
.set_shader_buffers
= si_set_shader_buffers
;
2850 sctx
->b
.set_sampler_views
= si_set_sampler_views
;
2851 sctx
->b
.create_texture_handle
= si_create_texture_handle
;
2852 sctx
->b
.delete_texture_handle
= si_delete_texture_handle
;
2853 sctx
->b
.make_texture_handle_resident
= si_make_texture_handle_resident
;
2854 sctx
->b
.create_image_handle
= si_create_image_handle
;
2855 sctx
->b
.delete_image_handle
= si_delete_image_handle
;
2856 sctx
->b
.make_image_handle_resident
= si_make_image_handle_resident
;
2858 if (!sctx
->has_graphics
)
2861 sctx
->b
.set_polygon_stipple
= si_set_polygon_stipple
;
2863 /* Shader user data. */
2864 sctx
->atoms
.s
.shader_pointers
.emit
= si_emit_graphics_shader_pointers
;
2866 /* Set default and immutable mappings. */
2868 assert(sctx
->chip_class
>= GFX10
);
2869 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2871 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2874 if (sctx
->chip_class
== GFX9
) {
2875 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2876 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2877 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2878 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2880 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2881 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2882 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2883 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2885 si_set_user_data_base(sctx
, PIPE_SHADER_FRAGMENT
, R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2888 static bool si_upload_shader_descriptors(struct si_context
*sctx
, unsigned mask
)
2890 unsigned dirty
= sctx
->descriptors_dirty
& mask
;
2892 /* Assume nothing will go wrong: */
2893 sctx
->shader_pointers_dirty
|= dirty
;
2896 unsigned i
= u_bit_scan(&dirty
);
2898 if (!si_upload_descriptors(sctx
, &sctx
->descriptors
[i
]))
2902 sctx
->descriptors_dirty
&= ~mask
;
2904 si_upload_bindless_descriptors(sctx
);
2909 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
)
2911 const unsigned mask
= u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE
);
2912 return si_upload_shader_descriptors(sctx
, mask
);
2915 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
)
2917 /* Does not update rw_buffers as that is not needed for compute shaders
2918 * and the input buffer is using the same SGPR's anyway.
2920 const unsigned mask
= u_bit_consecutive(SI_DESCS_FIRST_COMPUTE
,
2921 SI_NUM_DESCS
- SI_DESCS_FIRST_COMPUTE
);
2922 return si_upload_shader_descriptors(sctx
, mask
);
2925 void si_release_all_descriptors(struct si_context
*sctx
)
2929 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2930 si_release_buffer_resources(&sctx
->const_and_shader_buffers
[i
],
2931 si_const_and_shader_buffer_descriptors(sctx
, i
));
2932 si_release_sampler_views(&sctx
->samplers
[i
]);
2933 si_release_image_views(&sctx
->images
[i
]);
2935 si_release_buffer_resources(&sctx
->rw_buffers
,
2936 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2937 for (i
= 0; i
< SI_NUM_VERTEX_BUFFERS
; i
++)
2938 pipe_vertex_buffer_unreference(&sctx
->vertex_buffer
[i
]);
2940 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2941 si_release_descriptors(&sctx
->descriptors
[i
]);
2943 si_resource_reference(&sctx
->vb_descriptors_buffer
, NULL
);
2944 sctx
->vb_descriptors_gpu_list
= NULL
; /* points into a mapped buffer */
2946 si_release_bindless_descriptors(sctx
);
2949 void si_gfx_resources_add_all_to_bo_list(struct si_context
*sctx
)
2951 for (unsigned i
= 0; i
< SI_NUM_GRAPHICS_SHADERS
; i
++) {
2952 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[i
]);
2953 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[i
]);
2954 si_image_views_begin_new_cs(sctx
, &sctx
->images
[i
]);
2956 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2957 si_vertex_buffers_begin_new_cs(sctx
);
2959 if (sctx
->bo_list_add_all_resident_resources
)
2960 si_resident_buffers_add_all_to_bo_list(sctx
);
2962 assert(sctx
->bo_list_add_all_gfx_resources
);
2963 sctx
->bo_list_add_all_gfx_resources
= false;
2966 void si_compute_resources_add_all_to_bo_list(struct si_context
*sctx
)
2968 unsigned sh
= PIPE_SHADER_COMPUTE
;
2970 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[sh
]);
2971 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[sh
]);
2972 si_image_views_begin_new_cs(sctx
, &sctx
->images
[sh
]);
2973 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2975 if (sctx
->bo_list_add_all_resident_resources
)
2976 si_resident_buffers_add_all_to_bo_list(sctx
);
2978 assert(sctx
->bo_list_add_all_compute_resources
);
2979 sctx
->bo_list_add_all_compute_resources
= false;
2982 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
)
2984 for (unsigned i
= 0; i
< SI_NUM_DESCS
; ++i
)
2985 si_descriptors_begin_new_cs(sctx
, &sctx
->descriptors
[i
]);
2986 si_descriptors_begin_new_cs(sctx
, &sctx
->bindless_descriptors
);
2988 si_shader_pointers_begin_new_cs(sctx
);
2990 sctx
->bo_list_add_all_resident_resources
= true;
2991 sctx
->bo_list_add_all_gfx_resources
= true;
2992 sctx
->bo_list_add_all_compute_resources
= true;
2995 void si_set_active_descriptors(struct si_context
*sctx
, unsigned desc_idx
,
2996 uint64_t new_active_mask
)
2998 struct si_descriptors
*desc
= &sctx
->descriptors
[desc_idx
];
3000 /* Ignore no-op updates and updates that disable all slots. */
3001 if (!new_active_mask
||
3002 new_active_mask
== u_bit_consecutive64(desc
->first_active_slot
,
3003 desc
->num_active_slots
))
3007 u_bit_scan_consecutive_range64(&new_active_mask
, &first
, &count
);
3008 assert(new_active_mask
== 0);
3010 /* Upload/dump descriptors if slots are being enabled. */
3011 if (first
< desc
->first_active_slot
||
3012 first
+ count
> desc
->first_active_slot
+ desc
->num_active_slots
)
3013 sctx
->descriptors_dirty
|= 1u << desc_idx
;
3015 desc
->first_active_slot
= first
;
3016 desc
->num_active_slots
= count
;
3019 void si_set_active_descriptors_for_shader(struct si_context
*sctx
,
3020 struct si_shader_selector
*sel
)
3025 si_set_active_descriptors(sctx
,
3026 si_const_and_shader_buffer_descriptors_idx(sel
->type
),
3027 sel
->active_const_and_shader_buffers
);
3028 si_set_active_descriptors(sctx
,
3029 si_sampler_and_image_descriptors_idx(sel
->type
),
3030 sel
->active_samplers_and_images
);