2 * Copyright 2013 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 /* Resource binding slots and sampler states (each described with 8 or
26 * 4 dwords) are stored in lists in memory which is accessed by shaders
27 * using scalar load instructions.
29 * This file is responsible for managing such lists. It keeps a copy of all
30 * descriptors in CPU memory and re-uploads a whole list if some slots have
33 * This code is also reponsible for updating shader pointers to those lists.
35 * Note that CP DMA can't be used for updating the lists, because a GPU hang
36 * could leave the list in a mid-IB state and the next IB would get wrong
37 * descriptors and the whole context would be unusable at that point.
38 * (Note: The register shadowing can't be used due to the same reason)
40 * Also, uploading descriptors to newly allocated memory doesn't require
44 * Possible scenarios for one 16 dword image+sampler slot:
46 * | Image | w/ FMASK | Buffer | NULL
47 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
48 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
49 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
50 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
52 * FMASK implies MSAA, therefore no sampler state.
53 * Sampler states are never unbound except when FMASK is bound.
56 #include "radeon/r600_cs.h"
61 #include "util/hash_table.h"
62 #include "util/u_idalloc.h"
63 #include "util/u_format.h"
64 #include "util/u_memory.h"
65 #include "util/u_upload_mgr.h"
68 /* NULL image and buffer descriptor for textures (alpha = 1) and images
71 * For images, all fields must be zero except for the swizzle, which
72 * supports arbitrary combinations of 0s and 1s. The texture type must be
73 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
75 * For buffers, all fields must be zero. If they are not, the hw hangs.
77 * This is the only reason why the buffer descriptor must be in words [4:7].
79 static uint32_t null_texture_descriptor
[8] = {
83 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1
) |
84 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
85 /* the rest must contain zeros, which is also used by the buffer
89 static uint32_t null_image_descriptor
[8] = {
93 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
94 /* the rest must contain zeros, which is also used by the buffer
98 static uint64_t si_desc_extract_buffer_address(uint32_t *desc
)
100 uint64_t va
= desc
[0] |
101 ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc
[1]) << 32);
103 /* Sign-extend the 48-bit address. */
104 if (va
& (1ull << 47))
105 va
|= 0xffffull
<< 48;
109 static void si_init_descriptor_list(uint32_t *desc_list
,
110 unsigned element_dw_size
,
111 unsigned num_elements
,
112 const uint32_t *null_descriptor
)
116 /* Initialize the array to NULL descriptors if the element size is 8. */
117 if (null_descriptor
) {
118 assert(element_dw_size
% 8 == 0);
119 for (i
= 0; i
< num_elements
* element_dw_size
/ 8; i
++)
120 memcpy(desc_list
+ i
* 8, null_descriptor
, 8 * 4);
124 static void si_init_descriptors(struct si_descriptors
*desc
,
125 short shader_userdata_rel_index
,
126 unsigned element_dw_size
,
127 unsigned num_elements
)
129 desc
->list
= CALLOC(num_elements
, element_dw_size
* 4);
130 desc
->element_dw_size
= element_dw_size
;
131 desc
->num_elements
= num_elements
;
132 desc
->shader_userdata_offset
= shader_userdata_rel_index
* 4;
133 desc
->slot_index_to_bind_directly
= -1;
136 static void si_release_descriptors(struct si_descriptors
*desc
)
138 r600_resource_reference(&desc
->buffer
, NULL
);
142 static bool si_upload_descriptors(struct si_context
*sctx
,
143 struct si_descriptors
*desc
)
145 unsigned slot_size
= desc
->element_dw_size
* 4;
146 unsigned first_slot_offset
= desc
->first_active_slot
* slot_size
;
147 unsigned upload_size
= desc
->num_active_slots
* slot_size
;
149 /* Skip the upload if no shader is using the descriptors. dirty_mask
150 * will stay dirty and the descriptors will be uploaded when there is
151 * a shader using them.
156 /* If there is just one active descriptor, bind it directly. */
157 if ((int)desc
->first_active_slot
== desc
->slot_index_to_bind_directly
&&
158 desc
->num_active_slots
== 1) {
159 uint32_t *descriptor
= &desc
->list
[desc
->slot_index_to_bind_directly
*
160 desc
->element_dw_size
];
162 /* The buffer is already in the buffer list. */
163 r600_resource_reference(&desc
->buffer
, NULL
);
164 desc
->gpu_list
= NULL
;
165 desc
->gpu_address
= si_desc_extract_buffer_address(descriptor
);
166 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
171 unsigned buffer_offset
;
172 u_upload_alloc(sctx
->b
.b
.const_uploader
, first_slot_offset
, upload_size
,
173 si_optimal_tcc_alignment(sctx
, upload_size
),
174 &buffer_offset
, (struct pipe_resource
**)&desc
->buffer
,
177 desc
->gpu_address
= 0;
178 return false; /* skip the draw call */
181 util_memcpy_cpu_to_le32(ptr
, (char*)desc
->list
+ first_slot_offset
,
183 desc
->gpu_list
= ptr
- first_slot_offset
/ 4;
185 radeon_add_to_buffer_list(sctx
, sctx
->b
.gfx_cs
, desc
->buffer
,
186 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
188 /* The shader pointer should point to slot 0. */
189 buffer_offset
-= first_slot_offset
;
190 desc
->gpu_address
= desc
->buffer
->gpu_address
+ buffer_offset
;
192 assert(desc
->buffer
->flags
& RADEON_FLAG_32BIT
);
193 assert((desc
->buffer
->gpu_address
>> 32) == sctx
->screen
->info
.address32_hi
);
194 assert((desc
->gpu_address
>> 32) == sctx
->screen
->info
.address32_hi
);
196 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
201 si_descriptors_begin_new_cs(struct si_context
*sctx
, struct si_descriptors
*desc
)
206 radeon_add_to_buffer_list(sctx
, sctx
->b
.gfx_cs
, desc
->buffer
,
207 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
212 static inline enum radeon_bo_priority
213 si_get_sampler_view_priority(struct r600_resource
*res
)
215 if (res
->b
.b
.target
== PIPE_BUFFER
)
216 return RADEON_PRIO_SAMPLER_BUFFER
;
218 if (res
->b
.b
.nr_samples
> 1)
219 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA
;
221 return RADEON_PRIO_SAMPLER_TEXTURE
;
225 si_sampler_and_image_descriptors_idx(unsigned shader
)
227 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
228 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
;
231 static struct si_descriptors
*
232 si_sampler_and_image_descriptors(struct si_context
*sctx
, unsigned shader
)
234 return &sctx
->descriptors
[si_sampler_and_image_descriptors_idx(shader
)];
237 static void si_release_sampler_views(struct si_samplers
*samplers
)
241 for (i
= 0; i
< ARRAY_SIZE(samplers
->views
); i
++) {
242 pipe_sampler_view_reference(&samplers
->views
[i
], NULL
);
246 static void si_sampler_view_add_buffer(struct si_context
*sctx
,
247 struct pipe_resource
*resource
,
248 enum radeon_bo_usage usage
,
249 bool is_stencil_sampler
,
252 struct r600_resource
*rres
;
253 struct r600_texture
*rtex
;
254 enum radeon_bo_priority priority
;
259 if (resource
->target
!= PIPE_BUFFER
) {
260 struct r600_texture
*tex
= (struct r600_texture
*)resource
;
262 if (tex
->is_depth
&& !si_can_sample_zs(tex
, is_stencil_sampler
))
263 resource
= &tex
->flushed_depth_texture
->resource
.b
.b
;
266 rres
= (struct r600_resource
*)resource
;
267 priority
= si_get_sampler_view_priority(rres
);
269 radeon_add_to_gfx_buffer_list_check_mem(sctx
, rres
, usage
, priority
,
272 if (resource
->target
== PIPE_BUFFER
)
275 /* Now add separate DCC or HTILE. */
276 rtex
= (struct r600_texture
*)resource
;
277 if (rtex
->dcc_separate_buffer
) {
278 radeon_add_to_gfx_buffer_list_check_mem(sctx
, rtex
->dcc_separate_buffer
,
279 usage
, RADEON_PRIO_DCC
, check_mem
);
283 static void si_sampler_views_begin_new_cs(struct si_context
*sctx
,
284 struct si_samplers
*samplers
)
286 unsigned mask
= samplers
->enabled_mask
;
288 /* Add buffers to the CS. */
290 int i
= u_bit_scan(&mask
);
291 struct si_sampler_view
*sview
= (struct si_sampler_view
*)samplers
->views
[i
];
293 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
295 sview
->is_stencil_sampler
, false);
299 /* Set buffer descriptor fields that can be changed by reallocations. */
300 static void si_set_buf_desc_address(struct r600_resource
*buf
,
301 uint64_t offset
, uint32_t *state
)
303 uint64_t va
= buf
->gpu_address
+ offset
;
306 state
[1] &= C_008F04_BASE_ADDRESS_HI
;
307 state
[1] |= S_008F04_BASE_ADDRESS_HI(va
>> 32);
310 /* Set texture descriptor fields that can be changed by reallocations.
313 * \param base_level_info information of the level of BASE_ADDRESS
314 * \param base_level the level of BASE_ADDRESS
315 * \param first_level pipe_sampler_view.u.tex.first_level
316 * \param block_width util_format_get_blockwidth()
317 * \param is_stencil select between separate Z & Stencil
318 * \param state descriptor to update
320 void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen
,
321 struct r600_texture
*tex
,
322 const struct legacy_surf_level
*base_level_info
,
323 unsigned base_level
, unsigned first_level
,
324 unsigned block_width
, bool is_stencil
,
327 uint64_t va
, meta_va
= 0;
329 if (tex
->is_depth
&& !si_can_sample_zs(tex
, is_stencil
)) {
330 tex
= tex
->flushed_depth_texture
;
334 va
= tex
->resource
.gpu_address
;
336 if (sscreen
->info
.chip_class
>= GFX9
) {
337 /* Only stencil_offset needs to be added here. */
339 va
+= tex
->surface
.u
.gfx9
.stencil_offset
;
341 va
+= tex
->surface
.u
.gfx9
.surf_offset
;
343 va
+= base_level_info
->offset
;
347 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
348 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
350 /* Only macrotiled modes can set tile swizzle.
351 * GFX9 doesn't use (legacy) base_level_info.
353 if (sscreen
->info
.chip_class
>= GFX9
||
354 base_level_info
->mode
== RADEON_SURF_MODE_2D
)
355 state
[0] |= tex
->surface
.tile_swizzle
;
357 if (sscreen
->info
.chip_class
>= VI
) {
358 state
[6] &= C_008F28_COMPRESSION_EN
;
361 if (vi_dcc_enabled(tex
, first_level
)) {
362 meta_va
= (!tex
->dcc_separate_buffer
? tex
->resource
.gpu_address
: 0) +
365 if (sscreen
->info
.chip_class
== VI
) {
366 meta_va
+= base_level_info
->dcc_offset
;
367 assert(base_level_info
->mode
== RADEON_SURF_MODE_2D
);
370 meta_va
|= (uint32_t)tex
->surface
.tile_swizzle
<< 8;
371 } else if (vi_tc_compat_htile_enabled(tex
, first_level
)) {
372 meta_va
= tex
->resource
.gpu_address
+ tex
->htile_offset
;
376 state
[6] |= S_008F28_COMPRESSION_EN(1);
377 state
[7] = meta_va
>> 8;
381 if (sscreen
->info
.chip_class
>= GFX9
) {
382 state
[3] &= C_008F1C_SW_MODE
;
383 state
[4] &= C_008F20_PITCH_GFX9
;
386 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
387 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.stencil
.epitch
);
389 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
);
390 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.surf
.epitch
);
393 state
[5] &= C_008F24_META_DATA_ADDRESS
&
394 C_008F24_META_PIPE_ALIGNED
&
395 C_008F24_META_RB_ALIGNED
;
397 struct gfx9_surf_meta_flags meta
;
400 meta
= tex
->surface
.u
.gfx9
.dcc
;
402 meta
= tex
->surface
.u
.gfx9
.htile
;
404 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
405 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
406 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
410 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
411 unsigned index
= si_tile_mode_index(tex
, base_level
, is_stencil
);
413 state
[3] &= C_008F1C_TILING_INDEX
;
414 state
[3] |= S_008F1C_TILING_INDEX(index
);
415 state
[4] &= C_008F20_PITCH_GFX6
;
416 state
[4] |= S_008F20_PITCH_GFX6(pitch
- 1);
420 static void si_set_sampler_state_desc(struct si_sampler_state
*sstate
,
421 struct si_sampler_view
*sview
,
422 struct r600_texture
*tex
,
425 if (sview
&& sview
->is_integer
)
426 memcpy(desc
, sstate
->integer_val
, 4*4);
427 else if (tex
&& tex
->upgraded_depth
&&
428 (!sview
|| !sview
->is_stencil_sampler
))
429 memcpy(desc
, sstate
->upgraded_depth_val
, 4*4);
431 memcpy(desc
, sstate
->val
, 4*4);
434 static void si_set_sampler_view_desc(struct si_context
*sctx
,
435 struct si_sampler_view
*sview
,
436 struct si_sampler_state
*sstate
,
439 struct pipe_sampler_view
*view
= &sview
->base
;
440 struct r600_texture
*rtex
= (struct r600_texture
*)view
->texture
;
441 bool is_buffer
= rtex
->resource
.b
.b
.target
== PIPE_BUFFER
;
443 if (unlikely(!is_buffer
&& sview
->dcc_incompatible
)) {
444 if (vi_dcc_enabled(rtex
, view
->u
.tex
.first_level
))
445 if (!si_texture_disable_dcc(sctx
, rtex
))
446 si_decompress_dcc(&sctx
->b
.b
, rtex
);
448 sview
->dcc_incompatible
= false;
451 assert(rtex
); /* views with texture == NULL aren't supported */
452 memcpy(desc
, sview
->state
, 8*4);
455 si_set_buf_desc_address(&rtex
->resource
,
456 sview
->base
.u
.buf
.offset
,
459 bool is_separate_stencil
= rtex
->db_compatible
&&
460 sview
->is_stencil_sampler
;
462 si_set_mutable_tex_desc_fields(sctx
->screen
, rtex
,
463 sview
->base_level_info
,
465 sview
->base
.u
.tex
.first_level
,
471 if (!is_buffer
&& rtex
->fmask
.size
) {
472 memcpy(desc
+ 8, sview
->fmask_state
, 8*4);
474 /* Disable FMASK and bind sampler state in [12:15]. */
475 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
478 si_set_sampler_state_desc(sstate
, sview
,
479 is_buffer
? NULL
: rtex
,
484 static bool color_needs_decompression(struct r600_texture
*rtex
)
486 return rtex
->fmask
.size
||
487 (rtex
->dirty_level_mask
&&
488 (rtex
->cmask
.size
|| rtex
->dcc_offset
));
491 static bool depth_needs_decompression(struct r600_texture
*rtex
)
493 /* If the depth/stencil texture is TC-compatible, no decompression
494 * will be done. The decompression function will only flush DB caches
495 * to make it coherent with shaders. That's necessary because the driver
496 * doesn't flush DB caches in any other case.
498 return rtex
->db_compatible
;
501 static void si_set_sampler_view(struct si_context
*sctx
,
503 unsigned slot
, struct pipe_sampler_view
*view
,
504 bool disallow_early_out
)
506 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
507 struct si_sampler_view
*rview
= (struct si_sampler_view
*)view
;
508 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(sctx
, shader
);
509 unsigned desc_slot
= si_get_sampler_slot(slot
);
510 uint32_t *desc
= descs
->list
+ desc_slot
* 16;
512 if (samplers
->views
[slot
] == view
&& !disallow_early_out
)
516 struct r600_texture
*rtex
= (struct r600_texture
*)view
->texture
;
518 si_set_sampler_view_desc(sctx
, rview
,
519 samplers
->sampler_states
[slot
], desc
);
521 if (rtex
->resource
.b
.b
.target
== PIPE_BUFFER
) {
522 rtex
->resource
.bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
523 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
524 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
526 if (depth_needs_decompression(rtex
)) {
527 samplers
->needs_depth_decompress_mask
|= 1u << slot
;
529 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
531 if (color_needs_decompression(rtex
)) {
532 samplers
->needs_color_decompress_mask
|= 1u << slot
;
534 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
537 if (rtex
->dcc_offset
&&
538 p_atomic_read(&rtex
->framebuffers_bound
))
539 sctx
->need_check_render_feedback
= true;
542 pipe_sampler_view_reference(&samplers
->views
[slot
], view
);
543 samplers
->enabled_mask
|= 1u << slot
;
545 /* Since this can flush, it must be done after enabled_mask is
547 si_sampler_view_add_buffer(sctx
, view
->texture
,
549 rview
->is_stencil_sampler
, true);
551 pipe_sampler_view_reference(&samplers
->views
[slot
], NULL
);
552 memcpy(desc
, null_texture_descriptor
, 8*4);
553 /* Only clear the lower dwords of FMASK. */
554 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
555 /* Re-set the sampler state if we are transitioning from FMASK. */
556 if (samplers
->sampler_states
[slot
])
557 si_set_sampler_state_desc(samplers
->sampler_states
[slot
], NULL
, NULL
,
560 samplers
->enabled_mask
&= ~(1u << slot
);
561 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
562 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
565 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
568 static void si_update_shader_needs_decompress_mask(struct si_context
*sctx
,
571 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
572 unsigned shader_bit
= 1 << shader
;
574 if (samplers
->needs_depth_decompress_mask
||
575 samplers
->needs_color_decompress_mask
||
576 sctx
->images
[shader
].needs_color_decompress_mask
)
577 sctx
->shader_needs_decompress_mask
|= shader_bit
;
579 sctx
->shader_needs_decompress_mask
&= ~shader_bit
;
582 static void si_set_sampler_views(struct pipe_context
*ctx
,
583 enum pipe_shader_type shader
, unsigned start
,
585 struct pipe_sampler_view
**views
)
587 struct si_context
*sctx
= (struct si_context
*)ctx
;
590 if (!count
|| shader
>= SI_NUM_SHADERS
)
594 for (i
= 0; i
< count
; i
++)
595 si_set_sampler_view(sctx
, shader
, start
+ i
, views
[i
], false);
597 for (i
= 0; i
< count
; i
++)
598 si_set_sampler_view(sctx
, shader
, start
+ i
, NULL
, false);
601 si_update_shader_needs_decompress_mask(sctx
, shader
);
605 si_samplers_update_needs_color_decompress_mask(struct si_samplers
*samplers
)
607 unsigned mask
= samplers
->enabled_mask
;
610 int i
= u_bit_scan(&mask
);
611 struct pipe_resource
*res
= samplers
->views
[i
]->texture
;
613 if (res
&& res
->target
!= PIPE_BUFFER
) {
614 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
616 if (color_needs_decompression(rtex
)) {
617 samplers
->needs_color_decompress_mask
|= 1u << i
;
619 samplers
->needs_color_decompress_mask
&= ~(1u << i
);
628 si_release_image_views(struct si_images
*images
)
632 for (i
= 0; i
< SI_NUM_IMAGES
; ++i
) {
633 struct pipe_image_view
*view
= &images
->views
[i
];
635 pipe_resource_reference(&view
->resource
, NULL
);
640 si_image_views_begin_new_cs(struct si_context
*sctx
, struct si_images
*images
)
642 uint mask
= images
->enabled_mask
;
644 /* Add buffers to the CS. */
646 int i
= u_bit_scan(&mask
);
647 struct pipe_image_view
*view
= &images
->views
[i
];
649 assert(view
->resource
);
651 si_sampler_view_add_buffer(sctx
, view
->resource
,
652 RADEON_USAGE_READWRITE
, false, false);
657 si_disable_shader_image(struct si_context
*ctx
, unsigned shader
, unsigned slot
)
659 struct si_images
*images
= &ctx
->images
[shader
];
661 if (images
->enabled_mask
& (1u << slot
)) {
662 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
663 unsigned desc_slot
= si_get_image_slot(slot
);
665 pipe_resource_reference(&images
->views
[slot
].resource
, NULL
);
666 images
->needs_color_decompress_mask
&= ~(1 << slot
);
668 memcpy(descs
->list
+ desc_slot
*8, null_image_descriptor
, 8*4);
669 images
->enabled_mask
&= ~(1u << slot
);
670 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
675 si_mark_image_range_valid(const struct pipe_image_view
*view
)
677 struct r600_resource
*res
= (struct r600_resource
*)view
->resource
;
679 assert(res
&& res
->b
.b
.target
== PIPE_BUFFER
);
681 util_range_add(&res
->valid_buffer_range
,
683 view
->u
.buf
.offset
+ view
->u
.buf
.size
);
686 static void si_set_shader_image_desc(struct si_context
*ctx
,
687 const struct pipe_image_view
*view
,
688 bool skip_decompress
,
689 uint32_t *desc
, uint32_t *fmask_desc
)
691 struct si_screen
*screen
= ctx
->screen
;
692 struct r600_resource
*res
;
694 res
= (struct r600_resource
*)view
->resource
;
696 if (res
->b
.b
.target
== PIPE_BUFFER
) {
697 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
698 si_mark_image_range_valid(view
);
700 si_make_buffer_descriptor(screen
, res
,
703 view
->u
.buf
.size
, desc
);
704 si_set_buf_desc_address(res
, view
->u
.buf
.offset
, desc
+ 4);
706 static const unsigned char swizzle
[4] = { 0, 1, 2, 3 };
707 struct r600_texture
*tex
= (struct r600_texture
*)res
;
708 unsigned level
= view
->u
.tex
.level
;
709 unsigned width
, height
, depth
, hw_level
;
710 bool uses_dcc
= vi_dcc_enabled(tex
, level
);
711 unsigned access
= view
->access
;
713 /* Clear the write flag when writes can't occur.
714 * Note that DCC_DECOMPRESS for MSAA doesn't work in some cases,
715 * so we don't wanna trigger it.
718 (!fmask_desc
&& tex
->fmask
.size
!= 0)) {
719 assert(!"Z/S and MSAA image stores are not supported");
720 access
&= ~PIPE_IMAGE_ACCESS_WRITE
;
723 assert(!tex
->is_depth
);
724 assert(fmask_desc
|| tex
->fmask
.size
== 0);
726 if (uses_dcc
&& !skip_decompress
&&
727 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
||
728 !vi_dcc_formats_compatible(res
->b
.b
.format
, view
->format
))) {
729 /* If DCC can't be disabled, at least decompress it.
730 * The decompression is relatively cheap if the surface
731 * has been decompressed already.
733 if (!si_texture_disable_dcc(ctx
, tex
))
734 si_decompress_dcc(&ctx
->b
.b
, tex
);
737 if (ctx
->b
.chip_class
>= GFX9
) {
738 /* Always set the base address. The swizzle modes don't
739 * allow setting mipmap level offsets as the base.
741 width
= res
->b
.b
.width0
;
742 height
= res
->b
.b
.height0
;
743 depth
= res
->b
.b
.depth0
;
746 /* Always force the base level to the selected level.
748 * This is required for 3D textures, where otherwise
749 * selecting a single slice for non-layered bindings
750 * fails. It doesn't hurt the other targets.
752 width
= u_minify(res
->b
.b
.width0
, level
);
753 height
= u_minify(res
->b
.b
.height0
, level
);
754 depth
= u_minify(res
->b
.b
.depth0
, level
);
758 si_make_texture_descriptor(screen
, tex
,
759 false, res
->b
.b
.target
,
760 view
->format
, swizzle
,
762 view
->u
.tex
.first_layer
,
763 view
->u
.tex
.last_layer
,
764 width
, height
, depth
,
766 si_set_mutable_tex_desc_fields(screen
, tex
,
767 &tex
->surface
.u
.legacy
.level
[level
],
769 util_format_get_blockwidth(view
->format
),
774 static void si_set_shader_image(struct si_context
*ctx
,
776 unsigned slot
, const struct pipe_image_view
*view
,
777 bool skip_decompress
)
779 struct si_images
*images
= &ctx
->images
[shader
];
780 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
781 struct r600_resource
*res
;
782 unsigned desc_slot
= si_get_image_slot(slot
);
783 uint32_t *desc
= descs
->list
+ desc_slot
* 8;
785 if (!view
|| !view
->resource
) {
786 si_disable_shader_image(ctx
, shader
, slot
);
790 res
= (struct r600_resource
*)view
->resource
;
792 if (&images
->views
[slot
] != view
)
793 util_copy_image_view(&images
->views
[slot
], view
);
795 si_set_shader_image_desc(ctx
, view
, skip_decompress
, desc
, NULL
);
797 if (res
->b
.b
.target
== PIPE_BUFFER
) {
798 images
->needs_color_decompress_mask
&= ~(1 << slot
);
799 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
801 struct r600_texture
*tex
= (struct r600_texture
*)res
;
802 unsigned level
= view
->u
.tex
.level
;
804 if (color_needs_decompression(tex
)) {
805 images
->needs_color_decompress_mask
|= 1 << slot
;
807 images
->needs_color_decompress_mask
&= ~(1 << slot
);
810 if (vi_dcc_enabled(tex
, level
) &&
811 p_atomic_read(&tex
->framebuffers_bound
))
812 ctx
->need_check_render_feedback
= true;
815 images
->enabled_mask
|= 1u << slot
;
816 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
818 /* Since this can flush, it must be done after enabled_mask is updated. */
819 si_sampler_view_add_buffer(ctx
, &res
->b
.b
,
820 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
) ?
821 RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
,
826 si_set_shader_images(struct pipe_context
*pipe
,
827 enum pipe_shader_type shader
,
828 unsigned start_slot
, unsigned count
,
829 const struct pipe_image_view
*views
)
831 struct si_context
*ctx
= (struct si_context
*)pipe
;
834 assert(shader
< SI_NUM_SHADERS
);
839 assert(start_slot
+ count
<= SI_NUM_IMAGES
);
842 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
843 si_set_shader_image(ctx
, shader
, slot
, &views
[i
], false);
845 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
846 si_set_shader_image(ctx
, shader
, slot
, NULL
, false);
849 si_update_shader_needs_decompress_mask(ctx
, shader
);
853 si_images_update_needs_color_decompress_mask(struct si_images
*images
)
855 unsigned mask
= images
->enabled_mask
;
858 int i
= u_bit_scan(&mask
);
859 struct pipe_resource
*res
= images
->views
[i
].resource
;
861 if (res
&& res
->target
!= PIPE_BUFFER
) {
862 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
864 if (color_needs_decompression(rtex
)) {
865 images
->needs_color_decompress_mask
|= 1 << i
;
867 images
->needs_color_decompress_mask
&= ~(1 << i
);
873 void si_update_ps_colorbuf0_slot(struct si_context
*sctx
)
875 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
876 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
877 unsigned slot
= SI_PS_IMAGE_COLORBUF0
;
878 struct pipe_surface
*surf
= NULL
;
880 /* si_texture_disable_dcc can get us here again. */
881 if (sctx
->blitter
->running
)
884 /* See whether FBFETCH is used and color buffer 0 is set. */
885 if (sctx
->ps_shader
.cso
&&
886 sctx
->ps_shader
.cso
->info
.opcode_count
[TGSI_OPCODE_FBFETCH
] &&
887 sctx
->framebuffer
.state
.nr_cbufs
&&
888 sctx
->framebuffer
.state
.cbufs
[0])
889 surf
= sctx
->framebuffer
.state
.cbufs
[0];
891 /* Return if FBFETCH transitions from disabled to disabled. */
892 if (!buffers
->buffers
[slot
] && !surf
)
895 sctx
->ps_uses_fbfetch
= surf
!= NULL
;
896 si_update_ps_iter_samples(sctx
);
899 struct r600_texture
*tex
= (struct r600_texture
*)surf
->texture
;
900 struct pipe_image_view view
;
903 assert(!tex
->is_depth
);
905 /* Disable DCC, because the texture is used as both a sampler
908 si_texture_disable_dcc(sctx
, tex
);
910 if (tex
->resource
.b
.b
.nr_samples
<= 1 && tex
->cmask_buffer
) {
912 assert(tex
->cmask_buffer
!= &tex
->resource
);
913 si_eliminate_fast_color_clear(sctx
, tex
);
914 si_texture_discard_cmask(sctx
->screen
, tex
);
917 view
.resource
= surf
->texture
;
918 view
.format
= surf
->format
;
919 view
.access
= PIPE_IMAGE_ACCESS_READ
;
920 view
.u
.tex
.first_layer
= surf
->u
.tex
.first_layer
;
921 view
.u
.tex
.last_layer
= surf
->u
.tex
.last_layer
;
922 view
.u
.tex
.level
= surf
->u
.tex
.level
;
924 /* Set the descriptor. */
925 uint32_t *desc
= descs
->list
+ slot
*4;
926 memset(desc
, 0, 16 * 4);
927 si_set_shader_image_desc(sctx
, &view
, true, desc
, desc
+ 8);
929 pipe_resource_reference(&buffers
->buffers
[slot
], &tex
->resource
.b
.b
);
930 radeon_add_to_buffer_list(sctx
, sctx
->b
.gfx_cs
,
931 &tex
->resource
, RADEON_USAGE_READ
,
932 RADEON_PRIO_SHADER_RW_IMAGE
);
933 buffers
->enabled_mask
|= 1u << slot
;
935 /* Clear the descriptor. */
936 memset(descs
->list
+ slot
*4, 0, 8*4);
937 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
938 buffers
->enabled_mask
&= ~(1u << slot
);
941 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
946 static void si_bind_sampler_states(struct pipe_context
*ctx
,
947 enum pipe_shader_type shader
,
948 unsigned start
, unsigned count
, void **states
)
950 struct si_context
*sctx
= (struct si_context
*)ctx
;
951 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
952 struct si_descriptors
*desc
= si_sampler_and_image_descriptors(sctx
, shader
);
953 struct si_sampler_state
**sstates
= (struct si_sampler_state
**)states
;
956 if (!count
|| shader
>= SI_NUM_SHADERS
)
959 for (i
= 0; i
< count
; i
++) {
960 unsigned slot
= start
+ i
;
961 unsigned desc_slot
= si_get_sampler_slot(slot
);
964 sstates
[i
] == samplers
->sampler_states
[slot
])
968 assert(sstates
[i
]->magic
== SI_SAMPLER_STATE_MAGIC
);
970 samplers
->sampler_states
[slot
] = sstates
[i
];
972 /* If FMASK is bound, don't overwrite it.
973 * The sampler state will be set after FMASK is unbound.
975 struct si_sampler_view
*sview
=
976 (struct si_sampler_view
*)samplers
->views
[slot
];
978 struct r600_texture
*tex
= NULL
;
980 if (sview
&& sview
->base
.texture
&&
981 sview
->base
.texture
->target
!= PIPE_BUFFER
)
982 tex
= (struct r600_texture
*)sview
->base
.texture
;
984 if (tex
&& tex
->fmask
.size
)
987 si_set_sampler_state_desc(sstates
[i
], sview
, tex
,
988 desc
->list
+ desc_slot
* 16 + 12);
990 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
994 /* BUFFER RESOURCES */
996 static void si_init_buffer_resources(struct si_buffer_resources
*buffers
,
997 struct si_descriptors
*descs
,
998 unsigned num_buffers
,
999 short shader_userdata_rel_index
,
1000 enum radeon_bo_usage shader_usage
,
1001 enum radeon_bo_usage shader_usage_constbuf
,
1002 enum radeon_bo_priority priority
,
1003 enum radeon_bo_priority priority_constbuf
)
1005 buffers
->shader_usage
= shader_usage
;
1006 buffers
->shader_usage_constbuf
= shader_usage_constbuf
;
1007 buffers
->priority
= priority
;
1008 buffers
->priority_constbuf
= priority_constbuf
;
1009 buffers
->buffers
= CALLOC(num_buffers
, sizeof(struct pipe_resource
*));
1011 si_init_descriptors(descs
, shader_userdata_rel_index
, 4, num_buffers
);
1014 static void si_release_buffer_resources(struct si_buffer_resources
*buffers
,
1015 struct si_descriptors
*descs
)
1019 for (i
= 0; i
< descs
->num_elements
; i
++) {
1020 pipe_resource_reference(&buffers
->buffers
[i
], NULL
);
1023 FREE(buffers
->buffers
);
1026 static void si_buffer_resources_begin_new_cs(struct si_context
*sctx
,
1027 struct si_buffer_resources
*buffers
)
1029 unsigned mask
= buffers
->enabled_mask
;
1031 /* Add buffers to the CS. */
1033 int i
= u_bit_scan(&mask
);
1035 radeon_add_to_buffer_list(sctx
, sctx
->b
.gfx_cs
,
1036 r600_resource(buffers
->buffers
[i
]),
1037 i
< SI_NUM_SHADER_BUFFERS
? buffers
->shader_usage
:
1038 buffers
->shader_usage_constbuf
,
1039 i
< SI_NUM_SHADER_BUFFERS
? buffers
->priority
:
1040 buffers
->priority_constbuf
);
1044 static void si_get_buffer_from_descriptors(struct si_buffer_resources
*buffers
,
1045 struct si_descriptors
*descs
,
1046 unsigned idx
, struct pipe_resource
**buf
,
1047 unsigned *offset
, unsigned *size
)
1049 pipe_resource_reference(buf
, buffers
->buffers
[idx
]);
1051 struct r600_resource
*res
= r600_resource(*buf
);
1052 const uint32_t *desc
= descs
->list
+ idx
* 4;
1057 assert(G_008F04_STRIDE(desc
[1]) == 0);
1058 va
= ((uint64_t)desc
[1] << 32) | desc
[0];
1060 assert(va
>= res
->gpu_address
&& va
+ *size
<= res
->gpu_address
+ res
->bo_size
);
1061 *offset
= va
- res
->gpu_address
;
1065 /* VERTEX BUFFERS */
1067 static void si_vertex_buffers_begin_new_cs(struct si_context
*sctx
)
1069 int count
= sctx
->vertex_elements
? sctx
->vertex_elements
->count
: 0;
1072 for (i
= 0; i
< count
; i
++) {
1073 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1075 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1077 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1080 radeon_add_to_buffer_list(sctx
, sctx
->b
.gfx_cs
,
1081 (struct r600_resource
*)sctx
->vertex_buffer
[vb
].buffer
.resource
,
1082 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1085 if (!sctx
->vb_descriptors_buffer
)
1087 radeon_add_to_buffer_list(sctx
, sctx
->b
.gfx_cs
,
1088 sctx
->vb_descriptors_buffer
, RADEON_USAGE_READ
,
1089 RADEON_PRIO_DESCRIPTORS
);
1092 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
)
1094 struct si_vertex_elements
*velems
= sctx
->vertex_elements
;
1096 unsigned desc_list_byte_size
;
1097 unsigned first_vb_use_mask
;
1100 if (!sctx
->vertex_buffers_dirty
|| !velems
)
1103 count
= velems
->count
;
1108 desc_list_byte_size
= velems
->desc_list_byte_size
;
1109 first_vb_use_mask
= velems
->first_vb_use_mask
;
1111 /* Vertex buffer descriptors are the only ones which are uploaded
1112 * directly through a staging buffer and don't go through
1113 * the fine-grained upload path.
1115 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0,
1116 desc_list_byte_size
,
1117 si_optimal_tcc_alignment(sctx
, desc_list_byte_size
),
1118 &sctx
->vb_descriptors_offset
,
1119 (struct pipe_resource
**)&sctx
->vb_descriptors_buffer
,
1121 if (!sctx
->vb_descriptors_buffer
) {
1122 sctx
->vb_descriptors_offset
= 0;
1123 sctx
->vb_descriptors_gpu_list
= NULL
;
1127 sctx
->vb_descriptors_gpu_list
= ptr
;
1128 radeon_add_to_buffer_list(sctx
, sctx
->b
.gfx_cs
,
1129 sctx
->vb_descriptors_buffer
, RADEON_USAGE_READ
,
1130 RADEON_PRIO_DESCRIPTORS
);
1132 assert(count
<= SI_MAX_ATTRIBS
);
1134 for (i
= 0; i
< count
; i
++) {
1135 struct pipe_vertex_buffer
*vb
;
1136 struct r600_resource
*rbuffer
;
1137 unsigned vbo_index
= velems
->vertex_buffer_index
[i
];
1138 uint32_t *desc
= &ptr
[i
*4];
1140 vb
= &sctx
->vertex_buffer
[vbo_index
];
1141 rbuffer
= (struct r600_resource
*)vb
->buffer
.resource
;
1143 memset(desc
, 0, 16);
1147 int64_t offset
= (int64_t)((int)vb
->buffer_offset
) +
1148 velems
->src_offset
[i
];
1149 uint64_t va
= rbuffer
->gpu_address
+ offset
;
1151 int64_t num_records
= (int64_t)rbuffer
->b
.b
.width0
- offset
;
1152 if (sctx
->b
.chip_class
!= VI
&& vb
->stride
) {
1153 /* Round up by rounding down and adding 1 */
1154 num_records
= (num_records
- velems
->format_size
[i
]) /
1157 assert(num_records
>= 0 && num_records
<= UINT_MAX
);
1160 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1161 S_008F04_STRIDE(vb
->stride
);
1162 desc
[2] = num_records
;
1163 desc
[3] = velems
->rsrc_word3
[i
];
1165 if (first_vb_use_mask
& (1 << i
)) {
1166 radeon_add_to_buffer_list(sctx
, sctx
->b
.gfx_cs
,
1167 (struct r600_resource
*)vb
->buffer
.resource
,
1168 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1172 /* Don't flush the const cache. It would have a very negative effect
1173 * on performance (confirmed by testing). New descriptors are always
1174 * uploaded to a fresh new buffer, so I don't think flushing the const
1175 * cache is needed. */
1176 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
1177 sctx
->vertex_buffers_dirty
= false;
1178 sctx
->vertex_buffer_pointer_dirty
= true;
1179 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VBO_DESCRIPTORS
;
1184 /* CONSTANT BUFFERS */
1187 si_const_and_shader_buffer_descriptors_idx(unsigned shader
)
1189 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
1190 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
;
1193 static struct si_descriptors
*
1194 si_const_and_shader_buffer_descriptors(struct si_context
*sctx
, unsigned shader
)
1196 return &sctx
->descriptors
[si_const_and_shader_buffer_descriptors_idx(shader
)];
1199 void si_upload_const_buffer(struct si_context
*sctx
, struct r600_resource
**rbuffer
,
1200 const uint8_t *ptr
, unsigned size
, uint32_t *const_offset
)
1204 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0, size
,
1205 si_optimal_tcc_alignment(sctx
, size
),
1207 (struct pipe_resource
**)rbuffer
, &tmp
);
1209 util_memcpy_cpu_to_le32(tmp
, ptr
, size
);
1212 static void si_set_constant_buffer(struct si_context
*sctx
,
1213 struct si_buffer_resources
*buffers
,
1214 unsigned descriptors_idx
,
1215 uint slot
, const struct pipe_constant_buffer
*input
)
1217 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1218 assert(slot
< descs
->num_elements
);
1219 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1221 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1222 * with a NULL buffer). We need to use a dummy buffer instead. */
1223 if (sctx
->b
.chip_class
== CIK
&&
1224 (!input
|| (!input
->buffer
&& !input
->user_buffer
)))
1225 input
= &sctx
->null_const_buf
;
1227 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
1228 struct pipe_resource
*buffer
= NULL
;
1231 /* Upload the user buffer if needed. */
1232 if (input
->user_buffer
) {
1233 unsigned buffer_offset
;
1235 si_upload_const_buffer(sctx
,
1236 (struct r600_resource
**)&buffer
, input
->user_buffer
,
1237 input
->buffer_size
, &buffer_offset
);
1239 /* Just unbind on failure. */
1240 si_set_constant_buffer(sctx
, buffers
, descriptors_idx
, slot
, NULL
);
1243 va
= r600_resource(buffer
)->gpu_address
+ buffer_offset
;
1245 pipe_resource_reference(&buffer
, input
->buffer
);
1246 va
= r600_resource(buffer
)->gpu_address
+ input
->buffer_offset
;
1247 /* Only track usage for non-user buffers. */
1248 r600_resource(buffer
)->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
1251 /* Set the descriptor. */
1252 uint32_t *desc
= descs
->list
+ slot
*4;
1254 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1256 desc
[2] = input
->buffer_size
;
1257 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1258 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1259 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1260 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1261 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1262 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1264 buffers
->buffers
[slot
] = buffer
;
1265 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1266 (struct r600_resource
*)buffer
,
1267 buffers
->shader_usage_constbuf
,
1268 buffers
->priority_constbuf
, true);
1269 buffers
->enabled_mask
|= 1u << slot
;
1271 /* Clear the descriptor. */
1272 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1273 buffers
->enabled_mask
&= ~(1u << slot
);
1276 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1279 void si_set_rw_buffer(struct si_context
*sctx
,
1280 uint slot
, const struct pipe_constant_buffer
*input
)
1282 si_set_constant_buffer(sctx
, &sctx
->rw_buffers
,
1283 SI_DESCS_RW_BUFFERS
, slot
, input
);
1286 static void si_pipe_set_constant_buffer(struct pipe_context
*ctx
,
1287 enum pipe_shader_type shader
, uint slot
,
1288 const struct pipe_constant_buffer
*input
)
1290 struct si_context
*sctx
= (struct si_context
*)ctx
;
1292 if (shader
>= SI_NUM_SHADERS
)
1295 if (slot
== 0 && input
&& input
->buffer
&&
1296 !(r600_resource(input
->buffer
)->flags
& RADEON_FLAG_32BIT
)) {
1297 assert(!"constant buffer 0 must have a 32-bit VM address, use const_uploader");
1301 slot
= si_get_constbuf_slot(slot
);
1302 si_set_constant_buffer(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1303 si_const_and_shader_buffer_descriptors_idx(shader
),
1307 void si_get_pipe_constant_buffer(struct si_context
*sctx
, uint shader
,
1308 uint slot
, struct pipe_constant_buffer
*cbuf
)
1310 cbuf
->user_buffer
= NULL
;
1311 si_get_buffer_from_descriptors(
1312 &sctx
->const_and_shader_buffers
[shader
],
1313 si_const_and_shader_buffer_descriptors(sctx
, shader
),
1314 si_get_constbuf_slot(slot
),
1315 &cbuf
->buffer
, &cbuf
->buffer_offset
, &cbuf
->buffer_size
);
1318 /* SHADER BUFFERS */
1320 static void si_set_shader_buffers(struct pipe_context
*ctx
,
1321 enum pipe_shader_type shader
,
1322 unsigned start_slot
, unsigned count
,
1323 const struct pipe_shader_buffer
*sbuffers
)
1325 struct si_context
*sctx
= (struct si_context
*)ctx
;
1326 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1327 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1330 assert(start_slot
+ count
<= SI_NUM_SHADER_BUFFERS
);
1332 for (i
= 0; i
< count
; ++i
) {
1333 const struct pipe_shader_buffer
*sbuffer
= sbuffers
? &sbuffers
[i
] : NULL
;
1334 struct r600_resource
*buf
;
1335 unsigned slot
= si_get_shaderbuf_slot(start_slot
+ i
);
1336 uint32_t *desc
= descs
->list
+ slot
* 4;
1339 if (!sbuffer
|| !sbuffer
->buffer
) {
1340 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1341 memset(desc
, 0, sizeof(uint32_t) * 4);
1342 buffers
->enabled_mask
&= ~(1u << slot
);
1343 sctx
->descriptors_dirty
|=
1344 1u << si_const_and_shader_buffer_descriptors_idx(shader
);
1348 buf
= (struct r600_resource
*)sbuffer
->buffer
;
1349 va
= buf
->gpu_address
+ sbuffer
->buffer_offset
;
1352 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1354 desc
[2] = sbuffer
->buffer_size
;
1355 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1356 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1357 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1358 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1359 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1360 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1362 pipe_resource_reference(&buffers
->buffers
[slot
], &buf
->b
.b
);
1363 radeon_add_to_gfx_buffer_list_check_mem(sctx
, buf
,
1364 buffers
->shader_usage
,
1365 buffers
->priority
, true);
1366 buf
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
1368 buffers
->enabled_mask
|= 1u << slot
;
1369 sctx
->descriptors_dirty
|=
1370 1u << si_const_and_shader_buffer_descriptors_idx(shader
);
1372 util_range_add(&buf
->valid_buffer_range
, sbuffer
->buffer_offset
,
1373 sbuffer
->buffer_offset
+ sbuffer
->buffer_size
);
1377 void si_get_shader_buffers(struct si_context
*sctx
,
1378 enum pipe_shader_type shader
,
1379 uint start_slot
, uint count
,
1380 struct pipe_shader_buffer
*sbuf
)
1382 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1383 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1385 for (unsigned i
= 0; i
< count
; ++i
) {
1386 si_get_buffer_from_descriptors(
1388 si_get_shaderbuf_slot(start_slot
+ i
),
1389 &sbuf
[i
].buffer
, &sbuf
[i
].buffer_offset
,
1390 &sbuf
[i
].buffer_size
);
1396 void si_set_ring_buffer(struct pipe_context
*ctx
, uint slot
,
1397 struct pipe_resource
*buffer
,
1398 unsigned stride
, unsigned num_records
,
1399 bool add_tid
, bool swizzle
,
1400 unsigned element_size
, unsigned index_stride
, uint64_t offset
)
1402 struct si_context
*sctx
= (struct si_context
*)ctx
;
1403 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1404 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1406 /* The stride field in the resource descriptor has 14 bits */
1407 assert(stride
< (1 << 14));
1409 assert(slot
< descs
->num_elements
);
1410 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1415 va
= r600_resource(buffer
)->gpu_address
+ offset
;
1417 switch (element_size
) {
1419 assert(!"Unsupported ring buffer element size");
1435 switch (index_stride
) {
1437 assert(!"Unsupported ring buffer index stride");
1453 if (sctx
->b
.chip_class
>= VI
&& stride
)
1454 num_records
*= stride
;
1456 /* Set the descriptor. */
1457 uint32_t *desc
= descs
->list
+ slot
*4;
1459 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1460 S_008F04_STRIDE(stride
) |
1461 S_008F04_SWIZZLE_ENABLE(swizzle
);
1462 desc
[2] = num_records
;
1463 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1464 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1465 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1466 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1467 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1468 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1469 S_008F0C_INDEX_STRIDE(index_stride
) |
1470 S_008F0C_ADD_TID_ENABLE(add_tid
);
1472 if (sctx
->b
.chip_class
>= GFX9
)
1473 assert(!swizzle
|| element_size
== 1); /* always 4 bytes on GFX9 */
1475 desc
[3] |= S_008F0C_ELEMENT_SIZE(element_size
);
1477 pipe_resource_reference(&buffers
->buffers
[slot
], buffer
);
1478 radeon_add_to_buffer_list(sctx
, sctx
->b
.gfx_cs
,
1479 (struct r600_resource
*)buffer
,
1480 buffers
->shader_usage
, buffers
->priority
);
1481 buffers
->enabled_mask
|= 1u << slot
;
1483 /* Clear the descriptor. */
1484 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1485 buffers
->enabled_mask
&= ~(1u << slot
);
1488 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1491 static void si_desc_reset_buffer_offset(uint32_t *desc
, uint64_t old_buf_va
,
1492 struct pipe_resource
*new_buf
)
1494 /* Retrieve the buffer offset from the descriptor. */
1495 uint64_t old_desc_va
= si_desc_extract_buffer_address(desc
);
1497 assert(old_buf_va
<= old_desc_va
);
1498 uint64_t offset_within_buffer
= old_desc_va
- old_buf_va
;
1500 /* Update the descriptor. */
1501 si_set_buf_desc_address(r600_resource(new_buf
), offset_within_buffer
,
1505 /* INTERNAL CONST BUFFERS */
1507 static void si_set_polygon_stipple(struct pipe_context
*ctx
,
1508 const struct pipe_poly_stipple
*state
)
1510 struct si_context
*sctx
= (struct si_context
*)ctx
;
1511 struct pipe_constant_buffer cb
= {};
1512 unsigned stipple
[32];
1515 for (i
= 0; i
< 32; i
++)
1516 stipple
[i
] = util_bitreverse(state
->stipple
[i
]);
1518 cb
.user_buffer
= stipple
;
1519 cb
.buffer_size
= sizeof(stipple
);
1521 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
, &cb
);
1524 /* TEXTURE METADATA ENABLE/DISABLE */
1527 si_resident_handles_update_needs_color_decompress(struct si_context
*sctx
)
1529 util_dynarray_clear(&sctx
->resident_tex_needs_color_decompress
);
1530 util_dynarray_clear(&sctx
->resident_img_needs_color_decompress
);
1532 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1533 struct si_texture_handle
*, tex_handle
) {
1534 struct pipe_resource
*res
= (*tex_handle
)->view
->texture
;
1535 struct r600_texture
*rtex
;
1537 if (!res
|| res
->target
== PIPE_BUFFER
)
1540 rtex
= (struct r600_texture
*)res
;
1541 if (!color_needs_decompression(rtex
))
1544 util_dynarray_append(&sctx
->resident_tex_needs_color_decompress
,
1545 struct si_texture_handle
*, *tex_handle
);
1548 util_dynarray_foreach(&sctx
->resident_img_handles
,
1549 struct si_image_handle
*, img_handle
) {
1550 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1551 struct pipe_resource
*res
= view
->resource
;
1552 struct r600_texture
*rtex
;
1554 if (!res
|| res
->target
== PIPE_BUFFER
)
1557 rtex
= (struct r600_texture
*)res
;
1558 if (!color_needs_decompression(rtex
))
1561 util_dynarray_append(&sctx
->resident_img_needs_color_decompress
,
1562 struct si_image_handle
*, *img_handle
);
1566 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1567 * while the texture is bound, possibly by a different context. In that case,
1568 * call this function to update needs_*_decompress_masks.
1570 void si_update_needs_color_decompress_masks(struct si_context
*sctx
)
1572 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
1573 si_samplers_update_needs_color_decompress_mask(&sctx
->samplers
[i
]);
1574 si_images_update_needs_color_decompress_mask(&sctx
->images
[i
]);
1575 si_update_shader_needs_decompress_mask(sctx
, i
);
1578 si_resident_handles_update_needs_color_decompress(sctx
);
1581 /* BUFFER DISCARD/INVALIDATION */
1583 /** Reset descriptors of buffer resources after \p buf has been invalidated. */
1584 static void si_reset_buffer_resources(struct si_context
*sctx
,
1585 struct si_buffer_resources
*buffers
,
1586 unsigned descriptors_idx
,
1588 struct pipe_resource
*buf
,
1590 enum radeon_bo_usage usage
,
1591 enum radeon_bo_priority priority
)
1593 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1594 unsigned mask
= buffers
->enabled_mask
& slot_mask
;
1597 unsigned i
= u_bit_scan(&mask
);
1598 if (buffers
->buffers
[i
] == buf
) {
1599 si_desc_reset_buffer_offset(descs
->list
+ i
*4,
1601 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1603 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1604 (struct r600_resource
*)buf
,
1605 usage
, priority
, true);
1610 /* Update all resource bindings where the buffer is bound, including
1611 * all resource descriptors. This is invalidate_buffer without
1612 * the invalidation. */
1613 void si_rebind_buffer(struct si_context
*sctx
, struct pipe_resource
*buf
,
1616 struct r600_resource
*rbuffer
= r600_resource(buf
);
1618 unsigned num_elems
= sctx
->vertex_elements
?
1619 sctx
->vertex_elements
->count
: 0;
1621 /* We changed the buffer, now we need to bind it where the old one
1622 * was bound. This consists of 2 things:
1623 * 1) Updating the resource descriptor and dirtying it.
1624 * 2) Adding a relocation to the CS, so that it's usable.
1627 /* Vertex buffers. */
1628 if (rbuffer
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
1629 for (i
= 0; i
< num_elems
; i
++) {
1630 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1632 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1634 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1637 if (sctx
->vertex_buffer
[vb
].buffer
.resource
== buf
) {
1638 sctx
->vertex_buffers_dirty
= true;
1644 /* Streamout buffers. (other internal buffers can't be invalidated) */
1645 if (rbuffer
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
1646 for (i
= SI_VS_STREAMOUT_BUF0
; i
<= SI_VS_STREAMOUT_BUF3
; i
++) {
1647 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1648 struct si_descriptors
*descs
=
1649 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1651 if (buffers
->buffers
[i
] != buf
)
1654 si_desc_reset_buffer_offset(descs
->list
+ i
*4,
1656 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1658 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1659 rbuffer
, buffers
->shader_usage
,
1660 RADEON_PRIO_SHADER_RW_BUFFER
,
1663 /* Update the streamout state. */
1664 if (sctx
->streamout
.begin_emitted
)
1665 si_emit_streamout_end(sctx
);
1666 sctx
->streamout
.append_bitmask
=
1667 sctx
->streamout
.enabled_mask
;
1668 si_streamout_buffers_dirty(sctx
);
1672 /* Constant and shader buffers. */
1673 if (rbuffer
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1674 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1675 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1676 si_const_and_shader_buffer_descriptors_idx(shader
),
1677 u_bit_consecutive(SI_NUM_SHADER_BUFFERS
, SI_NUM_CONST_BUFFERS
),
1679 sctx
->const_and_shader_buffers
[shader
].shader_usage_constbuf
,
1680 sctx
->const_and_shader_buffers
[shader
].priority_constbuf
);
1683 if (rbuffer
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
1684 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1685 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1686 si_const_and_shader_buffer_descriptors_idx(shader
),
1687 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS
),
1689 sctx
->const_and_shader_buffers
[shader
].shader_usage
,
1690 sctx
->const_and_shader_buffers
[shader
].priority
);
1693 if (rbuffer
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
1694 /* Texture buffers - update bindings. */
1695 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1696 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1697 struct si_descriptors
*descs
=
1698 si_sampler_and_image_descriptors(sctx
, shader
);
1699 unsigned mask
= samplers
->enabled_mask
;
1702 unsigned i
= u_bit_scan(&mask
);
1703 if (samplers
->views
[i
]->texture
== buf
) {
1704 unsigned desc_slot
= si_get_sampler_slot(i
);
1706 si_desc_reset_buffer_offset(descs
->list
+
1709 sctx
->descriptors_dirty
|=
1710 1u << si_sampler_and_image_descriptors_idx(shader
);
1712 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1713 rbuffer
, RADEON_USAGE_READ
,
1714 RADEON_PRIO_SAMPLER_BUFFER
,
1722 if (rbuffer
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
1723 for (shader
= 0; shader
< SI_NUM_SHADERS
; ++shader
) {
1724 struct si_images
*images
= &sctx
->images
[shader
];
1725 struct si_descriptors
*descs
=
1726 si_sampler_and_image_descriptors(sctx
, shader
);
1727 unsigned mask
= images
->enabled_mask
;
1730 unsigned i
= u_bit_scan(&mask
);
1732 if (images
->views
[i
].resource
== buf
) {
1733 unsigned desc_slot
= si_get_image_slot(i
);
1735 if (images
->views
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
)
1736 si_mark_image_range_valid(&images
->views
[i
]);
1738 si_desc_reset_buffer_offset(
1739 descs
->list
+ desc_slot
* 8 + 4,
1741 sctx
->descriptors_dirty
|=
1742 1u << si_sampler_and_image_descriptors_idx(shader
);
1744 radeon_add_to_gfx_buffer_list_check_mem(
1746 RADEON_USAGE_READWRITE
,
1747 RADEON_PRIO_SAMPLER_BUFFER
, true);
1753 /* Bindless texture handles */
1754 if (rbuffer
->texture_handle_allocated
) {
1755 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1757 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1758 struct si_texture_handle
*, tex_handle
) {
1759 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
1760 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1762 if (view
->texture
== buf
) {
1763 si_set_buf_desc_address(rbuffer
,
1766 desc_slot
* 16 + 4);
1768 (*tex_handle
)->desc_dirty
= true;
1769 sctx
->bindless_descriptors_dirty
= true;
1771 radeon_add_to_gfx_buffer_list_check_mem(
1774 RADEON_PRIO_SAMPLER_BUFFER
, true);
1779 /* Bindless image handles */
1780 if (rbuffer
->image_handle_allocated
) {
1781 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1783 util_dynarray_foreach(&sctx
->resident_img_handles
,
1784 struct si_image_handle
*, img_handle
) {
1785 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1786 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1788 if (view
->resource
== buf
) {
1789 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
1790 si_mark_image_range_valid(view
);
1792 si_set_buf_desc_address(rbuffer
,
1795 desc_slot
* 16 + 4);
1797 (*img_handle
)->desc_dirty
= true;
1798 sctx
->bindless_descriptors_dirty
= true;
1800 radeon_add_to_gfx_buffer_list_check_mem(
1802 RADEON_USAGE_READWRITE
,
1803 RADEON_PRIO_SAMPLER_BUFFER
, true);
1809 static void si_upload_bindless_descriptor(struct si_context
*sctx
,
1811 unsigned num_dwords
)
1813 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1814 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
1815 unsigned desc_slot_offset
= desc_slot
* 16;
1819 data
= desc
->list
+ desc_slot_offset
;
1820 va
= desc
->gpu_address
+ desc_slot_offset
* 4;
1822 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + num_dwords
, 0));
1823 radeon_emit(cs
, S_370_DST_SEL(V_370_TC_L2
) |
1824 S_370_WR_CONFIRM(1) |
1825 S_370_ENGINE_SEL(V_370_ME
));
1826 radeon_emit(cs
, va
);
1827 radeon_emit(cs
, va
>> 32);
1828 radeon_emit_array(cs
, data
, num_dwords
);
1831 static void si_upload_bindless_descriptors(struct si_context
*sctx
)
1833 if (!sctx
->bindless_descriptors_dirty
)
1836 /* Wait for graphics/compute to be idle before updating the resident
1837 * descriptors directly in memory, in case the GPU is using them.
1839 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
1840 SI_CONTEXT_CS_PARTIAL_FLUSH
;
1841 si_emit_cache_flush(sctx
);
1843 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1844 struct si_texture_handle
*, tex_handle
) {
1845 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1847 if (!(*tex_handle
)->desc_dirty
)
1850 si_upload_bindless_descriptor(sctx
, desc_slot
, 16);
1851 (*tex_handle
)->desc_dirty
= false;
1854 util_dynarray_foreach(&sctx
->resident_img_handles
,
1855 struct si_image_handle
*, img_handle
) {
1856 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1858 if (!(*img_handle
)->desc_dirty
)
1861 si_upload_bindless_descriptor(sctx
, desc_slot
, 8);
1862 (*img_handle
)->desc_dirty
= false;
1865 /* Invalidate L1 because it doesn't know that L2 changed. */
1866 sctx
->b
.flags
|= SI_CONTEXT_INV_SMEM_L1
;
1867 si_emit_cache_flush(sctx
);
1869 sctx
->bindless_descriptors_dirty
= false;
1872 /* Update mutable image descriptor fields of all resident textures. */
1873 static void si_update_bindless_texture_descriptor(struct si_context
*sctx
,
1874 struct si_texture_handle
*tex_handle
)
1876 struct si_sampler_view
*sview
= (struct si_sampler_view
*)tex_handle
->view
;
1877 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1878 unsigned desc_slot_offset
= tex_handle
->desc_slot
* 16;
1879 uint32_t desc_list
[16];
1881 if (sview
->base
.texture
->target
== PIPE_BUFFER
)
1884 memcpy(desc_list
, desc
->list
+ desc_slot_offset
, sizeof(desc_list
));
1885 si_set_sampler_view_desc(sctx
, sview
, &tex_handle
->sstate
,
1886 desc
->list
+ desc_slot_offset
);
1888 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1889 sizeof(desc_list
))) {
1890 tex_handle
->desc_dirty
= true;
1891 sctx
->bindless_descriptors_dirty
= true;
1895 static void si_update_bindless_image_descriptor(struct si_context
*sctx
,
1896 struct si_image_handle
*img_handle
)
1898 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1899 unsigned desc_slot_offset
= img_handle
->desc_slot
* 16;
1900 struct pipe_image_view
*view
= &img_handle
->view
;
1901 uint32_t desc_list
[8];
1903 if (view
->resource
->target
== PIPE_BUFFER
)
1906 memcpy(desc_list
, desc
->list
+ desc_slot_offset
,
1908 si_set_shader_image_desc(sctx
, view
, true,
1909 desc
->list
+ desc_slot_offset
, NULL
);
1911 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1912 sizeof(desc_list
))) {
1913 img_handle
->desc_dirty
= true;
1914 sctx
->bindless_descriptors_dirty
= true;
1918 static void si_update_all_resident_texture_descriptors(struct si_context
*sctx
)
1920 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1921 struct si_texture_handle
*, tex_handle
) {
1922 si_update_bindless_texture_descriptor(sctx
, *tex_handle
);
1925 util_dynarray_foreach(&sctx
->resident_img_handles
,
1926 struct si_image_handle
*, img_handle
) {
1927 si_update_bindless_image_descriptor(sctx
, *img_handle
);
1930 si_upload_bindless_descriptors(sctx
);
1933 /* Update mutable image descriptor fields of all bound textures. */
1934 void si_update_all_texture_descriptors(struct si_context
*sctx
)
1938 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1939 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1940 struct si_images
*images
= &sctx
->images
[shader
];
1944 mask
= images
->enabled_mask
;
1946 unsigned i
= u_bit_scan(&mask
);
1947 struct pipe_image_view
*view
= &images
->views
[i
];
1949 if (!view
->resource
||
1950 view
->resource
->target
== PIPE_BUFFER
)
1953 si_set_shader_image(sctx
, shader
, i
, view
, true);
1956 /* Sampler views. */
1957 mask
= samplers
->enabled_mask
;
1959 unsigned i
= u_bit_scan(&mask
);
1960 struct pipe_sampler_view
*view
= samplers
->views
[i
];
1964 view
->texture
->target
== PIPE_BUFFER
)
1967 si_set_sampler_view(sctx
, shader
, i
,
1968 samplers
->views
[i
], true);
1971 si_update_shader_needs_decompress_mask(sctx
, shader
);
1974 si_update_all_resident_texture_descriptors(sctx
);
1975 si_update_ps_colorbuf0_slot(sctx
);
1978 /* SHADER USER DATA */
1980 static void si_mark_shader_pointers_dirty(struct si_context
*sctx
,
1983 sctx
->shader_pointers_dirty
|=
1984 u_bit_consecutive(SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
,
1985 SI_NUM_SHADER_DESCS
);
1987 if (shader
== PIPE_SHADER_VERTEX
)
1988 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
1990 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
1993 static void si_shader_pointers_begin_new_cs(struct si_context
*sctx
)
1995 sctx
->shader_pointers_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
1996 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
1997 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
1998 sctx
->graphics_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
1999 sctx
->compute_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
2002 /* Set a base register address for user data constants in the given shader.
2003 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
2005 static void si_set_user_data_base(struct si_context
*sctx
,
2006 unsigned shader
, uint32_t new_base
)
2008 uint32_t *base
= &sctx
->shader_pointers
.sh_base
[shader
];
2010 if (*base
!= new_base
) {
2014 si_mark_shader_pointers_dirty(sctx
, shader
);
2016 if (shader
== PIPE_SHADER_VERTEX
)
2017 sctx
->last_vs_state
= ~0;
2022 /* This must be called when these shaders are changed from non-NULL to NULL
2025 * - tessellation control shader
2026 * - tessellation evaluation shader
2028 void si_shader_change_notify(struct si_context
*sctx
)
2030 /* VS can be bound as VS, ES, or LS. */
2031 if (sctx
->tes_shader
.cso
) {
2032 if (sctx
->b
.chip_class
>= GFX9
) {
2033 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2034 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2036 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2037 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2039 } else if (sctx
->gs_shader
.cso
) {
2040 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2041 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2043 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2044 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2047 /* TES can be bound as ES, VS, or not bound. */
2048 if (sctx
->tes_shader
.cso
) {
2049 if (sctx
->gs_shader
.cso
)
2050 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
2051 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2053 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
2054 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2056 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, 0);
2060 static void si_emit_shader_pointer_head(struct radeon_winsys_cs
*cs
,
2062 unsigned pointer_count
)
2064 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
* (HAVE_32BIT_POINTERS
? 1 : 2), 0));
2065 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
2068 static void si_emit_shader_pointer_body(struct si_screen
*sscreen
,
2069 struct radeon_winsys_cs
*cs
,
2072 radeon_emit(cs
, va
);
2074 if (HAVE_32BIT_POINTERS
)
2075 assert(va
== 0 || (va
>> 32) == sscreen
->info
.address32_hi
);
2077 radeon_emit(cs
, va
>> 32);
2080 static void si_emit_shader_pointer(struct si_context
*sctx
,
2081 struct si_descriptors
*desc
,
2084 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
2085 unsigned sh_offset
= sh_base
+ desc
->shader_userdata_offset
;
2087 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2088 si_emit_shader_pointer_body(sctx
->screen
, cs
, desc
->gpu_address
);
2091 static void si_emit_consecutive_shader_pointers(struct si_context
*sctx
,
2092 unsigned pointer_mask
,
2098 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
2099 unsigned mask
= sctx
->shader_pointers_dirty
& pointer_mask
;
2103 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
2105 struct si_descriptors
*descs
= &sctx
->descriptors
[start
];
2106 unsigned sh_offset
= sh_base
+ descs
->shader_userdata_offset
;
2108 si_emit_shader_pointer_head(cs
, sh_offset
, count
);
2109 for (int i
= 0; i
< count
; i
++)
2110 si_emit_shader_pointer_body(sctx
->screen
, cs
,
2111 descs
[i
].gpu_address
);
2115 static void si_emit_disjoint_shader_pointers(struct si_context
*sctx
,
2116 unsigned pointer_mask
,
2122 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
2123 unsigned mask
= sctx
->shader_pointers_dirty
& pointer_mask
;
2126 struct si_descriptors
*descs
= &sctx
->descriptors
[u_bit_scan(&mask
)];
2127 unsigned sh_offset
= sh_base
+ descs
->shader_userdata_offset
;
2129 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2130 si_emit_shader_pointer_body(sctx
->screen
, cs
, descs
->gpu_address
);
2134 static void si_emit_global_shader_pointers(struct si_context
*sctx
,
2135 struct si_descriptors
*descs
)
2137 if (sctx
->b
.chip_class
== GFX9
) {
2138 /* Broadcast it to all shader stages. */
2139 si_emit_shader_pointer(sctx
, descs
,
2140 R_00B530_SPI_SHADER_USER_DATA_COMMON_0
);
2144 si_emit_shader_pointer(sctx
, descs
,
2145 R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2146 si_emit_shader_pointer(sctx
, descs
,
2147 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2148 si_emit_shader_pointer(sctx
, descs
,
2149 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2150 si_emit_shader_pointer(sctx
, descs
,
2151 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2152 si_emit_shader_pointer(sctx
, descs
,
2153 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2154 si_emit_shader_pointer(sctx
, descs
,
2155 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2158 void si_emit_graphics_shader_pointers(struct si_context
*sctx
,
2159 struct r600_atom
*atom
)
2161 uint32_t *sh_base
= sctx
->shader_pointers
.sh_base
;
2163 if (sctx
->shader_pointers_dirty
& (1 << SI_DESCS_RW_BUFFERS
)) {
2164 si_emit_global_shader_pointers(sctx
,
2165 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2168 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(VERTEX
),
2169 sh_base
[PIPE_SHADER_VERTEX
]);
2170 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_EVAL
),
2171 sh_base
[PIPE_SHADER_TESS_EVAL
]);
2172 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(FRAGMENT
),
2173 sh_base
[PIPE_SHADER_FRAGMENT
]);
2174 if (HAVE_32BIT_POINTERS
|| sctx
->b
.chip_class
<= VI
) {
2175 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_CTRL
),
2176 sh_base
[PIPE_SHADER_TESS_CTRL
]);
2177 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(GEOMETRY
),
2178 sh_base
[PIPE_SHADER_GEOMETRY
]);
2180 si_emit_disjoint_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_CTRL
),
2181 sh_base
[PIPE_SHADER_TESS_CTRL
]);
2182 si_emit_disjoint_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(GEOMETRY
),
2183 sh_base
[PIPE_SHADER_GEOMETRY
]);
2186 sctx
->shader_pointers_dirty
&=
2187 ~u_bit_consecutive(SI_DESCS_RW_BUFFERS
, SI_DESCS_FIRST_COMPUTE
);
2189 if (sctx
->vertex_buffer_pointer_dirty
) {
2190 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
2192 /* Find the location of the VB descriptor pointer. */
2193 /* TODO: In the future, the pointer will be packed in unused
2194 * bits of the first 2 VB descriptors. */
2195 unsigned sh_dw_offset
= SI_VS_NUM_USER_SGPR
;
2196 if (sctx
->b
.chip_class
>= GFX9
) {
2197 if (sctx
->tes_shader
.cso
)
2198 sh_dw_offset
= GFX9_TCS_NUM_USER_SGPR
;
2199 else if (sctx
->gs_shader
.cso
)
2200 sh_dw_offset
= GFX9_VSGS_NUM_USER_SGPR
;
2203 unsigned sh_offset
= sh_base
[PIPE_SHADER_VERTEX
] + sh_dw_offset
* 4;
2204 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2205 si_emit_shader_pointer_body(sctx
->screen
, cs
,
2206 sctx
->vb_descriptors_buffer
->gpu_address
+
2207 sctx
->vb_descriptors_offset
);
2208 sctx
->vertex_buffer_pointer_dirty
= false;
2211 if (sctx
->graphics_bindless_pointer_dirty
) {
2212 si_emit_global_shader_pointers(sctx
,
2213 &sctx
->bindless_descriptors
);
2214 sctx
->graphics_bindless_pointer_dirty
= false;
2218 void si_emit_compute_shader_pointers(struct si_context
*sctx
)
2220 unsigned base
= R_00B900_COMPUTE_USER_DATA_0
;
2222 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(COMPUTE
),
2223 R_00B900_COMPUTE_USER_DATA_0
);
2224 sctx
->shader_pointers_dirty
&= ~SI_DESCS_SHADER_MASK(COMPUTE
);
2226 if (sctx
->compute_bindless_pointer_dirty
) {
2227 si_emit_shader_pointer(sctx
, &sctx
->bindless_descriptors
, base
);
2228 sctx
->compute_bindless_pointer_dirty
= false;
2234 static void si_init_bindless_descriptors(struct si_context
*sctx
,
2235 struct si_descriptors
*desc
,
2236 short shader_userdata_rel_index
,
2237 unsigned num_elements
)
2239 MAYBE_UNUSED
unsigned desc_slot
;
2241 si_init_descriptors(desc
, shader_userdata_rel_index
, 16, num_elements
);
2242 sctx
->bindless_descriptors
.num_active_slots
= num_elements
;
2244 /* The first bindless descriptor is stored at slot 1, because 0 is not
2245 * considered to be a valid handle.
2247 sctx
->num_bindless_descriptors
= 1;
2249 /* Track which bindless slots are used (or not). */
2250 util_idalloc_init(&sctx
->bindless_used_slots
);
2251 util_idalloc_resize(&sctx
->bindless_used_slots
, num_elements
);
2253 /* Reserve slot 0 because it's an invalid handle for bindless. */
2254 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2255 assert(desc_slot
== 0);
2258 static void si_release_bindless_descriptors(struct si_context
*sctx
)
2260 si_release_descriptors(&sctx
->bindless_descriptors
);
2261 util_idalloc_fini(&sctx
->bindless_used_slots
);
2264 static unsigned si_get_first_free_bindless_slot(struct si_context
*sctx
)
2266 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2269 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2270 if (desc_slot
>= desc
->num_elements
) {
2271 /* The array of bindless descriptors is full, resize it. */
2272 unsigned slot_size
= desc
->element_dw_size
* 4;
2273 unsigned new_num_elements
= desc
->num_elements
* 2;
2275 desc
->list
= REALLOC(desc
->list
, desc
->num_elements
* slot_size
,
2276 new_num_elements
* slot_size
);
2277 desc
->num_elements
= new_num_elements
;
2278 desc
->num_active_slots
= new_num_elements
;
2286 si_create_bindless_descriptor(struct si_context
*sctx
, uint32_t *desc_list
,
2289 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2290 unsigned desc_slot
, desc_slot_offset
;
2292 /* Find a free slot. */
2293 desc_slot
= si_get_first_free_bindless_slot(sctx
);
2295 /* For simplicity, sampler and image bindless descriptors use fixed
2296 * 16-dword slots for now. Image descriptors only need 8-dword but this
2297 * doesn't really matter because no real apps use image handles.
2299 desc_slot_offset
= desc_slot
* 16;
2301 /* Copy the descriptor into the array. */
2302 memcpy(desc
->list
+ desc_slot_offset
, desc_list
, size
);
2304 /* Re-upload the whole array of bindless descriptors into a new buffer.
2306 if (!si_upload_descriptors(sctx
, desc
))
2309 /* Make sure to re-emit the shader pointers for all stages. */
2310 sctx
->graphics_bindless_pointer_dirty
= true;
2311 sctx
->compute_bindless_pointer_dirty
= true;
2316 static void si_update_bindless_buffer_descriptor(struct si_context
*sctx
,
2318 struct pipe_resource
*resource
,
2322 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2323 struct r600_resource
*buf
= r600_resource(resource
);
2324 unsigned desc_slot_offset
= desc_slot
* 16;
2325 uint32_t *desc_list
= desc
->list
+ desc_slot_offset
+ 4;
2326 uint64_t old_desc_va
;
2328 assert(resource
->target
== PIPE_BUFFER
);
2330 /* Retrieve the old buffer addr from the descriptor. */
2331 old_desc_va
= si_desc_extract_buffer_address(desc_list
);
2333 if (old_desc_va
!= buf
->gpu_address
+ offset
) {
2334 /* The buffer has been invalidated when the handle wasn't
2335 * resident, update the descriptor and the dirty flag.
2337 si_set_buf_desc_address(buf
, offset
, &desc_list
[0]);
2343 static uint64_t si_create_texture_handle(struct pipe_context
*ctx
,
2344 struct pipe_sampler_view
*view
,
2345 const struct pipe_sampler_state
*state
)
2347 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
2348 struct si_context
*sctx
= (struct si_context
*)ctx
;
2349 struct si_texture_handle
*tex_handle
;
2350 struct si_sampler_state
*sstate
;
2351 uint32_t desc_list
[16];
2354 tex_handle
= CALLOC_STRUCT(si_texture_handle
);
2358 memset(desc_list
, 0, sizeof(desc_list
));
2359 si_init_descriptor_list(&desc_list
[0], 16, 1, null_texture_descriptor
);
2361 sstate
= ctx
->create_sampler_state(ctx
, state
);
2367 si_set_sampler_view_desc(sctx
, sview
, sstate
, &desc_list
[0]);
2368 memcpy(&tex_handle
->sstate
, sstate
, sizeof(*sstate
));
2369 ctx
->delete_sampler_state(ctx
, sstate
);
2371 tex_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2373 if (!tex_handle
->desc_slot
) {
2378 handle
= tex_handle
->desc_slot
;
2380 if (!_mesa_hash_table_insert(sctx
->tex_handles
,
2381 (void *)(uintptr_t)handle
,
2387 pipe_sampler_view_reference(&tex_handle
->view
, view
);
2389 r600_resource(sview
->base
.texture
)->texture_handle_allocated
= true;
2394 static void si_delete_texture_handle(struct pipe_context
*ctx
, uint64_t handle
)
2396 struct si_context
*sctx
= (struct si_context
*)ctx
;
2397 struct si_texture_handle
*tex_handle
;
2398 struct hash_entry
*entry
;
2400 entry
= _mesa_hash_table_search(sctx
->tex_handles
,
2401 (void *)(uintptr_t)handle
);
2405 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2407 /* Allow this descriptor slot to be re-used. */
2408 util_idalloc_free(&sctx
->bindless_used_slots
, tex_handle
->desc_slot
);
2410 pipe_sampler_view_reference(&tex_handle
->view
, NULL
);
2411 _mesa_hash_table_remove(sctx
->tex_handles
, entry
);
2415 static void si_make_texture_handle_resident(struct pipe_context
*ctx
,
2416 uint64_t handle
, bool resident
)
2418 struct si_context
*sctx
= (struct si_context
*)ctx
;
2419 struct si_texture_handle
*tex_handle
;
2420 struct si_sampler_view
*sview
;
2421 struct hash_entry
*entry
;
2423 entry
= _mesa_hash_table_search(sctx
->tex_handles
,
2424 (void *)(uintptr_t)handle
);
2428 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2429 sview
= (struct si_sampler_view
*)tex_handle
->view
;
2432 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2433 struct r600_texture
*rtex
=
2434 (struct r600_texture
*)sview
->base
.texture
;
2436 if (depth_needs_decompression(rtex
)) {
2437 util_dynarray_append(
2438 &sctx
->resident_tex_needs_depth_decompress
,
2439 struct si_texture_handle
*,
2443 if (color_needs_decompression(rtex
)) {
2444 util_dynarray_append(
2445 &sctx
->resident_tex_needs_color_decompress
,
2446 struct si_texture_handle
*,
2450 if (rtex
->dcc_offset
&&
2451 p_atomic_read(&rtex
->framebuffers_bound
))
2452 sctx
->need_check_render_feedback
= true;
2454 si_update_bindless_texture_descriptor(sctx
, tex_handle
);
2456 si_update_bindless_buffer_descriptor(sctx
,
2457 tex_handle
->desc_slot
,
2458 sview
->base
.texture
,
2459 sview
->base
.u
.buf
.offset
,
2460 &tex_handle
->desc_dirty
);
2463 /* Re-upload the descriptor if it has been updated while it
2466 if (tex_handle
->desc_dirty
)
2467 sctx
->bindless_descriptors_dirty
= true;
2469 /* Add the texture handle to the per-context list. */
2470 util_dynarray_append(&sctx
->resident_tex_handles
,
2471 struct si_texture_handle
*, tex_handle
);
2473 /* Add the buffers to the current CS in case si_begin_new_cs()
2474 * is not going to be called.
2476 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2478 sview
->is_stencil_sampler
, false);
2480 /* Remove the texture handle from the per-context list. */
2481 util_dynarray_delete_unordered(&sctx
->resident_tex_handles
,
2482 struct si_texture_handle
*,
2485 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2486 util_dynarray_delete_unordered(
2487 &sctx
->resident_tex_needs_depth_decompress
,
2488 struct si_texture_handle
*, tex_handle
);
2490 util_dynarray_delete_unordered(
2491 &sctx
->resident_tex_needs_color_decompress
,
2492 struct si_texture_handle
*, tex_handle
);
2497 static uint64_t si_create_image_handle(struct pipe_context
*ctx
,
2498 const struct pipe_image_view
*view
)
2500 struct si_context
*sctx
= (struct si_context
*)ctx
;
2501 struct si_image_handle
*img_handle
;
2502 uint32_t desc_list
[8];
2505 if (!view
|| !view
->resource
)
2508 img_handle
= CALLOC_STRUCT(si_image_handle
);
2512 memset(desc_list
, 0, sizeof(desc_list
));
2513 si_init_descriptor_list(&desc_list
[0], 8, 1, null_image_descriptor
);
2515 si_set_shader_image_desc(sctx
, view
, false, &desc_list
[0], NULL
);
2517 img_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2519 if (!img_handle
->desc_slot
) {
2524 handle
= img_handle
->desc_slot
;
2526 if (!_mesa_hash_table_insert(sctx
->img_handles
,
2527 (void *)(uintptr_t)handle
,
2533 util_copy_image_view(&img_handle
->view
, view
);
2535 r600_resource(view
->resource
)->image_handle_allocated
= true;
2540 static void si_delete_image_handle(struct pipe_context
*ctx
, uint64_t handle
)
2542 struct si_context
*sctx
= (struct si_context
*)ctx
;
2543 struct si_image_handle
*img_handle
;
2544 struct hash_entry
*entry
;
2546 entry
= _mesa_hash_table_search(sctx
->img_handles
,
2547 (void *)(uintptr_t)handle
);
2551 img_handle
= (struct si_image_handle
*)entry
->data
;
2553 util_copy_image_view(&img_handle
->view
, NULL
);
2554 _mesa_hash_table_remove(sctx
->img_handles
, entry
);
2558 static void si_make_image_handle_resident(struct pipe_context
*ctx
,
2559 uint64_t handle
, unsigned access
,
2562 struct si_context
*sctx
= (struct si_context
*)ctx
;
2563 struct si_image_handle
*img_handle
;
2564 struct pipe_image_view
*view
;
2565 struct r600_resource
*res
;
2566 struct hash_entry
*entry
;
2568 entry
= _mesa_hash_table_search(sctx
->img_handles
,
2569 (void *)(uintptr_t)handle
);
2573 img_handle
= (struct si_image_handle
*)entry
->data
;
2574 view
= &img_handle
->view
;
2575 res
= (struct r600_resource
*)view
->resource
;
2578 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2579 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
2580 unsigned level
= view
->u
.tex
.level
;
2582 if (color_needs_decompression(rtex
)) {
2583 util_dynarray_append(
2584 &sctx
->resident_img_needs_color_decompress
,
2585 struct si_image_handle
*,
2589 if (vi_dcc_enabled(rtex
, level
) &&
2590 p_atomic_read(&rtex
->framebuffers_bound
))
2591 sctx
->need_check_render_feedback
= true;
2593 si_update_bindless_image_descriptor(sctx
, img_handle
);
2595 si_update_bindless_buffer_descriptor(sctx
,
2596 img_handle
->desc_slot
,
2599 &img_handle
->desc_dirty
);
2602 /* Re-upload the descriptor if it has been updated while it
2605 if (img_handle
->desc_dirty
)
2606 sctx
->bindless_descriptors_dirty
= true;
2608 /* Add the image handle to the per-context list. */
2609 util_dynarray_append(&sctx
->resident_img_handles
,
2610 struct si_image_handle
*, img_handle
);
2612 /* Add the buffers to the current CS in case si_begin_new_cs()
2613 * is not going to be called.
2615 si_sampler_view_add_buffer(sctx
, view
->resource
,
2616 (access
& PIPE_IMAGE_ACCESS_WRITE
) ?
2617 RADEON_USAGE_READWRITE
:
2618 RADEON_USAGE_READ
, false, false);
2620 /* Remove the image handle from the per-context list. */
2621 util_dynarray_delete_unordered(&sctx
->resident_img_handles
,
2622 struct si_image_handle
*,
2625 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2626 util_dynarray_delete_unordered(
2627 &sctx
->resident_img_needs_color_decompress
,
2628 struct si_image_handle
*,
2635 void si_all_resident_buffers_begin_new_cs(struct si_context
*sctx
)
2637 unsigned num_resident_tex_handles
, num_resident_img_handles
;
2639 num_resident_tex_handles
= sctx
->resident_tex_handles
.size
/
2640 sizeof(struct si_texture_handle
*);
2641 num_resident_img_handles
= sctx
->resident_img_handles
.size
/
2642 sizeof(struct si_image_handle
*);
2644 /* Add all resident texture handles. */
2645 util_dynarray_foreach(&sctx
->resident_tex_handles
,
2646 struct si_texture_handle
*, tex_handle
) {
2647 struct si_sampler_view
*sview
=
2648 (struct si_sampler_view
*)(*tex_handle
)->view
;
2650 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2652 sview
->is_stencil_sampler
, false);
2655 /* Add all resident image handles. */
2656 util_dynarray_foreach(&sctx
->resident_img_handles
,
2657 struct si_image_handle
*, img_handle
) {
2658 struct pipe_image_view
*view
= &(*img_handle
)->view
;
2660 si_sampler_view_add_buffer(sctx
, view
->resource
,
2661 RADEON_USAGE_READWRITE
,
2665 sctx
->b
.num_resident_handles
+= num_resident_tex_handles
+
2666 num_resident_img_handles
;
2669 /* INIT/DEINIT/UPLOAD */
2671 void si_init_all_descriptors(struct si_context
*sctx
)
2675 #if !HAVE_32BIT_POINTERS
2676 STATIC_ASSERT(GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES
% 2 == 0);
2679 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2680 bool is_2nd
= sctx
->b
.chip_class
>= GFX9
&&
2681 (i
== PIPE_SHADER_TESS_CTRL
||
2682 i
== PIPE_SHADER_GEOMETRY
);
2683 unsigned num_sampler_slots
= SI_NUM_IMAGES
/ 2 + SI_NUM_SAMPLERS
;
2684 unsigned num_buffer_slots
= SI_NUM_SHADER_BUFFERS
+ SI_NUM_CONST_BUFFERS
;
2686 struct si_descriptors
*desc
;
2689 if (i
== PIPE_SHADER_TESS_CTRL
) {
2690 rel_dw_offset
= (R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
-
2691 R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2692 } else { /* PIPE_SHADER_GEOMETRY */
2693 rel_dw_offset
= (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
-
2694 R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2697 rel_dw_offset
= SI_SGPR_CONST_AND_SHADER_BUFFERS
;
2699 desc
= si_const_and_shader_buffer_descriptors(sctx
, i
);
2700 si_init_buffer_resources(&sctx
->const_and_shader_buffers
[i
], desc
,
2701 num_buffer_slots
, rel_dw_offset
,
2702 RADEON_USAGE_READWRITE
,
2704 RADEON_PRIO_SHADER_RW_BUFFER
,
2705 RADEON_PRIO_CONST_BUFFER
);
2706 desc
->slot_index_to_bind_directly
= si_get_constbuf_slot(0);
2709 #if HAVE_32BIT_POINTERS
2710 if (i
== PIPE_SHADER_TESS_CTRL
) {
2711 rel_dw_offset
= (R_00B40C_SPI_SHADER_USER_DATA_ADDR_HI_HS
-
2712 R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2713 } else { /* PIPE_SHADER_GEOMETRY */
2714 rel_dw_offset
= (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS
-
2715 R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2718 rel_dw_offset
= GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES
;
2721 rel_dw_offset
= SI_SGPR_SAMPLERS_AND_IMAGES
;
2724 desc
= si_sampler_and_image_descriptors(sctx
, i
);
2725 si_init_descriptors(desc
, rel_dw_offset
, 16, num_sampler_slots
);
2728 for (j
= 0; j
< SI_NUM_IMAGES
; j
++)
2729 memcpy(desc
->list
+ j
* 8, null_image_descriptor
, 8 * 4);
2730 for (; j
< SI_NUM_IMAGES
+ SI_NUM_SAMPLERS
* 2; j
++)
2731 memcpy(desc
->list
+ j
* 8, null_texture_descriptor
, 8 * 4);
2734 si_init_buffer_resources(&sctx
->rw_buffers
,
2735 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
],
2736 SI_NUM_RW_BUFFERS
, SI_SGPR_RW_BUFFERS
,
2737 /* The second set of usage/priority is used by
2738 * const buffers in RW buffer slots. */
2739 RADEON_USAGE_READWRITE
, RADEON_USAGE_READ
,
2740 RADEON_PRIO_SHADER_RINGS
, RADEON_PRIO_CONST_BUFFER
);
2741 sctx
->descriptors
[SI_DESCS_RW_BUFFERS
].num_active_slots
= SI_NUM_RW_BUFFERS
;
2743 /* Initialize an array of 1024 bindless descriptors, when the limit is
2744 * reached, just make it larger and re-upload the whole array.
2746 si_init_bindless_descriptors(sctx
, &sctx
->bindless_descriptors
,
2747 SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES
,
2750 sctx
->descriptors_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2752 /* Set pipe_context functions. */
2753 sctx
->b
.b
.bind_sampler_states
= si_bind_sampler_states
;
2754 sctx
->b
.b
.set_shader_images
= si_set_shader_images
;
2755 sctx
->b
.b
.set_constant_buffer
= si_pipe_set_constant_buffer
;
2756 sctx
->b
.b
.set_polygon_stipple
= si_set_polygon_stipple
;
2757 sctx
->b
.b
.set_shader_buffers
= si_set_shader_buffers
;
2758 sctx
->b
.b
.set_sampler_views
= si_set_sampler_views
;
2759 sctx
->b
.b
.create_texture_handle
= si_create_texture_handle
;
2760 sctx
->b
.b
.delete_texture_handle
= si_delete_texture_handle
;
2761 sctx
->b
.b
.make_texture_handle_resident
= si_make_texture_handle_resident
;
2762 sctx
->b
.b
.create_image_handle
= si_create_image_handle
;
2763 sctx
->b
.b
.delete_image_handle
= si_delete_image_handle
;
2764 sctx
->b
.b
.make_image_handle_resident
= si_make_image_handle_resident
;
2766 /* Shader user data. */
2767 si_init_atom(sctx
, &sctx
->shader_pointers
.atom
, &sctx
->atoms
.s
.shader_pointers
,
2768 si_emit_graphics_shader_pointers
);
2770 /* Set default and immutable mappings. */
2771 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2773 if (sctx
->b
.chip_class
>= GFX9
) {
2774 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2775 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2776 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2777 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2779 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2780 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2781 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2782 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2784 si_set_user_data_base(sctx
, PIPE_SHADER_FRAGMENT
, R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2787 static bool si_upload_shader_descriptors(struct si_context
*sctx
, unsigned mask
)
2789 unsigned dirty
= sctx
->descriptors_dirty
& mask
;
2791 /* Assume nothing will go wrong: */
2792 sctx
->shader_pointers_dirty
|= dirty
;
2795 unsigned i
= u_bit_scan(&dirty
);
2797 if (!si_upload_descriptors(sctx
, &sctx
->descriptors
[i
]))
2801 sctx
->descriptors_dirty
&= ~mask
;
2803 si_upload_bindless_descriptors(sctx
);
2808 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
)
2810 const unsigned mask
= u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE
);
2811 return si_upload_shader_descriptors(sctx
, mask
);
2814 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
)
2816 /* Does not update rw_buffers as that is not needed for compute shaders
2817 * and the input buffer is using the same SGPR's anyway.
2819 const unsigned mask
= u_bit_consecutive(SI_DESCS_FIRST_COMPUTE
,
2820 SI_NUM_DESCS
- SI_DESCS_FIRST_COMPUTE
);
2821 return si_upload_shader_descriptors(sctx
, mask
);
2824 void si_release_all_descriptors(struct si_context
*sctx
)
2828 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2829 si_release_buffer_resources(&sctx
->const_and_shader_buffers
[i
],
2830 si_const_and_shader_buffer_descriptors(sctx
, i
));
2831 si_release_sampler_views(&sctx
->samplers
[i
]);
2832 si_release_image_views(&sctx
->images
[i
]);
2834 si_release_buffer_resources(&sctx
->rw_buffers
,
2835 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2836 for (i
= 0; i
< SI_NUM_VERTEX_BUFFERS
; i
++)
2837 pipe_vertex_buffer_unreference(&sctx
->vertex_buffer
[i
]);
2839 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2840 si_release_descriptors(&sctx
->descriptors
[i
]);
2842 r600_resource_reference(&sctx
->vb_descriptors_buffer
, NULL
);
2843 sctx
->vb_descriptors_gpu_list
= NULL
; /* points into a mapped buffer */
2845 si_release_bindless_descriptors(sctx
);
2848 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
)
2852 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2853 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[i
]);
2854 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[i
]);
2855 si_image_views_begin_new_cs(sctx
, &sctx
->images
[i
]);
2857 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2858 si_vertex_buffers_begin_new_cs(sctx
);
2860 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2861 si_descriptors_begin_new_cs(sctx
, &sctx
->descriptors
[i
]);
2862 si_descriptors_begin_new_cs(sctx
, &sctx
->bindless_descriptors
);
2864 si_shader_pointers_begin_new_cs(sctx
);
2867 void si_set_active_descriptors(struct si_context
*sctx
, unsigned desc_idx
,
2868 uint64_t new_active_mask
)
2870 struct si_descriptors
*desc
= &sctx
->descriptors
[desc_idx
];
2872 /* Ignore no-op updates and updates that disable all slots. */
2873 if (!new_active_mask
||
2874 new_active_mask
== u_bit_consecutive64(desc
->first_active_slot
,
2875 desc
->num_active_slots
))
2879 u_bit_scan_consecutive_range64(&new_active_mask
, &first
, &count
);
2880 assert(new_active_mask
== 0);
2882 /* Upload/dump descriptors if slots are being enabled. */
2883 if (first
< desc
->first_active_slot
||
2884 first
+ count
> desc
->first_active_slot
+ desc
->num_active_slots
)
2885 sctx
->descriptors_dirty
|= 1u << desc_idx
;
2887 desc
->first_active_slot
= first
;
2888 desc
->num_active_slots
= count
;
2891 void si_set_active_descriptors_for_shader(struct si_context
*sctx
,
2892 struct si_shader_selector
*sel
)
2897 si_set_active_descriptors(sctx
,
2898 si_const_and_shader_buffer_descriptors_idx(sel
->type
),
2899 sel
->active_const_and_shader_buffers
);
2900 si_set_active_descriptors(sctx
,
2901 si_sampler_and_image_descriptors_idx(sel
->type
),
2902 sel
->active_samplers_and_images
);