2 * Copyright 2013 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 /* Resource binding slots and sampler states (each described with 8 or
26 * 4 dwords) are stored in lists in memory which is accessed by shaders
27 * using scalar load instructions.
29 * This file is responsible for managing such lists. It keeps a copy of all
30 * descriptors in CPU memory and re-uploads a whole list if some slots have
33 * This code is also reponsible for updating shader pointers to those lists.
35 * Note that CP DMA can't be used for updating the lists, because a GPU hang
36 * could leave the list in a mid-IB state and the next IB would get wrong
37 * descriptors and the whole context would be unusable at that point.
38 * (Note: The register shadowing can't be used due to the same reason)
40 * Also, uploading descriptors to newly allocated memory doesn't require
44 * Possible scenarios for one 16 dword image+sampler slot:
46 * | Image | w/ FMASK | Buffer | NULL
47 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
48 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
49 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
50 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
52 * FMASK implies MSAA, therefore no sampler state.
53 * Sampler states are never unbound except when FMASK is bound.
60 #include "util/hash_table.h"
61 #include "util/u_idalloc.h"
62 #include "util/u_format.h"
63 #include "util/u_memory.h"
64 #include "util/u_upload_mgr.h"
67 /* NULL image and buffer descriptor for textures (alpha = 1) and images
70 * For images, all fields must be zero except for the swizzle, which
71 * supports arbitrary combinations of 0s and 1s. The texture type must be
72 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
74 * For buffers, all fields must be zero. If they are not, the hw hangs.
76 * This is the only reason why the buffer descriptor must be in words [4:7].
78 static uint32_t null_texture_descriptor
[8] = {
82 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1
) |
83 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
84 /* the rest must contain zeros, which is also used by the buffer
88 static uint32_t null_image_descriptor
[8] = {
92 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
93 /* the rest must contain zeros, which is also used by the buffer
97 static uint64_t si_desc_extract_buffer_address(const uint32_t *desc
)
99 uint64_t va
= desc
[0] |
100 ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc
[1]) << 32);
102 /* Sign-extend the 48-bit address. */
104 va
= (int64_t)va
>> 16;
108 static void si_init_descriptor_list(uint32_t *desc_list
,
109 unsigned element_dw_size
,
110 unsigned num_elements
,
111 const uint32_t *null_descriptor
)
115 /* Initialize the array to NULL descriptors if the element size is 8. */
116 if (null_descriptor
) {
117 assert(element_dw_size
% 8 == 0);
118 for (i
= 0; i
< num_elements
* element_dw_size
/ 8; i
++)
119 memcpy(desc_list
+ i
* 8, null_descriptor
, 8 * 4);
123 static void si_init_descriptors(struct si_descriptors
*desc
,
124 short shader_userdata_rel_index
,
125 unsigned element_dw_size
,
126 unsigned num_elements
)
128 desc
->list
= CALLOC(num_elements
, element_dw_size
* 4);
129 desc
->element_dw_size
= element_dw_size
;
130 desc
->num_elements
= num_elements
;
131 desc
->shader_userdata_offset
= shader_userdata_rel_index
* 4;
132 desc
->slot_index_to_bind_directly
= -1;
135 static void si_release_descriptors(struct si_descriptors
*desc
)
137 si_resource_reference(&desc
->buffer
, NULL
);
141 static bool si_upload_descriptors(struct si_context
*sctx
,
142 struct si_descriptors
*desc
)
144 unsigned slot_size
= desc
->element_dw_size
* 4;
145 unsigned first_slot_offset
= desc
->first_active_slot
* slot_size
;
146 unsigned upload_size
= desc
->num_active_slots
* slot_size
;
148 /* Skip the upload if no shader is using the descriptors. dirty_mask
149 * will stay dirty and the descriptors will be uploaded when there is
150 * a shader using them.
155 /* If there is just one active descriptor, bind it directly. */
156 if ((int)desc
->first_active_slot
== desc
->slot_index_to_bind_directly
&&
157 desc
->num_active_slots
== 1) {
158 uint32_t *descriptor
= &desc
->list
[desc
->slot_index_to_bind_directly
*
159 desc
->element_dw_size
];
161 /* The buffer is already in the buffer list. */
162 si_resource_reference(&desc
->buffer
, NULL
);
163 desc
->gpu_list
= NULL
;
164 desc
->gpu_address
= si_desc_extract_buffer_address(descriptor
);
165 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
170 unsigned buffer_offset
;
171 u_upload_alloc(sctx
->b
.const_uploader
, first_slot_offset
, upload_size
,
172 si_optimal_tcc_alignment(sctx
, upload_size
),
173 &buffer_offset
, (struct pipe_resource
**)&desc
->buffer
,
176 desc
->gpu_address
= 0;
177 return false; /* skip the draw call */
180 util_memcpy_cpu_to_le32(ptr
, (char*)desc
->list
+ first_slot_offset
,
182 desc
->gpu_list
= ptr
- first_slot_offset
/ 4;
184 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, desc
->buffer
,
185 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
187 /* The shader pointer should point to slot 0. */
188 buffer_offset
-= first_slot_offset
;
189 desc
->gpu_address
= desc
->buffer
->gpu_address
+ buffer_offset
;
191 assert(desc
->buffer
->flags
& RADEON_FLAG_32BIT
);
192 assert((desc
->buffer
->gpu_address
>> 32) == sctx
->screen
->info
.address32_hi
);
193 assert((desc
->gpu_address
>> 32) == sctx
->screen
->info
.address32_hi
);
195 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
200 si_descriptors_begin_new_cs(struct si_context
*sctx
, struct si_descriptors
*desc
)
205 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, desc
->buffer
,
206 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
211 static inline enum radeon_bo_priority
212 si_get_sampler_view_priority(struct si_resource
*res
)
214 if (res
->b
.b
.target
== PIPE_BUFFER
)
215 return RADEON_PRIO_SAMPLER_BUFFER
;
217 if (res
->b
.b
.nr_samples
> 1)
218 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA
;
220 return RADEON_PRIO_SAMPLER_TEXTURE
;
224 si_sampler_and_image_descriptors_idx(unsigned shader
)
226 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
227 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
;
230 static struct si_descriptors
*
231 si_sampler_and_image_descriptors(struct si_context
*sctx
, unsigned shader
)
233 return &sctx
->descriptors
[si_sampler_and_image_descriptors_idx(shader
)];
236 static void si_release_sampler_views(struct si_samplers
*samplers
)
240 for (i
= 0; i
< ARRAY_SIZE(samplers
->views
); i
++) {
241 pipe_sampler_view_reference(&samplers
->views
[i
], NULL
);
245 static void si_sampler_view_add_buffer(struct si_context
*sctx
,
246 struct pipe_resource
*resource
,
247 enum radeon_bo_usage usage
,
248 bool is_stencil_sampler
,
251 struct si_texture
*tex
= (struct si_texture
*)resource
;
252 enum radeon_bo_priority priority
;
257 /* Use the flushed depth texture if direct sampling is unsupported. */
258 if (resource
->target
!= PIPE_BUFFER
&&
259 tex
->is_depth
&& !si_can_sample_zs(tex
, is_stencil_sampler
))
260 tex
= tex
->flushed_depth_texture
;
262 priority
= si_get_sampler_view_priority(&tex
->buffer
);
263 radeon_add_to_gfx_buffer_list_check_mem(sctx
, &tex
->buffer
, usage
, priority
,
266 if (resource
->target
== PIPE_BUFFER
)
269 /* Add separate DCC. */
270 if (tex
->dcc_separate_buffer
) {
271 radeon_add_to_gfx_buffer_list_check_mem(sctx
, tex
->dcc_separate_buffer
,
272 usage
, RADEON_PRIO_SEPARATE_META
, check_mem
);
276 static void si_sampler_views_begin_new_cs(struct si_context
*sctx
,
277 struct si_samplers
*samplers
)
279 unsigned mask
= samplers
->enabled_mask
;
281 /* Add buffers to the CS. */
283 int i
= u_bit_scan(&mask
);
284 struct si_sampler_view
*sview
= (struct si_sampler_view
*)samplers
->views
[i
];
286 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
288 sview
->is_stencil_sampler
, false);
292 /* Set buffer descriptor fields that can be changed by reallocations. */
293 static void si_set_buf_desc_address(struct si_resource
*buf
,
294 uint64_t offset
, uint32_t *state
)
296 uint64_t va
= buf
->gpu_address
+ offset
;
299 state
[1] &= C_008F04_BASE_ADDRESS_HI
;
300 state
[1] |= S_008F04_BASE_ADDRESS_HI(va
>> 32);
303 /* Set texture descriptor fields that can be changed by reallocations.
306 * \param base_level_info information of the level of BASE_ADDRESS
307 * \param base_level the level of BASE_ADDRESS
308 * \param first_level pipe_sampler_view.u.tex.first_level
309 * \param block_width util_format_get_blockwidth()
310 * \param is_stencil select between separate Z & Stencil
311 * \param state descriptor to update
313 void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen
,
314 struct si_texture
*tex
,
315 const struct legacy_surf_level
*base_level_info
,
316 unsigned base_level
, unsigned first_level
,
317 unsigned block_width
, bool is_stencil
,
320 uint64_t va
, meta_va
= 0;
322 if (tex
->is_depth
&& !si_can_sample_zs(tex
, is_stencil
)) {
323 tex
= tex
->flushed_depth_texture
;
327 va
= tex
->buffer
.gpu_address
;
329 if (sscreen
->info
.chip_class
>= GFX9
) {
330 /* Only stencil_offset needs to be added here. */
332 va
+= tex
->surface
.u
.gfx9
.stencil_offset
;
334 va
+= tex
->surface
.u
.gfx9
.surf_offset
;
336 va
+= base_level_info
->offset
;
340 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
341 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
343 /* Only macrotiled modes can set tile swizzle.
344 * GFX9 doesn't use (legacy) base_level_info.
346 if (sscreen
->info
.chip_class
>= GFX9
||
347 base_level_info
->mode
== RADEON_SURF_MODE_2D
)
348 state
[0] |= tex
->surface
.tile_swizzle
;
350 if (sscreen
->info
.chip_class
>= VI
) {
351 state
[6] &= C_008F28_COMPRESSION_EN
;
354 if (vi_dcc_enabled(tex
, first_level
)) {
355 meta_va
= (!tex
->dcc_separate_buffer
? tex
->buffer
.gpu_address
: 0) +
358 if (sscreen
->info
.chip_class
== VI
) {
359 meta_va
+= base_level_info
->dcc_offset
;
360 assert(base_level_info
->mode
== RADEON_SURF_MODE_2D
);
363 meta_va
|= (uint32_t)tex
->surface
.tile_swizzle
<< 8;
364 } else if (vi_tc_compat_htile_enabled(tex
, first_level
)) {
365 meta_va
= tex
->buffer
.gpu_address
+ tex
->htile_offset
;
369 state
[6] |= S_008F28_COMPRESSION_EN(1);
370 state
[7] = meta_va
>> 8;
374 if (sscreen
->info
.chip_class
>= GFX9
) {
375 state
[3] &= C_008F1C_SW_MODE
;
376 state
[4] &= C_008F20_PITCH_GFX9
;
379 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
380 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.stencil
.epitch
);
382 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
);
383 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.surf
.epitch
);
386 state
[5] &= C_008F24_META_DATA_ADDRESS
&
387 C_008F24_META_PIPE_ALIGNED
&
388 C_008F24_META_RB_ALIGNED
;
390 struct gfx9_surf_meta_flags meta
;
393 meta
= tex
->surface
.u
.gfx9
.dcc
;
395 meta
= tex
->surface
.u
.gfx9
.htile
;
397 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
398 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
399 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
403 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
404 unsigned index
= si_tile_mode_index(tex
, base_level
, is_stencil
);
406 state
[3] &= C_008F1C_TILING_INDEX
;
407 state
[3] |= S_008F1C_TILING_INDEX(index
);
408 state
[4] &= C_008F20_PITCH_GFX6
;
409 state
[4] |= S_008F20_PITCH_GFX6(pitch
- 1);
413 static void si_set_sampler_state_desc(struct si_sampler_state
*sstate
,
414 struct si_sampler_view
*sview
,
415 struct si_texture
*tex
,
418 if (sview
&& sview
->is_integer
)
419 memcpy(desc
, sstate
->integer_val
, 4*4);
420 else if (tex
&& tex
->upgraded_depth
&&
421 (!sview
|| !sview
->is_stencil_sampler
))
422 memcpy(desc
, sstate
->upgraded_depth_val
, 4*4);
424 memcpy(desc
, sstate
->val
, 4*4);
427 static void si_set_sampler_view_desc(struct si_context
*sctx
,
428 struct si_sampler_view
*sview
,
429 struct si_sampler_state
*sstate
,
432 struct pipe_sampler_view
*view
= &sview
->base
;
433 struct si_texture
*tex
= (struct si_texture
*)view
->texture
;
434 bool is_buffer
= tex
->buffer
.b
.b
.target
== PIPE_BUFFER
;
436 if (unlikely(!is_buffer
&& sview
->dcc_incompatible
)) {
437 if (vi_dcc_enabled(tex
, view
->u
.tex
.first_level
))
438 if (!si_texture_disable_dcc(sctx
, tex
))
439 si_decompress_dcc(sctx
, tex
);
441 sview
->dcc_incompatible
= false;
444 assert(tex
); /* views with texture == NULL aren't supported */
445 memcpy(desc
, sview
->state
, 8*4);
448 si_set_buf_desc_address(&tex
->buffer
,
449 sview
->base
.u
.buf
.offset
,
452 bool is_separate_stencil
= tex
->db_compatible
&&
453 sview
->is_stencil_sampler
;
455 si_set_mutable_tex_desc_fields(sctx
->screen
, tex
,
456 sview
->base_level_info
,
458 sview
->base
.u
.tex
.first_level
,
464 if (!is_buffer
&& tex
->surface
.fmask_size
) {
465 memcpy(desc
+ 8, sview
->fmask_state
, 8*4);
467 /* Disable FMASK and bind sampler state in [12:15]. */
468 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
471 si_set_sampler_state_desc(sstate
, sview
,
472 is_buffer
? NULL
: tex
,
477 static bool color_needs_decompression(struct si_texture
*tex
)
479 return tex
->surface
.fmask_size
||
480 (tex
->dirty_level_mask
&&
481 (tex
->cmask_buffer
|| tex
->dcc_offset
));
484 static bool depth_needs_decompression(struct si_texture
*tex
)
486 /* If the depth/stencil texture is TC-compatible, no decompression
487 * will be done. The decompression function will only flush DB caches
488 * to make it coherent with shaders. That's necessary because the driver
489 * doesn't flush DB caches in any other case.
491 return tex
->db_compatible
;
494 static void si_set_sampler_view(struct si_context
*sctx
,
496 unsigned slot
, struct pipe_sampler_view
*view
,
497 bool disallow_early_out
)
499 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
500 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
501 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(sctx
, shader
);
502 unsigned desc_slot
= si_get_sampler_slot(slot
);
503 uint32_t *desc
= descs
->list
+ desc_slot
* 16;
505 if (samplers
->views
[slot
] == view
&& !disallow_early_out
)
509 struct si_texture
*tex
= (struct si_texture
*)view
->texture
;
511 si_set_sampler_view_desc(sctx
, sview
,
512 samplers
->sampler_states
[slot
], desc
);
514 if (tex
->buffer
.b
.b
.target
== PIPE_BUFFER
) {
515 tex
->buffer
.bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
516 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
517 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
519 if (depth_needs_decompression(tex
)) {
520 samplers
->needs_depth_decompress_mask
|= 1u << slot
;
522 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
524 if (color_needs_decompression(tex
)) {
525 samplers
->needs_color_decompress_mask
|= 1u << slot
;
527 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
530 if (tex
->dcc_offset
&&
531 p_atomic_read(&tex
->framebuffers_bound
))
532 sctx
->need_check_render_feedback
= true;
535 pipe_sampler_view_reference(&samplers
->views
[slot
], view
);
536 samplers
->enabled_mask
|= 1u << slot
;
538 /* Since this can flush, it must be done after enabled_mask is
540 si_sampler_view_add_buffer(sctx
, view
->texture
,
542 sview
->is_stencil_sampler
, true);
544 pipe_sampler_view_reference(&samplers
->views
[slot
], NULL
);
545 memcpy(desc
, null_texture_descriptor
, 8*4);
546 /* Only clear the lower dwords of FMASK. */
547 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
548 /* Re-set the sampler state if we are transitioning from FMASK. */
549 if (samplers
->sampler_states
[slot
])
550 si_set_sampler_state_desc(samplers
->sampler_states
[slot
], NULL
, NULL
,
553 samplers
->enabled_mask
&= ~(1u << slot
);
554 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
555 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
558 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
561 static void si_update_shader_needs_decompress_mask(struct si_context
*sctx
,
564 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
565 unsigned shader_bit
= 1 << shader
;
567 if (samplers
->needs_depth_decompress_mask
||
568 samplers
->needs_color_decompress_mask
||
569 sctx
->images
[shader
].needs_color_decompress_mask
)
570 sctx
->shader_needs_decompress_mask
|= shader_bit
;
572 sctx
->shader_needs_decompress_mask
&= ~shader_bit
;
575 static void si_set_sampler_views(struct pipe_context
*ctx
,
576 enum pipe_shader_type shader
, unsigned start
,
578 struct pipe_sampler_view
**views
)
580 struct si_context
*sctx
= (struct si_context
*)ctx
;
583 if (!count
|| shader
>= SI_NUM_SHADERS
)
587 for (i
= 0; i
< count
; i
++)
588 si_set_sampler_view(sctx
, shader
, start
+ i
, views
[i
], false);
590 for (i
= 0; i
< count
; i
++)
591 si_set_sampler_view(sctx
, shader
, start
+ i
, NULL
, false);
594 si_update_shader_needs_decompress_mask(sctx
, shader
);
598 si_samplers_update_needs_color_decompress_mask(struct si_samplers
*samplers
)
600 unsigned mask
= samplers
->enabled_mask
;
603 int i
= u_bit_scan(&mask
);
604 struct pipe_resource
*res
= samplers
->views
[i
]->texture
;
606 if (res
&& res
->target
!= PIPE_BUFFER
) {
607 struct si_texture
*tex
= (struct si_texture
*)res
;
609 if (color_needs_decompression(tex
)) {
610 samplers
->needs_color_decompress_mask
|= 1u << i
;
612 samplers
->needs_color_decompress_mask
&= ~(1u << i
);
621 si_release_image_views(struct si_images
*images
)
625 for (i
= 0; i
< SI_NUM_IMAGES
; ++i
) {
626 struct pipe_image_view
*view
= &images
->views
[i
];
628 pipe_resource_reference(&view
->resource
, NULL
);
633 si_image_views_begin_new_cs(struct si_context
*sctx
, struct si_images
*images
)
635 uint mask
= images
->enabled_mask
;
637 /* Add buffers to the CS. */
639 int i
= u_bit_scan(&mask
);
640 struct pipe_image_view
*view
= &images
->views
[i
];
642 assert(view
->resource
);
644 si_sampler_view_add_buffer(sctx
, view
->resource
,
645 RADEON_USAGE_READWRITE
, false, false);
650 si_disable_shader_image(struct si_context
*ctx
, unsigned shader
, unsigned slot
)
652 struct si_images
*images
= &ctx
->images
[shader
];
654 if (images
->enabled_mask
& (1u << slot
)) {
655 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
656 unsigned desc_slot
= si_get_image_slot(slot
);
658 pipe_resource_reference(&images
->views
[slot
].resource
, NULL
);
659 images
->needs_color_decompress_mask
&= ~(1 << slot
);
661 memcpy(descs
->list
+ desc_slot
*8, null_image_descriptor
, 8*4);
662 images
->enabled_mask
&= ~(1u << slot
);
663 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
668 si_mark_image_range_valid(const struct pipe_image_view
*view
)
670 struct si_resource
*res
= si_resource(view
->resource
);
672 if (res
->b
.b
.target
!= PIPE_BUFFER
)
675 util_range_add(&res
->valid_buffer_range
,
677 view
->u
.buf
.offset
+ view
->u
.buf
.size
);
680 static void si_set_shader_image_desc(struct si_context
*ctx
,
681 const struct pipe_image_view
*view
,
682 bool skip_decompress
,
683 uint32_t *desc
, uint32_t *fmask_desc
)
685 struct si_screen
*screen
= ctx
->screen
;
686 struct si_resource
*res
;
688 res
= si_resource(view
->resource
);
690 if (res
->b
.b
.target
== PIPE_BUFFER
||
691 view
->shader_access
& SI_IMAGE_ACCESS_AS_BUFFER
) {
692 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
693 si_mark_image_range_valid(view
);
695 si_make_buffer_descriptor(screen
, res
,
698 view
->u
.buf
.size
, desc
);
699 si_set_buf_desc_address(res
, view
->u
.buf
.offset
, desc
+ 4);
701 static const unsigned char swizzle
[4] = { 0, 1, 2, 3 };
702 struct si_texture
*tex
= (struct si_texture
*)res
;
703 unsigned level
= view
->u
.tex
.level
;
704 unsigned width
, height
, depth
, hw_level
;
705 bool uses_dcc
= vi_dcc_enabled(tex
, level
);
706 unsigned access
= view
->access
;
708 /* Clear the write flag when writes can't occur.
709 * Note that DCC_DECOMPRESS for MSAA doesn't work in some cases,
710 * so we don't wanna trigger it.
713 (!fmask_desc
&& tex
->surface
.fmask_size
!= 0)) {
714 assert(!"Z/S and MSAA image stores are not supported");
715 access
&= ~PIPE_IMAGE_ACCESS_WRITE
;
718 assert(!tex
->is_depth
);
719 assert(fmask_desc
|| tex
->surface
.fmask_size
== 0);
721 if (uses_dcc
&& !skip_decompress
&&
722 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
||
723 !vi_dcc_formats_compatible(res
->b
.b
.format
, view
->format
))) {
724 /* If DCC can't be disabled, at least decompress it.
725 * The decompression is relatively cheap if the surface
726 * has been decompressed already.
728 if (!si_texture_disable_dcc(ctx
, tex
))
729 si_decompress_dcc(ctx
, tex
);
732 if (ctx
->chip_class
>= GFX9
) {
733 /* Always set the base address. The swizzle modes don't
734 * allow setting mipmap level offsets as the base.
736 width
= res
->b
.b
.width0
;
737 height
= res
->b
.b
.height0
;
738 depth
= res
->b
.b
.depth0
;
741 /* Always force the base level to the selected level.
743 * This is required for 3D textures, where otherwise
744 * selecting a single slice for non-layered bindings
745 * fails. It doesn't hurt the other targets.
747 width
= u_minify(res
->b
.b
.width0
, level
);
748 height
= u_minify(res
->b
.b
.height0
, level
);
749 depth
= u_minify(res
->b
.b
.depth0
, level
);
753 si_make_texture_descriptor(screen
, tex
,
754 false, res
->b
.b
.target
,
755 view
->format
, swizzle
,
757 view
->u
.tex
.first_layer
,
758 view
->u
.tex
.last_layer
,
759 width
, height
, depth
,
761 si_set_mutable_tex_desc_fields(screen
, tex
,
762 &tex
->surface
.u
.legacy
.level
[level
],
764 util_format_get_blockwidth(view
->format
),
769 static void si_set_shader_image(struct si_context
*ctx
,
771 unsigned slot
, const struct pipe_image_view
*view
,
772 bool skip_decompress
)
774 struct si_images
*images
= &ctx
->images
[shader
];
775 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
776 struct si_resource
*res
;
777 unsigned desc_slot
= si_get_image_slot(slot
);
778 uint32_t *desc
= descs
->list
+ desc_slot
* 8;
780 if (!view
|| !view
->resource
) {
781 si_disable_shader_image(ctx
, shader
, slot
);
785 res
= si_resource(view
->resource
);
787 if (&images
->views
[slot
] != view
)
788 util_copy_image_view(&images
->views
[slot
], view
);
790 si_set_shader_image_desc(ctx
, view
, skip_decompress
, desc
, NULL
);
792 if (res
->b
.b
.target
== PIPE_BUFFER
||
793 view
->shader_access
& SI_IMAGE_ACCESS_AS_BUFFER
) {
794 images
->needs_color_decompress_mask
&= ~(1 << slot
);
795 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
797 struct si_texture
*tex
= (struct si_texture
*)res
;
798 unsigned level
= view
->u
.tex
.level
;
800 if (color_needs_decompression(tex
)) {
801 images
->needs_color_decompress_mask
|= 1 << slot
;
803 images
->needs_color_decompress_mask
&= ~(1 << slot
);
806 if (vi_dcc_enabled(tex
, level
) &&
807 p_atomic_read(&tex
->framebuffers_bound
))
808 ctx
->need_check_render_feedback
= true;
811 images
->enabled_mask
|= 1u << slot
;
812 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
814 /* Since this can flush, it must be done after enabled_mask is updated. */
815 si_sampler_view_add_buffer(ctx
, &res
->b
.b
,
816 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
) ?
817 RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
,
822 si_set_shader_images(struct pipe_context
*pipe
,
823 enum pipe_shader_type shader
,
824 unsigned start_slot
, unsigned count
,
825 const struct pipe_image_view
*views
)
827 struct si_context
*ctx
= (struct si_context
*)pipe
;
830 assert(shader
< SI_NUM_SHADERS
);
835 assert(start_slot
+ count
<= SI_NUM_IMAGES
);
838 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
839 si_set_shader_image(ctx
, shader
, slot
, &views
[i
], false);
841 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
842 si_set_shader_image(ctx
, shader
, slot
, NULL
, false);
845 si_update_shader_needs_decompress_mask(ctx
, shader
);
849 si_images_update_needs_color_decompress_mask(struct si_images
*images
)
851 unsigned mask
= images
->enabled_mask
;
854 int i
= u_bit_scan(&mask
);
855 struct pipe_resource
*res
= images
->views
[i
].resource
;
857 if (res
&& res
->target
!= PIPE_BUFFER
) {
858 struct si_texture
*tex
= (struct si_texture
*)res
;
860 if (color_needs_decompression(tex
)) {
861 images
->needs_color_decompress_mask
|= 1 << i
;
863 images
->needs_color_decompress_mask
&= ~(1 << i
);
869 void si_update_ps_colorbuf0_slot(struct si_context
*sctx
)
871 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
872 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
873 unsigned slot
= SI_PS_IMAGE_COLORBUF0
;
874 struct pipe_surface
*surf
= NULL
;
876 /* si_texture_disable_dcc can get us here again. */
877 if (sctx
->blitter
->running
)
880 /* See whether FBFETCH is used and color buffer 0 is set. */
881 if (sctx
->ps_shader
.cso
&&
882 sctx
->ps_shader
.cso
->info
.opcode_count
[TGSI_OPCODE_FBFETCH
] &&
883 sctx
->framebuffer
.state
.nr_cbufs
&&
884 sctx
->framebuffer
.state
.cbufs
[0])
885 surf
= sctx
->framebuffer
.state
.cbufs
[0];
887 /* Return if FBFETCH transitions from disabled to disabled. */
888 if (!buffers
->buffers
[slot
] && !surf
)
891 sctx
->ps_uses_fbfetch
= surf
!= NULL
;
892 si_update_ps_iter_samples(sctx
);
895 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
896 struct pipe_image_view view
;
899 assert(!tex
->is_depth
);
901 /* Disable DCC, because the texture is used as both a sampler
904 si_texture_disable_dcc(sctx
, tex
);
906 if (tex
->buffer
.b
.b
.nr_samples
<= 1 && tex
->cmask_buffer
) {
908 assert(tex
->cmask_buffer
!= &tex
->buffer
);
909 si_eliminate_fast_color_clear(sctx
, tex
);
910 si_texture_discard_cmask(sctx
->screen
, tex
);
913 view
.resource
= surf
->texture
;
914 view
.format
= surf
->format
;
915 view
.access
= PIPE_IMAGE_ACCESS_READ
;
916 view
.u
.tex
.first_layer
= surf
->u
.tex
.first_layer
;
917 view
.u
.tex
.last_layer
= surf
->u
.tex
.last_layer
;
918 view
.u
.tex
.level
= surf
->u
.tex
.level
;
920 /* Set the descriptor. */
921 uint32_t *desc
= descs
->list
+ slot
*4;
922 memset(desc
, 0, 16 * 4);
923 si_set_shader_image_desc(sctx
, &view
, true, desc
, desc
+ 8);
925 pipe_resource_reference(&buffers
->buffers
[slot
], &tex
->buffer
.b
.b
);
926 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
927 &tex
->buffer
, RADEON_USAGE_READ
,
928 RADEON_PRIO_SHADER_RW_IMAGE
);
929 buffers
->enabled_mask
|= 1u << slot
;
931 /* Clear the descriptor. */
932 memset(descs
->list
+ slot
*4, 0, 8*4);
933 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
934 buffers
->enabled_mask
&= ~(1u << slot
);
937 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
942 static void si_bind_sampler_states(struct pipe_context
*ctx
,
943 enum pipe_shader_type shader
,
944 unsigned start
, unsigned count
, void **states
)
946 struct si_context
*sctx
= (struct si_context
*)ctx
;
947 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
948 struct si_descriptors
*desc
= si_sampler_and_image_descriptors(sctx
, shader
);
949 struct si_sampler_state
**sstates
= (struct si_sampler_state
**)states
;
952 if (!count
|| shader
>= SI_NUM_SHADERS
)
955 for (i
= 0; i
< count
; i
++) {
956 unsigned slot
= start
+ i
;
957 unsigned desc_slot
= si_get_sampler_slot(slot
);
960 sstates
[i
] == samplers
->sampler_states
[slot
])
964 assert(sstates
[i
]->magic
== SI_SAMPLER_STATE_MAGIC
);
966 samplers
->sampler_states
[slot
] = sstates
[i
];
968 /* If FMASK is bound, don't overwrite it.
969 * The sampler state will be set after FMASK is unbound.
971 struct si_sampler_view
*sview
=
972 (struct si_sampler_view
*)samplers
->views
[slot
];
974 struct si_texture
*tex
= NULL
;
976 if (sview
&& sview
->base
.texture
&&
977 sview
->base
.texture
->target
!= PIPE_BUFFER
)
978 tex
= (struct si_texture
*)sview
->base
.texture
;
980 if (tex
&& tex
->surface
.fmask_size
)
983 si_set_sampler_state_desc(sstates
[i
], sview
, tex
,
984 desc
->list
+ desc_slot
* 16 + 12);
986 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
990 /* BUFFER RESOURCES */
992 static void si_init_buffer_resources(struct si_buffer_resources
*buffers
,
993 struct si_descriptors
*descs
,
994 unsigned num_buffers
,
995 short shader_userdata_rel_index
,
996 enum radeon_bo_priority priority
,
997 enum radeon_bo_priority priority_constbuf
)
999 buffers
->priority
= priority
;
1000 buffers
->priority_constbuf
= priority_constbuf
;
1001 buffers
->buffers
= CALLOC(num_buffers
, sizeof(struct pipe_resource
*));
1003 si_init_descriptors(descs
, shader_userdata_rel_index
, 4, num_buffers
);
1006 static void si_release_buffer_resources(struct si_buffer_resources
*buffers
,
1007 struct si_descriptors
*descs
)
1011 for (i
= 0; i
< descs
->num_elements
; i
++) {
1012 pipe_resource_reference(&buffers
->buffers
[i
], NULL
);
1015 FREE(buffers
->buffers
);
1018 static void si_buffer_resources_begin_new_cs(struct si_context
*sctx
,
1019 struct si_buffer_resources
*buffers
)
1021 unsigned mask
= buffers
->enabled_mask
;
1023 /* Add buffers to the CS. */
1025 int i
= u_bit_scan(&mask
);
1027 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1028 si_resource(buffers
->buffers
[i
]),
1029 buffers
->writable_mask
& (1u << i
) ? RADEON_USAGE_READWRITE
:
1031 i
< SI_NUM_SHADER_BUFFERS
? buffers
->priority
:
1032 buffers
->priority_constbuf
);
1036 static void si_get_buffer_from_descriptors(struct si_buffer_resources
*buffers
,
1037 struct si_descriptors
*descs
,
1038 unsigned idx
, struct pipe_resource
**buf
,
1039 unsigned *offset
, unsigned *size
)
1041 pipe_resource_reference(buf
, buffers
->buffers
[idx
]);
1043 struct si_resource
*res
= si_resource(*buf
);
1044 const uint32_t *desc
= descs
->list
+ idx
* 4;
1049 assert(G_008F04_STRIDE(desc
[1]) == 0);
1050 va
= si_desc_extract_buffer_address(desc
);
1052 assert(va
>= res
->gpu_address
&& va
+ *size
<= res
->gpu_address
+ res
->bo_size
);
1053 *offset
= va
- res
->gpu_address
;
1057 /* VERTEX BUFFERS */
1059 static void si_vertex_buffers_begin_new_cs(struct si_context
*sctx
)
1061 int count
= sctx
->vertex_elements
? sctx
->vertex_elements
->count
: 0;
1064 for (i
= 0; i
< count
; i
++) {
1065 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1067 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1069 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1072 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1073 si_resource(sctx
->vertex_buffer
[vb
].buffer
.resource
),
1074 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1077 if (!sctx
->vb_descriptors_buffer
)
1079 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1080 sctx
->vb_descriptors_buffer
, RADEON_USAGE_READ
,
1081 RADEON_PRIO_DESCRIPTORS
);
1084 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
)
1086 struct si_vertex_elements
*velems
= sctx
->vertex_elements
;
1088 unsigned desc_list_byte_size
;
1089 unsigned first_vb_use_mask
;
1092 if (!sctx
->vertex_buffers_dirty
|| !velems
)
1095 count
= velems
->count
;
1100 desc_list_byte_size
= velems
->desc_list_byte_size
;
1101 first_vb_use_mask
= velems
->first_vb_use_mask
;
1103 /* Vertex buffer descriptors are the only ones which are uploaded
1104 * directly through a staging buffer and don't go through
1105 * the fine-grained upload path.
1107 u_upload_alloc(sctx
->b
.const_uploader
, 0,
1108 desc_list_byte_size
,
1109 si_optimal_tcc_alignment(sctx
, desc_list_byte_size
),
1110 &sctx
->vb_descriptors_offset
,
1111 (struct pipe_resource
**)&sctx
->vb_descriptors_buffer
,
1113 if (!sctx
->vb_descriptors_buffer
) {
1114 sctx
->vb_descriptors_offset
= 0;
1115 sctx
->vb_descriptors_gpu_list
= NULL
;
1119 sctx
->vb_descriptors_gpu_list
= ptr
;
1120 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1121 sctx
->vb_descriptors_buffer
, RADEON_USAGE_READ
,
1122 RADEON_PRIO_DESCRIPTORS
);
1124 assert(count
<= SI_MAX_ATTRIBS
);
1126 for (i
= 0; i
< count
; i
++) {
1127 struct pipe_vertex_buffer
*vb
;
1128 struct si_resource
*buf
;
1129 unsigned vbo_index
= velems
->vertex_buffer_index
[i
];
1130 uint32_t *desc
= &ptr
[i
*4];
1132 vb
= &sctx
->vertex_buffer
[vbo_index
];
1133 buf
= si_resource(vb
->buffer
.resource
);
1135 memset(desc
, 0, 16);
1139 int64_t offset
= (int64_t)((int)vb
->buffer_offset
) +
1140 velems
->src_offset
[i
];
1141 uint64_t va
= buf
->gpu_address
+ offset
;
1143 int64_t num_records
= (int64_t)buf
->b
.b
.width0
- offset
;
1144 if (sctx
->chip_class
!= VI
&& vb
->stride
) {
1145 /* Round up by rounding down and adding 1 */
1146 num_records
= (num_records
- velems
->format_size
[i
]) /
1149 assert(num_records
>= 0 && num_records
<= UINT_MAX
);
1152 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1153 S_008F04_STRIDE(vb
->stride
);
1154 desc
[2] = num_records
;
1155 desc
[3] = velems
->rsrc_word3
[i
];
1157 if (first_vb_use_mask
& (1 << i
)) {
1158 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1159 si_resource(vb
->buffer
.resource
),
1160 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1164 /* Don't flush the const cache. It would have a very negative effect
1165 * on performance (confirmed by testing). New descriptors are always
1166 * uploaded to a fresh new buffer, so I don't think flushing the const
1167 * cache is needed. */
1168 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
1169 sctx
->vertex_buffers_dirty
= false;
1170 sctx
->vertex_buffer_pointer_dirty
= true;
1171 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VBO_DESCRIPTORS
;
1176 /* CONSTANT BUFFERS */
1179 si_const_and_shader_buffer_descriptors_idx(unsigned shader
)
1181 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
1182 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
;
1185 static struct si_descriptors
*
1186 si_const_and_shader_buffer_descriptors(struct si_context
*sctx
, unsigned shader
)
1188 return &sctx
->descriptors
[si_const_and_shader_buffer_descriptors_idx(shader
)];
1191 void si_upload_const_buffer(struct si_context
*sctx
, struct si_resource
**buf
,
1192 const uint8_t *ptr
, unsigned size
, uint32_t *const_offset
)
1196 u_upload_alloc(sctx
->b
.const_uploader
, 0, size
,
1197 si_optimal_tcc_alignment(sctx
, size
),
1199 (struct pipe_resource
**)buf
, &tmp
);
1201 util_memcpy_cpu_to_le32(tmp
, ptr
, size
);
1204 static void si_set_constant_buffer(struct si_context
*sctx
,
1205 struct si_buffer_resources
*buffers
,
1206 unsigned descriptors_idx
,
1207 uint slot
, const struct pipe_constant_buffer
*input
)
1209 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1210 assert(slot
< descs
->num_elements
);
1211 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1213 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1214 * with a NULL buffer). We need to use a dummy buffer instead. */
1215 if (sctx
->chip_class
== CIK
&&
1216 (!input
|| (!input
->buffer
&& !input
->user_buffer
)))
1217 input
= &sctx
->null_const_buf
;
1219 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
1220 struct pipe_resource
*buffer
= NULL
;
1223 /* Upload the user buffer if needed. */
1224 if (input
->user_buffer
) {
1225 unsigned buffer_offset
;
1227 si_upload_const_buffer(sctx
,
1228 (struct si_resource
**)&buffer
, input
->user_buffer
,
1229 input
->buffer_size
, &buffer_offset
);
1231 /* Just unbind on failure. */
1232 si_set_constant_buffer(sctx
, buffers
, descriptors_idx
, slot
, NULL
);
1235 va
= si_resource(buffer
)->gpu_address
+ buffer_offset
;
1237 pipe_resource_reference(&buffer
, input
->buffer
);
1238 va
= si_resource(buffer
)->gpu_address
+ input
->buffer_offset
;
1241 /* Set the descriptor. */
1242 uint32_t *desc
= descs
->list
+ slot
*4;
1244 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1246 desc
[2] = input
->buffer_size
;
1247 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1248 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1249 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1250 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1251 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1252 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1254 buffers
->buffers
[slot
] = buffer
;
1255 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1256 si_resource(buffer
),
1258 buffers
->priority_constbuf
, true);
1259 buffers
->enabled_mask
|= 1u << slot
;
1261 /* Clear the descriptor. */
1262 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1263 buffers
->enabled_mask
&= ~(1u << slot
);
1266 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1269 static void si_pipe_set_constant_buffer(struct pipe_context
*ctx
,
1270 enum pipe_shader_type shader
, uint slot
,
1271 const struct pipe_constant_buffer
*input
)
1273 struct si_context
*sctx
= (struct si_context
*)ctx
;
1275 if (shader
>= SI_NUM_SHADERS
)
1278 if (slot
== 0 && input
&& input
->buffer
&&
1279 !(si_resource(input
->buffer
)->flags
& RADEON_FLAG_32BIT
)) {
1280 assert(!"constant buffer 0 must have a 32-bit VM address, use const_uploader");
1284 if (input
&& input
->buffer
)
1285 si_resource(input
->buffer
)->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
1287 slot
= si_get_constbuf_slot(slot
);
1288 si_set_constant_buffer(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1289 si_const_and_shader_buffer_descriptors_idx(shader
),
1293 void si_get_pipe_constant_buffer(struct si_context
*sctx
, uint shader
,
1294 uint slot
, struct pipe_constant_buffer
*cbuf
)
1296 cbuf
->user_buffer
= NULL
;
1297 si_get_buffer_from_descriptors(
1298 &sctx
->const_and_shader_buffers
[shader
],
1299 si_const_and_shader_buffer_descriptors(sctx
, shader
),
1300 si_get_constbuf_slot(slot
),
1301 &cbuf
->buffer
, &cbuf
->buffer_offset
, &cbuf
->buffer_size
);
1304 /* SHADER BUFFERS */
1306 static void si_set_shader_buffer(struct si_context
*sctx
,
1307 struct si_buffer_resources
*buffers
,
1308 unsigned descriptors_idx
,
1309 uint slot
, const struct pipe_shader_buffer
*sbuffer
,
1310 bool writable
, enum radeon_bo_priority priority
)
1312 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1313 uint32_t *desc
= descs
->list
+ slot
* 4;
1315 if (!sbuffer
|| !sbuffer
->buffer
) {
1316 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1317 memset(desc
, 0, sizeof(uint32_t) * 4);
1318 buffers
->enabled_mask
&= ~(1u << slot
);
1319 buffers
->writable_mask
&= ~(1u << slot
);
1320 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1324 struct si_resource
*buf
= si_resource(sbuffer
->buffer
);
1325 uint64_t va
= buf
->gpu_address
+ sbuffer
->buffer_offset
;
1328 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1330 desc
[2] = sbuffer
->buffer_size
;
1331 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1332 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1333 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1334 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1335 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1336 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1338 pipe_resource_reference(&buffers
->buffers
[slot
], &buf
->b
.b
);
1339 radeon_add_to_gfx_buffer_list_check_mem(sctx
, buf
,
1340 writable
? RADEON_USAGE_READWRITE
:
1344 buffers
->writable_mask
|= 1u << slot
;
1346 buffers
->writable_mask
&= ~(1u << slot
);
1348 buffers
->enabled_mask
|= 1u << slot
;
1349 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1351 util_range_add(&buf
->valid_buffer_range
, sbuffer
->buffer_offset
,
1352 sbuffer
->buffer_offset
+ sbuffer
->buffer_size
);
1355 static void si_set_shader_buffers(struct pipe_context
*ctx
,
1356 enum pipe_shader_type shader
,
1357 unsigned start_slot
, unsigned count
,
1358 const struct pipe_shader_buffer
*sbuffers
,
1359 unsigned writable_bitmask
)
1361 struct si_context
*sctx
= (struct si_context
*)ctx
;
1362 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1363 unsigned descriptors_idx
= si_const_and_shader_buffer_descriptors_idx(shader
);
1366 assert(start_slot
+ count
<= SI_NUM_SHADER_BUFFERS
);
1368 for (i
= 0; i
< count
; ++i
) {
1369 const struct pipe_shader_buffer
*sbuffer
= sbuffers
? &sbuffers
[i
] : NULL
;
1370 unsigned slot
= si_get_shaderbuf_slot(start_slot
+ i
);
1372 if (sbuffer
&& sbuffer
->buffer
)
1373 si_resource(sbuffer
->buffer
)->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
1375 si_set_shader_buffer(sctx
, buffers
, descriptors_idx
, slot
, sbuffer
,
1376 !!(writable_bitmask
& (1u << i
)),
1381 void si_get_shader_buffers(struct si_context
*sctx
,
1382 enum pipe_shader_type shader
,
1383 uint start_slot
, uint count
,
1384 struct pipe_shader_buffer
*sbuf
)
1386 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1387 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1389 for (unsigned i
= 0; i
< count
; ++i
) {
1390 si_get_buffer_from_descriptors(
1392 si_get_shaderbuf_slot(start_slot
+ i
),
1393 &sbuf
[i
].buffer
, &sbuf
[i
].buffer_offset
,
1394 &sbuf
[i
].buffer_size
);
1400 void si_set_rw_buffer(struct si_context
*sctx
,
1401 uint slot
, const struct pipe_constant_buffer
*input
)
1403 si_set_constant_buffer(sctx
, &sctx
->rw_buffers
, SI_DESCS_RW_BUFFERS
,
1407 void si_set_rw_shader_buffer(struct si_context
*sctx
, uint slot
,
1408 const struct pipe_shader_buffer
*sbuffer
)
1410 si_set_shader_buffer(sctx
, &sctx
->rw_buffers
, SI_DESCS_RW_BUFFERS
,
1411 slot
, sbuffer
, true, RADEON_PRIO_SHADER_RW_BUFFER
);
1414 void si_set_ring_buffer(struct si_context
*sctx
, uint slot
,
1415 struct pipe_resource
*buffer
,
1416 unsigned stride
, unsigned num_records
,
1417 bool add_tid
, bool swizzle
,
1418 unsigned element_size
, unsigned index_stride
, uint64_t offset
)
1420 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1421 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1423 /* The stride field in the resource descriptor has 14 bits */
1424 assert(stride
< (1 << 14));
1426 assert(slot
< descs
->num_elements
);
1427 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1432 va
= si_resource(buffer
)->gpu_address
+ offset
;
1434 switch (element_size
) {
1436 assert(!"Unsupported ring buffer element size");
1452 switch (index_stride
) {
1454 assert(!"Unsupported ring buffer index stride");
1470 if (sctx
->chip_class
>= VI
&& stride
)
1471 num_records
*= stride
;
1473 /* Set the descriptor. */
1474 uint32_t *desc
= descs
->list
+ slot
*4;
1476 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1477 S_008F04_STRIDE(stride
) |
1478 S_008F04_SWIZZLE_ENABLE(swizzle
);
1479 desc
[2] = num_records
;
1480 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1481 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1482 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1483 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1484 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1485 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1486 S_008F0C_INDEX_STRIDE(index_stride
) |
1487 S_008F0C_ADD_TID_ENABLE(add_tid
);
1489 if (sctx
->chip_class
>= GFX9
)
1490 assert(!swizzle
|| element_size
== 1); /* always 4 bytes on GFX9 */
1492 desc
[3] |= S_008F0C_ELEMENT_SIZE(element_size
);
1494 pipe_resource_reference(&buffers
->buffers
[slot
], buffer
);
1495 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1496 si_resource(buffer
),
1497 RADEON_USAGE_READWRITE
, buffers
->priority
);
1498 buffers
->enabled_mask
|= 1u << slot
;
1500 /* Clear the descriptor. */
1501 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1502 buffers
->enabled_mask
&= ~(1u << slot
);
1505 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1508 static void si_desc_reset_buffer_offset(uint32_t *desc
, uint64_t old_buf_va
,
1509 struct pipe_resource
*new_buf
)
1511 /* Retrieve the buffer offset from the descriptor. */
1512 uint64_t old_desc_va
= si_desc_extract_buffer_address(desc
);
1514 assert(old_buf_va
<= old_desc_va
);
1515 uint64_t offset_within_buffer
= old_desc_va
- old_buf_va
;
1517 /* Update the descriptor. */
1518 si_set_buf_desc_address(si_resource(new_buf
), offset_within_buffer
,
1522 /* INTERNAL CONST BUFFERS */
1524 static void si_set_polygon_stipple(struct pipe_context
*ctx
,
1525 const struct pipe_poly_stipple
*state
)
1527 struct si_context
*sctx
= (struct si_context
*)ctx
;
1528 struct pipe_constant_buffer cb
= {};
1529 unsigned stipple
[32];
1532 for (i
= 0; i
< 32; i
++)
1533 stipple
[i
] = util_bitreverse(state
->stipple
[i
]);
1535 cb
.user_buffer
= stipple
;
1536 cb
.buffer_size
= sizeof(stipple
);
1538 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
, &cb
);
1541 /* TEXTURE METADATA ENABLE/DISABLE */
1544 si_resident_handles_update_needs_color_decompress(struct si_context
*sctx
)
1546 util_dynarray_clear(&sctx
->resident_tex_needs_color_decompress
);
1547 util_dynarray_clear(&sctx
->resident_img_needs_color_decompress
);
1549 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1550 struct si_texture_handle
*, tex_handle
) {
1551 struct pipe_resource
*res
= (*tex_handle
)->view
->texture
;
1552 struct si_texture
*tex
;
1554 if (!res
|| res
->target
== PIPE_BUFFER
)
1557 tex
= (struct si_texture
*)res
;
1558 if (!color_needs_decompression(tex
))
1561 util_dynarray_append(&sctx
->resident_tex_needs_color_decompress
,
1562 struct si_texture_handle
*, *tex_handle
);
1565 util_dynarray_foreach(&sctx
->resident_img_handles
,
1566 struct si_image_handle
*, img_handle
) {
1567 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1568 struct pipe_resource
*res
= view
->resource
;
1569 struct si_texture
*tex
;
1571 if (!res
|| res
->target
== PIPE_BUFFER
)
1574 tex
= (struct si_texture
*)res
;
1575 if (!color_needs_decompression(tex
))
1578 util_dynarray_append(&sctx
->resident_img_needs_color_decompress
,
1579 struct si_image_handle
*, *img_handle
);
1583 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1584 * while the texture is bound, possibly by a different context. In that case,
1585 * call this function to update needs_*_decompress_masks.
1587 void si_update_needs_color_decompress_masks(struct si_context
*sctx
)
1589 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
1590 si_samplers_update_needs_color_decompress_mask(&sctx
->samplers
[i
]);
1591 si_images_update_needs_color_decompress_mask(&sctx
->images
[i
]);
1592 si_update_shader_needs_decompress_mask(sctx
, i
);
1595 si_resident_handles_update_needs_color_decompress(sctx
);
1598 /* BUFFER DISCARD/INVALIDATION */
1600 /** Reset descriptors of buffer resources after \p buf has been invalidated. */
1601 static void si_reset_buffer_resources(struct si_context
*sctx
,
1602 struct si_buffer_resources
*buffers
,
1603 unsigned descriptors_idx
,
1605 struct pipe_resource
*buf
,
1607 enum radeon_bo_priority priority
)
1609 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1610 unsigned mask
= buffers
->enabled_mask
& slot_mask
;
1613 unsigned i
= u_bit_scan(&mask
);
1614 if (buffers
->buffers
[i
] == buf
) {
1615 si_desc_reset_buffer_offset(descs
->list
+ i
*4,
1617 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1619 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1621 buffers
->writable_mask
& (1u << i
) ?
1622 RADEON_USAGE_READWRITE
:
1629 /* Update all resource bindings where the buffer is bound, including
1630 * all resource descriptors. This is invalidate_buffer without
1631 * the invalidation. */
1632 void si_rebind_buffer(struct si_context
*sctx
, struct pipe_resource
*buf
,
1635 struct si_resource
*buffer
= si_resource(buf
);
1637 unsigned num_elems
= sctx
->vertex_elements
?
1638 sctx
->vertex_elements
->count
: 0;
1640 /* We changed the buffer, now we need to bind it where the old one
1641 * was bound. This consists of 2 things:
1642 * 1) Updating the resource descriptor and dirtying it.
1643 * 2) Adding a relocation to the CS, so that it's usable.
1646 /* Vertex buffers. */
1647 if (buffer
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
1648 for (i
= 0; i
< num_elems
; i
++) {
1649 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1651 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1653 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1656 if (sctx
->vertex_buffer
[vb
].buffer
.resource
== buf
) {
1657 sctx
->vertex_buffers_dirty
= true;
1663 /* Streamout buffers. (other internal buffers can't be invalidated) */
1664 if (buffer
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
1665 for (i
= SI_VS_STREAMOUT_BUF0
; i
<= SI_VS_STREAMOUT_BUF3
; i
++) {
1666 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1667 struct si_descriptors
*descs
=
1668 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1670 if (buffers
->buffers
[i
] != buf
)
1673 si_desc_reset_buffer_offset(descs
->list
+ i
*4,
1675 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1677 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1678 buffer
, RADEON_USAGE_WRITE
,
1679 RADEON_PRIO_SHADER_RW_BUFFER
,
1682 /* Update the streamout state. */
1683 if (sctx
->streamout
.begin_emitted
)
1684 si_emit_streamout_end(sctx
);
1685 sctx
->streamout
.append_bitmask
=
1686 sctx
->streamout
.enabled_mask
;
1687 si_streamout_buffers_dirty(sctx
);
1691 /* Constant and shader buffers. */
1692 if (buffer
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1693 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1694 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1695 si_const_and_shader_buffer_descriptors_idx(shader
),
1696 u_bit_consecutive(SI_NUM_SHADER_BUFFERS
, SI_NUM_CONST_BUFFERS
),
1698 sctx
->const_and_shader_buffers
[shader
].priority_constbuf
);
1701 if (buffer
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
1702 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1703 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1704 si_const_and_shader_buffer_descriptors_idx(shader
),
1705 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS
),
1707 sctx
->const_and_shader_buffers
[shader
].priority
);
1710 if (buffer
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
1711 /* Texture buffers - update bindings. */
1712 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1713 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1714 struct si_descriptors
*descs
=
1715 si_sampler_and_image_descriptors(sctx
, shader
);
1716 unsigned mask
= samplers
->enabled_mask
;
1719 unsigned i
= u_bit_scan(&mask
);
1720 if (samplers
->views
[i
]->texture
== buf
) {
1721 unsigned desc_slot
= si_get_sampler_slot(i
);
1723 si_desc_reset_buffer_offset(descs
->list
+
1726 sctx
->descriptors_dirty
|=
1727 1u << si_sampler_and_image_descriptors_idx(shader
);
1729 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1730 buffer
, RADEON_USAGE_READ
,
1731 RADEON_PRIO_SAMPLER_BUFFER
,
1739 if (buffer
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
1740 for (shader
= 0; shader
< SI_NUM_SHADERS
; ++shader
) {
1741 struct si_images
*images
= &sctx
->images
[shader
];
1742 struct si_descriptors
*descs
=
1743 si_sampler_and_image_descriptors(sctx
, shader
);
1744 unsigned mask
= images
->enabled_mask
;
1747 unsigned i
= u_bit_scan(&mask
);
1749 if (images
->views
[i
].resource
== buf
) {
1750 unsigned desc_slot
= si_get_image_slot(i
);
1752 if (images
->views
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
)
1753 si_mark_image_range_valid(&images
->views
[i
]);
1755 si_desc_reset_buffer_offset(
1756 descs
->list
+ desc_slot
* 8 + 4,
1758 sctx
->descriptors_dirty
|=
1759 1u << si_sampler_and_image_descriptors_idx(shader
);
1761 radeon_add_to_gfx_buffer_list_check_mem(
1763 RADEON_USAGE_READWRITE
,
1764 RADEON_PRIO_SAMPLER_BUFFER
, true);
1770 /* Bindless texture handles */
1771 if (buffer
->texture_handle_allocated
) {
1772 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1774 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1775 struct si_texture_handle
*, tex_handle
) {
1776 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
1777 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1779 if (view
->texture
== buf
) {
1780 si_set_buf_desc_address(buffer
,
1783 desc_slot
* 16 + 4);
1785 (*tex_handle
)->desc_dirty
= true;
1786 sctx
->bindless_descriptors_dirty
= true;
1788 radeon_add_to_gfx_buffer_list_check_mem(
1791 RADEON_PRIO_SAMPLER_BUFFER
, true);
1796 /* Bindless image handles */
1797 if (buffer
->image_handle_allocated
) {
1798 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1800 util_dynarray_foreach(&sctx
->resident_img_handles
,
1801 struct si_image_handle
*, img_handle
) {
1802 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1803 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1805 if (view
->resource
== buf
) {
1806 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
1807 si_mark_image_range_valid(view
);
1809 si_set_buf_desc_address(buffer
,
1812 desc_slot
* 16 + 4);
1814 (*img_handle
)->desc_dirty
= true;
1815 sctx
->bindless_descriptors_dirty
= true;
1817 radeon_add_to_gfx_buffer_list_check_mem(
1819 RADEON_USAGE_READWRITE
,
1820 RADEON_PRIO_SAMPLER_BUFFER
, true);
1826 static void si_upload_bindless_descriptor(struct si_context
*sctx
,
1828 unsigned num_dwords
)
1830 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1831 unsigned desc_slot_offset
= desc_slot
* 16;
1835 data
= desc
->list
+ desc_slot_offset
;
1836 va
= desc
->gpu_address
+ desc_slot_offset
* 4;
1838 si_cp_write_data(sctx
, desc
->buffer
, va
- desc
->buffer
->gpu_address
,
1839 num_dwords
* 4, V_370_TC_L2
, V_370_ME
, data
);
1842 static void si_upload_bindless_descriptors(struct si_context
*sctx
)
1844 if (!sctx
->bindless_descriptors_dirty
)
1847 /* Wait for graphics/compute to be idle before updating the resident
1848 * descriptors directly in memory, in case the GPU is using them.
1850 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
1851 SI_CONTEXT_CS_PARTIAL_FLUSH
;
1852 si_emit_cache_flush(sctx
);
1854 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1855 struct si_texture_handle
*, tex_handle
) {
1856 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1858 if (!(*tex_handle
)->desc_dirty
)
1861 si_upload_bindless_descriptor(sctx
, desc_slot
, 16);
1862 (*tex_handle
)->desc_dirty
= false;
1865 util_dynarray_foreach(&sctx
->resident_img_handles
,
1866 struct si_image_handle
*, img_handle
) {
1867 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1869 if (!(*img_handle
)->desc_dirty
)
1872 si_upload_bindless_descriptor(sctx
, desc_slot
, 8);
1873 (*img_handle
)->desc_dirty
= false;
1876 /* Invalidate L1 because it doesn't know that L2 changed. */
1877 sctx
->flags
|= SI_CONTEXT_INV_SMEM_L1
;
1878 si_emit_cache_flush(sctx
);
1880 sctx
->bindless_descriptors_dirty
= false;
1883 /* Update mutable image descriptor fields of all resident textures. */
1884 static void si_update_bindless_texture_descriptor(struct si_context
*sctx
,
1885 struct si_texture_handle
*tex_handle
)
1887 struct si_sampler_view
*sview
= (struct si_sampler_view
*)tex_handle
->view
;
1888 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1889 unsigned desc_slot_offset
= tex_handle
->desc_slot
* 16;
1890 uint32_t desc_list
[16];
1892 if (sview
->base
.texture
->target
== PIPE_BUFFER
)
1895 memcpy(desc_list
, desc
->list
+ desc_slot_offset
, sizeof(desc_list
));
1896 si_set_sampler_view_desc(sctx
, sview
, &tex_handle
->sstate
,
1897 desc
->list
+ desc_slot_offset
);
1899 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1900 sizeof(desc_list
))) {
1901 tex_handle
->desc_dirty
= true;
1902 sctx
->bindless_descriptors_dirty
= true;
1906 static void si_update_bindless_image_descriptor(struct si_context
*sctx
,
1907 struct si_image_handle
*img_handle
)
1909 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1910 unsigned desc_slot_offset
= img_handle
->desc_slot
* 16;
1911 struct pipe_image_view
*view
= &img_handle
->view
;
1912 uint32_t desc_list
[8];
1914 if (view
->resource
->target
== PIPE_BUFFER
)
1917 memcpy(desc_list
, desc
->list
+ desc_slot_offset
,
1919 si_set_shader_image_desc(sctx
, view
, true,
1920 desc
->list
+ desc_slot_offset
, NULL
);
1922 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1923 sizeof(desc_list
))) {
1924 img_handle
->desc_dirty
= true;
1925 sctx
->bindless_descriptors_dirty
= true;
1929 static void si_update_all_resident_texture_descriptors(struct si_context
*sctx
)
1931 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1932 struct si_texture_handle
*, tex_handle
) {
1933 si_update_bindless_texture_descriptor(sctx
, *tex_handle
);
1936 util_dynarray_foreach(&sctx
->resident_img_handles
,
1937 struct si_image_handle
*, img_handle
) {
1938 si_update_bindless_image_descriptor(sctx
, *img_handle
);
1941 si_upload_bindless_descriptors(sctx
);
1944 /* Update mutable image descriptor fields of all bound textures. */
1945 void si_update_all_texture_descriptors(struct si_context
*sctx
)
1949 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1950 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1951 struct si_images
*images
= &sctx
->images
[shader
];
1955 mask
= images
->enabled_mask
;
1957 unsigned i
= u_bit_scan(&mask
);
1958 struct pipe_image_view
*view
= &images
->views
[i
];
1960 if (!view
->resource
||
1961 view
->resource
->target
== PIPE_BUFFER
)
1964 si_set_shader_image(sctx
, shader
, i
, view
, true);
1967 /* Sampler views. */
1968 mask
= samplers
->enabled_mask
;
1970 unsigned i
= u_bit_scan(&mask
);
1971 struct pipe_sampler_view
*view
= samplers
->views
[i
];
1975 view
->texture
->target
== PIPE_BUFFER
)
1978 si_set_sampler_view(sctx
, shader
, i
,
1979 samplers
->views
[i
], true);
1982 si_update_shader_needs_decompress_mask(sctx
, shader
);
1985 si_update_all_resident_texture_descriptors(sctx
);
1986 si_update_ps_colorbuf0_slot(sctx
);
1989 /* SHADER USER DATA */
1991 static void si_mark_shader_pointers_dirty(struct si_context
*sctx
,
1994 sctx
->shader_pointers_dirty
|=
1995 u_bit_consecutive(SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
,
1996 SI_NUM_SHADER_DESCS
);
1998 if (shader
== PIPE_SHADER_VERTEX
)
1999 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
2001 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
2004 static void si_shader_pointers_begin_new_cs(struct si_context
*sctx
)
2006 sctx
->shader_pointers_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2007 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
2008 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
2009 sctx
->graphics_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
2010 sctx
->compute_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
2013 /* Set a base register address for user data constants in the given shader.
2014 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
2016 static void si_set_user_data_base(struct si_context
*sctx
,
2017 unsigned shader
, uint32_t new_base
)
2019 uint32_t *base
= &sctx
->shader_pointers
.sh_base
[shader
];
2021 if (*base
!= new_base
) {
2025 si_mark_shader_pointers_dirty(sctx
, shader
);
2027 /* Any change in enabled shader stages requires re-emitting
2028 * the VS state SGPR, because it contains the clamp_vertex_color
2029 * state, which can be done in VS, TES, and GS.
2031 sctx
->last_vs_state
= ~0;
2035 /* This must be called when these shaders are changed from non-NULL to NULL
2038 * - tessellation control shader
2039 * - tessellation evaluation shader
2041 void si_shader_change_notify(struct si_context
*sctx
)
2043 /* VS can be bound as VS, ES, or LS. */
2044 if (sctx
->tes_shader
.cso
) {
2045 if (sctx
->chip_class
>= GFX9
) {
2046 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2047 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2049 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2050 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2052 } else if (sctx
->gs_shader
.cso
) {
2053 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2054 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2056 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2057 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2060 /* TES can be bound as ES, VS, or not bound. */
2061 if (sctx
->tes_shader
.cso
) {
2062 if (sctx
->gs_shader
.cso
)
2063 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
2064 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2066 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
2067 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2069 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, 0);
2073 static void si_emit_shader_pointer_head(struct radeon_cmdbuf
*cs
,
2075 unsigned pointer_count
)
2077 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
, 0));
2078 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
2081 static void si_emit_shader_pointer_body(struct si_screen
*sscreen
,
2082 struct radeon_cmdbuf
*cs
,
2085 radeon_emit(cs
, va
);
2087 assert(va
== 0 || (va
>> 32) == sscreen
->info
.address32_hi
);
2090 static void si_emit_shader_pointer(struct si_context
*sctx
,
2091 struct si_descriptors
*desc
,
2094 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2095 unsigned sh_offset
= sh_base
+ desc
->shader_userdata_offset
;
2097 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2098 si_emit_shader_pointer_body(sctx
->screen
, cs
, desc
->gpu_address
);
2101 static void si_emit_consecutive_shader_pointers(struct si_context
*sctx
,
2102 unsigned pointer_mask
,
2108 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2109 unsigned mask
= sctx
->shader_pointers_dirty
& pointer_mask
;
2113 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
2115 struct si_descriptors
*descs
= &sctx
->descriptors
[start
];
2116 unsigned sh_offset
= sh_base
+ descs
->shader_userdata_offset
;
2118 si_emit_shader_pointer_head(cs
, sh_offset
, count
);
2119 for (int i
= 0; i
< count
; i
++)
2120 si_emit_shader_pointer_body(sctx
->screen
, cs
,
2121 descs
[i
].gpu_address
);
2125 static void si_emit_global_shader_pointers(struct si_context
*sctx
,
2126 struct si_descriptors
*descs
)
2128 if (sctx
->chip_class
== GFX9
) {
2129 /* Broadcast it to all shader stages. */
2130 si_emit_shader_pointer(sctx
, descs
,
2131 R_00B530_SPI_SHADER_USER_DATA_COMMON_0
);
2135 si_emit_shader_pointer(sctx
, descs
,
2136 R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2137 si_emit_shader_pointer(sctx
, descs
,
2138 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2139 si_emit_shader_pointer(sctx
, descs
,
2140 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2141 si_emit_shader_pointer(sctx
, descs
,
2142 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2143 si_emit_shader_pointer(sctx
, descs
,
2144 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2145 si_emit_shader_pointer(sctx
, descs
,
2146 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2149 void si_emit_graphics_shader_pointers(struct si_context
*sctx
)
2151 uint32_t *sh_base
= sctx
->shader_pointers
.sh_base
;
2153 if (sctx
->shader_pointers_dirty
& (1 << SI_DESCS_RW_BUFFERS
)) {
2154 si_emit_global_shader_pointers(sctx
,
2155 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2158 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(VERTEX
),
2159 sh_base
[PIPE_SHADER_VERTEX
]);
2160 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_EVAL
),
2161 sh_base
[PIPE_SHADER_TESS_EVAL
]);
2162 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(FRAGMENT
),
2163 sh_base
[PIPE_SHADER_FRAGMENT
]);
2164 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_CTRL
),
2165 sh_base
[PIPE_SHADER_TESS_CTRL
]);
2166 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(GEOMETRY
),
2167 sh_base
[PIPE_SHADER_GEOMETRY
]);
2169 sctx
->shader_pointers_dirty
&=
2170 ~u_bit_consecutive(SI_DESCS_RW_BUFFERS
, SI_DESCS_FIRST_COMPUTE
);
2172 if (sctx
->vertex_buffer_pointer_dirty
) {
2173 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2175 /* Find the location of the VB descriptor pointer. */
2176 /* TODO: In the future, the pointer will be packed in unused
2177 * bits of the first 2 VB descriptors. */
2178 unsigned sh_dw_offset
= SI_VS_NUM_USER_SGPR
;
2179 if (sctx
->chip_class
>= GFX9
) {
2180 if (sctx
->tes_shader
.cso
)
2181 sh_dw_offset
= GFX9_TCS_NUM_USER_SGPR
;
2182 else if (sctx
->gs_shader
.cso
)
2183 sh_dw_offset
= GFX9_VSGS_NUM_USER_SGPR
;
2186 unsigned sh_offset
= sh_base
[PIPE_SHADER_VERTEX
] + sh_dw_offset
* 4;
2187 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2188 si_emit_shader_pointer_body(sctx
->screen
, cs
,
2189 sctx
->vb_descriptors_buffer
->gpu_address
+
2190 sctx
->vb_descriptors_offset
);
2191 sctx
->vertex_buffer_pointer_dirty
= false;
2194 if (sctx
->graphics_bindless_pointer_dirty
) {
2195 si_emit_global_shader_pointers(sctx
,
2196 &sctx
->bindless_descriptors
);
2197 sctx
->graphics_bindless_pointer_dirty
= false;
2201 void si_emit_compute_shader_pointers(struct si_context
*sctx
)
2203 unsigned base
= R_00B900_COMPUTE_USER_DATA_0
;
2205 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(COMPUTE
),
2206 R_00B900_COMPUTE_USER_DATA_0
);
2207 sctx
->shader_pointers_dirty
&= ~SI_DESCS_SHADER_MASK(COMPUTE
);
2209 if (sctx
->compute_bindless_pointer_dirty
) {
2210 si_emit_shader_pointer(sctx
, &sctx
->bindless_descriptors
, base
);
2211 sctx
->compute_bindless_pointer_dirty
= false;
2217 static void si_init_bindless_descriptors(struct si_context
*sctx
,
2218 struct si_descriptors
*desc
,
2219 short shader_userdata_rel_index
,
2220 unsigned num_elements
)
2222 MAYBE_UNUSED
unsigned desc_slot
;
2224 si_init_descriptors(desc
, shader_userdata_rel_index
, 16, num_elements
);
2225 sctx
->bindless_descriptors
.num_active_slots
= num_elements
;
2227 /* The first bindless descriptor is stored at slot 1, because 0 is not
2228 * considered to be a valid handle.
2230 sctx
->num_bindless_descriptors
= 1;
2232 /* Track which bindless slots are used (or not). */
2233 util_idalloc_init(&sctx
->bindless_used_slots
);
2234 util_idalloc_resize(&sctx
->bindless_used_slots
, num_elements
);
2236 /* Reserve slot 0 because it's an invalid handle for bindless. */
2237 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2238 assert(desc_slot
== 0);
2241 static void si_release_bindless_descriptors(struct si_context
*sctx
)
2243 si_release_descriptors(&sctx
->bindless_descriptors
);
2244 util_idalloc_fini(&sctx
->bindless_used_slots
);
2247 static unsigned si_get_first_free_bindless_slot(struct si_context
*sctx
)
2249 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2252 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2253 if (desc_slot
>= desc
->num_elements
) {
2254 /* The array of bindless descriptors is full, resize it. */
2255 unsigned slot_size
= desc
->element_dw_size
* 4;
2256 unsigned new_num_elements
= desc
->num_elements
* 2;
2258 desc
->list
= REALLOC(desc
->list
, desc
->num_elements
* slot_size
,
2259 new_num_elements
* slot_size
);
2260 desc
->num_elements
= new_num_elements
;
2261 desc
->num_active_slots
= new_num_elements
;
2269 si_create_bindless_descriptor(struct si_context
*sctx
, uint32_t *desc_list
,
2272 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2273 unsigned desc_slot
, desc_slot_offset
;
2275 /* Find a free slot. */
2276 desc_slot
= si_get_first_free_bindless_slot(sctx
);
2278 /* For simplicity, sampler and image bindless descriptors use fixed
2279 * 16-dword slots for now. Image descriptors only need 8-dword but this
2280 * doesn't really matter because no real apps use image handles.
2282 desc_slot_offset
= desc_slot
* 16;
2284 /* Copy the descriptor into the array. */
2285 memcpy(desc
->list
+ desc_slot_offset
, desc_list
, size
);
2287 /* Re-upload the whole array of bindless descriptors into a new buffer.
2289 if (!si_upload_descriptors(sctx
, desc
))
2292 /* Make sure to re-emit the shader pointers for all stages. */
2293 sctx
->graphics_bindless_pointer_dirty
= true;
2294 sctx
->compute_bindless_pointer_dirty
= true;
2299 static void si_update_bindless_buffer_descriptor(struct si_context
*sctx
,
2301 struct pipe_resource
*resource
,
2305 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2306 struct si_resource
*buf
= si_resource(resource
);
2307 unsigned desc_slot_offset
= desc_slot
* 16;
2308 uint32_t *desc_list
= desc
->list
+ desc_slot_offset
+ 4;
2309 uint64_t old_desc_va
;
2311 assert(resource
->target
== PIPE_BUFFER
);
2313 /* Retrieve the old buffer addr from the descriptor. */
2314 old_desc_va
= si_desc_extract_buffer_address(desc_list
);
2316 if (old_desc_va
!= buf
->gpu_address
+ offset
) {
2317 /* The buffer has been invalidated when the handle wasn't
2318 * resident, update the descriptor and the dirty flag.
2320 si_set_buf_desc_address(buf
, offset
, &desc_list
[0]);
2326 static uint64_t si_create_texture_handle(struct pipe_context
*ctx
,
2327 struct pipe_sampler_view
*view
,
2328 const struct pipe_sampler_state
*state
)
2330 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
2331 struct si_context
*sctx
= (struct si_context
*)ctx
;
2332 struct si_texture_handle
*tex_handle
;
2333 struct si_sampler_state
*sstate
;
2334 uint32_t desc_list
[16];
2337 tex_handle
= CALLOC_STRUCT(si_texture_handle
);
2341 memset(desc_list
, 0, sizeof(desc_list
));
2342 si_init_descriptor_list(&desc_list
[0], 16, 1, null_texture_descriptor
);
2344 sstate
= ctx
->create_sampler_state(ctx
, state
);
2350 si_set_sampler_view_desc(sctx
, sview
, sstate
, &desc_list
[0]);
2351 memcpy(&tex_handle
->sstate
, sstate
, sizeof(*sstate
));
2352 ctx
->delete_sampler_state(ctx
, sstate
);
2354 tex_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2356 if (!tex_handle
->desc_slot
) {
2361 handle
= tex_handle
->desc_slot
;
2363 if (!_mesa_hash_table_insert(sctx
->tex_handles
,
2364 (void *)(uintptr_t)handle
,
2370 pipe_sampler_view_reference(&tex_handle
->view
, view
);
2372 si_resource(sview
->base
.texture
)->texture_handle_allocated
= true;
2377 static void si_delete_texture_handle(struct pipe_context
*ctx
, uint64_t handle
)
2379 struct si_context
*sctx
= (struct si_context
*)ctx
;
2380 struct si_texture_handle
*tex_handle
;
2381 struct hash_entry
*entry
;
2383 entry
= _mesa_hash_table_search(sctx
->tex_handles
,
2384 (void *)(uintptr_t)handle
);
2388 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2390 /* Allow this descriptor slot to be re-used. */
2391 util_idalloc_free(&sctx
->bindless_used_slots
, tex_handle
->desc_slot
);
2393 pipe_sampler_view_reference(&tex_handle
->view
, NULL
);
2394 _mesa_hash_table_remove(sctx
->tex_handles
, entry
);
2398 static void si_make_texture_handle_resident(struct pipe_context
*ctx
,
2399 uint64_t handle
, bool resident
)
2401 struct si_context
*sctx
= (struct si_context
*)ctx
;
2402 struct si_texture_handle
*tex_handle
;
2403 struct si_sampler_view
*sview
;
2404 struct hash_entry
*entry
;
2406 entry
= _mesa_hash_table_search(sctx
->tex_handles
,
2407 (void *)(uintptr_t)handle
);
2411 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2412 sview
= (struct si_sampler_view
*)tex_handle
->view
;
2415 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2416 struct si_texture
*tex
=
2417 (struct si_texture
*)sview
->base
.texture
;
2419 if (depth_needs_decompression(tex
)) {
2420 util_dynarray_append(
2421 &sctx
->resident_tex_needs_depth_decompress
,
2422 struct si_texture_handle
*,
2426 if (color_needs_decompression(tex
)) {
2427 util_dynarray_append(
2428 &sctx
->resident_tex_needs_color_decompress
,
2429 struct si_texture_handle
*,
2433 if (tex
->dcc_offset
&&
2434 p_atomic_read(&tex
->framebuffers_bound
))
2435 sctx
->need_check_render_feedback
= true;
2437 si_update_bindless_texture_descriptor(sctx
, tex_handle
);
2439 si_update_bindless_buffer_descriptor(sctx
,
2440 tex_handle
->desc_slot
,
2441 sview
->base
.texture
,
2442 sview
->base
.u
.buf
.offset
,
2443 &tex_handle
->desc_dirty
);
2446 /* Re-upload the descriptor if it has been updated while it
2449 if (tex_handle
->desc_dirty
)
2450 sctx
->bindless_descriptors_dirty
= true;
2452 /* Add the texture handle to the per-context list. */
2453 util_dynarray_append(&sctx
->resident_tex_handles
,
2454 struct si_texture_handle
*, tex_handle
);
2456 /* Add the buffers to the current CS in case si_begin_new_cs()
2457 * is not going to be called.
2459 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2461 sview
->is_stencil_sampler
, false);
2463 /* Remove the texture handle from the per-context list. */
2464 util_dynarray_delete_unordered(&sctx
->resident_tex_handles
,
2465 struct si_texture_handle
*,
2468 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2469 util_dynarray_delete_unordered(
2470 &sctx
->resident_tex_needs_depth_decompress
,
2471 struct si_texture_handle
*, tex_handle
);
2473 util_dynarray_delete_unordered(
2474 &sctx
->resident_tex_needs_color_decompress
,
2475 struct si_texture_handle
*, tex_handle
);
2480 static uint64_t si_create_image_handle(struct pipe_context
*ctx
,
2481 const struct pipe_image_view
*view
)
2483 struct si_context
*sctx
= (struct si_context
*)ctx
;
2484 struct si_image_handle
*img_handle
;
2485 uint32_t desc_list
[8];
2488 if (!view
|| !view
->resource
)
2491 img_handle
= CALLOC_STRUCT(si_image_handle
);
2495 memset(desc_list
, 0, sizeof(desc_list
));
2496 si_init_descriptor_list(&desc_list
[0], 8, 1, null_image_descriptor
);
2498 si_set_shader_image_desc(sctx
, view
, false, &desc_list
[0], NULL
);
2500 img_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2502 if (!img_handle
->desc_slot
) {
2507 handle
= img_handle
->desc_slot
;
2509 if (!_mesa_hash_table_insert(sctx
->img_handles
,
2510 (void *)(uintptr_t)handle
,
2516 util_copy_image_view(&img_handle
->view
, view
);
2518 si_resource(view
->resource
)->image_handle_allocated
= true;
2523 static void si_delete_image_handle(struct pipe_context
*ctx
, uint64_t handle
)
2525 struct si_context
*sctx
= (struct si_context
*)ctx
;
2526 struct si_image_handle
*img_handle
;
2527 struct hash_entry
*entry
;
2529 entry
= _mesa_hash_table_search(sctx
->img_handles
,
2530 (void *)(uintptr_t)handle
);
2534 img_handle
= (struct si_image_handle
*)entry
->data
;
2536 util_copy_image_view(&img_handle
->view
, NULL
);
2537 _mesa_hash_table_remove(sctx
->img_handles
, entry
);
2541 static void si_make_image_handle_resident(struct pipe_context
*ctx
,
2542 uint64_t handle
, unsigned access
,
2545 struct si_context
*sctx
= (struct si_context
*)ctx
;
2546 struct si_image_handle
*img_handle
;
2547 struct pipe_image_view
*view
;
2548 struct si_resource
*res
;
2549 struct hash_entry
*entry
;
2551 entry
= _mesa_hash_table_search(sctx
->img_handles
,
2552 (void *)(uintptr_t)handle
);
2556 img_handle
= (struct si_image_handle
*)entry
->data
;
2557 view
= &img_handle
->view
;
2558 res
= si_resource(view
->resource
);
2561 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2562 struct si_texture
*tex
= (struct si_texture
*)res
;
2563 unsigned level
= view
->u
.tex
.level
;
2565 if (color_needs_decompression(tex
)) {
2566 util_dynarray_append(
2567 &sctx
->resident_img_needs_color_decompress
,
2568 struct si_image_handle
*,
2572 if (vi_dcc_enabled(tex
, level
) &&
2573 p_atomic_read(&tex
->framebuffers_bound
))
2574 sctx
->need_check_render_feedback
= true;
2576 si_update_bindless_image_descriptor(sctx
, img_handle
);
2578 si_update_bindless_buffer_descriptor(sctx
,
2579 img_handle
->desc_slot
,
2582 &img_handle
->desc_dirty
);
2585 /* Re-upload the descriptor if it has been updated while it
2588 if (img_handle
->desc_dirty
)
2589 sctx
->bindless_descriptors_dirty
= true;
2591 /* Add the image handle to the per-context list. */
2592 util_dynarray_append(&sctx
->resident_img_handles
,
2593 struct si_image_handle
*, img_handle
);
2595 /* Add the buffers to the current CS in case si_begin_new_cs()
2596 * is not going to be called.
2598 si_sampler_view_add_buffer(sctx
, view
->resource
,
2599 (access
& PIPE_IMAGE_ACCESS_WRITE
) ?
2600 RADEON_USAGE_READWRITE
:
2601 RADEON_USAGE_READ
, false, false);
2603 /* Remove the image handle from the per-context list. */
2604 util_dynarray_delete_unordered(&sctx
->resident_img_handles
,
2605 struct si_image_handle
*,
2608 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2609 util_dynarray_delete_unordered(
2610 &sctx
->resident_img_needs_color_decompress
,
2611 struct si_image_handle
*,
2618 void si_all_resident_buffers_begin_new_cs(struct si_context
*sctx
)
2620 unsigned num_resident_tex_handles
, num_resident_img_handles
;
2622 num_resident_tex_handles
= sctx
->resident_tex_handles
.size
/
2623 sizeof(struct si_texture_handle
*);
2624 num_resident_img_handles
= sctx
->resident_img_handles
.size
/
2625 sizeof(struct si_image_handle
*);
2627 /* Add all resident texture handles. */
2628 util_dynarray_foreach(&sctx
->resident_tex_handles
,
2629 struct si_texture_handle
*, tex_handle
) {
2630 struct si_sampler_view
*sview
=
2631 (struct si_sampler_view
*)(*tex_handle
)->view
;
2633 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2635 sview
->is_stencil_sampler
, false);
2638 /* Add all resident image handles. */
2639 util_dynarray_foreach(&sctx
->resident_img_handles
,
2640 struct si_image_handle
*, img_handle
) {
2641 struct pipe_image_view
*view
= &(*img_handle
)->view
;
2643 si_sampler_view_add_buffer(sctx
, view
->resource
,
2644 RADEON_USAGE_READWRITE
,
2648 sctx
->num_resident_handles
+= num_resident_tex_handles
+
2649 num_resident_img_handles
;
2652 /* INIT/DEINIT/UPLOAD */
2654 void si_init_all_descriptors(struct si_context
*sctx
)
2657 unsigned first_shader
=
2658 sctx
->has_graphics
? 0 : PIPE_SHADER_COMPUTE
;
2660 for (i
= first_shader
; i
< SI_NUM_SHADERS
; i
++) {
2661 bool is_2nd
= sctx
->chip_class
>= GFX9
&&
2662 (i
== PIPE_SHADER_TESS_CTRL
||
2663 i
== PIPE_SHADER_GEOMETRY
);
2664 unsigned num_sampler_slots
= SI_NUM_IMAGES
/ 2 + SI_NUM_SAMPLERS
;
2665 unsigned num_buffer_slots
= SI_NUM_SHADER_BUFFERS
+ SI_NUM_CONST_BUFFERS
;
2667 struct si_descriptors
*desc
;
2670 if (i
== PIPE_SHADER_TESS_CTRL
) {
2671 rel_dw_offset
= (R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
-
2672 R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2673 } else { /* PIPE_SHADER_GEOMETRY */
2674 rel_dw_offset
= (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
-
2675 R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2678 rel_dw_offset
= SI_SGPR_CONST_AND_SHADER_BUFFERS
;
2680 desc
= si_const_and_shader_buffer_descriptors(sctx
, i
);
2681 si_init_buffer_resources(&sctx
->const_and_shader_buffers
[i
], desc
,
2682 num_buffer_slots
, rel_dw_offset
,
2683 RADEON_PRIO_SHADER_RW_BUFFER
,
2684 RADEON_PRIO_CONST_BUFFER
);
2685 desc
->slot_index_to_bind_directly
= si_get_constbuf_slot(0);
2688 if (i
== PIPE_SHADER_TESS_CTRL
) {
2689 rel_dw_offset
= (R_00B40C_SPI_SHADER_USER_DATA_ADDR_HI_HS
-
2690 R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2691 } else { /* PIPE_SHADER_GEOMETRY */
2692 rel_dw_offset
= (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS
-
2693 R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2696 rel_dw_offset
= SI_SGPR_SAMPLERS_AND_IMAGES
;
2699 desc
= si_sampler_and_image_descriptors(sctx
, i
);
2700 si_init_descriptors(desc
, rel_dw_offset
, 16, num_sampler_slots
);
2703 for (j
= 0; j
< SI_NUM_IMAGES
; j
++)
2704 memcpy(desc
->list
+ j
* 8, null_image_descriptor
, 8 * 4);
2705 for (; j
< SI_NUM_IMAGES
+ SI_NUM_SAMPLERS
* 2; j
++)
2706 memcpy(desc
->list
+ j
* 8, null_texture_descriptor
, 8 * 4);
2709 si_init_buffer_resources(&sctx
->rw_buffers
,
2710 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
],
2711 SI_NUM_RW_BUFFERS
, SI_SGPR_RW_BUFFERS
,
2712 /* The second priority is used by
2713 * const buffers in RW buffer slots. */
2714 RADEON_PRIO_SHADER_RINGS
, RADEON_PRIO_CONST_BUFFER
);
2715 sctx
->descriptors
[SI_DESCS_RW_BUFFERS
].num_active_slots
= SI_NUM_RW_BUFFERS
;
2717 /* Initialize an array of 1024 bindless descriptors, when the limit is
2718 * reached, just make it larger and re-upload the whole array.
2720 si_init_bindless_descriptors(sctx
, &sctx
->bindless_descriptors
,
2721 SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES
,
2724 sctx
->descriptors_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2726 /* Set pipe_context functions. */
2727 sctx
->b
.bind_sampler_states
= si_bind_sampler_states
;
2728 sctx
->b
.set_shader_images
= si_set_shader_images
;
2729 sctx
->b
.set_constant_buffer
= si_pipe_set_constant_buffer
;
2730 sctx
->b
.set_shader_buffers
= si_set_shader_buffers
;
2731 sctx
->b
.set_sampler_views
= si_set_sampler_views
;
2732 sctx
->b
.create_texture_handle
= si_create_texture_handle
;
2733 sctx
->b
.delete_texture_handle
= si_delete_texture_handle
;
2734 sctx
->b
.make_texture_handle_resident
= si_make_texture_handle_resident
;
2735 sctx
->b
.create_image_handle
= si_create_image_handle
;
2736 sctx
->b
.delete_image_handle
= si_delete_image_handle
;
2737 sctx
->b
.make_image_handle_resident
= si_make_image_handle_resident
;
2739 if (!sctx
->has_graphics
)
2742 sctx
->b
.set_polygon_stipple
= si_set_polygon_stipple
;
2744 /* Shader user data. */
2745 sctx
->atoms
.s
.shader_pointers
.emit
= si_emit_graphics_shader_pointers
;
2747 /* Set default and immutable mappings. */
2748 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2750 if (sctx
->chip_class
>= GFX9
) {
2751 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2752 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2753 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2754 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2756 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2757 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2758 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2759 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2761 si_set_user_data_base(sctx
, PIPE_SHADER_FRAGMENT
, R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2764 static bool si_upload_shader_descriptors(struct si_context
*sctx
, unsigned mask
)
2766 unsigned dirty
= sctx
->descriptors_dirty
& mask
;
2768 /* Assume nothing will go wrong: */
2769 sctx
->shader_pointers_dirty
|= dirty
;
2772 unsigned i
= u_bit_scan(&dirty
);
2774 if (!si_upload_descriptors(sctx
, &sctx
->descriptors
[i
]))
2778 sctx
->descriptors_dirty
&= ~mask
;
2780 si_upload_bindless_descriptors(sctx
);
2785 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
)
2787 const unsigned mask
= u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE
);
2788 return si_upload_shader_descriptors(sctx
, mask
);
2791 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
)
2793 /* Does not update rw_buffers as that is not needed for compute shaders
2794 * and the input buffer is using the same SGPR's anyway.
2796 const unsigned mask
= u_bit_consecutive(SI_DESCS_FIRST_COMPUTE
,
2797 SI_NUM_DESCS
- SI_DESCS_FIRST_COMPUTE
);
2798 return si_upload_shader_descriptors(sctx
, mask
);
2801 void si_release_all_descriptors(struct si_context
*sctx
)
2805 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2806 si_release_buffer_resources(&sctx
->const_and_shader_buffers
[i
],
2807 si_const_and_shader_buffer_descriptors(sctx
, i
));
2808 si_release_sampler_views(&sctx
->samplers
[i
]);
2809 si_release_image_views(&sctx
->images
[i
]);
2811 si_release_buffer_resources(&sctx
->rw_buffers
,
2812 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2813 for (i
= 0; i
< SI_NUM_VERTEX_BUFFERS
; i
++)
2814 pipe_vertex_buffer_unreference(&sctx
->vertex_buffer
[i
]);
2816 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2817 si_release_descriptors(&sctx
->descriptors
[i
]);
2819 si_resource_reference(&sctx
->vb_descriptors_buffer
, NULL
);
2820 sctx
->vb_descriptors_gpu_list
= NULL
; /* points into a mapped buffer */
2822 si_release_bindless_descriptors(sctx
);
2825 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
)
2829 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2830 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[i
]);
2831 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[i
]);
2832 si_image_views_begin_new_cs(sctx
, &sctx
->images
[i
]);
2834 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2835 si_vertex_buffers_begin_new_cs(sctx
);
2837 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2838 si_descriptors_begin_new_cs(sctx
, &sctx
->descriptors
[i
]);
2839 si_descriptors_begin_new_cs(sctx
, &sctx
->bindless_descriptors
);
2841 si_shader_pointers_begin_new_cs(sctx
);
2844 void si_set_active_descriptors(struct si_context
*sctx
, unsigned desc_idx
,
2845 uint64_t new_active_mask
)
2847 struct si_descriptors
*desc
= &sctx
->descriptors
[desc_idx
];
2849 /* Ignore no-op updates and updates that disable all slots. */
2850 if (!new_active_mask
||
2851 new_active_mask
== u_bit_consecutive64(desc
->first_active_slot
,
2852 desc
->num_active_slots
))
2856 u_bit_scan_consecutive_range64(&new_active_mask
, &first
, &count
);
2857 assert(new_active_mask
== 0);
2859 /* Upload/dump descriptors if slots are being enabled. */
2860 if (first
< desc
->first_active_slot
||
2861 first
+ count
> desc
->first_active_slot
+ desc
->num_active_slots
)
2862 sctx
->descriptors_dirty
|= 1u << desc_idx
;
2864 desc
->first_active_slot
= first
;
2865 desc
->num_active_slots
= count
;
2868 void si_set_active_descriptors_for_shader(struct si_context
*sctx
,
2869 struct si_shader_selector
*sel
)
2874 si_set_active_descriptors(sctx
,
2875 si_const_and_shader_buffer_descriptors_idx(sel
->type
),
2876 sel
->active_const_and_shader_buffers
);
2877 si_set_active_descriptors(sctx
,
2878 si_sampler_and_image_descriptors_idx(sel
->type
),
2879 sel
->active_samplers_and_images
);