2 * Copyright 2013 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 /* Resource binding slots and sampler states (each described with 8 or
26 * 4 dwords) are stored in lists in memory which is accessed by shaders
27 * using scalar load instructions.
29 * This file is responsible for managing such lists. It keeps a copy of all
30 * descriptors in CPU memory and re-uploads a whole list if some slots have
33 * This code is also reponsible for updating shader pointers to those lists.
35 * Note that CP DMA can't be used for updating the lists, because a GPU hang
36 * could leave the list in a mid-IB state and the next IB would get wrong
37 * descriptors and the whole context would be unusable at that point.
38 * (Note: The register shadowing can't be used due to the same reason)
40 * Also, uploading descriptors to newly allocated memory doesn't require
44 * Possible scenarios for one 16 dword image+sampler slot:
46 * | Image | w/ FMASK | Buffer | NULL
47 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
48 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
49 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
50 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
52 * FMASK implies MSAA, therefore no sampler state.
53 * Sampler states are never unbound except when FMASK is bound.
60 #include "util/hash_table.h"
61 #include "util/u_idalloc.h"
62 #include "util/u_format.h"
63 #include "util/u_memory.h"
64 #include "util/u_upload_mgr.h"
67 /* NULL image and buffer descriptor for textures (alpha = 1) and images
70 * For images, all fields must be zero except for the swizzle, which
71 * supports arbitrary combinations of 0s and 1s. The texture type must be
72 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
74 * For buffers, all fields must be zero. If they are not, the hw hangs.
76 * This is the only reason why the buffer descriptor must be in words [4:7].
78 static uint32_t null_texture_descriptor
[8] = {
82 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1
) |
83 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
84 /* the rest must contain zeros, which is also used by the buffer
88 static uint32_t null_image_descriptor
[8] = {
92 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
93 /* the rest must contain zeros, which is also used by the buffer
97 static uint64_t si_desc_extract_buffer_address(const uint32_t *desc
)
99 uint64_t va
= desc
[0] |
100 ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc
[1]) << 32);
102 /* Sign-extend the 48-bit address. */
104 va
= (int64_t)va
>> 16;
108 static void si_init_descriptor_list(uint32_t *desc_list
,
109 unsigned element_dw_size
,
110 unsigned num_elements
,
111 const uint32_t *null_descriptor
)
115 /* Initialize the array to NULL descriptors if the element size is 8. */
116 if (null_descriptor
) {
117 assert(element_dw_size
% 8 == 0);
118 for (i
= 0; i
< num_elements
* element_dw_size
/ 8; i
++)
119 memcpy(desc_list
+ i
* 8, null_descriptor
, 8 * 4);
123 static void si_init_descriptors(struct si_descriptors
*desc
,
124 short shader_userdata_rel_index
,
125 unsigned element_dw_size
,
126 unsigned num_elements
)
128 desc
->list
= CALLOC(num_elements
, element_dw_size
* 4);
129 desc
->element_dw_size
= element_dw_size
;
130 desc
->num_elements
= num_elements
;
131 desc
->shader_userdata_offset
= shader_userdata_rel_index
* 4;
132 desc
->slot_index_to_bind_directly
= -1;
135 static void si_release_descriptors(struct si_descriptors
*desc
)
137 si_resource_reference(&desc
->buffer
, NULL
);
141 static bool si_upload_descriptors(struct si_context
*sctx
,
142 struct si_descriptors
*desc
)
144 unsigned slot_size
= desc
->element_dw_size
* 4;
145 unsigned first_slot_offset
= desc
->first_active_slot
* slot_size
;
146 unsigned upload_size
= desc
->num_active_slots
* slot_size
;
148 /* Skip the upload if no shader is using the descriptors. dirty_mask
149 * will stay dirty and the descriptors will be uploaded when there is
150 * a shader using them.
155 /* If there is just one active descriptor, bind it directly. */
156 if ((int)desc
->first_active_slot
== desc
->slot_index_to_bind_directly
&&
157 desc
->num_active_slots
== 1) {
158 uint32_t *descriptor
= &desc
->list
[desc
->slot_index_to_bind_directly
*
159 desc
->element_dw_size
];
161 /* The buffer is already in the buffer list. */
162 si_resource_reference(&desc
->buffer
, NULL
);
163 desc
->gpu_list
= NULL
;
164 desc
->gpu_address
= si_desc_extract_buffer_address(descriptor
);
165 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
170 unsigned buffer_offset
;
171 u_upload_alloc(sctx
->b
.const_uploader
, first_slot_offset
, upload_size
,
172 si_optimal_tcc_alignment(sctx
, upload_size
),
173 &buffer_offset
, (struct pipe_resource
**)&desc
->buffer
,
176 desc
->gpu_address
= 0;
177 return false; /* skip the draw call */
180 util_memcpy_cpu_to_le32(ptr
, (char*)desc
->list
+ first_slot_offset
,
182 desc
->gpu_list
= ptr
- first_slot_offset
/ 4;
184 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, desc
->buffer
,
185 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
187 /* The shader pointer should point to slot 0. */
188 buffer_offset
-= first_slot_offset
;
189 desc
->gpu_address
= desc
->buffer
->gpu_address
+ buffer_offset
;
191 assert(desc
->buffer
->flags
& RADEON_FLAG_32BIT
);
192 assert((desc
->buffer
->gpu_address
>> 32) == sctx
->screen
->info
.address32_hi
);
193 assert((desc
->gpu_address
>> 32) == sctx
->screen
->info
.address32_hi
);
195 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
200 si_descriptors_begin_new_cs(struct si_context
*sctx
, struct si_descriptors
*desc
)
205 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, desc
->buffer
,
206 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
211 static inline enum radeon_bo_priority
212 si_get_sampler_view_priority(struct si_resource
*res
)
214 if (res
->b
.b
.target
== PIPE_BUFFER
)
215 return RADEON_PRIO_SAMPLER_BUFFER
;
217 if (res
->b
.b
.nr_samples
> 1)
218 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA
;
220 return RADEON_PRIO_SAMPLER_TEXTURE
;
224 si_sampler_and_image_descriptors_idx(unsigned shader
)
226 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
227 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
;
230 static struct si_descriptors
*
231 si_sampler_and_image_descriptors(struct si_context
*sctx
, unsigned shader
)
233 return &sctx
->descriptors
[si_sampler_and_image_descriptors_idx(shader
)];
236 static void si_release_sampler_views(struct si_samplers
*samplers
)
240 for (i
= 0; i
< ARRAY_SIZE(samplers
->views
); i
++) {
241 pipe_sampler_view_reference(&samplers
->views
[i
], NULL
);
245 static void si_sampler_view_add_buffer(struct si_context
*sctx
,
246 struct pipe_resource
*resource
,
247 enum radeon_bo_usage usage
,
248 bool is_stencil_sampler
,
251 struct si_texture
*tex
= (struct si_texture
*)resource
;
252 enum radeon_bo_priority priority
;
257 /* Use the flushed depth texture if direct sampling is unsupported. */
258 if (resource
->target
!= PIPE_BUFFER
&&
259 tex
->is_depth
&& !si_can_sample_zs(tex
, is_stencil_sampler
))
260 tex
= tex
->flushed_depth_texture
;
262 priority
= si_get_sampler_view_priority(&tex
->buffer
);
263 radeon_add_to_gfx_buffer_list_check_mem(sctx
, &tex
->buffer
, usage
, priority
,
266 if (resource
->target
== PIPE_BUFFER
)
269 /* Add separate DCC. */
270 if (tex
->dcc_separate_buffer
) {
271 radeon_add_to_gfx_buffer_list_check_mem(sctx
, tex
->dcc_separate_buffer
,
272 usage
, RADEON_PRIO_SEPARATE_META
, check_mem
);
276 static void si_sampler_views_begin_new_cs(struct si_context
*sctx
,
277 struct si_samplers
*samplers
)
279 unsigned mask
= samplers
->enabled_mask
;
281 /* Add buffers to the CS. */
283 int i
= u_bit_scan(&mask
);
284 struct si_sampler_view
*sview
= (struct si_sampler_view
*)samplers
->views
[i
];
286 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
288 sview
->is_stencil_sampler
, false);
292 /* Set buffer descriptor fields that can be changed by reallocations. */
293 static void si_set_buf_desc_address(struct si_resource
*buf
,
294 uint64_t offset
, uint32_t *state
)
296 uint64_t va
= buf
->gpu_address
+ offset
;
299 state
[1] &= C_008F04_BASE_ADDRESS_HI
;
300 state
[1] |= S_008F04_BASE_ADDRESS_HI(va
>> 32);
303 /* Set texture descriptor fields that can be changed by reallocations.
306 * \param base_level_info information of the level of BASE_ADDRESS
307 * \param base_level the level of BASE_ADDRESS
308 * \param first_level pipe_sampler_view.u.tex.first_level
309 * \param block_width util_format_get_blockwidth()
310 * \param is_stencil select between separate Z & Stencil
311 * \param state descriptor to update
313 void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen
,
314 struct si_texture
*tex
,
315 const struct legacy_surf_level
*base_level_info
,
316 unsigned base_level
, unsigned first_level
,
317 unsigned block_width
, bool is_stencil
,
320 uint64_t va
, meta_va
= 0;
322 if (tex
->is_depth
&& !si_can_sample_zs(tex
, is_stencil
)) {
323 tex
= tex
->flushed_depth_texture
;
327 va
= tex
->buffer
.gpu_address
;
329 if (sscreen
->info
.chip_class
>= GFX9
) {
330 /* Only stencil_offset needs to be added here. */
332 va
+= tex
->surface
.u
.gfx9
.stencil_offset
;
334 va
+= tex
->surface
.u
.gfx9
.surf_offset
;
336 va
+= base_level_info
->offset
;
340 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
341 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
343 /* Only macrotiled modes can set tile swizzle.
344 * GFX9 doesn't use (legacy) base_level_info.
346 if (sscreen
->info
.chip_class
>= GFX9
||
347 base_level_info
->mode
== RADEON_SURF_MODE_2D
)
348 state
[0] |= tex
->surface
.tile_swizzle
;
350 if (sscreen
->info
.chip_class
>= VI
) {
351 state
[6] &= C_008F28_COMPRESSION_EN
;
354 if (vi_dcc_enabled(tex
, first_level
)) {
355 meta_va
= (!tex
->dcc_separate_buffer
? tex
->buffer
.gpu_address
: 0) +
358 if (sscreen
->info
.chip_class
== VI
) {
359 meta_va
+= base_level_info
->dcc_offset
;
360 assert(base_level_info
->mode
== RADEON_SURF_MODE_2D
);
363 meta_va
|= (uint32_t)tex
->surface
.tile_swizzle
<< 8;
364 } else if (vi_tc_compat_htile_enabled(tex
, first_level
)) {
365 meta_va
= tex
->buffer
.gpu_address
+ tex
->htile_offset
;
369 state
[6] |= S_008F28_COMPRESSION_EN(1);
370 state
[7] = meta_va
>> 8;
374 if (sscreen
->info
.chip_class
>= GFX9
) {
375 state
[3] &= C_008F1C_SW_MODE
;
376 state
[4] &= C_008F20_PITCH_GFX9
;
379 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
380 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.stencil
.epitch
);
382 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
);
383 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.surf
.epitch
);
386 state
[5] &= C_008F24_META_DATA_ADDRESS
&
387 C_008F24_META_PIPE_ALIGNED
&
388 C_008F24_META_RB_ALIGNED
;
390 struct gfx9_surf_meta_flags meta
;
393 meta
= tex
->surface
.u
.gfx9
.dcc
;
395 meta
= tex
->surface
.u
.gfx9
.htile
;
397 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
398 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
399 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
403 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
404 unsigned index
= si_tile_mode_index(tex
, base_level
, is_stencil
);
406 state
[3] &= C_008F1C_TILING_INDEX
;
407 state
[3] |= S_008F1C_TILING_INDEX(index
);
408 state
[4] &= C_008F20_PITCH_GFX6
;
409 state
[4] |= S_008F20_PITCH_GFX6(pitch
- 1);
413 static void si_set_sampler_state_desc(struct si_sampler_state
*sstate
,
414 struct si_sampler_view
*sview
,
415 struct si_texture
*tex
,
418 if (sview
&& sview
->is_integer
)
419 memcpy(desc
, sstate
->integer_val
, 4*4);
420 else if (tex
&& tex
->upgraded_depth
&&
421 (!sview
|| !sview
->is_stencil_sampler
))
422 memcpy(desc
, sstate
->upgraded_depth_val
, 4*4);
424 memcpy(desc
, sstate
->val
, 4*4);
427 static void si_set_sampler_view_desc(struct si_context
*sctx
,
428 struct si_sampler_view
*sview
,
429 struct si_sampler_state
*sstate
,
432 struct pipe_sampler_view
*view
= &sview
->base
;
433 struct si_texture
*tex
= (struct si_texture
*)view
->texture
;
434 bool is_buffer
= tex
->buffer
.b
.b
.target
== PIPE_BUFFER
;
436 if (unlikely(!is_buffer
&& sview
->dcc_incompatible
)) {
437 if (vi_dcc_enabled(tex
, view
->u
.tex
.first_level
))
438 if (!si_texture_disable_dcc(sctx
, tex
))
439 si_decompress_dcc(sctx
, tex
);
441 sview
->dcc_incompatible
= false;
444 assert(tex
); /* views with texture == NULL aren't supported */
445 memcpy(desc
, sview
->state
, 8*4);
448 si_set_buf_desc_address(&tex
->buffer
,
449 sview
->base
.u
.buf
.offset
,
452 bool is_separate_stencil
= tex
->db_compatible
&&
453 sview
->is_stencil_sampler
;
455 si_set_mutable_tex_desc_fields(sctx
->screen
, tex
,
456 sview
->base_level_info
,
458 sview
->base
.u
.tex
.first_level
,
464 if (!is_buffer
&& tex
->surface
.fmask_size
) {
465 memcpy(desc
+ 8, sview
->fmask_state
, 8*4);
467 /* Disable FMASK and bind sampler state in [12:15]. */
468 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
471 si_set_sampler_state_desc(sstate
, sview
,
472 is_buffer
? NULL
: tex
,
477 static bool color_needs_decompression(struct si_texture
*tex
)
479 return tex
->surface
.fmask_size
||
480 (tex
->dirty_level_mask
&&
481 (tex
->cmask_buffer
|| tex
->dcc_offset
));
484 static bool depth_needs_decompression(struct si_texture
*tex
)
486 /* If the depth/stencil texture is TC-compatible, no decompression
487 * will be done. The decompression function will only flush DB caches
488 * to make it coherent with shaders. That's necessary because the driver
489 * doesn't flush DB caches in any other case.
491 return tex
->db_compatible
;
494 static void si_set_sampler_view(struct si_context
*sctx
,
496 unsigned slot
, struct pipe_sampler_view
*view
,
497 bool disallow_early_out
)
499 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
500 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
501 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(sctx
, shader
);
502 unsigned desc_slot
= si_get_sampler_slot(slot
);
503 uint32_t *desc
= descs
->list
+ desc_slot
* 16;
505 if (samplers
->views
[slot
] == view
&& !disallow_early_out
)
509 struct si_texture
*tex
= (struct si_texture
*)view
->texture
;
511 si_set_sampler_view_desc(sctx
, sview
,
512 samplers
->sampler_states
[slot
], desc
);
514 if (tex
->buffer
.b
.b
.target
== PIPE_BUFFER
) {
515 tex
->buffer
.bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
516 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
517 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
519 if (depth_needs_decompression(tex
)) {
520 samplers
->needs_depth_decompress_mask
|= 1u << slot
;
522 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
524 if (color_needs_decompression(tex
)) {
525 samplers
->needs_color_decompress_mask
|= 1u << slot
;
527 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
530 if (tex
->dcc_offset
&&
531 p_atomic_read(&tex
->framebuffers_bound
))
532 sctx
->need_check_render_feedback
= true;
535 pipe_sampler_view_reference(&samplers
->views
[slot
], view
);
536 samplers
->enabled_mask
|= 1u << slot
;
538 /* Since this can flush, it must be done after enabled_mask is
540 si_sampler_view_add_buffer(sctx
, view
->texture
,
542 sview
->is_stencil_sampler
, true);
544 pipe_sampler_view_reference(&samplers
->views
[slot
], NULL
);
545 memcpy(desc
, null_texture_descriptor
, 8*4);
546 /* Only clear the lower dwords of FMASK. */
547 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
548 /* Re-set the sampler state if we are transitioning from FMASK. */
549 if (samplers
->sampler_states
[slot
])
550 si_set_sampler_state_desc(samplers
->sampler_states
[slot
], NULL
, NULL
,
553 samplers
->enabled_mask
&= ~(1u << slot
);
554 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
555 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
558 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
561 static void si_update_shader_needs_decompress_mask(struct si_context
*sctx
,
564 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
565 unsigned shader_bit
= 1 << shader
;
567 if (samplers
->needs_depth_decompress_mask
||
568 samplers
->needs_color_decompress_mask
||
569 sctx
->images
[shader
].needs_color_decompress_mask
)
570 sctx
->shader_needs_decompress_mask
|= shader_bit
;
572 sctx
->shader_needs_decompress_mask
&= ~shader_bit
;
575 static void si_set_sampler_views(struct pipe_context
*ctx
,
576 enum pipe_shader_type shader
, unsigned start
,
578 struct pipe_sampler_view
**views
)
580 struct si_context
*sctx
= (struct si_context
*)ctx
;
583 if (!count
|| shader
>= SI_NUM_SHADERS
)
587 for (i
= 0; i
< count
; i
++)
588 si_set_sampler_view(sctx
, shader
, start
+ i
, views
[i
], false);
590 for (i
= 0; i
< count
; i
++)
591 si_set_sampler_view(sctx
, shader
, start
+ i
, NULL
, false);
594 si_update_shader_needs_decompress_mask(sctx
, shader
);
598 si_samplers_update_needs_color_decompress_mask(struct si_samplers
*samplers
)
600 unsigned mask
= samplers
->enabled_mask
;
603 int i
= u_bit_scan(&mask
);
604 struct pipe_resource
*res
= samplers
->views
[i
]->texture
;
606 if (res
&& res
->target
!= PIPE_BUFFER
) {
607 struct si_texture
*tex
= (struct si_texture
*)res
;
609 if (color_needs_decompression(tex
)) {
610 samplers
->needs_color_decompress_mask
|= 1u << i
;
612 samplers
->needs_color_decompress_mask
&= ~(1u << i
);
621 si_release_image_views(struct si_images
*images
)
625 for (i
= 0; i
< SI_NUM_IMAGES
; ++i
) {
626 struct pipe_image_view
*view
= &images
->views
[i
];
628 pipe_resource_reference(&view
->resource
, NULL
);
633 si_image_views_begin_new_cs(struct si_context
*sctx
, struct si_images
*images
)
635 uint mask
= images
->enabled_mask
;
637 /* Add buffers to the CS. */
639 int i
= u_bit_scan(&mask
);
640 struct pipe_image_view
*view
= &images
->views
[i
];
642 assert(view
->resource
);
644 si_sampler_view_add_buffer(sctx
, view
->resource
,
645 RADEON_USAGE_READWRITE
, false, false);
650 si_disable_shader_image(struct si_context
*ctx
, unsigned shader
, unsigned slot
)
652 struct si_images
*images
= &ctx
->images
[shader
];
654 if (images
->enabled_mask
& (1u << slot
)) {
655 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
656 unsigned desc_slot
= si_get_image_slot(slot
);
658 pipe_resource_reference(&images
->views
[slot
].resource
, NULL
);
659 images
->needs_color_decompress_mask
&= ~(1 << slot
);
661 memcpy(descs
->list
+ desc_slot
*8, null_image_descriptor
, 8*4);
662 images
->enabled_mask
&= ~(1u << slot
);
663 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
668 si_mark_image_range_valid(const struct pipe_image_view
*view
)
670 struct si_resource
*res
= si_resource(view
->resource
);
672 assert(res
&& res
->b
.b
.target
== PIPE_BUFFER
);
674 util_range_add(&res
->valid_buffer_range
,
676 view
->u
.buf
.offset
+ view
->u
.buf
.size
);
679 static void si_set_shader_image_desc(struct si_context
*ctx
,
680 const struct pipe_image_view
*view
,
681 bool skip_decompress
,
682 uint32_t *desc
, uint32_t *fmask_desc
)
684 struct si_screen
*screen
= ctx
->screen
;
685 struct si_resource
*res
;
687 res
= si_resource(view
->resource
);
689 if (res
->b
.b
.target
== PIPE_BUFFER
) {
690 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
691 si_mark_image_range_valid(view
);
693 si_make_buffer_descriptor(screen
, res
,
696 view
->u
.buf
.size
, desc
);
697 si_set_buf_desc_address(res
, view
->u
.buf
.offset
, desc
+ 4);
699 static const unsigned char swizzle
[4] = { 0, 1, 2, 3 };
700 struct si_texture
*tex
= (struct si_texture
*)res
;
701 unsigned level
= view
->u
.tex
.level
;
702 unsigned width
, height
, depth
, hw_level
;
703 bool uses_dcc
= vi_dcc_enabled(tex
, level
);
704 unsigned access
= view
->access
;
706 /* Clear the write flag when writes can't occur.
707 * Note that DCC_DECOMPRESS for MSAA doesn't work in some cases,
708 * so we don't wanna trigger it.
711 (!fmask_desc
&& tex
->surface
.fmask_size
!= 0)) {
712 assert(!"Z/S and MSAA image stores are not supported");
713 access
&= ~PIPE_IMAGE_ACCESS_WRITE
;
716 assert(!tex
->is_depth
);
717 assert(fmask_desc
|| tex
->surface
.fmask_size
== 0);
719 if (uses_dcc
&& !skip_decompress
&&
720 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
||
721 !vi_dcc_formats_compatible(res
->b
.b
.format
, view
->format
))) {
722 /* If DCC can't be disabled, at least decompress it.
723 * The decompression is relatively cheap if the surface
724 * has been decompressed already.
726 if (!si_texture_disable_dcc(ctx
, tex
))
727 si_decompress_dcc(ctx
, tex
);
730 if (ctx
->chip_class
>= GFX9
) {
731 /* Always set the base address. The swizzle modes don't
732 * allow setting mipmap level offsets as the base.
734 width
= res
->b
.b
.width0
;
735 height
= res
->b
.b
.height0
;
736 depth
= res
->b
.b
.depth0
;
739 /* Always force the base level to the selected level.
741 * This is required for 3D textures, where otherwise
742 * selecting a single slice for non-layered bindings
743 * fails. It doesn't hurt the other targets.
745 width
= u_minify(res
->b
.b
.width0
, level
);
746 height
= u_minify(res
->b
.b
.height0
, level
);
747 depth
= u_minify(res
->b
.b
.depth0
, level
);
751 si_make_texture_descriptor(screen
, tex
,
752 false, res
->b
.b
.target
,
753 view
->format
, swizzle
,
755 view
->u
.tex
.first_layer
,
756 view
->u
.tex
.last_layer
,
757 width
, height
, depth
,
759 si_set_mutable_tex_desc_fields(screen
, tex
,
760 &tex
->surface
.u
.legacy
.level
[level
],
762 util_format_get_blockwidth(view
->format
),
767 static void si_set_shader_image(struct si_context
*ctx
,
769 unsigned slot
, const struct pipe_image_view
*view
,
770 bool skip_decompress
)
772 struct si_images
*images
= &ctx
->images
[shader
];
773 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
774 struct si_resource
*res
;
775 unsigned desc_slot
= si_get_image_slot(slot
);
776 uint32_t *desc
= descs
->list
+ desc_slot
* 8;
778 if (!view
|| !view
->resource
) {
779 si_disable_shader_image(ctx
, shader
, slot
);
783 res
= si_resource(view
->resource
);
785 if (&images
->views
[slot
] != view
)
786 util_copy_image_view(&images
->views
[slot
], view
);
788 si_set_shader_image_desc(ctx
, view
, skip_decompress
, desc
, NULL
);
790 if (res
->b
.b
.target
== PIPE_BUFFER
) {
791 images
->needs_color_decompress_mask
&= ~(1 << slot
);
792 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
794 struct si_texture
*tex
= (struct si_texture
*)res
;
795 unsigned level
= view
->u
.tex
.level
;
797 if (color_needs_decompression(tex
)) {
798 images
->needs_color_decompress_mask
|= 1 << slot
;
800 images
->needs_color_decompress_mask
&= ~(1 << slot
);
803 if (vi_dcc_enabled(tex
, level
) &&
804 p_atomic_read(&tex
->framebuffers_bound
))
805 ctx
->need_check_render_feedback
= true;
808 images
->enabled_mask
|= 1u << slot
;
809 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
811 /* Since this can flush, it must be done after enabled_mask is updated. */
812 si_sampler_view_add_buffer(ctx
, &res
->b
.b
,
813 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
) ?
814 RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
,
819 si_set_shader_images(struct pipe_context
*pipe
,
820 enum pipe_shader_type shader
,
821 unsigned start_slot
, unsigned count
,
822 const struct pipe_image_view
*views
)
824 struct si_context
*ctx
= (struct si_context
*)pipe
;
827 assert(shader
< SI_NUM_SHADERS
);
832 assert(start_slot
+ count
<= SI_NUM_IMAGES
);
835 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
836 si_set_shader_image(ctx
, shader
, slot
, &views
[i
], false);
838 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
839 si_set_shader_image(ctx
, shader
, slot
, NULL
, false);
842 si_update_shader_needs_decompress_mask(ctx
, shader
);
846 si_images_update_needs_color_decompress_mask(struct si_images
*images
)
848 unsigned mask
= images
->enabled_mask
;
851 int i
= u_bit_scan(&mask
);
852 struct pipe_resource
*res
= images
->views
[i
].resource
;
854 if (res
&& res
->target
!= PIPE_BUFFER
) {
855 struct si_texture
*tex
= (struct si_texture
*)res
;
857 if (color_needs_decompression(tex
)) {
858 images
->needs_color_decompress_mask
|= 1 << i
;
860 images
->needs_color_decompress_mask
&= ~(1 << i
);
866 void si_update_ps_colorbuf0_slot(struct si_context
*sctx
)
868 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
869 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
870 unsigned slot
= SI_PS_IMAGE_COLORBUF0
;
871 struct pipe_surface
*surf
= NULL
;
873 /* si_texture_disable_dcc can get us here again. */
874 if (sctx
->blitter
->running
)
877 /* See whether FBFETCH is used and color buffer 0 is set. */
878 if (sctx
->ps_shader
.cso
&&
879 sctx
->ps_shader
.cso
->info
.opcode_count
[TGSI_OPCODE_FBFETCH
] &&
880 sctx
->framebuffer
.state
.nr_cbufs
&&
881 sctx
->framebuffer
.state
.cbufs
[0])
882 surf
= sctx
->framebuffer
.state
.cbufs
[0];
884 /* Return if FBFETCH transitions from disabled to disabled. */
885 if (!buffers
->buffers
[slot
] && !surf
)
888 sctx
->ps_uses_fbfetch
= surf
!= NULL
;
889 si_update_ps_iter_samples(sctx
);
892 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
893 struct pipe_image_view view
;
896 assert(!tex
->is_depth
);
898 /* Disable DCC, because the texture is used as both a sampler
901 si_texture_disable_dcc(sctx
, tex
);
903 if (tex
->buffer
.b
.b
.nr_samples
<= 1 && tex
->cmask_buffer
) {
905 assert(tex
->cmask_buffer
!= &tex
->buffer
);
906 si_eliminate_fast_color_clear(sctx
, tex
);
907 si_texture_discard_cmask(sctx
->screen
, tex
);
910 view
.resource
= surf
->texture
;
911 view
.format
= surf
->format
;
912 view
.access
= PIPE_IMAGE_ACCESS_READ
;
913 view
.u
.tex
.first_layer
= surf
->u
.tex
.first_layer
;
914 view
.u
.tex
.last_layer
= surf
->u
.tex
.last_layer
;
915 view
.u
.tex
.level
= surf
->u
.tex
.level
;
917 /* Set the descriptor. */
918 uint32_t *desc
= descs
->list
+ slot
*4;
919 memset(desc
, 0, 16 * 4);
920 si_set_shader_image_desc(sctx
, &view
, true, desc
, desc
+ 8);
922 pipe_resource_reference(&buffers
->buffers
[slot
], &tex
->buffer
.b
.b
);
923 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
924 &tex
->buffer
, RADEON_USAGE_READ
,
925 RADEON_PRIO_SHADER_RW_IMAGE
);
926 buffers
->enabled_mask
|= 1u << slot
;
928 /* Clear the descriptor. */
929 memset(descs
->list
+ slot
*4, 0, 8*4);
930 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
931 buffers
->enabled_mask
&= ~(1u << slot
);
934 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
939 static void si_bind_sampler_states(struct pipe_context
*ctx
,
940 enum pipe_shader_type shader
,
941 unsigned start
, unsigned count
, void **states
)
943 struct si_context
*sctx
= (struct si_context
*)ctx
;
944 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
945 struct si_descriptors
*desc
= si_sampler_and_image_descriptors(sctx
, shader
);
946 struct si_sampler_state
**sstates
= (struct si_sampler_state
**)states
;
949 if (!count
|| shader
>= SI_NUM_SHADERS
)
952 for (i
= 0; i
< count
; i
++) {
953 unsigned slot
= start
+ i
;
954 unsigned desc_slot
= si_get_sampler_slot(slot
);
957 sstates
[i
] == samplers
->sampler_states
[slot
])
961 assert(sstates
[i
]->magic
== SI_SAMPLER_STATE_MAGIC
);
963 samplers
->sampler_states
[slot
] = sstates
[i
];
965 /* If FMASK is bound, don't overwrite it.
966 * The sampler state will be set after FMASK is unbound.
968 struct si_sampler_view
*sview
=
969 (struct si_sampler_view
*)samplers
->views
[slot
];
971 struct si_texture
*tex
= NULL
;
973 if (sview
&& sview
->base
.texture
&&
974 sview
->base
.texture
->target
!= PIPE_BUFFER
)
975 tex
= (struct si_texture
*)sview
->base
.texture
;
977 if (tex
&& tex
->surface
.fmask_size
)
980 si_set_sampler_state_desc(sstates
[i
], sview
, tex
,
981 desc
->list
+ desc_slot
* 16 + 12);
983 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
987 /* BUFFER RESOURCES */
989 static void si_init_buffer_resources(struct si_buffer_resources
*buffers
,
990 struct si_descriptors
*descs
,
991 unsigned num_buffers
,
992 short shader_userdata_rel_index
,
993 enum radeon_bo_usage shader_usage
,
994 enum radeon_bo_usage shader_usage_constbuf
,
995 enum radeon_bo_priority priority
,
996 enum radeon_bo_priority priority_constbuf
)
998 buffers
->shader_usage
= shader_usage
;
999 buffers
->shader_usage_constbuf
= shader_usage_constbuf
;
1000 buffers
->priority
= priority
;
1001 buffers
->priority_constbuf
= priority_constbuf
;
1002 buffers
->buffers
= CALLOC(num_buffers
, sizeof(struct pipe_resource
*));
1004 si_init_descriptors(descs
, shader_userdata_rel_index
, 4, num_buffers
);
1007 static void si_release_buffer_resources(struct si_buffer_resources
*buffers
,
1008 struct si_descriptors
*descs
)
1012 for (i
= 0; i
< descs
->num_elements
; i
++) {
1013 pipe_resource_reference(&buffers
->buffers
[i
], NULL
);
1016 FREE(buffers
->buffers
);
1019 static void si_buffer_resources_begin_new_cs(struct si_context
*sctx
,
1020 struct si_buffer_resources
*buffers
)
1022 unsigned mask
= buffers
->enabled_mask
;
1024 /* Add buffers to the CS. */
1026 int i
= u_bit_scan(&mask
);
1028 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1029 si_resource(buffers
->buffers
[i
]),
1030 i
< SI_NUM_SHADER_BUFFERS
? buffers
->shader_usage
:
1031 buffers
->shader_usage_constbuf
,
1032 i
< SI_NUM_SHADER_BUFFERS
? buffers
->priority
:
1033 buffers
->priority_constbuf
);
1037 static void si_get_buffer_from_descriptors(struct si_buffer_resources
*buffers
,
1038 struct si_descriptors
*descs
,
1039 unsigned idx
, struct pipe_resource
**buf
,
1040 unsigned *offset
, unsigned *size
)
1042 pipe_resource_reference(buf
, buffers
->buffers
[idx
]);
1044 struct si_resource
*res
= si_resource(*buf
);
1045 const uint32_t *desc
= descs
->list
+ idx
* 4;
1050 assert(G_008F04_STRIDE(desc
[1]) == 0);
1051 va
= si_desc_extract_buffer_address(desc
);
1053 assert(va
>= res
->gpu_address
&& va
+ *size
<= res
->gpu_address
+ res
->bo_size
);
1054 *offset
= va
- res
->gpu_address
;
1058 /* VERTEX BUFFERS */
1060 static void si_vertex_buffers_begin_new_cs(struct si_context
*sctx
)
1062 int count
= sctx
->vertex_elements
? sctx
->vertex_elements
->count
: 0;
1065 for (i
= 0; i
< count
; i
++) {
1066 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1068 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1070 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1073 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1074 si_resource(sctx
->vertex_buffer
[vb
].buffer
.resource
),
1075 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1078 if (!sctx
->vb_descriptors_buffer
)
1080 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1081 sctx
->vb_descriptors_buffer
, RADEON_USAGE_READ
,
1082 RADEON_PRIO_DESCRIPTORS
);
1085 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
)
1087 struct si_vertex_elements
*velems
= sctx
->vertex_elements
;
1089 unsigned desc_list_byte_size
;
1090 unsigned first_vb_use_mask
;
1093 if (!sctx
->vertex_buffers_dirty
|| !velems
)
1096 count
= velems
->count
;
1101 desc_list_byte_size
= velems
->desc_list_byte_size
;
1102 first_vb_use_mask
= velems
->first_vb_use_mask
;
1104 /* Vertex buffer descriptors are the only ones which are uploaded
1105 * directly through a staging buffer and don't go through
1106 * the fine-grained upload path.
1108 u_upload_alloc(sctx
->b
.const_uploader
, 0,
1109 desc_list_byte_size
,
1110 si_optimal_tcc_alignment(sctx
, desc_list_byte_size
),
1111 &sctx
->vb_descriptors_offset
,
1112 (struct pipe_resource
**)&sctx
->vb_descriptors_buffer
,
1114 if (!sctx
->vb_descriptors_buffer
) {
1115 sctx
->vb_descriptors_offset
= 0;
1116 sctx
->vb_descriptors_gpu_list
= NULL
;
1120 sctx
->vb_descriptors_gpu_list
= ptr
;
1121 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1122 sctx
->vb_descriptors_buffer
, RADEON_USAGE_READ
,
1123 RADEON_PRIO_DESCRIPTORS
);
1125 assert(count
<= SI_MAX_ATTRIBS
);
1127 for (i
= 0; i
< count
; i
++) {
1128 struct pipe_vertex_buffer
*vb
;
1129 struct si_resource
*rbuffer
;
1130 unsigned vbo_index
= velems
->vertex_buffer_index
[i
];
1131 uint32_t *desc
= &ptr
[i
*4];
1133 vb
= &sctx
->vertex_buffer
[vbo_index
];
1134 rbuffer
= si_resource(vb
->buffer
.resource
);
1136 memset(desc
, 0, 16);
1140 int64_t offset
= (int64_t)((int)vb
->buffer_offset
) +
1141 velems
->src_offset
[i
];
1142 uint64_t va
= rbuffer
->gpu_address
+ offset
;
1144 int64_t num_records
= (int64_t)rbuffer
->b
.b
.width0
- offset
;
1145 if (sctx
->chip_class
!= VI
&& vb
->stride
) {
1146 /* Round up by rounding down and adding 1 */
1147 num_records
= (num_records
- velems
->format_size
[i
]) /
1150 assert(num_records
>= 0 && num_records
<= UINT_MAX
);
1153 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1154 S_008F04_STRIDE(vb
->stride
);
1155 desc
[2] = num_records
;
1156 desc
[3] = velems
->rsrc_word3
[i
];
1158 if (first_vb_use_mask
& (1 << i
)) {
1159 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1160 si_resource(vb
->buffer
.resource
),
1161 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1165 /* Don't flush the const cache. It would have a very negative effect
1166 * on performance (confirmed by testing). New descriptors are always
1167 * uploaded to a fresh new buffer, so I don't think flushing the const
1168 * cache is needed. */
1169 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
1170 sctx
->vertex_buffers_dirty
= false;
1171 sctx
->vertex_buffer_pointer_dirty
= true;
1172 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VBO_DESCRIPTORS
;
1177 /* CONSTANT BUFFERS */
1180 si_const_and_shader_buffer_descriptors_idx(unsigned shader
)
1182 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
1183 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
;
1186 static struct si_descriptors
*
1187 si_const_and_shader_buffer_descriptors(struct si_context
*sctx
, unsigned shader
)
1189 return &sctx
->descriptors
[si_const_and_shader_buffer_descriptors_idx(shader
)];
1192 void si_upload_const_buffer(struct si_context
*sctx
, struct si_resource
**rbuffer
,
1193 const uint8_t *ptr
, unsigned size
, uint32_t *const_offset
)
1197 u_upload_alloc(sctx
->b
.const_uploader
, 0, size
,
1198 si_optimal_tcc_alignment(sctx
, size
),
1200 (struct pipe_resource
**)rbuffer
, &tmp
);
1202 util_memcpy_cpu_to_le32(tmp
, ptr
, size
);
1205 static void si_set_constant_buffer(struct si_context
*sctx
,
1206 struct si_buffer_resources
*buffers
,
1207 unsigned descriptors_idx
,
1208 uint slot
, const struct pipe_constant_buffer
*input
)
1210 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1211 assert(slot
< descs
->num_elements
);
1212 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1214 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1215 * with a NULL buffer). We need to use a dummy buffer instead. */
1216 if (sctx
->chip_class
== CIK
&&
1217 (!input
|| (!input
->buffer
&& !input
->user_buffer
)))
1218 input
= &sctx
->null_const_buf
;
1220 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
1221 struct pipe_resource
*buffer
= NULL
;
1224 /* Upload the user buffer if needed. */
1225 if (input
->user_buffer
) {
1226 unsigned buffer_offset
;
1228 si_upload_const_buffer(sctx
,
1229 (struct si_resource
**)&buffer
, input
->user_buffer
,
1230 input
->buffer_size
, &buffer_offset
);
1232 /* Just unbind on failure. */
1233 si_set_constant_buffer(sctx
, buffers
, descriptors_idx
, slot
, NULL
);
1236 va
= si_resource(buffer
)->gpu_address
+ buffer_offset
;
1238 pipe_resource_reference(&buffer
, input
->buffer
);
1239 va
= si_resource(buffer
)->gpu_address
+ input
->buffer_offset
;
1242 /* Set the descriptor. */
1243 uint32_t *desc
= descs
->list
+ slot
*4;
1245 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1247 desc
[2] = input
->buffer_size
;
1248 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1249 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1250 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1251 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1252 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1253 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1255 buffers
->buffers
[slot
] = buffer
;
1256 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1257 si_resource(buffer
),
1258 buffers
->shader_usage_constbuf
,
1259 buffers
->priority_constbuf
, true);
1260 buffers
->enabled_mask
|= 1u << slot
;
1262 /* Clear the descriptor. */
1263 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1264 buffers
->enabled_mask
&= ~(1u << slot
);
1267 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1270 static void si_pipe_set_constant_buffer(struct pipe_context
*ctx
,
1271 enum pipe_shader_type shader
, uint slot
,
1272 const struct pipe_constant_buffer
*input
)
1274 struct si_context
*sctx
= (struct si_context
*)ctx
;
1276 if (shader
>= SI_NUM_SHADERS
)
1279 if (slot
== 0 && input
&& input
->buffer
&&
1280 !(si_resource(input
->buffer
)->flags
& RADEON_FLAG_32BIT
)) {
1281 assert(!"constant buffer 0 must have a 32-bit VM address, use const_uploader");
1285 if (input
&& input
->buffer
)
1286 si_resource(input
->buffer
)->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
1288 slot
= si_get_constbuf_slot(slot
);
1289 si_set_constant_buffer(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1290 si_const_and_shader_buffer_descriptors_idx(shader
),
1294 void si_get_pipe_constant_buffer(struct si_context
*sctx
, uint shader
,
1295 uint slot
, struct pipe_constant_buffer
*cbuf
)
1297 cbuf
->user_buffer
= NULL
;
1298 si_get_buffer_from_descriptors(
1299 &sctx
->const_and_shader_buffers
[shader
],
1300 si_const_and_shader_buffer_descriptors(sctx
, shader
),
1301 si_get_constbuf_slot(slot
),
1302 &cbuf
->buffer
, &cbuf
->buffer_offset
, &cbuf
->buffer_size
);
1305 /* SHADER BUFFERS */
1307 static void si_set_shader_buffer(struct si_context
*sctx
,
1308 struct si_buffer_resources
*buffers
,
1309 unsigned descriptors_idx
,
1310 uint slot
, const struct pipe_shader_buffer
*sbuffer
,
1311 enum radeon_bo_priority priority
)
1313 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1314 uint32_t *desc
= descs
->list
+ slot
* 4;
1316 if (!sbuffer
|| !sbuffer
->buffer
) {
1317 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1318 memset(desc
, 0, sizeof(uint32_t) * 4);
1319 buffers
->enabled_mask
&= ~(1u << slot
);
1320 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1324 struct si_resource
*buf
= si_resource(sbuffer
->buffer
);
1325 uint64_t va
= buf
->gpu_address
+ sbuffer
->buffer_offset
;
1328 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1330 desc
[2] = sbuffer
->buffer_size
;
1331 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1332 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1333 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1334 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1335 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1336 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1338 pipe_resource_reference(&buffers
->buffers
[slot
], &buf
->b
.b
);
1339 radeon_add_to_gfx_buffer_list_check_mem(sctx
, buf
,
1340 buffers
->shader_usage
,
1343 buffers
->enabled_mask
|= 1u << slot
;
1344 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1346 util_range_add(&buf
->valid_buffer_range
, sbuffer
->buffer_offset
,
1347 sbuffer
->buffer_offset
+ sbuffer
->buffer_size
);
1350 static void si_set_shader_buffers(struct pipe_context
*ctx
,
1351 enum pipe_shader_type shader
,
1352 unsigned start_slot
, unsigned count
,
1353 const struct pipe_shader_buffer
*sbuffers
)
1355 struct si_context
*sctx
= (struct si_context
*)ctx
;
1356 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1357 unsigned descriptors_idx
= si_const_and_shader_buffer_descriptors_idx(shader
);
1360 assert(start_slot
+ count
<= SI_NUM_SHADER_BUFFERS
);
1362 for (i
= 0; i
< count
; ++i
) {
1363 const struct pipe_shader_buffer
*sbuffer
= sbuffers
? &sbuffers
[i
] : NULL
;
1364 unsigned slot
= si_get_shaderbuf_slot(start_slot
+ i
);
1366 if (sbuffer
&& sbuffer
->buffer
)
1367 si_resource(sbuffer
->buffer
)->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
1369 si_set_shader_buffer(sctx
, buffers
, descriptors_idx
, slot
, sbuffer
,
1374 void si_get_shader_buffers(struct si_context
*sctx
,
1375 enum pipe_shader_type shader
,
1376 uint start_slot
, uint count
,
1377 struct pipe_shader_buffer
*sbuf
)
1379 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1380 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1382 for (unsigned i
= 0; i
< count
; ++i
) {
1383 si_get_buffer_from_descriptors(
1385 si_get_shaderbuf_slot(start_slot
+ i
),
1386 &sbuf
[i
].buffer
, &sbuf
[i
].buffer_offset
,
1387 &sbuf
[i
].buffer_size
);
1393 void si_set_rw_buffer(struct si_context
*sctx
,
1394 uint slot
, const struct pipe_constant_buffer
*input
)
1396 si_set_constant_buffer(sctx
, &sctx
->rw_buffers
, SI_DESCS_RW_BUFFERS
,
1400 void si_set_rw_shader_buffer(struct si_context
*sctx
, uint slot
,
1401 const struct pipe_shader_buffer
*sbuffer
)
1403 si_set_shader_buffer(sctx
, &sctx
->rw_buffers
, SI_DESCS_RW_BUFFERS
,
1404 slot
, sbuffer
, RADEON_PRIO_SHADER_RW_BUFFER
);
1407 void si_set_ring_buffer(struct si_context
*sctx
, uint slot
,
1408 struct pipe_resource
*buffer
,
1409 unsigned stride
, unsigned num_records
,
1410 bool add_tid
, bool swizzle
,
1411 unsigned element_size
, unsigned index_stride
, uint64_t offset
)
1413 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1414 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1416 /* The stride field in the resource descriptor has 14 bits */
1417 assert(stride
< (1 << 14));
1419 assert(slot
< descs
->num_elements
);
1420 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1425 va
= si_resource(buffer
)->gpu_address
+ offset
;
1427 switch (element_size
) {
1429 assert(!"Unsupported ring buffer element size");
1445 switch (index_stride
) {
1447 assert(!"Unsupported ring buffer index stride");
1463 if (sctx
->chip_class
>= VI
&& stride
)
1464 num_records
*= stride
;
1466 /* Set the descriptor. */
1467 uint32_t *desc
= descs
->list
+ slot
*4;
1469 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1470 S_008F04_STRIDE(stride
) |
1471 S_008F04_SWIZZLE_ENABLE(swizzle
);
1472 desc
[2] = num_records
;
1473 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1474 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1475 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1476 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1477 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1478 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1479 S_008F0C_INDEX_STRIDE(index_stride
) |
1480 S_008F0C_ADD_TID_ENABLE(add_tid
);
1482 if (sctx
->chip_class
>= GFX9
)
1483 assert(!swizzle
|| element_size
== 1); /* always 4 bytes on GFX9 */
1485 desc
[3] |= S_008F0C_ELEMENT_SIZE(element_size
);
1487 pipe_resource_reference(&buffers
->buffers
[slot
], buffer
);
1488 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1489 si_resource(buffer
),
1490 buffers
->shader_usage
, buffers
->priority
);
1491 buffers
->enabled_mask
|= 1u << slot
;
1493 /* Clear the descriptor. */
1494 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1495 buffers
->enabled_mask
&= ~(1u << slot
);
1498 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1501 static void si_desc_reset_buffer_offset(uint32_t *desc
, uint64_t old_buf_va
,
1502 struct pipe_resource
*new_buf
)
1504 /* Retrieve the buffer offset from the descriptor. */
1505 uint64_t old_desc_va
= si_desc_extract_buffer_address(desc
);
1507 assert(old_buf_va
<= old_desc_va
);
1508 uint64_t offset_within_buffer
= old_desc_va
- old_buf_va
;
1510 /* Update the descriptor. */
1511 si_set_buf_desc_address(si_resource(new_buf
), offset_within_buffer
,
1515 /* INTERNAL CONST BUFFERS */
1517 static void si_set_polygon_stipple(struct pipe_context
*ctx
,
1518 const struct pipe_poly_stipple
*state
)
1520 struct si_context
*sctx
= (struct si_context
*)ctx
;
1521 struct pipe_constant_buffer cb
= {};
1522 unsigned stipple
[32];
1525 for (i
= 0; i
< 32; i
++)
1526 stipple
[i
] = util_bitreverse(state
->stipple
[i
]);
1528 cb
.user_buffer
= stipple
;
1529 cb
.buffer_size
= sizeof(stipple
);
1531 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
, &cb
);
1534 /* TEXTURE METADATA ENABLE/DISABLE */
1537 si_resident_handles_update_needs_color_decompress(struct si_context
*sctx
)
1539 util_dynarray_clear(&sctx
->resident_tex_needs_color_decompress
);
1540 util_dynarray_clear(&sctx
->resident_img_needs_color_decompress
);
1542 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1543 struct si_texture_handle
*, tex_handle
) {
1544 struct pipe_resource
*res
= (*tex_handle
)->view
->texture
;
1545 struct si_texture
*tex
;
1547 if (!res
|| res
->target
== PIPE_BUFFER
)
1550 tex
= (struct si_texture
*)res
;
1551 if (!color_needs_decompression(tex
))
1554 util_dynarray_append(&sctx
->resident_tex_needs_color_decompress
,
1555 struct si_texture_handle
*, *tex_handle
);
1558 util_dynarray_foreach(&sctx
->resident_img_handles
,
1559 struct si_image_handle
*, img_handle
) {
1560 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1561 struct pipe_resource
*res
= view
->resource
;
1562 struct si_texture
*tex
;
1564 if (!res
|| res
->target
== PIPE_BUFFER
)
1567 tex
= (struct si_texture
*)res
;
1568 if (!color_needs_decompression(tex
))
1571 util_dynarray_append(&sctx
->resident_img_needs_color_decompress
,
1572 struct si_image_handle
*, *img_handle
);
1576 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1577 * while the texture is bound, possibly by a different context. In that case,
1578 * call this function to update needs_*_decompress_masks.
1580 void si_update_needs_color_decompress_masks(struct si_context
*sctx
)
1582 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
1583 si_samplers_update_needs_color_decompress_mask(&sctx
->samplers
[i
]);
1584 si_images_update_needs_color_decompress_mask(&sctx
->images
[i
]);
1585 si_update_shader_needs_decompress_mask(sctx
, i
);
1588 si_resident_handles_update_needs_color_decompress(sctx
);
1591 /* BUFFER DISCARD/INVALIDATION */
1593 /** Reset descriptors of buffer resources after \p buf has been invalidated. */
1594 static void si_reset_buffer_resources(struct si_context
*sctx
,
1595 struct si_buffer_resources
*buffers
,
1596 unsigned descriptors_idx
,
1598 struct pipe_resource
*buf
,
1600 enum radeon_bo_usage usage
,
1601 enum radeon_bo_priority priority
)
1603 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1604 unsigned mask
= buffers
->enabled_mask
& slot_mask
;
1607 unsigned i
= u_bit_scan(&mask
);
1608 if (buffers
->buffers
[i
] == buf
) {
1609 si_desc_reset_buffer_offset(descs
->list
+ i
*4,
1611 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1613 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1615 usage
, priority
, true);
1620 /* Update all resource bindings where the buffer is bound, including
1621 * all resource descriptors. This is invalidate_buffer without
1622 * the invalidation. */
1623 void si_rebind_buffer(struct si_context
*sctx
, struct pipe_resource
*buf
,
1626 struct si_resource
*rbuffer
= si_resource(buf
);
1628 unsigned num_elems
= sctx
->vertex_elements
?
1629 sctx
->vertex_elements
->count
: 0;
1631 /* We changed the buffer, now we need to bind it where the old one
1632 * was bound. This consists of 2 things:
1633 * 1) Updating the resource descriptor and dirtying it.
1634 * 2) Adding a relocation to the CS, so that it's usable.
1637 /* Vertex buffers. */
1638 if (rbuffer
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
1639 for (i
= 0; i
< num_elems
; i
++) {
1640 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1642 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1644 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1647 if (sctx
->vertex_buffer
[vb
].buffer
.resource
== buf
) {
1648 sctx
->vertex_buffers_dirty
= true;
1654 /* Streamout buffers. (other internal buffers can't be invalidated) */
1655 if (rbuffer
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
1656 for (i
= SI_VS_STREAMOUT_BUF0
; i
<= SI_VS_STREAMOUT_BUF3
; i
++) {
1657 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1658 struct si_descriptors
*descs
=
1659 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1661 if (buffers
->buffers
[i
] != buf
)
1664 si_desc_reset_buffer_offset(descs
->list
+ i
*4,
1666 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1668 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1669 rbuffer
, buffers
->shader_usage
,
1670 RADEON_PRIO_SHADER_RW_BUFFER
,
1673 /* Update the streamout state. */
1674 if (sctx
->streamout
.begin_emitted
)
1675 si_emit_streamout_end(sctx
);
1676 sctx
->streamout
.append_bitmask
=
1677 sctx
->streamout
.enabled_mask
;
1678 si_streamout_buffers_dirty(sctx
);
1682 /* Constant and shader buffers. */
1683 if (rbuffer
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1684 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1685 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1686 si_const_and_shader_buffer_descriptors_idx(shader
),
1687 u_bit_consecutive(SI_NUM_SHADER_BUFFERS
, SI_NUM_CONST_BUFFERS
),
1689 sctx
->const_and_shader_buffers
[shader
].shader_usage_constbuf
,
1690 sctx
->const_and_shader_buffers
[shader
].priority_constbuf
);
1693 if (rbuffer
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
1694 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1695 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1696 si_const_and_shader_buffer_descriptors_idx(shader
),
1697 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS
),
1699 sctx
->const_and_shader_buffers
[shader
].shader_usage
,
1700 sctx
->const_and_shader_buffers
[shader
].priority
);
1703 if (rbuffer
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
1704 /* Texture buffers - update bindings. */
1705 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1706 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1707 struct si_descriptors
*descs
=
1708 si_sampler_and_image_descriptors(sctx
, shader
);
1709 unsigned mask
= samplers
->enabled_mask
;
1712 unsigned i
= u_bit_scan(&mask
);
1713 if (samplers
->views
[i
]->texture
== buf
) {
1714 unsigned desc_slot
= si_get_sampler_slot(i
);
1716 si_desc_reset_buffer_offset(descs
->list
+
1719 sctx
->descriptors_dirty
|=
1720 1u << si_sampler_and_image_descriptors_idx(shader
);
1722 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1723 rbuffer
, RADEON_USAGE_READ
,
1724 RADEON_PRIO_SAMPLER_BUFFER
,
1732 if (rbuffer
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
1733 for (shader
= 0; shader
< SI_NUM_SHADERS
; ++shader
) {
1734 struct si_images
*images
= &sctx
->images
[shader
];
1735 struct si_descriptors
*descs
=
1736 si_sampler_and_image_descriptors(sctx
, shader
);
1737 unsigned mask
= images
->enabled_mask
;
1740 unsigned i
= u_bit_scan(&mask
);
1742 if (images
->views
[i
].resource
== buf
) {
1743 unsigned desc_slot
= si_get_image_slot(i
);
1745 if (images
->views
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
)
1746 si_mark_image_range_valid(&images
->views
[i
]);
1748 si_desc_reset_buffer_offset(
1749 descs
->list
+ desc_slot
* 8 + 4,
1751 sctx
->descriptors_dirty
|=
1752 1u << si_sampler_and_image_descriptors_idx(shader
);
1754 radeon_add_to_gfx_buffer_list_check_mem(
1756 RADEON_USAGE_READWRITE
,
1757 RADEON_PRIO_SAMPLER_BUFFER
, true);
1763 /* Bindless texture handles */
1764 if (rbuffer
->texture_handle_allocated
) {
1765 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1767 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1768 struct si_texture_handle
*, tex_handle
) {
1769 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
1770 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1772 if (view
->texture
== buf
) {
1773 si_set_buf_desc_address(rbuffer
,
1776 desc_slot
* 16 + 4);
1778 (*tex_handle
)->desc_dirty
= true;
1779 sctx
->bindless_descriptors_dirty
= true;
1781 radeon_add_to_gfx_buffer_list_check_mem(
1784 RADEON_PRIO_SAMPLER_BUFFER
, true);
1789 /* Bindless image handles */
1790 if (rbuffer
->image_handle_allocated
) {
1791 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1793 util_dynarray_foreach(&sctx
->resident_img_handles
,
1794 struct si_image_handle
*, img_handle
) {
1795 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1796 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1798 if (view
->resource
== buf
) {
1799 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
1800 si_mark_image_range_valid(view
);
1802 si_set_buf_desc_address(rbuffer
,
1805 desc_slot
* 16 + 4);
1807 (*img_handle
)->desc_dirty
= true;
1808 sctx
->bindless_descriptors_dirty
= true;
1810 radeon_add_to_gfx_buffer_list_check_mem(
1812 RADEON_USAGE_READWRITE
,
1813 RADEON_PRIO_SAMPLER_BUFFER
, true);
1819 static void si_upload_bindless_descriptor(struct si_context
*sctx
,
1821 unsigned num_dwords
)
1823 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1824 unsigned desc_slot_offset
= desc_slot
* 16;
1828 data
= desc
->list
+ desc_slot_offset
;
1829 va
= desc
->gpu_address
+ desc_slot_offset
* 4;
1831 si_cp_write_data(sctx
, desc
->buffer
, va
- desc
->buffer
->gpu_address
,
1832 num_dwords
* 4, V_370_TC_L2
, V_370_ME
, data
);
1835 static void si_upload_bindless_descriptors(struct si_context
*sctx
)
1837 if (!sctx
->bindless_descriptors_dirty
)
1840 /* Wait for graphics/compute to be idle before updating the resident
1841 * descriptors directly in memory, in case the GPU is using them.
1843 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
1844 SI_CONTEXT_CS_PARTIAL_FLUSH
;
1845 si_emit_cache_flush(sctx
);
1847 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1848 struct si_texture_handle
*, tex_handle
) {
1849 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1851 if (!(*tex_handle
)->desc_dirty
)
1854 si_upload_bindless_descriptor(sctx
, desc_slot
, 16);
1855 (*tex_handle
)->desc_dirty
= false;
1858 util_dynarray_foreach(&sctx
->resident_img_handles
,
1859 struct si_image_handle
*, img_handle
) {
1860 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1862 if (!(*img_handle
)->desc_dirty
)
1865 si_upload_bindless_descriptor(sctx
, desc_slot
, 8);
1866 (*img_handle
)->desc_dirty
= false;
1869 /* Invalidate L1 because it doesn't know that L2 changed. */
1870 sctx
->flags
|= SI_CONTEXT_INV_SMEM_L1
;
1871 si_emit_cache_flush(sctx
);
1873 sctx
->bindless_descriptors_dirty
= false;
1876 /* Update mutable image descriptor fields of all resident textures. */
1877 static void si_update_bindless_texture_descriptor(struct si_context
*sctx
,
1878 struct si_texture_handle
*tex_handle
)
1880 struct si_sampler_view
*sview
= (struct si_sampler_view
*)tex_handle
->view
;
1881 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1882 unsigned desc_slot_offset
= tex_handle
->desc_slot
* 16;
1883 uint32_t desc_list
[16];
1885 if (sview
->base
.texture
->target
== PIPE_BUFFER
)
1888 memcpy(desc_list
, desc
->list
+ desc_slot_offset
, sizeof(desc_list
));
1889 si_set_sampler_view_desc(sctx
, sview
, &tex_handle
->sstate
,
1890 desc
->list
+ desc_slot_offset
);
1892 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1893 sizeof(desc_list
))) {
1894 tex_handle
->desc_dirty
= true;
1895 sctx
->bindless_descriptors_dirty
= true;
1899 static void si_update_bindless_image_descriptor(struct si_context
*sctx
,
1900 struct si_image_handle
*img_handle
)
1902 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1903 unsigned desc_slot_offset
= img_handle
->desc_slot
* 16;
1904 struct pipe_image_view
*view
= &img_handle
->view
;
1905 uint32_t desc_list
[8];
1907 if (view
->resource
->target
== PIPE_BUFFER
)
1910 memcpy(desc_list
, desc
->list
+ desc_slot_offset
,
1912 si_set_shader_image_desc(sctx
, view
, true,
1913 desc
->list
+ desc_slot_offset
, NULL
);
1915 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1916 sizeof(desc_list
))) {
1917 img_handle
->desc_dirty
= true;
1918 sctx
->bindless_descriptors_dirty
= true;
1922 static void si_update_all_resident_texture_descriptors(struct si_context
*sctx
)
1924 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1925 struct si_texture_handle
*, tex_handle
) {
1926 si_update_bindless_texture_descriptor(sctx
, *tex_handle
);
1929 util_dynarray_foreach(&sctx
->resident_img_handles
,
1930 struct si_image_handle
*, img_handle
) {
1931 si_update_bindless_image_descriptor(sctx
, *img_handle
);
1934 si_upload_bindless_descriptors(sctx
);
1937 /* Update mutable image descriptor fields of all bound textures. */
1938 void si_update_all_texture_descriptors(struct si_context
*sctx
)
1942 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1943 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1944 struct si_images
*images
= &sctx
->images
[shader
];
1948 mask
= images
->enabled_mask
;
1950 unsigned i
= u_bit_scan(&mask
);
1951 struct pipe_image_view
*view
= &images
->views
[i
];
1953 if (!view
->resource
||
1954 view
->resource
->target
== PIPE_BUFFER
)
1957 si_set_shader_image(sctx
, shader
, i
, view
, true);
1960 /* Sampler views. */
1961 mask
= samplers
->enabled_mask
;
1963 unsigned i
= u_bit_scan(&mask
);
1964 struct pipe_sampler_view
*view
= samplers
->views
[i
];
1968 view
->texture
->target
== PIPE_BUFFER
)
1971 si_set_sampler_view(sctx
, shader
, i
,
1972 samplers
->views
[i
], true);
1975 si_update_shader_needs_decompress_mask(sctx
, shader
);
1978 si_update_all_resident_texture_descriptors(sctx
);
1979 si_update_ps_colorbuf0_slot(sctx
);
1982 /* SHADER USER DATA */
1984 static void si_mark_shader_pointers_dirty(struct si_context
*sctx
,
1987 sctx
->shader_pointers_dirty
|=
1988 u_bit_consecutive(SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
,
1989 SI_NUM_SHADER_DESCS
);
1991 if (shader
== PIPE_SHADER_VERTEX
)
1992 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
1994 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
1997 static void si_shader_pointers_begin_new_cs(struct si_context
*sctx
)
1999 sctx
->shader_pointers_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2000 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
2001 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
2002 sctx
->graphics_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
2003 sctx
->compute_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
2006 /* Set a base register address for user data constants in the given shader.
2007 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
2009 static void si_set_user_data_base(struct si_context
*sctx
,
2010 unsigned shader
, uint32_t new_base
)
2012 uint32_t *base
= &sctx
->shader_pointers
.sh_base
[shader
];
2014 if (*base
!= new_base
) {
2018 si_mark_shader_pointers_dirty(sctx
, shader
);
2020 /* Any change in enabled shader stages requires re-emitting
2021 * the VS state SGPR, because it contains the clamp_vertex_color
2022 * state, which can be done in VS, TES, and GS.
2024 sctx
->last_vs_state
= ~0;
2028 /* This must be called when these shaders are changed from non-NULL to NULL
2031 * - tessellation control shader
2032 * - tessellation evaluation shader
2034 void si_shader_change_notify(struct si_context
*sctx
)
2036 /* VS can be bound as VS, ES, or LS. */
2037 if (sctx
->tes_shader
.cso
) {
2038 if (sctx
->chip_class
>= GFX9
) {
2039 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2040 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2042 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2043 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2045 } else if (sctx
->gs_shader
.cso
) {
2046 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2047 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2049 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2050 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2053 /* TES can be bound as ES, VS, or not bound. */
2054 if (sctx
->tes_shader
.cso
) {
2055 if (sctx
->gs_shader
.cso
)
2056 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
2057 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2059 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
2060 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2062 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, 0);
2066 static void si_emit_shader_pointer_head(struct radeon_cmdbuf
*cs
,
2068 unsigned pointer_count
)
2070 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
, 0));
2071 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
2074 static void si_emit_shader_pointer_body(struct si_screen
*sscreen
,
2075 struct radeon_cmdbuf
*cs
,
2078 radeon_emit(cs
, va
);
2080 assert(va
== 0 || (va
>> 32) == sscreen
->info
.address32_hi
);
2083 static void si_emit_shader_pointer(struct si_context
*sctx
,
2084 struct si_descriptors
*desc
,
2087 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2088 unsigned sh_offset
= sh_base
+ desc
->shader_userdata_offset
;
2090 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2091 si_emit_shader_pointer_body(sctx
->screen
, cs
, desc
->gpu_address
);
2094 static void si_emit_consecutive_shader_pointers(struct si_context
*sctx
,
2095 unsigned pointer_mask
,
2101 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2102 unsigned mask
= sctx
->shader_pointers_dirty
& pointer_mask
;
2106 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
2108 struct si_descriptors
*descs
= &sctx
->descriptors
[start
];
2109 unsigned sh_offset
= sh_base
+ descs
->shader_userdata_offset
;
2111 si_emit_shader_pointer_head(cs
, sh_offset
, count
);
2112 for (int i
= 0; i
< count
; i
++)
2113 si_emit_shader_pointer_body(sctx
->screen
, cs
,
2114 descs
[i
].gpu_address
);
2118 static void si_emit_global_shader_pointers(struct si_context
*sctx
,
2119 struct si_descriptors
*descs
)
2121 if (sctx
->chip_class
== GFX9
) {
2122 /* Broadcast it to all shader stages. */
2123 si_emit_shader_pointer(sctx
, descs
,
2124 R_00B530_SPI_SHADER_USER_DATA_COMMON_0
);
2128 si_emit_shader_pointer(sctx
, descs
,
2129 R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2130 si_emit_shader_pointer(sctx
, descs
,
2131 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2132 si_emit_shader_pointer(sctx
, descs
,
2133 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2134 si_emit_shader_pointer(sctx
, descs
,
2135 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2136 si_emit_shader_pointer(sctx
, descs
,
2137 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2138 si_emit_shader_pointer(sctx
, descs
,
2139 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2142 void si_emit_graphics_shader_pointers(struct si_context
*sctx
)
2144 uint32_t *sh_base
= sctx
->shader_pointers
.sh_base
;
2146 if (sctx
->shader_pointers_dirty
& (1 << SI_DESCS_RW_BUFFERS
)) {
2147 si_emit_global_shader_pointers(sctx
,
2148 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2151 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(VERTEX
),
2152 sh_base
[PIPE_SHADER_VERTEX
]);
2153 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_EVAL
),
2154 sh_base
[PIPE_SHADER_TESS_EVAL
]);
2155 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(FRAGMENT
),
2156 sh_base
[PIPE_SHADER_FRAGMENT
]);
2157 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_CTRL
),
2158 sh_base
[PIPE_SHADER_TESS_CTRL
]);
2159 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(GEOMETRY
),
2160 sh_base
[PIPE_SHADER_GEOMETRY
]);
2162 sctx
->shader_pointers_dirty
&=
2163 ~u_bit_consecutive(SI_DESCS_RW_BUFFERS
, SI_DESCS_FIRST_COMPUTE
);
2165 if (sctx
->vertex_buffer_pointer_dirty
) {
2166 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2168 /* Find the location of the VB descriptor pointer. */
2169 /* TODO: In the future, the pointer will be packed in unused
2170 * bits of the first 2 VB descriptors. */
2171 unsigned sh_dw_offset
= SI_VS_NUM_USER_SGPR
;
2172 if (sctx
->chip_class
>= GFX9
) {
2173 if (sctx
->tes_shader
.cso
)
2174 sh_dw_offset
= GFX9_TCS_NUM_USER_SGPR
;
2175 else if (sctx
->gs_shader
.cso
)
2176 sh_dw_offset
= GFX9_VSGS_NUM_USER_SGPR
;
2179 unsigned sh_offset
= sh_base
[PIPE_SHADER_VERTEX
] + sh_dw_offset
* 4;
2180 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2181 si_emit_shader_pointer_body(sctx
->screen
, cs
,
2182 sctx
->vb_descriptors_buffer
->gpu_address
+
2183 sctx
->vb_descriptors_offset
);
2184 sctx
->vertex_buffer_pointer_dirty
= false;
2187 if (sctx
->graphics_bindless_pointer_dirty
) {
2188 si_emit_global_shader_pointers(sctx
,
2189 &sctx
->bindless_descriptors
);
2190 sctx
->graphics_bindless_pointer_dirty
= false;
2194 void si_emit_compute_shader_pointers(struct si_context
*sctx
)
2196 unsigned base
= R_00B900_COMPUTE_USER_DATA_0
;
2198 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(COMPUTE
),
2199 R_00B900_COMPUTE_USER_DATA_0
);
2200 sctx
->shader_pointers_dirty
&= ~SI_DESCS_SHADER_MASK(COMPUTE
);
2202 if (sctx
->compute_bindless_pointer_dirty
) {
2203 si_emit_shader_pointer(sctx
, &sctx
->bindless_descriptors
, base
);
2204 sctx
->compute_bindless_pointer_dirty
= false;
2210 static void si_init_bindless_descriptors(struct si_context
*sctx
,
2211 struct si_descriptors
*desc
,
2212 short shader_userdata_rel_index
,
2213 unsigned num_elements
)
2215 MAYBE_UNUSED
unsigned desc_slot
;
2217 si_init_descriptors(desc
, shader_userdata_rel_index
, 16, num_elements
);
2218 sctx
->bindless_descriptors
.num_active_slots
= num_elements
;
2220 /* The first bindless descriptor is stored at slot 1, because 0 is not
2221 * considered to be a valid handle.
2223 sctx
->num_bindless_descriptors
= 1;
2225 /* Track which bindless slots are used (or not). */
2226 util_idalloc_init(&sctx
->bindless_used_slots
);
2227 util_idalloc_resize(&sctx
->bindless_used_slots
, num_elements
);
2229 /* Reserve slot 0 because it's an invalid handle for bindless. */
2230 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2231 assert(desc_slot
== 0);
2234 static void si_release_bindless_descriptors(struct si_context
*sctx
)
2236 si_release_descriptors(&sctx
->bindless_descriptors
);
2237 util_idalloc_fini(&sctx
->bindless_used_slots
);
2240 static unsigned si_get_first_free_bindless_slot(struct si_context
*sctx
)
2242 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2245 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2246 if (desc_slot
>= desc
->num_elements
) {
2247 /* The array of bindless descriptors is full, resize it. */
2248 unsigned slot_size
= desc
->element_dw_size
* 4;
2249 unsigned new_num_elements
= desc
->num_elements
* 2;
2251 desc
->list
= REALLOC(desc
->list
, desc
->num_elements
* slot_size
,
2252 new_num_elements
* slot_size
);
2253 desc
->num_elements
= new_num_elements
;
2254 desc
->num_active_slots
= new_num_elements
;
2262 si_create_bindless_descriptor(struct si_context
*sctx
, uint32_t *desc_list
,
2265 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2266 unsigned desc_slot
, desc_slot_offset
;
2268 /* Find a free slot. */
2269 desc_slot
= si_get_first_free_bindless_slot(sctx
);
2271 /* For simplicity, sampler and image bindless descriptors use fixed
2272 * 16-dword slots for now. Image descriptors only need 8-dword but this
2273 * doesn't really matter because no real apps use image handles.
2275 desc_slot_offset
= desc_slot
* 16;
2277 /* Copy the descriptor into the array. */
2278 memcpy(desc
->list
+ desc_slot_offset
, desc_list
, size
);
2280 /* Re-upload the whole array of bindless descriptors into a new buffer.
2282 if (!si_upload_descriptors(sctx
, desc
))
2285 /* Make sure to re-emit the shader pointers for all stages. */
2286 sctx
->graphics_bindless_pointer_dirty
= true;
2287 sctx
->compute_bindless_pointer_dirty
= true;
2292 static void si_update_bindless_buffer_descriptor(struct si_context
*sctx
,
2294 struct pipe_resource
*resource
,
2298 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2299 struct si_resource
*buf
= si_resource(resource
);
2300 unsigned desc_slot_offset
= desc_slot
* 16;
2301 uint32_t *desc_list
= desc
->list
+ desc_slot_offset
+ 4;
2302 uint64_t old_desc_va
;
2304 assert(resource
->target
== PIPE_BUFFER
);
2306 /* Retrieve the old buffer addr from the descriptor. */
2307 old_desc_va
= si_desc_extract_buffer_address(desc_list
);
2309 if (old_desc_va
!= buf
->gpu_address
+ offset
) {
2310 /* The buffer has been invalidated when the handle wasn't
2311 * resident, update the descriptor and the dirty flag.
2313 si_set_buf_desc_address(buf
, offset
, &desc_list
[0]);
2319 static uint64_t si_create_texture_handle(struct pipe_context
*ctx
,
2320 struct pipe_sampler_view
*view
,
2321 const struct pipe_sampler_state
*state
)
2323 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
2324 struct si_context
*sctx
= (struct si_context
*)ctx
;
2325 struct si_texture_handle
*tex_handle
;
2326 struct si_sampler_state
*sstate
;
2327 uint32_t desc_list
[16];
2330 tex_handle
= CALLOC_STRUCT(si_texture_handle
);
2334 memset(desc_list
, 0, sizeof(desc_list
));
2335 si_init_descriptor_list(&desc_list
[0], 16, 1, null_texture_descriptor
);
2337 sstate
= ctx
->create_sampler_state(ctx
, state
);
2343 si_set_sampler_view_desc(sctx
, sview
, sstate
, &desc_list
[0]);
2344 memcpy(&tex_handle
->sstate
, sstate
, sizeof(*sstate
));
2345 ctx
->delete_sampler_state(ctx
, sstate
);
2347 tex_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2349 if (!tex_handle
->desc_slot
) {
2354 handle
= tex_handle
->desc_slot
;
2356 if (!_mesa_hash_table_insert(sctx
->tex_handles
,
2357 (void *)(uintptr_t)handle
,
2363 pipe_sampler_view_reference(&tex_handle
->view
, view
);
2365 si_resource(sview
->base
.texture
)->texture_handle_allocated
= true;
2370 static void si_delete_texture_handle(struct pipe_context
*ctx
, uint64_t handle
)
2372 struct si_context
*sctx
= (struct si_context
*)ctx
;
2373 struct si_texture_handle
*tex_handle
;
2374 struct hash_entry
*entry
;
2376 entry
= _mesa_hash_table_search(sctx
->tex_handles
,
2377 (void *)(uintptr_t)handle
);
2381 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2383 /* Allow this descriptor slot to be re-used. */
2384 util_idalloc_free(&sctx
->bindless_used_slots
, tex_handle
->desc_slot
);
2386 pipe_sampler_view_reference(&tex_handle
->view
, NULL
);
2387 _mesa_hash_table_remove(sctx
->tex_handles
, entry
);
2391 static void si_make_texture_handle_resident(struct pipe_context
*ctx
,
2392 uint64_t handle
, bool resident
)
2394 struct si_context
*sctx
= (struct si_context
*)ctx
;
2395 struct si_texture_handle
*tex_handle
;
2396 struct si_sampler_view
*sview
;
2397 struct hash_entry
*entry
;
2399 entry
= _mesa_hash_table_search(sctx
->tex_handles
,
2400 (void *)(uintptr_t)handle
);
2404 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2405 sview
= (struct si_sampler_view
*)tex_handle
->view
;
2408 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2409 struct si_texture
*tex
=
2410 (struct si_texture
*)sview
->base
.texture
;
2412 if (depth_needs_decompression(tex
)) {
2413 util_dynarray_append(
2414 &sctx
->resident_tex_needs_depth_decompress
,
2415 struct si_texture_handle
*,
2419 if (color_needs_decompression(tex
)) {
2420 util_dynarray_append(
2421 &sctx
->resident_tex_needs_color_decompress
,
2422 struct si_texture_handle
*,
2426 if (tex
->dcc_offset
&&
2427 p_atomic_read(&tex
->framebuffers_bound
))
2428 sctx
->need_check_render_feedback
= true;
2430 si_update_bindless_texture_descriptor(sctx
, tex_handle
);
2432 si_update_bindless_buffer_descriptor(sctx
,
2433 tex_handle
->desc_slot
,
2434 sview
->base
.texture
,
2435 sview
->base
.u
.buf
.offset
,
2436 &tex_handle
->desc_dirty
);
2439 /* Re-upload the descriptor if it has been updated while it
2442 if (tex_handle
->desc_dirty
)
2443 sctx
->bindless_descriptors_dirty
= true;
2445 /* Add the texture handle to the per-context list. */
2446 util_dynarray_append(&sctx
->resident_tex_handles
,
2447 struct si_texture_handle
*, tex_handle
);
2449 /* Add the buffers to the current CS in case si_begin_new_cs()
2450 * is not going to be called.
2452 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2454 sview
->is_stencil_sampler
, false);
2456 /* Remove the texture handle from the per-context list. */
2457 util_dynarray_delete_unordered(&sctx
->resident_tex_handles
,
2458 struct si_texture_handle
*,
2461 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2462 util_dynarray_delete_unordered(
2463 &sctx
->resident_tex_needs_depth_decompress
,
2464 struct si_texture_handle
*, tex_handle
);
2466 util_dynarray_delete_unordered(
2467 &sctx
->resident_tex_needs_color_decompress
,
2468 struct si_texture_handle
*, tex_handle
);
2473 static uint64_t si_create_image_handle(struct pipe_context
*ctx
,
2474 const struct pipe_image_view
*view
)
2476 struct si_context
*sctx
= (struct si_context
*)ctx
;
2477 struct si_image_handle
*img_handle
;
2478 uint32_t desc_list
[8];
2481 if (!view
|| !view
->resource
)
2484 img_handle
= CALLOC_STRUCT(si_image_handle
);
2488 memset(desc_list
, 0, sizeof(desc_list
));
2489 si_init_descriptor_list(&desc_list
[0], 8, 1, null_image_descriptor
);
2491 si_set_shader_image_desc(sctx
, view
, false, &desc_list
[0], NULL
);
2493 img_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2495 if (!img_handle
->desc_slot
) {
2500 handle
= img_handle
->desc_slot
;
2502 if (!_mesa_hash_table_insert(sctx
->img_handles
,
2503 (void *)(uintptr_t)handle
,
2509 util_copy_image_view(&img_handle
->view
, view
);
2511 si_resource(view
->resource
)->image_handle_allocated
= true;
2516 static void si_delete_image_handle(struct pipe_context
*ctx
, uint64_t handle
)
2518 struct si_context
*sctx
= (struct si_context
*)ctx
;
2519 struct si_image_handle
*img_handle
;
2520 struct hash_entry
*entry
;
2522 entry
= _mesa_hash_table_search(sctx
->img_handles
,
2523 (void *)(uintptr_t)handle
);
2527 img_handle
= (struct si_image_handle
*)entry
->data
;
2529 util_copy_image_view(&img_handle
->view
, NULL
);
2530 _mesa_hash_table_remove(sctx
->img_handles
, entry
);
2534 static void si_make_image_handle_resident(struct pipe_context
*ctx
,
2535 uint64_t handle
, unsigned access
,
2538 struct si_context
*sctx
= (struct si_context
*)ctx
;
2539 struct si_image_handle
*img_handle
;
2540 struct pipe_image_view
*view
;
2541 struct si_resource
*res
;
2542 struct hash_entry
*entry
;
2544 entry
= _mesa_hash_table_search(sctx
->img_handles
,
2545 (void *)(uintptr_t)handle
);
2549 img_handle
= (struct si_image_handle
*)entry
->data
;
2550 view
= &img_handle
->view
;
2551 res
= si_resource(view
->resource
);
2554 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2555 struct si_texture
*tex
= (struct si_texture
*)res
;
2556 unsigned level
= view
->u
.tex
.level
;
2558 if (color_needs_decompression(tex
)) {
2559 util_dynarray_append(
2560 &sctx
->resident_img_needs_color_decompress
,
2561 struct si_image_handle
*,
2565 if (vi_dcc_enabled(tex
, level
) &&
2566 p_atomic_read(&tex
->framebuffers_bound
))
2567 sctx
->need_check_render_feedback
= true;
2569 si_update_bindless_image_descriptor(sctx
, img_handle
);
2571 si_update_bindless_buffer_descriptor(sctx
,
2572 img_handle
->desc_slot
,
2575 &img_handle
->desc_dirty
);
2578 /* Re-upload the descriptor if it has been updated while it
2581 if (img_handle
->desc_dirty
)
2582 sctx
->bindless_descriptors_dirty
= true;
2584 /* Add the image handle to the per-context list. */
2585 util_dynarray_append(&sctx
->resident_img_handles
,
2586 struct si_image_handle
*, img_handle
);
2588 /* Add the buffers to the current CS in case si_begin_new_cs()
2589 * is not going to be called.
2591 si_sampler_view_add_buffer(sctx
, view
->resource
,
2592 (access
& PIPE_IMAGE_ACCESS_WRITE
) ?
2593 RADEON_USAGE_READWRITE
:
2594 RADEON_USAGE_READ
, false, false);
2596 /* Remove the image handle from the per-context list. */
2597 util_dynarray_delete_unordered(&sctx
->resident_img_handles
,
2598 struct si_image_handle
*,
2601 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2602 util_dynarray_delete_unordered(
2603 &sctx
->resident_img_needs_color_decompress
,
2604 struct si_image_handle
*,
2611 void si_all_resident_buffers_begin_new_cs(struct si_context
*sctx
)
2613 unsigned num_resident_tex_handles
, num_resident_img_handles
;
2615 num_resident_tex_handles
= sctx
->resident_tex_handles
.size
/
2616 sizeof(struct si_texture_handle
*);
2617 num_resident_img_handles
= sctx
->resident_img_handles
.size
/
2618 sizeof(struct si_image_handle
*);
2620 /* Add all resident texture handles. */
2621 util_dynarray_foreach(&sctx
->resident_tex_handles
,
2622 struct si_texture_handle
*, tex_handle
) {
2623 struct si_sampler_view
*sview
=
2624 (struct si_sampler_view
*)(*tex_handle
)->view
;
2626 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2628 sview
->is_stencil_sampler
, false);
2631 /* Add all resident image handles. */
2632 util_dynarray_foreach(&sctx
->resident_img_handles
,
2633 struct si_image_handle
*, img_handle
) {
2634 struct pipe_image_view
*view
= &(*img_handle
)->view
;
2636 si_sampler_view_add_buffer(sctx
, view
->resource
,
2637 RADEON_USAGE_READWRITE
,
2641 sctx
->num_resident_handles
+= num_resident_tex_handles
+
2642 num_resident_img_handles
;
2645 /* INIT/DEINIT/UPLOAD */
2647 void si_init_all_descriptors(struct si_context
*sctx
)
2651 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2652 bool is_2nd
= sctx
->chip_class
>= GFX9
&&
2653 (i
== PIPE_SHADER_TESS_CTRL
||
2654 i
== PIPE_SHADER_GEOMETRY
);
2655 unsigned num_sampler_slots
= SI_NUM_IMAGES
/ 2 + SI_NUM_SAMPLERS
;
2656 unsigned num_buffer_slots
= SI_NUM_SHADER_BUFFERS
+ SI_NUM_CONST_BUFFERS
;
2658 struct si_descriptors
*desc
;
2661 if (i
== PIPE_SHADER_TESS_CTRL
) {
2662 rel_dw_offset
= (R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
-
2663 R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2664 } else { /* PIPE_SHADER_GEOMETRY */
2665 rel_dw_offset
= (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
-
2666 R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2669 rel_dw_offset
= SI_SGPR_CONST_AND_SHADER_BUFFERS
;
2671 desc
= si_const_and_shader_buffer_descriptors(sctx
, i
);
2672 si_init_buffer_resources(&sctx
->const_and_shader_buffers
[i
], desc
,
2673 num_buffer_slots
, rel_dw_offset
,
2674 RADEON_USAGE_READWRITE
,
2676 RADEON_PRIO_SHADER_RW_BUFFER
,
2677 RADEON_PRIO_CONST_BUFFER
);
2678 desc
->slot_index_to_bind_directly
= si_get_constbuf_slot(0);
2681 if (i
== PIPE_SHADER_TESS_CTRL
) {
2682 rel_dw_offset
= (R_00B40C_SPI_SHADER_USER_DATA_ADDR_HI_HS
-
2683 R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2684 } else { /* PIPE_SHADER_GEOMETRY */
2685 rel_dw_offset
= (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS
-
2686 R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2689 rel_dw_offset
= SI_SGPR_SAMPLERS_AND_IMAGES
;
2692 desc
= si_sampler_and_image_descriptors(sctx
, i
);
2693 si_init_descriptors(desc
, rel_dw_offset
, 16, num_sampler_slots
);
2696 for (j
= 0; j
< SI_NUM_IMAGES
; j
++)
2697 memcpy(desc
->list
+ j
* 8, null_image_descriptor
, 8 * 4);
2698 for (; j
< SI_NUM_IMAGES
+ SI_NUM_SAMPLERS
* 2; j
++)
2699 memcpy(desc
->list
+ j
* 8, null_texture_descriptor
, 8 * 4);
2702 si_init_buffer_resources(&sctx
->rw_buffers
,
2703 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
],
2704 SI_NUM_RW_BUFFERS
, SI_SGPR_RW_BUFFERS
,
2705 /* The second set of usage/priority is used by
2706 * const buffers in RW buffer slots. */
2707 RADEON_USAGE_READWRITE
, RADEON_USAGE_READ
,
2708 RADEON_PRIO_SHADER_RINGS
, RADEON_PRIO_CONST_BUFFER
);
2709 sctx
->descriptors
[SI_DESCS_RW_BUFFERS
].num_active_slots
= SI_NUM_RW_BUFFERS
;
2711 /* Initialize an array of 1024 bindless descriptors, when the limit is
2712 * reached, just make it larger and re-upload the whole array.
2714 si_init_bindless_descriptors(sctx
, &sctx
->bindless_descriptors
,
2715 SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES
,
2718 sctx
->descriptors_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2720 /* Set pipe_context functions. */
2721 sctx
->b
.bind_sampler_states
= si_bind_sampler_states
;
2722 sctx
->b
.set_shader_images
= si_set_shader_images
;
2723 sctx
->b
.set_constant_buffer
= si_pipe_set_constant_buffer
;
2724 sctx
->b
.set_polygon_stipple
= si_set_polygon_stipple
;
2725 sctx
->b
.set_shader_buffers
= si_set_shader_buffers
;
2726 sctx
->b
.set_sampler_views
= si_set_sampler_views
;
2727 sctx
->b
.create_texture_handle
= si_create_texture_handle
;
2728 sctx
->b
.delete_texture_handle
= si_delete_texture_handle
;
2729 sctx
->b
.make_texture_handle_resident
= si_make_texture_handle_resident
;
2730 sctx
->b
.create_image_handle
= si_create_image_handle
;
2731 sctx
->b
.delete_image_handle
= si_delete_image_handle
;
2732 sctx
->b
.make_image_handle_resident
= si_make_image_handle_resident
;
2734 /* Shader user data. */
2735 sctx
->atoms
.s
.shader_pointers
.emit
= si_emit_graphics_shader_pointers
;
2737 /* Set default and immutable mappings. */
2738 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2740 if (sctx
->chip_class
>= GFX9
) {
2741 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2742 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2743 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2744 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2746 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2747 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2748 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2749 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2751 si_set_user_data_base(sctx
, PIPE_SHADER_FRAGMENT
, R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2754 static bool si_upload_shader_descriptors(struct si_context
*sctx
, unsigned mask
)
2756 unsigned dirty
= sctx
->descriptors_dirty
& mask
;
2758 /* Assume nothing will go wrong: */
2759 sctx
->shader_pointers_dirty
|= dirty
;
2762 unsigned i
= u_bit_scan(&dirty
);
2764 if (!si_upload_descriptors(sctx
, &sctx
->descriptors
[i
]))
2768 sctx
->descriptors_dirty
&= ~mask
;
2770 si_upload_bindless_descriptors(sctx
);
2775 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
)
2777 const unsigned mask
= u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE
);
2778 return si_upload_shader_descriptors(sctx
, mask
);
2781 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
)
2783 /* Does not update rw_buffers as that is not needed for compute shaders
2784 * and the input buffer is using the same SGPR's anyway.
2786 const unsigned mask
= u_bit_consecutive(SI_DESCS_FIRST_COMPUTE
,
2787 SI_NUM_DESCS
- SI_DESCS_FIRST_COMPUTE
);
2788 return si_upload_shader_descriptors(sctx
, mask
);
2791 void si_release_all_descriptors(struct si_context
*sctx
)
2795 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2796 si_release_buffer_resources(&sctx
->const_and_shader_buffers
[i
],
2797 si_const_and_shader_buffer_descriptors(sctx
, i
));
2798 si_release_sampler_views(&sctx
->samplers
[i
]);
2799 si_release_image_views(&sctx
->images
[i
]);
2801 si_release_buffer_resources(&sctx
->rw_buffers
,
2802 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2803 for (i
= 0; i
< SI_NUM_VERTEX_BUFFERS
; i
++)
2804 pipe_vertex_buffer_unreference(&sctx
->vertex_buffer
[i
]);
2806 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2807 si_release_descriptors(&sctx
->descriptors
[i
]);
2809 si_resource_reference(&sctx
->vb_descriptors_buffer
, NULL
);
2810 sctx
->vb_descriptors_gpu_list
= NULL
; /* points into a mapped buffer */
2812 si_release_bindless_descriptors(sctx
);
2815 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
)
2819 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2820 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[i
]);
2821 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[i
]);
2822 si_image_views_begin_new_cs(sctx
, &sctx
->images
[i
]);
2824 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2825 si_vertex_buffers_begin_new_cs(sctx
);
2827 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2828 si_descriptors_begin_new_cs(sctx
, &sctx
->descriptors
[i
]);
2829 si_descriptors_begin_new_cs(sctx
, &sctx
->bindless_descriptors
);
2831 si_shader_pointers_begin_new_cs(sctx
);
2834 void si_set_active_descriptors(struct si_context
*sctx
, unsigned desc_idx
,
2835 uint64_t new_active_mask
)
2837 struct si_descriptors
*desc
= &sctx
->descriptors
[desc_idx
];
2839 /* Ignore no-op updates and updates that disable all slots. */
2840 if (!new_active_mask
||
2841 new_active_mask
== u_bit_consecutive64(desc
->first_active_slot
,
2842 desc
->num_active_slots
))
2846 u_bit_scan_consecutive_range64(&new_active_mask
, &first
, &count
);
2847 assert(new_active_mask
== 0);
2849 /* Upload/dump descriptors if slots are being enabled. */
2850 if (first
< desc
->first_active_slot
||
2851 first
+ count
> desc
->first_active_slot
+ desc
->num_active_slots
)
2852 sctx
->descriptors_dirty
|= 1u << desc_idx
;
2854 desc
->first_active_slot
= first
;
2855 desc
->num_active_slots
= count
;
2858 void si_set_active_descriptors_for_shader(struct si_context
*sctx
,
2859 struct si_shader_selector
*sel
)
2864 si_set_active_descriptors(sctx
,
2865 si_const_and_shader_buffer_descriptors_idx(sel
->type
),
2866 sel
->active_const_and_shader_buffers
);
2867 si_set_active_descriptors(sctx
,
2868 si_sampler_and_image_descriptors_idx(sel
->type
),
2869 sel
->active_samplers_and_images
);