2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 /* Resource binding slots and sampler states (each described with 8 or
25 * 4 dwords) are stored in lists in memory which is accessed by shaders
26 * using scalar load instructions.
28 * This file is responsible for managing such lists. It keeps a copy of all
29 * descriptors in CPU memory and re-uploads a whole list if some slots have
32 * This code is also reponsible for updating shader pointers to those lists.
34 * Note that CP DMA can't be used for updating the lists, because a GPU hang
35 * could leave the list in a mid-IB state and the next IB would get wrong
36 * descriptors and the whole context would be unusable at that point.
37 * (Note: The register shadowing can't be used due to the same reason)
39 * Also, uploading descriptors to newly allocated memory doesn't require
43 * Possible scenarios for one 16 dword image+sampler slot:
45 * | Image | w/ FMASK | Buffer | NULL
46 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
47 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
48 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
49 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
51 * FMASK implies MSAA, therefore no sampler state.
52 * Sampler states are never unbound except when FMASK is bound.
55 #include "radeon/r600_cs.h"
60 #include "util/hash_table.h"
61 #include "util/u_idalloc.h"
62 #include "util/u_format.h"
63 #include "util/u_memory.h"
64 #include "util/u_upload_mgr.h"
67 /* NULL image and buffer descriptor for textures (alpha = 1) and images
70 * For images, all fields must be zero except for the swizzle, which
71 * supports arbitrary combinations of 0s and 1s. The texture type must be
72 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
74 * For buffers, all fields must be zero. If they are not, the hw hangs.
76 * This is the only reason why the buffer descriptor must be in words [4:7].
78 static uint32_t null_texture_descriptor
[8] = {
82 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1
) |
83 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
84 /* the rest must contain zeros, which is also used by the buffer
88 static uint32_t null_image_descriptor
[8] = {
92 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
93 /* the rest must contain zeros, which is also used by the buffer
97 static uint64_t si_desc_extract_buffer_address(uint32_t *desc
)
99 uint64_t va
= desc
[0] |
100 ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc
[1]) << 32);
102 /* Sign-extend the 48-bit address. */
103 if (va
& (1ull << 47))
104 va
|= 0xffffull
<< 48;
108 static void si_init_descriptor_list(uint32_t *desc_list
,
109 unsigned element_dw_size
,
110 unsigned num_elements
,
111 const uint32_t *null_descriptor
)
115 /* Initialize the array to NULL descriptors if the element size is 8. */
116 if (null_descriptor
) {
117 assert(element_dw_size
% 8 == 0);
118 for (i
= 0; i
< num_elements
* element_dw_size
/ 8; i
++)
119 memcpy(desc_list
+ i
* 8, null_descriptor
, 8 * 4);
123 static void si_init_descriptors(struct si_descriptors
*desc
,
124 short shader_userdata_rel_index
,
125 unsigned element_dw_size
,
126 unsigned num_elements
)
128 desc
->list
= CALLOC(num_elements
, element_dw_size
* 4);
129 desc
->element_dw_size
= element_dw_size
;
130 desc
->num_elements
= num_elements
;
131 desc
->shader_userdata_offset
= shader_userdata_rel_index
* 4;
132 desc
->slot_index_to_bind_directly
= -1;
135 static void si_release_descriptors(struct si_descriptors
*desc
)
137 r600_resource_reference(&desc
->buffer
, NULL
);
141 static bool si_upload_descriptors(struct si_context
*sctx
,
142 struct si_descriptors
*desc
)
144 unsigned slot_size
= desc
->element_dw_size
* 4;
145 unsigned first_slot_offset
= desc
->first_active_slot
* slot_size
;
146 unsigned upload_size
= desc
->num_active_slots
* slot_size
;
148 /* Skip the upload if no shader is using the descriptors. dirty_mask
149 * will stay dirty and the descriptors will be uploaded when there is
150 * a shader using them.
155 /* If there is just one active descriptor, bind it directly. */
156 if ((int)desc
->first_active_slot
== desc
->slot_index_to_bind_directly
&&
157 desc
->num_active_slots
== 1) {
158 uint32_t *descriptor
= &desc
->list
[desc
->slot_index_to_bind_directly
*
159 desc
->element_dw_size
];
161 /* The buffer is already in the buffer list. */
162 r600_resource_reference(&desc
->buffer
, NULL
);
163 desc
->gpu_list
= NULL
;
164 desc
->gpu_address
= si_desc_extract_buffer_address(descriptor
);
165 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
170 unsigned buffer_offset
;
171 u_upload_alloc(sctx
->b
.b
.const_uploader
, first_slot_offset
, upload_size
,
172 si_optimal_tcc_alignment(sctx
, upload_size
),
173 &buffer_offset
, (struct pipe_resource
**)&desc
->buffer
,
176 desc
->gpu_address
= 0;
177 return false; /* skip the draw call */
180 util_memcpy_cpu_to_le32(ptr
, (char*)desc
->list
+ first_slot_offset
,
182 desc
->gpu_list
= ptr
- first_slot_offset
/ 4;
184 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, desc
->buffer
,
185 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
187 /* The shader pointer should point to slot 0. */
188 buffer_offset
-= first_slot_offset
;
189 desc
->gpu_address
= desc
->buffer
->gpu_address
+ buffer_offset
;
191 assert(desc
->buffer
->flags
& RADEON_FLAG_32BIT
);
192 assert((desc
->buffer
->gpu_address
>> 32) == sctx
->screen
->info
.address32_hi
);
193 assert((desc
->gpu_address
>> 32) == sctx
->screen
->info
.address32_hi
);
195 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
200 si_descriptors_begin_new_cs(struct si_context
*sctx
, struct si_descriptors
*desc
)
205 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, desc
->buffer
,
206 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
211 static inline enum radeon_bo_priority
212 si_get_sampler_view_priority(struct r600_resource
*res
)
214 if (res
->b
.b
.target
== PIPE_BUFFER
)
215 return RADEON_PRIO_SAMPLER_BUFFER
;
217 if (res
->b
.b
.nr_samples
> 1)
218 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA
;
220 return RADEON_PRIO_SAMPLER_TEXTURE
;
224 si_sampler_and_image_descriptors_idx(unsigned shader
)
226 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
227 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
;
230 static struct si_descriptors
*
231 si_sampler_and_image_descriptors(struct si_context
*sctx
, unsigned shader
)
233 return &sctx
->descriptors
[si_sampler_and_image_descriptors_idx(shader
)];
236 static void si_release_sampler_views(struct si_samplers
*samplers
)
240 for (i
= 0; i
< ARRAY_SIZE(samplers
->views
); i
++) {
241 pipe_sampler_view_reference(&samplers
->views
[i
], NULL
);
245 static void si_sampler_view_add_buffer(struct si_context
*sctx
,
246 struct pipe_resource
*resource
,
247 enum radeon_bo_usage usage
,
248 bool is_stencil_sampler
,
251 struct r600_resource
*rres
;
252 struct r600_texture
*rtex
;
253 enum radeon_bo_priority priority
;
258 if (resource
->target
!= PIPE_BUFFER
) {
259 struct r600_texture
*tex
= (struct r600_texture
*)resource
;
261 if (tex
->is_depth
&& !si_can_sample_zs(tex
, is_stencil_sampler
))
262 resource
= &tex
->flushed_depth_texture
->resource
.b
.b
;
265 rres
= (struct r600_resource
*)resource
;
266 priority
= si_get_sampler_view_priority(rres
);
268 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
269 rres
, usage
, priority
,
272 if (resource
->target
== PIPE_BUFFER
)
275 /* Now add separate DCC or HTILE. */
276 rtex
= (struct r600_texture
*)resource
;
277 if (rtex
->dcc_separate_buffer
) {
278 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
279 rtex
->dcc_separate_buffer
, usage
,
280 RADEON_PRIO_DCC
, check_mem
);
284 static void si_sampler_views_begin_new_cs(struct si_context
*sctx
,
285 struct si_samplers
*samplers
)
287 unsigned mask
= samplers
->enabled_mask
;
289 /* Add buffers to the CS. */
291 int i
= u_bit_scan(&mask
);
292 struct si_sampler_view
*sview
= (struct si_sampler_view
*)samplers
->views
[i
];
294 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
296 sview
->is_stencil_sampler
, false);
300 /* Set buffer descriptor fields that can be changed by reallocations. */
301 static void si_set_buf_desc_address(struct r600_resource
*buf
,
302 uint64_t offset
, uint32_t *state
)
304 uint64_t va
= buf
->gpu_address
+ offset
;
307 state
[1] &= C_008F04_BASE_ADDRESS_HI
;
308 state
[1] |= S_008F04_BASE_ADDRESS_HI(va
>> 32);
311 /* Set texture descriptor fields that can be changed by reallocations.
314 * \param base_level_info information of the level of BASE_ADDRESS
315 * \param base_level the level of BASE_ADDRESS
316 * \param first_level pipe_sampler_view.u.tex.first_level
317 * \param block_width util_format_get_blockwidth()
318 * \param is_stencil select between separate Z & Stencil
319 * \param state descriptor to update
321 void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen
,
322 struct r600_texture
*tex
,
323 const struct legacy_surf_level
*base_level_info
,
324 unsigned base_level
, unsigned first_level
,
325 unsigned block_width
, bool is_stencil
,
328 uint64_t va
, meta_va
= 0;
330 if (tex
->is_depth
&& !si_can_sample_zs(tex
, is_stencil
)) {
331 tex
= tex
->flushed_depth_texture
;
335 va
= tex
->resource
.gpu_address
;
337 if (sscreen
->info
.chip_class
>= GFX9
) {
338 /* Only stencil_offset needs to be added here. */
340 va
+= tex
->surface
.u
.gfx9
.stencil_offset
;
342 va
+= tex
->surface
.u
.gfx9
.surf_offset
;
344 va
+= base_level_info
->offset
;
348 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
349 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
351 /* Only macrotiled modes can set tile swizzle.
352 * GFX9 doesn't use (legacy) base_level_info.
354 if (sscreen
->info
.chip_class
>= GFX9
||
355 base_level_info
->mode
== RADEON_SURF_MODE_2D
)
356 state
[0] |= tex
->surface
.tile_swizzle
;
358 if (sscreen
->info
.chip_class
>= VI
) {
359 state
[6] &= C_008F28_COMPRESSION_EN
;
362 if (vi_dcc_enabled(tex
, first_level
)) {
363 meta_va
= (!tex
->dcc_separate_buffer
? tex
->resource
.gpu_address
: 0) +
366 if (sscreen
->info
.chip_class
== VI
) {
367 meta_va
+= base_level_info
->dcc_offset
;
368 assert(base_level_info
->mode
== RADEON_SURF_MODE_2D
);
371 meta_va
|= (uint32_t)tex
->surface
.tile_swizzle
<< 8;
372 } else if (vi_tc_compat_htile_enabled(tex
, first_level
)) {
373 meta_va
= tex
->resource
.gpu_address
+ tex
->htile_offset
;
377 state
[6] |= S_008F28_COMPRESSION_EN(1);
378 state
[7] = meta_va
>> 8;
382 if (sscreen
->info
.chip_class
>= GFX9
) {
383 state
[3] &= C_008F1C_SW_MODE
;
384 state
[4] &= C_008F20_PITCH_GFX9
;
387 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
388 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.stencil
.epitch
);
390 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
);
391 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.surf
.epitch
);
394 state
[5] &= C_008F24_META_DATA_ADDRESS
&
395 C_008F24_META_PIPE_ALIGNED
&
396 C_008F24_META_RB_ALIGNED
;
398 struct gfx9_surf_meta_flags meta
;
401 meta
= tex
->surface
.u
.gfx9
.dcc
;
403 meta
= tex
->surface
.u
.gfx9
.htile
;
405 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
406 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
407 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
411 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
412 unsigned index
= si_tile_mode_index(tex
, base_level
, is_stencil
);
414 state
[3] &= C_008F1C_TILING_INDEX
;
415 state
[3] |= S_008F1C_TILING_INDEX(index
);
416 state
[4] &= C_008F20_PITCH_GFX6
;
417 state
[4] |= S_008F20_PITCH_GFX6(pitch
- 1);
421 static void si_set_sampler_state_desc(struct si_sampler_state
*sstate
,
422 struct si_sampler_view
*sview
,
423 struct r600_texture
*tex
,
426 if (sview
&& sview
->is_integer
)
427 memcpy(desc
, sstate
->integer_val
, 4*4);
428 else if (tex
&& tex
->upgraded_depth
&&
429 (!sview
|| !sview
->is_stencil_sampler
))
430 memcpy(desc
, sstate
->upgraded_depth_val
, 4*4);
432 memcpy(desc
, sstate
->val
, 4*4);
435 static void si_set_sampler_view_desc(struct si_context
*sctx
,
436 struct si_sampler_view
*sview
,
437 struct si_sampler_state
*sstate
,
440 struct pipe_sampler_view
*view
= &sview
->base
;
441 struct r600_texture
*rtex
= (struct r600_texture
*)view
->texture
;
442 bool is_buffer
= rtex
->resource
.b
.b
.target
== PIPE_BUFFER
;
444 if (unlikely(!is_buffer
&& sview
->dcc_incompatible
)) {
445 if (vi_dcc_enabled(rtex
, view
->u
.tex
.first_level
))
446 if (!si_texture_disable_dcc(&sctx
->b
, rtex
))
447 sctx
->b
.decompress_dcc(&sctx
->b
.b
, rtex
);
449 sview
->dcc_incompatible
= false;
452 assert(rtex
); /* views with texture == NULL aren't supported */
453 memcpy(desc
, sview
->state
, 8*4);
456 si_set_buf_desc_address(&rtex
->resource
,
457 sview
->base
.u
.buf
.offset
,
460 bool is_separate_stencil
= rtex
->db_compatible
&&
461 sview
->is_stencil_sampler
;
463 si_set_mutable_tex_desc_fields(sctx
->screen
, rtex
,
464 sview
->base_level_info
,
466 sview
->base
.u
.tex
.first_level
,
472 if (!is_buffer
&& rtex
->fmask
.size
) {
473 memcpy(desc
+ 8, sview
->fmask_state
, 8*4);
475 /* Disable FMASK and bind sampler state in [12:15]. */
476 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
479 si_set_sampler_state_desc(sstate
, sview
,
480 is_buffer
? NULL
: rtex
,
485 static bool color_needs_decompression(struct r600_texture
*rtex
)
487 return rtex
->fmask
.size
||
488 (rtex
->dirty_level_mask
&&
489 (rtex
->cmask
.size
|| rtex
->dcc_offset
));
492 static bool depth_needs_decompression(struct r600_texture
*rtex
)
494 /* If the depth/stencil texture is TC-compatible, no decompression
495 * will be done. The decompression function will only flush DB caches
496 * to make it coherent with shaders. That's necessary because the driver
497 * doesn't flush DB caches in any other case.
499 return rtex
->db_compatible
;
502 static void si_set_sampler_view(struct si_context
*sctx
,
504 unsigned slot
, struct pipe_sampler_view
*view
,
505 bool disallow_early_out
)
507 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
508 struct si_sampler_view
*rview
= (struct si_sampler_view
*)view
;
509 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(sctx
, shader
);
510 unsigned desc_slot
= si_get_sampler_slot(slot
);
511 uint32_t *desc
= descs
->list
+ desc_slot
* 16;
513 if (samplers
->views
[slot
] == view
&& !disallow_early_out
)
517 struct r600_texture
*rtex
= (struct r600_texture
*)view
->texture
;
519 si_set_sampler_view_desc(sctx
, rview
,
520 samplers
->sampler_states
[slot
], desc
);
522 if (rtex
->resource
.b
.b
.target
== PIPE_BUFFER
) {
523 rtex
->resource
.bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
524 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
525 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
527 if (depth_needs_decompression(rtex
)) {
528 samplers
->needs_depth_decompress_mask
|= 1u << slot
;
530 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
532 if (color_needs_decompression(rtex
)) {
533 samplers
->needs_color_decompress_mask
|= 1u << slot
;
535 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
538 if (rtex
->dcc_offset
&&
539 p_atomic_read(&rtex
->framebuffers_bound
))
540 sctx
->need_check_render_feedback
= true;
543 pipe_sampler_view_reference(&samplers
->views
[slot
], view
);
544 samplers
->enabled_mask
|= 1u << slot
;
546 /* Since this can flush, it must be done after enabled_mask is
548 si_sampler_view_add_buffer(sctx
, view
->texture
,
550 rview
->is_stencil_sampler
, true);
552 pipe_sampler_view_reference(&samplers
->views
[slot
], NULL
);
553 memcpy(desc
, null_texture_descriptor
, 8*4);
554 /* Only clear the lower dwords of FMASK. */
555 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
556 /* Re-set the sampler state if we are transitioning from FMASK. */
557 if (samplers
->sampler_states
[slot
])
558 si_set_sampler_state_desc(samplers
->sampler_states
[slot
], NULL
, NULL
,
561 samplers
->enabled_mask
&= ~(1u << slot
);
562 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
563 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
566 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
569 static void si_update_shader_needs_decompress_mask(struct si_context
*sctx
,
572 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
573 unsigned shader_bit
= 1 << shader
;
575 if (samplers
->needs_depth_decompress_mask
||
576 samplers
->needs_color_decompress_mask
||
577 sctx
->images
[shader
].needs_color_decompress_mask
)
578 sctx
->shader_needs_decompress_mask
|= shader_bit
;
580 sctx
->shader_needs_decompress_mask
&= ~shader_bit
;
583 static void si_set_sampler_views(struct pipe_context
*ctx
,
584 enum pipe_shader_type shader
, unsigned start
,
586 struct pipe_sampler_view
**views
)
588 struct si_context
*sctx
= (struct si_context
*)ctx
;
591 if (!count
|| shader
>= SI_NUM_SHADERS
)
595 for (i
= 0; i
< count
; i
++)
596 si_set_sampler_view(sctx
, shader
, start
+ i
, views
[i
], false);
598 for (i
= 0; i
< count
; i
++)
599 si_set_sampler_view(sctx
, shader
, start
+ i
, NULL
, false);
602 si_update_shader_needs_decompress_mask(sctx
, shader
);
606 si_samplers_update_needs_color_decompress_mask(struct si_samplers
*samplers
)
608 unsigned mask
= samplers
->enabled_mask
;
611 int i
= u_bit_scan(&mask
);
612 struct pipe_resource
*res
= samplers
->views
[i
]->texture
;
614 if (res
&& res
->target
!= PIPE_BUFFER
) {
615 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
617 if (color_needs_decompression(rtex
)) {
618 samplers
->needs_color_decompress_mask
|= 1u << i
;
620 samplers
->needs_color_decompress_mask
&= ~(1u << i
);
629 si_release_image_views(struct si_images
*images
)
633 for (i
= 0; i
< SI_NUM_IMAGES
; ++i
) {
634 struct pipe_image_view
*view
= &images
->views
[i
];
636 pipe_resource_reference(&view
->resource
, NULL
);
641 si_image_views_begin_new_cs(struct si_context
*sctx
, struct si_images
*images
)
643 uint mask
= images
->enabled_mask
;
645 /* Add buffers to the CS. */
647 int i
= u_bit_scan(&mask
);
648 struct pipe_image_view
*view
= &images
->views
[i
];
650 assert(view
->resource
);
652 si_sampler_view_add_buffer(sctx
, view
->resource
,
653 RADEON_USAGE_READWRITE
, false, false);
658 si_disable_shader_image(struct si_context
*ctx
, unsigned shader
, unsigned slot
)
660 struct si_images
*images
= &ctx
->images
[shader
];
662 if (images
->enabled_mask
& (1u << slot
)) {
663 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
664 unsigned desc_slot
= si_get_image_slot(slot
);
666 pipe_resource_reference(&images
->views
[slot
].resource
, NULL
);
667 images
->needs_color_decompress_mask
&= ~(1 << slot
);
669 memcpy(descs
->list
+ desc_slot
*8, null_image_descriptor
, 8*4);
670 images
->enabled_mask
&= ~(1u << slot
);
671 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
676 si_mark_image_range_valid(const struct pipe_image_view
*view
)
678 struct r600_resource
*res
= (struct r600_resource
*)view
->resource
;
680 assert(res
&& res
->b
.b
.target
== PIPE_BUFFER
);
682 util_range_add(&res
->valid_buffer_range
,
684 view
->u
.buf
.offset
+ view
->u
.buf
.size
);
687 static void si_set_shader_image_desc(struct si_context
*ctx
,
688 const struct pipe_image_view
*view
,
689 bool skip_decompress
,
692 struct si_screen
*screen
= ctx
->screen
;
693 struct r600_resource
*res
;
695 res
= (struct r600_resource
*)view
->resource
;
697 if (res
->b
.b
.target
== PIPE_BUFFER
) {
698 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
699 si_mark_image_range_valid(view
);
701 si_make_buffer_descriptor(screen
, res
,
704 view
->u
.buf
.size
, desc
);
705 si_set_buf_desc_address(res
, view
->u
.buf
.offset
, desc
+ 4);
707 static const unsigned char swizzle
[4] = { 0, 1, 2, 3 };
708 struct r600_texture
*tex
= (struct r600_texture
*)res
;
709 unsigned level
= view
->u
.tex
.level
;
710 unsigned width
, height
, depth
, hw_level
;
711 bool uses_dcc
= vi_dcc_enabled(tex
, level
);
712 unsigned access
= view
->access
;
714 /* Clear the write flag when writes can't occur.
715 * Note that DCC_DECOMPRESS for MSAA doesn't work in some cases,
716 * so we don't wanna trigger it.
718 if (tex
->is_depth
|| tex
->resource
.b
.b
.nr_samples
>= 2) {
719 assert(!"Z/S and MSAA image stores are not supported");
720 access
&= ~PIPE_IMAGE_ACCESS_WRITE
;
723 assert(!tex
->is_depth
);
724 assert(tex
->fmask
.size
== 0);
726 if (uses_dcc
&& !skip_decompress
&&
727 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
||
728 !vi_dcc_formats_compatible(res
->b
.b
.format
, view
->format
))) {
729 /* If DCC can't be disabled, at least decompress it.
730 * The decompression is relatively cheap if the surface
731 * has been decompressed already.
733 if (!si_texture_disable_dcc(&ctx
->b
, tex
))
734 ctx
->b
.decompress_dcc(&ctx
->b
.b
, tex
);
737 if (ctx
->b
.chip_class
>= GFX9
) {
738 /* Always set the base address. The swizzle modes don't
739 * allow setting mipmap level offsets as the base.
741 width
= res
->b
.b
.width0
;
742 height
= res
->b
.b
.height0
;
743 depth
= res
->b
.b
.depth0
;
746 /* Always force the base level to the selected level.
748 * This is required for 3D textures, where otherwise
749 * selecting a single slice for non-layered bindings
750 * fails. It doesn't hurt the other targets.
752 width
= u_minify(res
->b
.b
.width0
, level
);
753 height
= u_minify(res
->b
.b
.height0
, level
);
754 depth
= u_minify(res
->b
.b
.depth0
, level
);
758 si_make_texture_descriptor(screen
, tex
,
759 false, res
->b
.b
.target
,
760 view
->format
, swizzle
,
762 view
->u
.tex
.first_layer
,
763 view
->u
.tex
.last_layer
,
764 width
, height
, depth
,
766 si_set_mutable_tex_desc_fields(screen
, tex
,
767 &tex
->surface
.u
.legacy
.level
[level
],
769 util_format_get_blockwidth(view
->format
),
774 static void si_set_shader_image(struct si_context
*ctx
,
776 unsigned slot
, const struct pipe_image_view
*view
,
777 bool skip_decompress
)
779 struct si_images
*images
= &ctx
->images
[shader
];
780 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
781 struct r600_resource
*res
;
782 unsigned desc_slot
= si_get_image_slot(slot
);
783 uint32_t *desc
= descs
->list
+ desc_slot
* 8;
785 if (!view
|| !view
->resource
) {
786 si_disable_shader_image(ctx
, shader
, slot
);
790 res
= (struct r600_resource
*)view
->resource
;
792 if (&images
->views
[slot
] != view
)
793 util_copy_image_view(&images
->views
[slot
], view
);
795 si_set_shader_image_desc(ctx
, view
, skip_decompress
, desc
);
797 if (res
->b
.b
.target
== PIPE_BUFFER
) {
798 images
->needs_color_decompress_mask
&= ~(1 << slot
);
799 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
801 struct r600_texture
*tex
= (struct r600_texture
*)res
;
802 unsigned level
= view
->u
.tex
.level
;
804 if (color_needs_decompression(tex
)) {
805 images
->needs_color_decompress_mask
|= 1 << slot
;
807 images
->needs_color_decompress_mask
&= ~(1 << slot
);
810 if (vi_dcc_enabled(tex
, level
) &&
811 p_atomic_read(&tex
->framebuffers_bound
))
812 ctx
->need_check_render_feedback
= true;
815 images
->enabled_mask
|= 1u << slot
;
816 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
818 /* Since this can flush, it must be done after enabled_mask is updated. */
819 si_sampler_view_add_buffer(ctx
, &res
->b
.b
,
820 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
) ?
821 RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
,
826 si_set_shader_images(struct pipe_context
*pipe
,
827 enum pipe_shader_type shader
,
828 unsigned start_slot
, unsigned count
,
829 const struct pipe_image_view
*views
)
831 struct si_context
*ctx
= (struct si_context
*)pipe
;
834 assert(shader
< SI_NUM_SHADERS
);
839 assert(start_slot
+ count
<= SI_NUM_IMAGES
);
842 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
843 si_set_shader_image(ctx
, shader
, slot
, &views
[i
], false);
845 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
846 si_set_shader_image(ctx
, shader
, slot
, NULL
, false);
849 si_update_shader_needs_decompress_mask(ctx
, shader
);
853 si_images_update_needs_color_decompress_mask(struct si_images
*images
)
855 unsigned mask
= images
->enabled_mask
;
858 int i
= u_bit_scan(&mask
);
859 struct pipe_resource
*res
= images
->views
[i
].resource
;
861 if (res
&& res
->target
!= PIPE_BUFFER
) {
862 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
864 if (color_needs_decompression(rtex
)) {
865 images
->needs_color_decompress_mask
|= 1 << i
;
867 images
->needs_color_decompress_mask
&= ~(1 << i
);
875 static void si_bind_sampler_states(struct pipe_context
*ctx
,
876 enum pipe_shader_type shader
,
877 unsigned start
, unsigned count
, void **states
)
879 struct si_context
*sctx
= (struct si_context
*)ctx
;
880 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
881 struct si_descriptors
*desc
= si_sampler_and_image_descriptors(sctx
, shader
);
882 struct si_sampler_state
**sstates
= (struct si_sampler_state
**)states
;
885 if (!count
|| shader
>= SI_NUM_SHADERS
)
888 for (i
= 0; i
< count
; i
++) {
889 unsigned slot
= start
+ i
;
890 unsigned desc_slot
= si_get_sampler_slot(slot
);
893 sstates
[i
] == samplers
->sampler_states
[slot
])
897 assert(sstates
[i
]->magic
== SI_SAMPLER_STATE_MAGIC
);
899 samplers
->sampler_states
[slot
] = sstates
[i
];
901 /* If FMASK is bound, don't overwrite it.
902 * The sampler state will be set after FMASK is unbound.
904 struct si_sampler_view
*sview
=
905 (struct si_sampler_view
*)samplers
->views
[slot
];
907 struct r600_texture
*tex
= NULL
;
909 if (sview
&& sview
->base
.texture
&&
910 sview
->base
.texture
->target
!= PIPE_BUFFER
)
911 tex
= (struct r600_texture
*)sview
->base
.texture
;
913 if (tex
&& tex
->fmask
.size
)
916 si_set_sampler_state_desc(sstates
[i
], sview
, tex
,
917 desc
->list
+ desc_slot
* 16 + 12);
919 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
923 /* BUFFER RESOURCES */
925 static void si_init_buffer_resources(struct si_buffer_resources
*buffers
,
926 struct si_descriptors
*descs
,
927 unsigned num_buffers
,
928 short shader_userdata_rel_index
,
929 enum radeon_bo_usage shader_usage
,
930 enum radeon_bo_usage shader_usage_constbuf
,
931 enum radeon_bo_priority priority
,
932 enum radeon_bo_priority priority_constbuf
)
934 buffers
->shader_usage
= shader_usage
;
935 buffers
->shader_usage_constbuf
= shader_usage_constbuf
;
936 buffers
->priority
= priority
;
937 buffers
->priority_constbuf
= priority_constbuf
;
938 buffers
->buffers
= CALLOC(num_buffers
, sizeof(struct pipe_resource
*));
940 si_init_descriptors(descs
, shader_userdata_rel_index
, 4, num_buffers
);
943 static void si_release_buffer_resources(struct si_buffer_resources
*buffers
,
944 struct si_descriptors
*descs
)
948 for (i
= 0; i
< descs
->num_elements
; i
++) {
949 pipe_resource_reference(&buffers
->buffers
[i
], NULL
);
952 FREE(buffers
->buffers
);
955 static void si_buffer_resources_begin_new_cs(struct si_context
*sctx
,
956 struct si_buffer_resources
*buffers
)
958 unsigned mask
= buffers
->enabled_mask
;
960 /* Add buffers to the CS. */
962 int i
= u_bit_scan(&mask
);
964 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
965 r600_resource(buffers
->buffers
[i
]),
966 i
< SI_NUM_SHADER_BUFFERS
? buffers
->shader_usage
:
967 buffers
->shader_usage_constbuf
,
968 i
< SI_NUM_SHADER_BUFFERS
? buffers
->priority
:
969 buffers
->priority_constbuf
);
973 static void si_get_buffer_from_descriptors(struct si_buffer_resources
*buffers
,
974 struct si_descriptors
*descs
,
975 unsigned idx
, struct pipe_resource
**buf
,
976 unsigned *offset
, unsigned *size
)
978 pipe_resource_reference(buf
, buffers
->buffers
[idx
]);
980 struct r600_resource
*res
= r600_resource(*buf
);
981 const uint32_t *desc
= descs
->list
+ idx
* 4;
986 assert(G_008F04_STRIDE(desc
[1]) == 0);
987 va
= ((uint64_t)desc
[1] << 32) | desc
[0];
989 assert(va
>= res
->gpu_address
&& va
+ *size
<= res
->gpu_address
+ res
->bo_size
);
990 *offset
= va
- res
->gpu_address
;
996 static void si_vertex_buffers_begin_new_cs(struct si_context
*sctx
)
998 int count
= sctx
->vertex_elements
? sctx
->vertex_elements
->count
: 0;
1001 for (i
= 0; i
< count
; i
++) {
1002 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1004 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1006 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1009 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1010 (struct r600_resource
*)sctx
->vertex_buffer
[vb
].buffer
.resource
,
1011 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1014 if (!sctx
->vb_descriptors_buffer
)
1016 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1017 sctx
->vb_descriptors_buffer
, RADEON_USAGE_READ
,
1018 RADEON_PRIO_DESCRIPTORS
);
1021 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
)
1023 struct si_vertex_elements
*velems
= sctx
->vertex_elements
;
1025 unsigned desc_list_byte_size
;
1026 unsigned first_vb_use_mask
;
1029 if (!sctx
->vertex_buffers_dirty
|| !velems
)
1032 count
= velems
->count
;
1037 desc_list_byte_size
= velems
->desc_list_byte_size
;
1038 first_vb_use_mask
= velems
->first_vb_use_mask
;
1040 /* Vertex buffer descriptors are the only ones which are uploaded
1041 * directly through a staging buffer and don't go through
1042 * the fine-grained upload path.
1044 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0,
1045 desc_list_byte_size
,
1046 si_optimal_tcc_alignment(sctx
, desc_list_byte_size
),
1047 &sctx
->vb_descriptors_offset
,
1048 (struct pipe_resource
**)&sctx
->vb_descriptors_buffer
,
1050 if (!sctx
->vb_descriptors_buffer
) {
1051 sctx
->vb_descriptors_offset
= 0;
1052 sctx
->vb_descriptors_gpu_list
= NULL
;
1056 sctx
->vb_descriptors_gpu_list
= ptr
;
1057 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1058 sctx
->vb_descriptors_buffer
, RADEON_USAGE_READ
,
1059 RADEON_PRIO_DESCRIPTORS
);
1061 assert(count
<= SI_MAX_ATTRIBS
);
1063 for (i
= 0; i
< count
; i
++) {
1064 struct pipe_vertex_buffer
*vb
;
1065 struct r600_resource
*rbuffer
;
1066 unsigned vbo_index
= velems
->vertex_buffer_index
[i
];
1067 uint32_t *desc
= &ptr
[i
*4];
1069 vb
= &sctx
->vertex_buffer
[vbo_index
];
1070 rbuffer
= (struct r600_resource
*)vb
->buffer
.resource
;
1072 memset(desc
, 0, 16);
1076 int64_t offset
= (int64_t)((int)vb
->buffer_offset
) +
1077 velems
->src_offset
[i
];
1078 uint64_t va
= rbuffer
->gpu_address
+ offset
;
1080 int64_t num_records
= (int64_t)rbuffer
->b
.b
.width0
- offset
;
1081 if (sctx
->b
.chip_class
!= VI
&& vb
->stride
) {
1082 /* Round up by rounding down and adding 1 */
1083 num_records
= (num_records
- velems
->format_size
[i
]) /
1086 assert(num_records
>= 0 && num_records
<= UINT_MAX
);
1089 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1090 S_008F04_STRIDE(vb
->stride
);
1091 desc
[2] = num_records
;
1092 desc
[3] = velems
->rsrc_word3
[i
];
1094 if (first_vb_use_mask
& (1 << i
)) {
1095 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1096 (struct r600_resource
*)vb
->buffer
.resource
,
1097 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1101 /* Don't flush the const cache. It would have a very negative effect
1102 * on performance (confirmed by testing). New descriptors are always
1103 * uploaded to a fresh new buffer, so I don't think flushing the const
1104 * cache is needed. */
1105 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
1106 sctx
->vertex_buffers_dirty
= false;
1107 sctx
->vertex_buffer_pointer_dirty
= true;
1108 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VBO_DESCRIPTORS
;
1113 /* CONSTANT BUFFERS */
1116 si_const_and_shader_buffer_descriptors_idx(unsigned shader
)
1118 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
1119 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
;
1122 static struct si_descriptors
*
1123 si_const_and_shader_buffer_descriptors(struct si_context
*sctx
, unsigned shader
)
1125 return &sctx
->descriptors
[si_const_and_shader_buffer_descriptors_idx(shader
)];
1128 void si_upload_const_buffer(struct si_context
*sctx
, struct r600_resource
**rbuffer
,
1129 const uint8_t *ptr
, unsigned size
, uint32_t *const_offset
)
1133 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0, size
,
1134 si_optimal_tcc_alignment(sctx
, size
),
1136 (struct pipe_resource
**)rbuffer
, &tmp
);
1138 util_memcpy_cpu_to_le32(tmp
, ptr
, size
);
1141 static void si_set_constant_buffer(struct si_context
*sctx
,
1142 struct si_buffer_resources
*buffers
,
1143 unsigned descriptors_idx
,
1144 uint slot
, const struct pipe_constant_buffer
*input
)
1146 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1147 assert(slot
< descs
->num_elements
);
1148 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1150 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1151 * with a NULL buffer). We need to use a dummy buffer instead. */
1152 if (sctx
->b
.chip_class
== CIK
&&
1153 (!input
|| (!input
->buffer
&& !input
->user_buffer
)))
1154 input
= &sctx
->null_const_buf
;
1156 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
1157 struct pipe_resource
*buffer
= NULL
;
1160 /* Upload the user buffer if needed. */
1161 if (input
->user_buffer
) {
1162 unsigned buffer_offset
;
1164 si_upload_const_buffer(sctx
,
1165 (struct r600_resource
**)&buffer
, input
->user_buffer
,
1166 input
->buffer_size
, &buffer_offset
);
1168 /* Just unbind on failure. */
1169 si_set_constant_buffer(sctx
, buffers
, descriptors_idx
, slot
, NULL
);
1172 va
= r600_resource(buffer
)->gpu_address
+ buffer_offset
;
1174 pipe_resource_reference(&buffer
, input
->buffer
);
1175 va
= r600_resource(buffer
)->gpu_address
+ input
->buffer_offset
;
1176 /* Only track usage for non-user buffers. */
1177 r600_resource(buffer
)->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
1180 /* Set the descriptor. */
1181 uint32_t *desc
= descs
->list
+ slot
*4;
1183 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1185 desc
[2] = input
->buffer_size
;
1186 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1187 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1188 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1189 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1190 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1191 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1193 buffers
->buffers
[slot
] = buffer
;
1194 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1195 (struct r600_resource
*)buffer
,
1196 buffers
->shader_usage_constbuf
,
1197 buffers
->priority_constbuf
, true);
1198 buffers
->enabled_mask
|= 1u << slot
;
1200 /* Clear the descriptor. */
1201 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1202 buffers
->enabled_mask
&= ~(1u << slot
);
1205 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1208 void si_set_rw_buffer(struct si_context
*sctx
,
1209 uint slot
, const struct pipe_constant_buffer
*input
)
1211 si_set_constant_buffer(sctx
, &sctx
->rw_buffers
,
1212 SI_DESCS_RW_BUFFERS
, slot
, input
);
1215 static void si_pipe_set_constant_buffer(struct pipe_context
*ctx
,
1216 enum pipe_shader_type shader
, uint slot
,
1217 const struct pipe_constant_buffer
*input
)
1219 struct si_context
*sctx
= (struct si_context
*)ctx
;
1221 if (shader
>= SI_NUM_SHADERS
)
1224 if (slot
== 0 && input
&& input
->buffer
&&
1225 !(r600_resource(input
->buffer
)->flags
& RADEON_FLAG_32BIT
)) {
1226 assert(!"constant buffer 0 must have a 32-bit VM address, use const_uploader");
1230 slot
= si_get_constbuf_slot(slot
);
1231 si_set_constant_buffer(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1232 si_const_and_shader_buffer_descriptors_idx(shader
),
1236 void si_get_pipe_constant_buffer(struct si_context
*sctx
, uint shader
,
1237 uint slot
, struct pipe_constant_buffer
*cbuf
)
1239 cbuf
->user_buffer
= NULL
;
1240 si_get_buffer_from_descriptors(
1241 &sctx
->const_and_shader_buffers
[shader
],
1242 si_const_and_shader_buffer_descriptors(sctx
, shader
),
1243 si_get_constbuf_slot(slot
),
1244 &cbuf
->buffer
, &cbuf
->buffer_offset
, &cbuf
->buffer_size
);
1247 /* SHADER BUFFERS */
1249 static void si_set_shader_buffers(struct pipe_context
*ctx
,
1250 enum pipe_shader_type shader
,
1251 unsigned start_slot
, unsigned count
,
1252 const struct pipe_shader_buffer
*sbuffers
)
1254 struct si_context
*sctx
= (struct si_context
*)ctx
;
1255 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1256 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1259 assert(start_slot
+ count
<= SI_NUM_SHADER_BUFFERS
);
1261 for (i
= 0; i
< count
; ++i
) {
1262 const struct pipe_shader_buffer
*sbuffer
= sbuffers
? &sbuffers
[i
] : NULL
;
1263 struct r600_resource
*buf
;
1264 unsigned slot
= si_get_shaderbuf_slot(start_slot
+ i
);
1265 uint32_t *desc
= descs
->list
+ slot
* 4;
1268 if (!sbuffer
|| !sbuffer
->buffer
) {
1269 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1270 memset(desc
, 0, sizeof(uint32_t) * 4);
1271 buffers
->enabled_mask
&= ~(1u << slot
);
1272 sctx
->descriptors_dirty
|=
1273 1u << si_const_and_shader_buffer_descriptors_idx(shader
);
1277 buf
= (struct r600_resource
*)sbuffer
->buffer
;
1278 va
= buf
->gpu_address
+ sbuffer
->buffer_offset
;
1281 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1283 desc
[2] = sbuffer
->buffer_size
;
1284 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1285 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1286 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1287 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1288 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1289 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1291 pipe_resource_reference(&buffers
->buffers
[slot
], &buf
->b
.b
);
1292 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
, buf
,
1293 buffers
->shader_usage
,
1294 buffers
->priority
, true);
1295 buf
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
1297 buffers
->enabled_mask
|= 1u << slot
;
1298 sctx
->descriptors_dirty
|=
1299 1u << si_const_and_shader_buffer_descriptors_idx(shader
);
1301 util_range_add(&buf
->valid_buffer_range
, sbuffer
->buffer_offset
,
1302 sbuffer
->buffer_offset
+ sbuffer
->buffer_size
);
1306 void si_get_shader_buffers(struct si_context
*sctx
,
1307 enum pipe_shader_type shader
,
1308 uint start_slot
, uint count
,
1309 struct pipe_shader_buffer
*sbuf
)
1311 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1312 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1314 for (unsigned i
= 0; i
< count
; ++i
) {
1315 si_get_buffer_from_descriptors(
1317 si_get_shaderbuf_slot(start_slot
+ i
),
1318 &sbuf
[i
].buffer
, &sbuf
[i
].buffer_offset
,
1319 &sbuf
[i
].buffer_size
);
1325 void si_set_ring_buffer(struct pipe_context
*ctx
, uint slot
,
1326 struct pipe_resource
*buffer
,
1327 unsigned stride
, unsigned num_records
,
1328 bool add_tid
, bool swizzle
,
1329 unsigned element_size
, unsigned index_stride
, uint64_t offset
)
1331 struct si_context
*sctx
= (struct si_context
*)ctx
;
1332 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1333 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1335 /* The stride field in the resource descriptor has 14 bits */
1336 assert(stride
< (1 << 14));
1338 assert(slot
< descs
->num_elements
);
1339 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1344 va
= r600_resource(buffer
)->gpu_address
+ offset
;
1346 switch (element_size
) {
1348 assert(!"Unsupported ring buffer element size");
1364 switch (index_stride
) {
1366 assert(!"Unsupported ring buffer index stride");
1382 if (sctx
->b
.chip_class
>= VI
&& stride
)
1383 num_records
*= stride
;
1385 /* Set the descriptor. */
1386 uint32_t *desc
= descs
->list
+ slot
*4;
1388 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1389 S_008F04_STRIDE(stride
) |
1390 S_008F04_SWIZZLE_ENABLE(swizzle
);
1391 desc
[2] = num_records
;
1392 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1393 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1394 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1395 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1396 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1397 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1398 S_008F0C_INDEX_STRIDE(index_stride
) |
1399 S_008F0C_ADD_TID_ENABLE(add_tid
);
1401 if (sctx
->b
.chip_class
>= GFX9
)
1402 assert(!swizzle
|| element_size
== 1); /* always 4 bytes on GFX9 */
1404 desc
[3] |= S_008F0C_ELEMENT_SIZE(element_size
);
1406 pipe_resource_reference(&buffers
->buffers
[slot
], buffer
);
1407 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1408 (struct r600_resource
*)buffer
,
1409 buffers
->shader_usage
, buffers
->priority
);
1410 buffers
->enabled_mask
|= 1u << slot
;
1412 /* Clear the descriptor. */
1413 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1414 buffers
->enabled_mask
&= ~(1u << slot
);
1417 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1420 static void si_desc_reset_buffer_offset(struct pipe_context
*ctx
,
1421 uint32_t *desc
, uint64_t old_buf_va
,
1422 struct pipe_resource
*new_buf
)
1424 /* Retrieve the buffer offset from the descriptor. */
1425 uint64_t old_desc_va
= si_desc_extract_buffer_address(desc
);
1427 assert(old_buf_va
<= old_desc_va
);
1428 uint64_t offset_within_buffer
= old_desc_va
- old_buf_va
;
1430 /* Update the descriptor. */
1431 si_set_buf_desc_address(r600_resource(new_buf
), offset_within_buffer
,
1435 /* INTERNAL CONST BUFFERS */
1437 static void si_set_polygon_stipple(struct pipe_context
*ctx
,
1438 const struct pipe_poly_stipple
*state
)
1440 struct si_context
*sctx
= (struct si_context
*)ctx
;
1441 struct pipe_constant_buffer cb
= {};
1442 unsigned stipple
[32];
1445 for (i
= 0; i
< 32; i
++)
1446 stipple
[i
] = util_bitreverse(state
->stipple
[i
]);
1448 cb
.user_buffer
= stipple
;
1449 cb
.buffer_size
= sizeof(stipple
);
1451 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
, &cb
);
1454 /* TEXTURE METADATA ENABLE/DISABLE */
1457 si_resident_handles_update_needs_color_decompress(struct si_context
*sctx
)
1459 util_dynarray_clear(&sctx
->resident_tex_needs_color_decompress
);
1460 util_dynarray_clear(&sctx
->resident_img_needs_color_decompress
);
1462 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1463 struct si_texture_handle
*, tex_handle
) {
1464 struct pipe_resource
*res
= (*tex_handle
)->view
->texture
;
1465 struct r600_texture
*rtex
;
1467 if (!res
|| res
->target
== PIPE_BUFFER
)
1470 rtex
= (struct r600_texture
*)res
;
1471 if (!color_needs_decompression(rtex
))
1474 util_dynarray_append(&sctx
->resident_tex_needs_color_decompress
,
1475 struct si_texture_handle
*, *tex_handle
);
1478 util_dynarray_foreach(&sctx
->resident_img_handles
,
1479 struct si_image_handle
*, img_handle
) {
1480 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1481 struct pipe_resource
*res
= view
->resource
;
1482 struct r600_texture
*rtex
;
1484 if (!res
|| res
->target
== PIPE_BUFFER
)
1487 rtex
= (struct r600_texture
*)res
;
1488 if (!color_needs_decompression(rtex
))
1491 util_dynarray_append(&sctx
->resident_img_needs_color_decompress
,
1492 struct si_image_handle
*, *img_handle
);
1496 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1497 * while the texture is bound, possibly by a different context. In that case,
1498 * call this function to update needs_*_decompress_masks.
1500 void si_update_needs_color_decompress_masks(struct si_context
*sctx
)
1502 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
1503 si_samplers_update_needs_color_decompress_mask(&sctx
->samplers
[i
]);
1504 si_images_update_needs_color_decompress_mask(&sctx
->images
[i
]);
1505 si_update_shader_needs_decompress_mask(sctx
, i
);
1508 si_resident_handles_update_needs_color_decompress(sctx
);
1511 /* BUFFER DISCARD/INVALIDATION */
1513 /** Reset descriptors of buffer resources after \p buf has been invalidated. */
1514 static void si_reset_buffer_resources(struct si_context
*sctx
,
1515 struct si_buffer_resources
*buffers
,
1516 unsigned descriptors_idx
,
1518 struct pipe_resource
*buf
,
1520 enum radeon_bo_usage usage
,
1521 enum radeon_bo_priority priority
)
1523 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1524 unsigned mask
= buffers
->enabled_mask
& slot_mask
;
1527 unsigned i
= u_bit_scan(&mask
);
1528 if (buffers
->buffers
[i
] == buf
) {
1529 si_desc_reset_buffer_offset(&sctx
->b
.b
,
1532 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1534 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1535 (struct r600_resource
*)buf
,
1536 usage
, priority
, true);
1541 static void si_rebind_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
,
1544 struct si_context
*sctx
= (struct si_context
*)ctx
;
1545 struct r600_resource
*rbuffer
= r600_resource(buf
);
1547 unsigned num_elems
= sctx
->vertex_elements
?
1548 sctx
->vertex_elements
->count
: 0;
1550 /* We changed the buffer, now we need to bind it where the old one
1551 * was bound. This consists of 2 things:
1552 * 1) Updating the resource descriptor and dirtying it.
1553 * 2) Adding a relocation to the CS, so that it's usable.
1556 /* Vertex buffers. */
1557 if (rbuffer
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
1558 for (i
= 0; i
< num_elems
; i
++) {
1559 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1561 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1563 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1566 if (sctx
->vertex_buffer
[vb
].buffer
.resource
== buf
) {
1567 sctx
->vertex_buffers_dirty
= true;
1573 /* Streamout buffers. (other internal buffers can't be invalidated) */
1574 if (rbuffer
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
1575 for (i
= SI_VS_STREAMOUT_BUF0
; i
<= SI_VS_STREAMOUT_BUF3
; i
++) {
1576 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1577 struct si_descriptors
*descs
=
1578 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1580 if (buffers
->buffers
[i
] != buf
)
1583 si_desc_reset_buffer_offset(ctx
, descs
->list
+ i
*4,
1585 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1587 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1588 rbuffer
, buffers
->shader_usage
,
1589 RADEON_PRIO_SHADER_RW_BUFFER
,
1592 /* Update the streamout state. */
1593 if (sctx
->streamout
.begin_emitted
)
1594 si_emit_streamout_end(sctx
);
1595 sctx
->streamout
.append_bitmask
=
1596 sctx
->streamout
.enabled_mask
;
1597 si_streamout_buffers_dirty(sctx
);
1601 /* Constant and shader buffers. */
1602 if (rbuffer
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1603 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1604 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1605 si_const_and_shader_buffer_descriptors_idx(shader
),
1606 u_bit_consecutive(SI_NUM_SHADER_BUFFERS
, SI_NUM_CONST_BUFFERS
),
1608 sctx
->const_and_shader_buffers
[shader
].shader_usage_constbuf
,
1609 sctx
->const_and_shader_buffers
[shader
].priority_constbuf
);
1612 if (rbuffer
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
1613 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1614 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1615 si_const_and_shader_buffer_descriptors_idx(shader
),
1616 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS
),
1618 sctx
->const_and_shader_buffers
[shader
].shader_usage
,
1619 sctx
->const_and_shader_buffers
[shader
].priority
);
1622 if (rbuffer
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
1623 /* Texture buffers - update bindings. */
1624 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1625 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1626 struct si_descriptors
*descs
=
1627 si_sampler_and_image_descriptors(sctx
, shader
);
1628 unsigned mask
= samplers
->enabled_mask
;
1631 unsigned i
= u_bit_scan(&mask
);
1632 if (samplers
->views
[i
]->texture
== buf
) {
1633 unsigned desc_slot
= si_get_sampler_slot(i
);
1635 si_desc_reset_buffer_offset(ctx
,
1639 sctx
->descriptors_dirty
|=
1640 1u << si_sampler_and_image_descriptors_idx(shader
);
1642 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1643 rbuffer
, RADEON_USAGE_READ
,
1644 RADEON_PRIO_SAMPLER_BUFFER
,
1652 if (rbuffer
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
1653 for (shader
= 0; shader
< SI_NUM_SHADERS
; ++shader
) {
1654 struct si_images
*images
= &sctx
->images
[shader
];
1655 struct si_descriptors
*descs
=
1656 si_sampler_and_image_descriptors(sctx
, shader
);
1657 unsigned mask
= images
->enabled_mask
;
1660 unsigned i
= u_bit_scan(&mask
);
1662 if (images
->views
[i
].resource
== buf
) {
1663 unsigned desc_slot
= si_get_image_slot(i
);
1665 if (images
->views
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
)
1666 si_mark_image_range_valid(&images
->views
[i
]);
1668 si_desc_reset_buffer_offset(
1669 ctx
, descs
->list
+ desc_slot
* 8 + 4,
1671 sctx
->descriptors_dirty
|=
1672 1u << si_sampler_and_image_descriptors_idx(shader
);
1674 radeon_add_to_buffer_list_check_mem(
1675 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1676 RADEON_USAGE_READWRITE
,
1677 RADEON_PRIO_SAMPLER_BUFFER
, true);
1683 /* Bindless texture handles */
1684 if (rbuffer
->texture_handle_allocated
) {
1685 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1687 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1688 struct si_texture_handle
*, tex_handle
) {
1689 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
1690 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1692 if (view
->texture
== buf
) {
1693 si_set_buf_desc_address(rbuffer
,
1696 desc_slot
* 16 + 4);
1698 (*tex_handle
)->desc_dirty
= true;
1699 sctx
->bindless_descriptors_dirty
= true;
1701 radeon_add_to_buffer_list_check_mem(
1702 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1704 RADEON_PRIO_SAMPLER_BUFFER
, true);
1709 /* Bindless image handles */
1710 if (rbuffer
->image_handle_allocated
) {
1711 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1713 util_dynarray_foreach(&sctx
->resident_img_handles
,
1714 struct si_image_handle
*, img_handle
) {
1715 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1716 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1718 if (view
->resource
== buf
) {
1719 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
1720 si_mark_image_range_valid(view
);
1722 si_set_buf_desc_address(rbuffer
,
1725 desc_slot
* 16 + 4);
1727 (*img_handle
)->desc_dirty
= true;
1728 sctx
->bindless_descriptors_dirty
= true;
1730 radeon_add_to_buffer_list_check_mem(
1731 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1732 RADEON_USAGE_READWRITE
,
1733 RADEON_PRIO_SAMPLER_BUFFER
, true);
1739 /* Reallocate a buffer a update all resource bindings where the buffer is
1742 * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
1743 * idle by discarding its contents. Apps usually tell us when to do this using
1744 * map_buffer flags, for example.
1746 static void si_invalidate_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
)
1748 struct si_context
*sctx
= (struct si_context
*)ctx
;
1749 struct r600_resource
*rbuffer
= r600_resource(buf
);
1750 uint64_t old_va
= rbuffer
->gpu_address
;
1752 /* Reallocate the buffer in the same pipe_resource. */
1753 si_alloc_resource(sctx
->screen
, rbuffer
);
1755 si_rebind_buffer(ctx
, buf
, old_va
);
1758 static void si_upload_bindless_descriptor(struct si_context
*sctx
,
1760 unsigned num_dwords
)
1762 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1763 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1764 unsigned desc_slot_offset
= desc_slot
* 16;
1768 data
= desc
->list
+ desc_slot_offset
;
1769 va
= desc
->gpu_address
+ desc_slot_offset
* 4;
1771 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + num_dwords
, 0));
1772 radeon_emit(cs
, S_370_DST_SEL(V_370_TC_L2
) |
1773 S_370_WR_CONFIRM(1) |
1774 S_370_ENGINE_SEL(V_370_ME
));
1775 radeon_emit(cs
, va
);
1776 radeon_emit(cs
, va
>> 32);
1777 radeon_emit_array(cs
, data
, num_dwords
);
1780 static void si_upload_bindless_descriptors(struct si_context
*sctx
)
1782 if (!sctx
->bindless_descriptors_dirty
)
1785 /* Wait for graphics/compute to be idle before updating the resident
1786 * descriptors directly in memory, in case the GPU is using them.
1788 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
1789 SI_CONTEXT_CS_PARTIAL_FLUSH
;
1790 si_emit_cache_flush(sctx
);
1792 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1793 struct si_texture_handle
*, tex_handle
) {
1794 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1796 if (!(*tex_handle
)->desc_dirty
)
1799 si_upload_bindless_descriptor(sctx
, desc_slot
, 16);
1800 (*tex_handle
)->desc_dirty
= false;
1803 util_dynarray_foreach(&sctx
->resident_img_handles
,
1804 struct si_image_handle
*, img_handle
) {
1805 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1807 if (!(*img_handle
)->desc_dirty
)
1810 si_upload_bindless_descriptor(sctx
, desc_slot
, 8);
1811 (*img_handle
)->desc_dirty
= false;
1814 /* Invalidate L1 because it doesn't know that L2 changed. */
1815 sctx
->b
.flags
|= SI_CONTEXT_INV_SMEM_L1
;
1816 si_emit_cache_flush(sctx
);
1818 sctx
->bindless_descriptors_dirty
= false;
1821 /* Update mutable image descriptor fields of all resident textures. */
1822 static void si_update_bindless_texture_descriptor(struct si_context
*sctx
,
1823 struct si_texture_handle
*tex_handle
)
1825 struct si_sampler_view
*sview
= (struct si_sampler_view
*)tex_handle
->view
;
1826 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1827 unsigned desc_slot_offset
= tex_handle
->desc_slot
* 16;
1828 uint32_t desc_list
[16];
1830 if (sview
->base
.texture
->target
== PIPE_BUFFER
)
1833 memcpy(desc_list
, desc
->list
+ desc_slot_offset
, sizeof(desc_list
));
1834 si_set_sampler_view_desc(sctx
, sview
, &tex_handle
->sstate
,
1835 desc
->list
+ desc_slot_offset
);
1837 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1838 sizeof(desc_list
))) {
1839 tex_handle
->desc_dirty
= true;
1840 sctx
->bindless_descriptors_dirty
= true;
1844 static void si_update_bindless_image_descriptor(struct si_context
*sctx
,
1845 struct si_image_handle
*img_handle
)
1847 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1848 unsigned desc_slot_offset
= img_handle
->desc_slot
* 16;
1849 struct pipe_image_view
*view
= &img_handle
->view
;
1850 uint32_t desc_list
[8];
1852 if (view
->resource
->target
== PIPE_BUFFER
)
1855 memcpy(desc_list
, desc
->list
+ desc_slot_offset
,
1857 si_set_shader_image_desc(sctx
, view
, true,
1858 desc
->list
+ desc_slot_offset
);
1860 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1861 sizeof(desc_list
))) {
1862 img_handle
->desc_dirty
= true;
1863 sctx
->bindless_descriptors_dirty
= true;
1867 static void si_update_all_resident_texture_descriptors(struct si_context
*sctx
)
1869 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1870 struct si_texture_handle
*, tex_handle
) {
1871 si_update_bindless_texture_descriptor(sctx
, *tex_handle
);
1874 util_dynarray_foreach(&sctx
->resident_img_handles
,
1875 struct si_image_handle
*, img_handle
) {
1876 si_update_bindless_image_descriptor(sctx
, *img_handle
);
1879 si_upload_bindless_descriptors(sctx
);
1882 /* Update mutable image descriptor fields of all bound textures. */
1883 void si_update_all_texture_descriptors(struct si_context
*sctx
)
1887 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1888 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1889 struct si_images
*images
= &sctx
->images
[shader
];
1893 mask
= images
->enabled_mask
;
1895 unsigned i
= u_bit_scan(&mask
);
1896 struct pipe_image_view
*view
= &images
->views
[i
];
1898 if (!view
->resource
||
1899 view
->resource
->target
== PIPE_BUFFER
)
1902 si_set_shader_image(sctx
, shader
, i
, view
, true);
1905 /* Sampler views. */
1906 mask
= samplers
->enabled_mask
;
1908 unsigned i
= u_bit_scan(&mask
);
1909 struct pipe_sampler_view
*view
= samplers
->views
[i
];
1913 view
->texture
->target
== PIPE_BUFFER
)
1916 si_set_sampler_view(sctx
, shader
, i
,
1917 samplers
->views
[i
], true);
1920 si_update_shader_needs_decompress_mask(sctx
, shader
);
1923 si_update_all_resident_texture_descriptors(sctx
);
1926 /* SHADER USER DATA */
1928 static void si_mark_shader_pointers_dirty(struct si_context
*sctx
,
1931 sctx
->shader_pointers_dirty
|=
1932 u_bit_consecutive(SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
,
1933 SI_NUM_SHADER_DESCS
);
1935 if (shader
== PIPE_SHADER_VERTEX
)
1936 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
1938 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
1941 static void si_shader_pointers_begin_new_cs(struct si_context
*sctx
)
1943 sctx
->shader_pointers_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
1944 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
1945 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
1946 sctx
->graphics_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
1947 sctx
->compute_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
1950 /* Set a base register address for user data constants in the given shader.
1951 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
1953 static void si_set_user_data_base(struct si_context
*sctx
,
1954 unsigned shader
, uint32_t new_base
)
1956 uint32_t *base
= &sctx
->shader_pointers
.sh_base
[shader
];
1958 if (*base
!= new_base
) {
1962 si_mark_shader_pointers_dirty(sctx
, shader
);
1964 if (shader
== PIPE_SHADER_VERTEX
)
1965 sctx
->last_vs_state
= ~0;
1970 /* This must be called when these shaders are changed from non-NULL to NULL
1973 * - tessellation control shader
1974 * - tessellation evaluation shader
1976 void si_shader_change_notify(struct si_context
*sctx
)
1978 /* VS can be bound as VS, ES, or LS. */
1979 if (sctx
->tes_shader
.cso
) {
1980 if (sctx
->b
.chip_class
>= GFX9
) {
1981 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1982 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
1984 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1985 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
1987 } else if (sctx
->gs_shader
.cso
) {
1988 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1989 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
1991 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1992 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1995 /* TES can be bound as ES, VS, or not bound. */
1996 if (sctx
->tes_shader
.cso
) {
1997 if (sctx
->gs_shader
.cso
)
1998 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
1999 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2001 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
2002 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2004 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, 0);
2008 static void si_emit_shader_pointer_head(struct radeon_winsys_cs
*cs
,
2010 unsigned pointer_count
)
2012 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
* (HAVE_32BIT_POINTERS
? 1 : 2), 0));
2013 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
2016 static void si_emit_shader_pointer_body(struct si_screen
*sscreen
,
2017 struct radeon_winsys_cs
*cs
,
2020 radeon_emit(cs
, va
);
2022 if (HAVE_32BIT_POINTERS
)
2023 assert(va
== 0 || (va
>> 32) == sscreen
->info
.address32_hi
);
2025 radeon_emit(cs
, va
>> 32);
2028 static void si_emit_shader_pointer(struct si_context
*sctx
,
2029 struct si_descriptors
*desc
,
2032 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2033 unsigned sh_offset
= sh_base
+ desc
->shader_userdata_offset
;
2035 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2036 si_emit_shader_pointer_body(sctx
->screen
, cs
, desc
->gpu_address
);
2039 static void si_emit_consecutive_shader_pointers(struct si_context
*sctx
,
2040 unsigned pointer_mask
,
2046 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2047 unsigned mask
= sctx
->shader_pointers_dirty
& pointer_mask
;
2051 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
2053 struct si_descriptors
*descs
= &sctx
->descriptors
[start
];
2054 unsigned sh_offset
= sh_base
+ descs
->shader_userdata_offset
;
2056 si_emit_shader_pointer_head(cs
, sh_offset
, count
);
2057 for (int i
= 0; i
< count
; i
++)
2058 si_emit_shader_pointer_body(sctx
->screen
, cs
,
2059 descs
[i
].gpu_address
);
2063 static void si_emit_disjoint_shader_pointers(struct si_context
*sctx
,
2064 unsigned pointer_mask
,
2070 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2071 unsigned mask
= sctx
->shader_pointers_dirty
& pointer_mask
;
2074 struct si_descriptors
*descs
= &sctx
->descriptors
[u_bit_scan(&mask
)];
2075 unsigned sh_offset
= sh_base
+ descs
->shader_userdata_offset
;
2077 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2078 si_emit_shader_pointer_body(sctx
->screen
, cs
, descs
->gpu_address
);
2082 static void si_emit_global_shader_pointers(struct si_context
*sctx
,
2083 struct si_descriptors
*descs
)
2085 if (sctx
->b
.chip_class
== GFX9
) {
2086 /* Broadcast it to all shader stages. */
2087 si_emit_shader_pointer(sctx
, descs
,
2088 R_00B530_SPI_SHADER_USER_DATA_COMMON_0
);
2092 si_emit_shader_pointer(sctx
, descs
,
2093 R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2094 si_emit_shader_pointer(sctx
, descs
,
2095 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2096 si_emit_shader_pointer(sctx
, descs
,
2097 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2098 si_emit_shader_pointer(sctx
, descs
,
2099 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2100 si_emit_shader_pointer(sctx
, descs
,
2101 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2102 si_emit_shader_pointer(sctx
, descs
,
2103 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2106 void si_emit_graphics_shader_pointers(struct si_context
*sctx
,
2107 struct r600_atom
*atom
)
2109 uint32_t *sh_base
= sctx
->shader_pointers
.sh_base
;
2111 if (sctx
->shader_pointers_dirty
& (1 << SI_DESCS_RW_BUFFERS
)) {
2112 si_emit_global_shader_pointers(sctx
,
2113 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2116 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(VERTEX
),
2117 sh_base
[PIPE_SHADER_VERTEX
]);
2118 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_EVAL
),
2119 sh_base
[PIPE_SHADER_TESS_EVAL
]);
2120 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(FRAGMENT
),
2121 sh_base
[PIPE_SHADER_FRAGMENT
]);
2122 if (HAVE_32BIT_POINTERS
|| sctx
->b
.chip_class
<= VI
) {
2123 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_CTRL
),
2124 sh_base
[PIPE_SHADER_TESS_CTRL
]);
2125 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(GEOMETRY
),
2126 sh_base
[PIPE_SHADER_GEOMETRY
]);
2128 si_emit_disjoint_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_CTRL
),
2129 sh_base
[PIPE_SHADER_TESS_CTRL
]);
2130 si_emit_disjoint_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(GEOMETRY
),
2131 sh_base
[PIPE_SHADER_GEOMETRY
]);
2134 sctx
->shader_pointers_dirty
&=
2135 ~u_bit_consecutive(SI_DESCS_RW_BUFFERS
, SI_DESCS_FIRST_COMPUTE
);
2137 if (sctx
->vertex_buffer_pointer_dirty
) {
2138 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2140 /* Find the location of the VB descriptor pointer. */
2141 /* TODO: In the future, the pointer will be packed in unused
2142 * bits of the first 2 VB descriptors. */
2143 unsigned sh_dw_offset
= SI_VS_NUM_USER_SGPR
;
2144 if (sctx
->b
.chip_class
>= GFX9
) {
2145 if (sctx
->tes_shader
.cso
)
2146 sh_dw_offset
= GFX9_TCS_NUM_USER_SGPR
;
2147 else if (sctx
->gs_shader
.cso
)
2148 sh_dw_offset
= GFX9_VSGS_NUM_USER_SGPR
;
2151 unsigned sh_offset
= sh_base
[PIPE_SHADER_VERTEX
] + sh_dw_offset
* 4;
2152 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2153 si_emit_shader_pointer_body(sctx
->screen
, cs
,
2154 sctx
->vb_descriptors_buffer
->gpu_address
+
2155 sctx
->vb_descriptors_offset
);
2156 sctx
->vertex_buffer_pointer_dirty
= false;
2159 if (sctx
->graphics_bindless_pointer_dirty
) {
2160 si_emit_global_shader_pointers(sctx
,
2161 &sctx
->bindless_descriptors
);
2162 sctx
->graphics_bindless_pointer_dirty
= false;
2166 void si_emit_compute_shader_pointers(struct si_context
*sctx
)
2168 unsigned base
= R_00B900_COMPUTE_USER_DATA_0
;
2170 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(COMPUTE
),
2171 R_00B900_COMPUTE_USER_DATA_0
);
2172 sctx
->shader_pointers_dirty
&= ~SI_DESCS_SHADER_MASK(COMPUTE
);
2174 if (sctx
->compute_bindless_pointer_dirty
) {
2175 si_emit_shader_pointer(sctx
, &sctx
->bindless_descriptors
, base
);
2176 sctx
->compute_bindless_pointer_dirty
= false;
2182 static void si_init_bindless_descriptors(struct si_context
*sctx
,
2183 struct si_descriptors
*desc
,
2184 short shader_userdata_rel_index
,
2185 unsigned num_elements
)
2187 MAYBE_UNUSED
unsigned desc_slot
;
2189 si_init_descriptors(desc
, shader_userdata_rel_index
, 16, num_elements
);
2190 sctx
->bindless_descriptors
.num_active_slots
= num_elements
;
2192 /* The first bindless descriptor is stored at slot 1, because 0 is not
2193 * considered to be a valid handle.
2195 sctx
->num_bindless_descriptors
= 1;
2197 /* Track which bindless slots are used (or not). */
2198 util_idalloc_init(&sctx
->bindless_used_slots
);
2199 util_idalloc_resize(&sctx
->bindless_used_slots
, num_elements
);
2201 /* Reserve slot 0 because it's an invalid handle for bindless. */
2202 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2203 assert(desc_slot
== 0);
2206 static void si_release_bindless_descriptors(struct si_context
*sctx
)
2208 si_release_descriptors(&sctx
->bindless_descriptors
);
2209 util_idalloc_fini(&sctx
->bindless_used_slots
);
2212 static unsigned si_get_first_free_bindless_slot(struct si_context
*sctx
)
2214 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2217 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2218 if (desc_slot
>= desc
->num_elements
) {
2219 /* The array of bindless descriptors is full, resize it. */
2220 unsigned slot_size
= desc
->element_dw_size
* 4;
2221 unsigned new_num_elements
= desc
->num_elements
* 2;
2223 desc
->list
= REALLOC(desc
->list
, desc
->num_elements
* slot_size
,
2224 new_num_elements
* slot_size
);
2225 desc
->num_elements
= new_num_elements
;
2226 desc
->num_active_slots
= new_num_elements
;
2234 si_create_bindless_descriptor(struct si_context
*sctx
, uint32_t *desc_list
,
2237 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2238 unsigned desc_slot
, desc_slot_offset
;
2240 /* Find a free slot. */
2241 desc_slot
= si_get_first_free_bindless_slot(sctx
);
2243 /* For simplicity, sampler and image bindless descriptors use fixed
2244 * 16-dword slots for now. Image descriptors only need 8-dword but this
2245 * doesn't really matter because no real apps use image handles.
2247 desc_slot_offset
= desc_slot
* 16;
2249 /* Copy the descriptor into the array. */
2250 memcpy(desc
->list
+ desc_slot_offset
, desc_list
, size
);
2252 /* Re-upload the whole array of bindless descriptors into a new buffer.
2254 if (!si_upload_descriptors(sctx
, desc
))
2257 /* Make sure to re-emit the shader pointers for all stages. */
2258 sctx
->graphics_bindless_pointer_dirty
= true;
2259 sctx
->compute_bindless_pointer_dirty
= true;
2264 static void si_update_bindless_buffer_descriptor(struct si_context
*sctx
,
2266 struct pipe_resource
*resource
,
2270 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2271 struct r600_resource
*buf
= r600_resource(resource
);
2272 unsigned desc_slot_offset
= desc_slot
* 16;
2273 uint32_t *desc_list
= desc
->list
+ desc_slot_offset
+ 4;
2274 uint64_t old_desc_va
;
2276 assert(resource
->target
== PIPE_BUFFER
);
2278 /* Retrieve the old buffer addr from the descriptor. */
2279 old_desc_va
= si_desc_extract_buffer_address(desc_list
);
2281 if (old_desc_va
!= buf
->gpu_address
+ offset
) {
2282 /* The buffer has been invalidated when the handle wasn't
2283 * resident, update the descriptor and the dirty flag.
2285 si_set_buf_desc_address(buf
, offset
, &desc_list
[0]);
2291 static uint64_t si_create_texture_handle(struct pipe_context
*ctx
,
2292 struct pipe_sampler_view
*view
,
2293 const struct pipe_sampler_state
*state
)
2295 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
2296 struct si_context
*sctx
= (struct si_context
*)ctx
;
2297 struct si_texture_handle
*tex_handle
;
2298 struct si_sampler_state
*sstate
;
2299 uint32_t desc_list
[16];
2302 tex_handle
= CALLOC_STRUCT(si_texture_handle
);
2306 memset(desc_list
, 0, sizeof(desc_list
));
2307 si_init_descriptor_list(&desc_list
[0], 16, 1, null_texture_descriptor
);
2309 sstate
= ctx
->create_sampler_state(ctx
, state
);
2315 si_set_sampler_view_desc(sctx
, sview
, sstate
, &desc_list
[0]);
2316 memcpy(&tex_handle
->sstate
, sstate
, sizeof(*sstate
));
2317 ctx
->delete_sampler_state(ctx
, sstate
);
2319 tex_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2321 if (!tex_handle
->desc_slot
) {
2326 handle
= tex_handle
->desc_slot
;
2328 if (!_mesa_hash_table_insert(sctx
->tex_handles
,
2329 (void *)(uintptr_t)handle
,
2335 pipe_sampler_view_reference(&tex_handle
->view
, view
);
2337 r600_resource(sview
->base
.texture
)->texture_handle_allocated
= true;
2342 static void si_delete_texture_handle(struct pipe_context
*ctx
, uint64_t handle
)
2344 struct si_context
*sctx
= (struct si_context
*)ctx
;
2345 struct si_texture_handle
*tex_handle
;
2346 struct hash_entry
*entry
;
2348 entry
= _mesa_hash_table_search(sctx
->tex_handles
,
2349 (void *)(uintptr_t)handle
);
2353 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2355 /* Allow this descriptor slot to be re-used. */
2356 util_idalloc_free(&sctx
->bindless_used_slots
, tex_handle
->desc_slot
);
2358 pipe_sampler_view_reference(&tex_handle
->view
, NULL
);
2359 _mesa_hash_table_remove(sctx
->tex_handles
, entry
);
2363 static void si_make_texture_handle_resident(struct pipe_context
*ctx
,
2364 uint64_t handle
, bool resident
)
2366 struct si_context
*sctx
= (struct si_context
*)ctx
;
2367 struct si_texture_handle
*tex_handle
;
2368 struct si_sampler_view
*sview
;
2369 struct hash_entry
*entry
;
2371 entry
= _mesa_hash_table_search(sctx
->tex_handles
,
2372 (void *)(uintptr_t)handle
);
2376 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2377 sview
= (struct si_sampler_view
*)tex_handle
->view
;
2380 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2381 struct r600_texture
*rtex
=
2382 (struct r600_texture
*)sview
->base
.texture
;
2384 if (depth_needs_decompression(rtex
)) {
2385 util_dynarray_append(
2386 &sctx
->resident_tex_needs_depth_decompress
,
2387 struct si_texture_handle
*,
2391 if (color_needs_decompression(rtex
)) {
2392 util_dynarray_append(
2393 &sctx
->resident_tex_needs_color_decompress
,
2394 struct si_texture_handle
*,
2398 if (rtex
->dcc_offset
&&
2399 p_atomic_read(&rtex
->framebuffers_bound
))
2400 sctx
->need_check_render_feedback
= true;
2402 si_update_bindless_texture_descriptor(sctx
, tex_handle
);
2404 si_update_bindless_buffer_descriptor(sctx
,
2405 tex_handle
->desc_slot
,
2406 sview
->base
.texture
,
2407 sview
->base
.u
.buf
.offset
,
2408 &tex_handle
->desc_dirty
);
2411 /* Re-upload the descriptor if it has been updated while it
2414 if (tex_handle
->desc_dirty
)
2415 sctx
->bindless_descriptors_dirty
= true;
2417 /* Add the texture handle to the per-context list. */
2418 util_dynarray_append(&sctx
->resident_tex_handles
,
2419 struct si_texture_handle
*, tex_handle
);
2421 /* Add the buffers to the current CS in case si_begin_new_cs()
2422 * is not going to be called.
2424 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2426 sview
->is_stencil_sampler
, false);
2428 /* Remove the texture handle from the per-context list. */
2429 util_dynarray_delete_unordered(&sctx
->resident_tex_handles
,
2430 struct si_texture_handle
*,
2433 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2434 util_dynarray_delete_unordered(
2435 &sctx
->resident_tex_needs_depth_decompress
,
2436 struct si_texture_handle
*, tex_handle
);
2438 util_dynarray_delete_unordered(
2439 &sctx
->resident_tex_needs_color_decompress
,
2440 struct si_texture_handle
*, tex_handle
);
2445 static uint64_t si_create_image_handle(struct pipe_context
*ctx
,
2446 const struct pipe_image_view
*view
)
2448 struct si_context
*sctx
= (struct si_context
*)ctx
;
2449 struct si_image_handle
*img_handle
;
2450 uint32_t desc_list
[8];
2453 if (!view
|| !view
->resource
)
2456 img_handle
= CALLOC_STRUCT(si_image_handle
);
2460 memset(desc_list
, 0, sizeof(desc_list
));
2461 si_init_descriptor_list(&desc_list
[0], 8, 1, null_image_descriptor
);
2463 si_set_shader_image_desc(sctx
, view
, false, &desc_list
[0]);
2465 img_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2467 if (!img_handle
->desc_slot
) {
2472 handle
= img_handle
->desc_slot
;
2474 if (!_mesa_hash_table_insert(sctx
->img_handles
,
2475 (void *)(uintptr_t)handle
,
2481 util_copy_image_view(&img_handle
->view
, view
);
2483 r600_resource(view
->resource
)->image_handle_allocated
= true;
2488 static void si_delete_image_handle(struct pipe_context
*ctx
, uint64_t handle
)
2490 struct si_context
*sctx
= (struct si_context
*)ctx
;
2491 struct si_image_handle
*img_handle
;
2492 struct hash_entry
*entry
;
2494 entry
= _mesa_hash_table_search(sctx
->img_handles
,
2495 (void *)(uintptr_t)handle
);
2499 img_handle
= (struct si_image_handle
*)entry
->data
;
2501 util_copy_image_view(&img_handle
->view
, NULL
);
2502 _mesa_hash_table_remove(sctx
->img_handles
, entry
);
2506 static void si_make_image_handle_resident(struct pipe_context
*ctx
,
2507 uint64_t handle
, unsigned access
,
2510 struct si_context
*sctx
= (struct si_context
*)ctx
;
2511 struct si_image_handle
*img_handle
;
2512 struct pipe_image_view
*view
;
2513 struct r600_resource
*res
;
2514 struct hash_entry
*entry
;
2516 entry
= _mesa_hash_table_search(sctx
->img_handles
,
2517 (void *)(uintptr_t)handle
);
2521 img_handle
= (struct si_image_handle
*)entry
->data
;
2522 view
= &img_handle
->view
;
2523 res
= (struct r600_resource
*)view
->resource
;
2526 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2527 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
2528 unsigned level
= view
->u
.tex
.level
;
2530 if (color_needs_decompression(rtex
)) {
2531 util_dynarray_append(
2532 &sctx
->resident_img_needs_color_decompress
,
2533 struct si_image_handle
*,
2537 if (vi_dcc_enabled(rtex
, level
) &&
2538 p_atomic_read(&rtex
->framebuffers_bound
))
2539 sctx
->need_check_render_feedback
= true;
2541 si_update_bindless_image_descriptor(sctx
, img_handle
);
2543 si_update_bindless_buffer_descriptor(sctx
,
2544 img_handle
->desc_slot
,
2547 &img_handle
->desc_dirty
);
2550 /* Re-upload the descriptor if it has been updated while it
2553 if (img_handle
->desc_dirty
)
2554 sctx
->bindless_descriptors_dirty
= true;
2556 /* Add the image handle to the per-context list. */
2557 util_dynarray_append(&sctx
->resident_img_handles
,
2558 struct si_image_handle
*, img_handle
);
2560 /* Add the buffers to the current CS in case si_begin_new_cs()
2561 * is not going to be called.
2563 si_sampler_view_add_buffer(sctx
, view
->resource
,
2564 (access
& PIPE_IMAGE_ACCESS_WRITE
) ?
2565 RADEON_USAGE_READWRITE
:
2566 RADEON_USAGE_READ
, false, false);
2568 /* Remove the image handle from the per-context list. */
2569 util_dynarray_delete_unordered(&sctx
->resident_img_handles
,
2570 struct si_image_handle
*,
2573 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2574 util_dynarray_delete_unordered(
2575 &sctx
->resident_img_needs_color_decompress
,
2576 struct si_image_handle
*,
2583 void si_all_resident_buffers_begin_new_cs(struct si_context
*sctx
)
2585 unsigned num_resident_tex_handles
, num_resident_img_handles
;
2587 num_resident_tex_handles
= sctx
->resident_tex_handles
.size
/
2588 sizeof(struct si_texture_handle
*);
2589 num_resident_img_handles
= sctx
->resident_img_handles
.size
/
2590 sizeof(struct si_image_handle
*);
2592 /* Add all resident texture handles. */
2593 util_dynarray_foreach(&sctx
->resident_tex_handles
,
2594 struct si_texture_handle
*, tex_handle
) {
2595 struct si_sampler_view
*sview
=
2596 (struct si_sampler_view
*)(*tex_handle
)->view
;
2598 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2600 sview
->is_stencil_sampler
, false);
2603 /* Add all resident image handles. */
2604 util_dynarray_foreach(&sctx
->resident_img_handles
,
2605 struct si_image_handle
*, img_handle
) {
2606 struct pipe_image_view
*view
= &(*img_handle
)->view
;
2608 si_sampler_view_add_buffer(sctx
, view
->resource
,
2609 RADEON_USAGE_READWRITE
,
2613 sctx
->b
.num_resident_handles
+= num_resident_tex_handles
+
2614 num_resident_img_handles
;
2617 /* INIT/DEINIT/UPLOAD */
2619 void si_init_all_descriptors(struct si_context
*sctx
)
2623 #if !HAVE_32BIT_POINTERS
2624 STATIC_ASSERT(GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES
% 2 == 0);
2627 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2628 bool is_2nd
= sctx
->b
.chip_class
>= GFX9
&&
2629 (i
== PIPE_SHADER_TESS_CTRL
||
2630 i
== PIPE_SHADER_GEOMETRY
);
2631 unsigned num_sampler_slots
= SI_NUM_IMAGES
/ 2 + SI_NUM_SAMPLERS
;
2632 unsigned num_buffer_slots
= SI_NUM_SHADER_BUFFERS
+ SI_NUM_CONST_BUFFERS
;
2634 struct si_descriptors
*desc
;
2637 if (i
== PIPE_SHADER_TESS_CTRL
) {
2638 rel_dw_offset
= (R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
-
2639 R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2640 } else { /* PIPE_SHADER_GEOMETRY */
2641 rel_dw_offset
= (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
-
2642 R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2645 rel_dw_offset
= SI_SGPR_CONST_AND_SHADER_BUFFERS
;
2647 desc
= si_const_and_shader_buffer_descriptors(sctx
, i
);
2648 si_init_buffer_resources(&sctx
->const_and_shader_buffers
[i
], desc
,
2649 num_buffer_slots
, rel_dw_offset
,
2650 RADEON_USAGE_READWRITE
,
2652 RADEON_PRIO_SHADER_RW_BUFFER
,
2653 RADEON_PRIO_CONST_BUFFER
);
2654 desc
->slot_index_to_bind_directly
= si_get_constbuf_slot(0);
2657 #if HAVE_32BIT_POINTERS
2658 if (i
== PIPE_SHADER_TESS_CTRL
) {
2659 rel_dw_offset
= (R_00B40C_SPI_SHADER_USER_DATA_ADDR_HI_HS
-
2660 R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2661 } else { /* PIPE_SHADER_GEOMETRY */
2662 rel_dw_offset
= (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS
-
2663 R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2666 rel_dw_offset
= GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES
;
2669 rel_dw_offset
= SI_SGPR_SAMPLERS_AND_IMAGES
;
2672 desc
= si_sampler_and_image_descriptors(sctx
, i
);
2673 si_init_descriptors(desc
, rel_dw_offset
, 16, num_sampler_slots
);
2676 for (j
= 0; j
< SI_NUM_IMAGES
; j
++)
2677 memcpy(desc
->list
+ j
* 8, null_image_descriptor
, 8 * 4);
2678 for (; j
< SI_NUM_IMAGES
+ SI_NUM_SAMPLERS
* 2; j
++)
2679 memcpy(desc
->list
+ j
* 8, null_texture_descriptor
, 8 * 4);
2682 si_init_buffer_resources(&sctx
->rw_buffers
,
2683 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
],
2684 SI_NUM_RW_BUFFERS
, SI_SGPR_RW_BUFFERS
,
2685 /* The second set of usage/priority is used by
2686 * const buffers in RW buffer slots. */
2687 RADEON_USAGE_READWRITE
, RADEON_USAGE_READ
,
2688 RADEON_PRIO_SHADER_RINGS
, RADEON_PRIO_CONST_BUFFER
);
2689 sctx
->descriptors
[SI_DESCS_RW_BUFFERS
].num_active_slots
= SI_NUM_RW_BUFFERS
;
2691 /* Initialize an array of 1024 bindless descriptors, when the limit is
2692 * reached, just make it larger and re-upload the whole array.
2694 si_init_bindless_descriptors(sctx
, &sctx
->bindless_descriptors
,
2695 SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES
,
2698 sctx
->descriptors_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2700 /* Set pipe_context functions. */
2701 sctx
->b
.b
.bind_sampler_states
= si_bind_sampler_states
;
2702 sctx
->b
.b
.set_shader_images
= si_set_shader_images
;
2703 sctx
->b
.b
.set_constant_buffer
= si_pipe_set_constant_buffer
;
2704 sctx
->b
.b
.set_polygon_stipple
= si_set_polygon_stipple
;
2705 sctx
->b
.b
.set_shader_buffers
= si_set_shader_buffers
;
2706 sctx
->b
.b
.set_sampler_views
= si_set_sampler_views
;
2707 sctx
->b
.b
.create_texture_handle
= si_create_texture_handle
;
2708 sctx
->b
.b
.delete_texture_handle
= si_delete_texture_handle
;
2709 sctx
->b
.b
.make_texture_handle_resident
= si_make_texture_handle_resident
;
2710 sctx
->b
.b
.create_image_handle
= si_create_image_handle
;
2711 sctx
->b
.b
.delete_image_handle
= si_delete_image_handle
;
2712 sctx
->b
.b
.make_image_handle_resident
= si_make_image_handle_resident
;
2713 sctx
->b
.invalidate_buffer
= si_invalidate_buffer
;
2714 sctx
->b
.rebind_buffer
= si_rebind_buffer
;
2716 /* Shader user data. */
2717 si_init_atom(sctx
, &sctx
->shader_pointers
.atom
, &sctx
->atoms
.s
.shader_pointers
,
2718 si_emit_graphics_shader_pointers
);
2720 /* Set default and immutable mappings. */
2721 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2723 if (sctx
->b
.chip_class
>= GFX9
) {
2724 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2725 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2726 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2727 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2729 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2730 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2731 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2732 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2734 si_set_user_data_base(sctx
, PIPE_SHADER_FRAGMENT
, R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2737 static bool si_upload_shader_descriptors(struct si_context
*sctx
, unsigned mask
)
2739 unsigned dirty
= sctx
->descriptors_dirty
& mask
;
2741 /* Assume nothing will go wrong: */
2742 sctx
->shader_pointers_dirty
|= dirty
;
2745 unsigned i
= u_bit_scan(&dirty
);
2747 if (!si_upload_descriptors(sctx
, &sctx
->descriptors
[i
]))
2751 sctx
->descriptors_dirty
&= ~mask
;
2753 si_upload_bindless_descriptors(sctx
);
2758 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
)
2760 const unsigned mask
= u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE
);
2761 return si_upload_shader_descriptors(sctx
, mask
);
2764 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
)
2766 /* Does not update rw_buffers as that is not needed for compute shaders
2767 * and the input buffer is using the same SGPR's anyway.
2769 const unsigned mask
= u_bit_consecutive(SI_DESCS_FIRST_COMPUTE
,
2770 SI_NUM_DESCS
- SI_DESCS_FIRST_COMPUTE
);
2771 return si_upload_shader_descriptors(sctx
, mask
);
2774 void si_release_all_descriptors(struct si_context
*sctx
)
2778 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2779 si_release_buffer_resources(&sctx
->const_and_shader_buffers
[i
],
2780 si_const_and_shader_buffer_descriptors(sctx
, i
));
2781 si_release_sampler_views(&sctx
->samplers
[i
]);
2782 si_release_image_views(&sctx
->images
[i
]);
2784 si_release_buffer_resources(&sctx
->rw_buffers
,
2785 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2786 for (i
= 0; i
< SI_NUM_VERTEX_BUFFERS
; i
++)
2787 pipe_vertex_buffer_unreference(&sctx
->vertex_buffer
[i
]);
2789 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2790 si_release_descriptors(&sctx
->descriptors
[i
]);
2792 r600_resource_reference(&sctx
->vb_descriptors_buffer
, NULL
);
2793 sctx
->vb_descriptors_gpu_list
= NULL
; /* points into a mapped buffer */
2795 si_release_bindless_descriptors(sctx
);
2798 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
)
2802 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2803 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[i
]);
2804 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[i
]);
2805 si_image_views_begin_new_cs(sctx
, &sctx
->images
[i
]);
2807 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2808 si_vertex_buffers_begin_new_cs(sctx
);
2810 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2811 si_descriptors_begin_new_cs(sctx
, &sctx
->descriptors
[i
]);
2812 si_descriptors_begin_new_cs(sctx
, &sctx
->bindless_descriptors
);
2814 si_shader_pointers_begin_new_cs(sctx
);
2817 void si_set_active_descriptors(struct si_context
*sctx
, unsigned desc_idx
,
2818 uint64_t new_active_mask
)
2820 struct si_descriptors
*desc
= &sctx
->descriptors
[desc_idx
];
2822 /* Ignore no-op updates and updates that disable all slots. */
2823 if (!new_active_mask
||
2824 new_active_mask
== u_bit_consecutive64(desc
->first_active_slot
,
2825 desc
->num_active_slots
))
2829 u_bit_scan_consecutive_range64(&new_active_mask
, &first
, &count
);
2830 assert(new_active_mask
== 0);
2832 /* Upload/dump descriptors if slots are being enabled. */
2833 if (first
< desc
->first_active_slot
||
2834 first
+ count
> desc
->first_active_slot
+ desc
->num_active_slots
)
2835 sctx
->descriptors_dirty
|= 1u << desc_idx
;
2837 desc
->first_active_slot
= first
;
2838 desc
->num_active_slots
= count
;
2841 void si_set_active_descriptors_for_shader(struct si_context
*sctx
,
2842 struct si_shader_selector
*sel
)
2847 si_set_active_descriptors(sctx
,
2848 si_const_and_shader_buffer_descriptors_idx(sel
->type
),
2849 sel
->active_const_and_shader_buffers
);
2850 si_set_active_descriptors(sctx
,
2851 si_sampler_and_image_descriptors_idx(sel
->type
),
2852 sel
->active_samplers_and_images
);