2 * Copyright 2013 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 /* Resource binding slots and sampler states (each described with 8 or
26 * 4 dwords) are stored in lists in memory which is accessed by shaders
27 * using scalar load instructions.
29 * This file is responsible for managing such lists. It keeps a copy of all
30 * descriptors in CPU memory and re-uploads a whole list if some slots have
33 * This code is also reponsible for updating shader pointers to those lists.
35 * Note that CP DMA can't be used for updating the lists, because a GPU hang
36 * could leave the list in a mid-IB state and the next IB would get wrong
37 * descriptors and the whole context would be unusable at that point.
38 * (Note: The register shadowing can't be used due to the same reason)
40 * Also, uploading descriptors to newly allocated memory doesn't require
44 * Possible scenarios for one 16 dword image+sampler slot:
46 * | Image | w/ FMASK | Buffer | NULL
47 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
48 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
49 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
50 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
52 * FMASK implies MSAA, therefore no sampler state.
53 * Sampler states are never unbound except when FMASK is bound.
60 #include "util/hash_table.h"
61 #include "util/u_idalloc.h"
62 #include "util/u_format.h"
63 #include "util/u_memory.h"
64 #include "util/u_upload_mgr.h"
67 /* NULL image and buffer descriptor for textures (alpha = 1) and images
70 * For images, all fields must be zero except for the swizzle, which
71 * supports arbitrary combinations of 0s and 1s. The texture type must be
72 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
74 * For buffers, all fields must be zero. If they are not, the hw hangs.
76 * This is the only reason why the buffer descriptor must be in words [4:7].
78 static uint32_t null_texture_descriptor
[8] = {
82 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1
) |
83 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
84 /* the rest must contain zeros, which is also used by the buffer
88 static uint32_t null_image_descriptor
[8] = {
92 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
93 /* the rest must contain zeros, which is also used by the buffer
97 static uint64_t si_desc_extract_buffer_address(const uint32_t *desc
)
99 uint64_t va
= desc
[0] |
100 ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc
[1]) << 32);
102 /* Sign-extend the 48-bit address. */
104 va
= (int64_t)va
>> 16;
108 static void si_init_descriptor_list(uint32_t *desc_list
,
109 unsigned element_dw_size
,
110 unsigned num_elements
,
111 const uint32_t *null_descriptor
)
115 /* Initialize the array to NULL descriptors if the element size is 8. */
116 if (null_descriptor
) {
117 assert(element_dw_size
% 8 == 0);
118 for (i
= 0; i
< num_elements
* element_dw_size
/ 8; i
++)
119 memcpy(desc_list
+ i
* 8, null_descriptor
, 8 * 4);
123 static void si_init_descriptors(struct si_descriptors
*desc
,
124 short shader_userdata_rel_index
,
125 unsigned element_dw_size
,
126 unsigned num_elements
)
128 desc
->list
= CALLOC(num_elements
, element_dw_size
* 4);
129 desc
->element_dw_size
= element_dw_size
;
130 desc
->num_elements
= num_elements
;
131 desc
->shader_userdata_offset
= shader_userdata_rel_index
* 4;
132 desc
->slot_index_to_bind_directly
= -1;
135 static void si_release_descriptors(struct si_descriptors
*desc
)
137 si_resource_reference(&desc
->buffer
, NULL
);
141 static bool si_upload_descriptors(struct si_context
*sctx
,
142 struct si_descriptors
*desc
)
144 unsigned slot_size
= desc
->element_dw_size
* 4;
145 unsigned first_slot_offset
= desc
->first_active_slot
* slot_size
;
146 unsigned upload_size
= desc
->num_active_slots
* slot_size
;
148 /* Skip the upload if no shader is using the descriptors. dirty_mask
149 * will stay dirty and the descriptors will be uploaded when there is
150 * a shader using them.
155 /* If there is just one active descriptor, bind it directly. */
156 if ((int)desc
->first_active_slot
== desc
->slot_index_to_bind_directly
&&
157 desc
->num_active_slots
== 1) {
158 uint32_t *descriptor
= &desc
->list
[desc
->slot_index_to_bind_directly
*
159 desc
->element_dw_size
];
161 /* The buffer is already in the buffer list. */
162 si_resource_reference(&desc
->buffer
, NULL
);
163 desc
->gpu_list
= NULL
;
164 desc
->gpu_address
= si_desc_extract_buffer_address(descriptor
);
165 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
170 unsigned buffer_offset
;
171 u_upload_alloc(sctx
->b
.const_uploader
, first_slot_offset
, upload_size
,
172 si_optimal_tcc_alignment(sctx
, upload_size
),
173 &buffer_offset
, (struct pipe_resource
**)&desc
->buffer
,
176 desc
->gpu_address
= 0;
177 return false; /* skip the draw call */
180 util_memcpy_cpu_to_le32(ptr
, (char*)desc
->list
+ first_slot_offset
,
182 desc
->gpu_list
= ptr
- first_slot_offset
/ 4;
184 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, desc
->buffer
,
185 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
187 /* The shader pointer should point to slot 0. */
188 buffer_offset
-= first_slot_offset
;
189 desc
->gpu_address
= desc
->buffer
->gpu_address
+ buffer_offset
;
191 assert(desc
->buffer
->flags
& RADEON_FLAG_32BIT
);
192 assert((desc
->buffer
->gpu_address
>> 32) == sctx
->screen
->info
.address32_hi
);
193 assert((desc
->gpu_address
>> 32) == sctx
->screen
->info
.address32_hi
);
195 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
200 si_descriptors_begin_new_cs(struct si_context
*sctx
, struct si_descriptors
*desc
)
205 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, desc
->buffer
,
206 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
211 static inline enum radeon_bo_priority
212 si_get_sampler_view_priority(struct si_resource
*res
)
214 if (res
->b
.b
.target
== PIPE_BUFFER
)
215 return RADEON_PRIO_SAMPLER_BUFFER
;
217 if (res
->b
.b
.nr_samples
> 1)
218 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA
;
220 return RADEON_PRIO_SAMPLER_TEXTURE
;
223 static struct si_descriptors
*
224 si_sampler_and_image_descriptors(struct si_context
*sctx
, unsigned shader
)
226 return &sctx
->descriptors
[si_sampler_and_image_descriptors_idx(shader
)];
229 static void si_release_sampler_views(struct si_samplers
*samplers
)
233 for (i
= 0; i
< ARRAY_SIZE(samplers
->views
); i
++) {
234 pipe_sampler_view_reference(&samplers
->views
[i
], NULL
);
238 static void si_sampler_view_add_buffer(struct si_context
*sctx
,
239 struct pipe_resource
*resource
,
240 enum radeon_bo_usage usage
,
241 bool is_stencil_sampler
,
244 struct si_texture
*tex
= (struct si_texture
*)resource
;
245 enum radeon_bo_priority priority
;
250 /* Use the flushed depth texture if direct sampling is unsupported. */
251 if (resource
->target
!= PIPE_BUFFER
&&
252 tex
->is_depth
&& !si_can_sample_zs(tex
, is_stencil_sampler
))
253 tex
= tex
->flushed_depth_texture
;
255 priority
= si_get_sampler_view_priority(&tex
->buffer
);
256 radeon_add_to_gfx_buffer_list_check_mem(sctx
, &tex
->buffer
, usage
, priority
,
259 if (resource
->target
== PIPE_BUFFER
)
262 /* Add separate DCC. */
263 if (tex
->dcc_separate_buffer
) {
264 radeon_add_to_gfx_buffer_list_check_mem(sctx
, tex
->dcc_separate_buffer
,
265 usage
, RADEON_PRIO_SEPARATE_META
, check_mem
);
269 static void si_sampler_views_begin_new_cs(struct si_context
*sctx
,
270 struct si_samplers
*samplers
)
272 unsigned mask
= samplers
->enabled_mask
;
274 /* Add buffers to the CS. */
276 int i
= u_bit_scan(&mask
);
277 struct si_sampler_view
*sview
= (struct si_sampler_view
*)samplers
->views
[i
];
279 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
281 sview
->is_stencil_sampler
, false);
285 /* Set buffer descriptor fields that can be changed by reallocations. */
286 static void si_set_buf_desc_address(struct si_resource
*buf
,
287 uint64_t offset
, uint32_t *state
)
289 uint64_t va
= buf
->gpu_address
+ offset
;
292 state
[1] &= C_008F04_BASE_ADDRESS_HI
;
293 state
[1] |= S_008F04_BASE_ADDRESS_HI(va
>> 32);
296 /* Set texture descriptor fields that can be changed by reallocations.
299 * \param base_level_info information of the level of BASE_ADDRESS
300 * \param base_level the level of BASE_ADDRESS
301 * \param first_level pipe_sampler_view.u.tex.first_level
302 * \param block_width util_format_get_blockwidth()
303 * \param is_stencil select between separate Z & Stencil
304 * \param state descriptor to update
306 void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen
,
307 struct si_texture
*tex
,
308 const struct legacy_surf_level
*base_level_info
,
309 unsigned base_level
, unsigned first_level
,
310 unsigned block_width
, bool is_stencil
,
313 uint64_t va
, meta_va
= 0;
315 if (tex
->is_depth
&& !si_can_sample_zs(tex
, is_stencil
)) {
316 tex
= tex
->flushed_depth_texture
;
320 va
= tex
->buffer
.gpu_address
;
322 if (sscreen
->info
.chip_class
>= GFX9
) {
323 /* Only stencil_offset needs to be added here. */
325 va
+= tex
->surface
.u
.gfx9
.stencil_offset
;
327 va
+= tex
->surface
.u
.gfx9
.surf_offset
;
329 va
+= base_level_info
->offset
;
333 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
334 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
336 /* Only macrotiled modes can set tile swizzle.
337 * GFX9 doesn't use (legacy) base_level_info.
339 if (sscreen
->info
.chip_class
>= GFX9
||
340 base_level_info
->mode
== RADEON_SURF_MODE_2D
)
341 state
[0] |= tex
->surface
.tile_swizzle
;
343 if (sscreen
->info
.chip_class
>= GFX8
) {
344 state
[6] &= C_008F28_COMPRESSION_EN
;
347 if (vi_dcc_enabled(tex
, first_level
)) {
348 meta_va
= (!tex
->dcc_separate_buffer
? tex
->buffer
.gpu_address
: 0) +
351 if (sscreen
->info
.chip_class
== GFX8
) {
352 meta_va
+= base_level_info
->dcc_offset
;
353 assert(base_level_info
->mode
== RADEON_SURF_MODE_2D
);
356 meta_va
|= (uint32_t)tex
->surface
.tile_swizzle
<< 8;
357 } else if (vi_tc_compat_htile_enabled(tex
, first_level
)) {
358 meta_va
= tex
->buffer
.gpu_address
+ tex
->htile_offset
;
362 state
[6] |= S_008F28_COMPRESSION_EN(1);
363 state
[7] = meta_va
>> 8;
367 if (sscreen
->info
.chip_class
>= GFX9
) {
368 state
[3] &= C_008F1C_SW_MODE
;
369 state
[4] &= C_008F20_PITCH_GFX9
;
372 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
373 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.stencil
.epitch
);
375 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
);
376 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.surf
.epitch
);
379 state
[5] &= C_008F24_META_DATA_ADDRESS
&
380 C_008F24_META_PIPE_ALIGNED
&
381 C_008F24_META_RB_ALIGNED
;
383 struct gfx9_surf_meta_flags meta
;
386 meta
= tex
->surface
.u
.gfx9
.dcc
;
388 meta
= tex
->surface
.u
.gfx9
.htile
;
390 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
391 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
392 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
396 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
397 unsigned index
= si_tile_mode_index(tex
, base_level
, is_stencil
);
399 state
[3] &= C_008F1C_TILING_INDEX
;
400 state
[3] |= S_008F1C_TILING_INDEX(index
);
401 state
[4] &= C_008F20_PITCH_GFX6
;
402 state
[4] |= S_008F20_PITCH_GFX6(pitch
- 1);
406 static void si_set_sampler_state_desc(struct si_sampler_state
*sstate
,
407 struct si_sampler_view
*sview
,
408 struct si_texture
*tex
,
411 if (sview
&& sview
->is_integer
)
412 memcpy(desc
, sstate
->integer_val
, 4*4);
413 else if (tex
&& tex
->upgraded_depth
&&
414 (!sview
|| !sview
->is_stencil_sampler
))
415 memcpy(desc
, sstate
->upgraded_depth_val
, 4*4);
417 memcpy(desc
, sstate
->val
, 4*4);
420 static void si_set_sampler_view_desc(struct si_context
*sctx
,
421 struct si_sampler_view
*sview
,
422 struct si_sampler_state
*sstate
,
425 struct pipe_sampler_view
*view
= &sview
->base
;
426 struct si_texture
*tex
= (struct si_texture
*)view
->texture
;
427 bool is_buffer
= tex
->buffer
.b
.b
.target
== PIPE_BUFFER
;
429 if (unlikely(!is_buffer
&& sview
->dcc_incompatible
)) {
430 if (vi_dcc_enabled(tex
, view
->u
.tex
.first_level
))
431 if (!si_texture_disable_dcc(sctx
, tex
))
432 si_decompress_dcc(sctx
, tex
);
434 sview
->dcc_incompatible
= false;
437 assert(tex
); /* views with texture == NULL aren't supported */
438 memcpy(desc
, sview
->state
, 8*4);
441 si_set_buf_desc_address(&tex
->buffer
,
442 sview
->base
.u
.buf
.offset
,
445 bool is_separate_stencil
= tex
->db_compatible
&&
446 sview
->is_stencil_sampler
;
448 si_set_mutable_tex_desc_fields(sctx
->screen
, tex
,
449 sview
->base_level_info
,
451 sview
->base
.u
.tex
.first_level
,
457 if (!is_buffer
&& tex
->surface
.fmask_size
) {
458 memcpy(desc
+ 8, sview
->fmask_state
, 8*4);
460 /* Disable FMASK and bind sampler state in [12:15]. */
461 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
464 si_set_sampler_state_desc(sstate
, sview
,
465 is_buffer
? NULL
: tex
,
470 static bool color_needs_decompression(struct si_texture
*tex
)
472 return tex
->surface
.fmask_size
||
473 (tex
->dirty_level_mask
&&
474 (tex
->cmask_buffer
|| tex
->dcc_offset
));
477 static bool depth_needs_decompression(struct si_texture
*tex
)
479 /* If the depth/stencil texture is TC-compatible, no decompression
480 * will be done. The decompression function will only flush DB caches
481 * to make it coherent with shaders. That's necessary because the driver
482 * doesn't flush DB caches in any other case.
484 return tex
->db_compatible
;
487 static void si_set_sampler_view(struct si_context
*sctx
,
489 unsigned slot
, struct pipe_sampler_view
*view
,
490 bool disallow_early_out
)
492 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
493 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
494 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(sctx
, shader
);
495 unsigned desc_slot
= si_get_sampler_slot(slot
);
496 uint32_t *desc
= descs
->list
+ desc_slot
* 16;
498 if (samplers
->views
[slot
] == view
&& !disallow_early_out
)
502 struct si_texture
*tex
= (struct si_texture
*)view
->texture
;
504 si_set_sampler_view_desc(sctx
, sview
,
505 samplers
->sampler_states
[slot
], desc
);
507 if (tex
->buffer
.b
.b
.target
== PIPE_BUFFER
) {
508 tex
->buffer
.bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
509 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
510 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
512 if (depth_needs_decompression(tex
)) {
513 samplers
->needs_depth_decompress_mask
|= 1u << slot
;
515 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
517 if (color_needs_decompression(tex
)) {
518 samplers
->needs_color_decompress_mask
|= 1u << slot
;
520 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
523 if (tex
->dcc_offset
&&
524 p_atomic_read(&tex
->framebuffers_bound
))
525 sctx
->need_check_render_feedback
= true;
528 pipe_sampler_view_reference(&samplers
->views
[slot
], view
);
529 samplers
->enabled_mask
|= 1u << slot
;
531 /* Since this can flush, it must be done after enabled_mask is
533 si_sampler_view_add_buffer(sctx
, view
->texture
,
535 sview
->is_stencil_sampler
, true);
537 pipe_sampler_view_reference(&samplers
->views
[slot
], NULL
);
538 memcpy(desc
, null_texture_descriptor
, 8*4);
539 /* Only clear the lower dwords of FMASK. */
540 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
541 /* Re-set the sampler state if we are transitioning from FMASK. */
542 if (samplers
->sampler_states
[slot
])
543 si_set_sampler_state_desc(samplers
->sampler_states
[slot
], NULL
, NULL
,
546 samplers
->enabled_mask
&= ~(1u << slot
);
547 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
548 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
551 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
554 static void si_update_shader_needs_decompress_mask(struct si_context
*sctx
,
557 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
558 unsigned shader_bit
= 1 << shader
;
560 if (samplers
->needs_depth_decompress_mask
||
561 samplers
->needs_color_decompress_mask
||
562 sctx
->images
[shader
].needs_color_decompress_mask
)
563 sctx
->shader_needs_decompress_mask
|= shader_bit
;
565 sctx
->shader_needs_decompress_mask
&= ~shader_bit
;
568 static void si_set_sampler_views(struct pipe_context
*ctx
,
569 enum pipe_shader_type shader
, unsigned start
,
571 struct pipe_sampler_view
**views
)
573 struct si_context
*sctx
= (struct si_context
*)ctx
;
576 if (!count
|| shader
>= SI_NUM_SHADERS
)
580 for (i
= 0; i
< count
; i
++)
581 si_set_sampler_view(sctx
, shader
, start
+ i
, views
[i
], false);
583 for (i
= 0; i
< count
; i
++)
584 si_set_sampler_view(sctx
, shader
, start
+ i
, NULL
, false);
587 si_update_shader_needs_decompress_mask(sctx
, shader
);
591 si_samplers_update_needs_color_decompress_mask(struct si_samplers
*samplers
)
593 unsigned mask
= samplers
->enabled_mask
;
596 int i
= u_bit_scan(&mask
);
597 struct pipe_resource
*res
= samplers
->views
[i
]->texture
;
599 if (res
&& res
->target
!= PIPE_BUFFER
) {
600 struct si_texture
*tex
= (struct si_texture
*)res
;
602 if (color_needs_decompression(tex
)) {
603 samplers
->needs_color_decompress_mask
|= 1u << i
;
605 samplers
->needs_color_decompress_mask
&= ~(1u << i
);
614 si_release_image_views(struct si_images
*images
)
618 for (i
= 0; i
< SI_NUM_IMAGES
; ++i
) {
619 struct pipe_image_view
*view
= &images
->views
[i
];
621 pipe_resource_reference(&view
->resource
, NULL
);
626 si_image_views_begin_new_cs(struct si_context
*sctx
, struct si_images
*images
)
628 uint mask
= images
->enabled_mask
;
630 /* Add buffers to the CS. */
632 int i
= u_bit_scan(&mask
);
633 struct pipe_image_view
*view
= &images
->views
[i
];
635 assert(view
->resource
);
637 si_sampler_view_add_buffer(sctx
, view
->resource
,
638 RADEON_USAGE_READWRITE
, false, false);
643 si_disable_shader_image(struct si_context
*ctx
, unsigned shader
, unsigned slot
)
645 struct si_images
*images
= &ctx
->images
[shader
];
647 if (images
->enabled_mask
& (1u << slot
)) {
648 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
649 unsigned desc_slot
= si_get_image_slot(slot
);
651 pipe_resource_reference(&images
->views
[slot
].resource
, NULL
);
652 images
->needs_color_decompress_mask
&= ~(1 << slot
);
654 memcpy(descs
->list
+ desc_slot
*8, null_image_descriptor
, 8*4);
655 images
->enabled_mask
&= ~(1u << slot
);
656 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
661 si_mark_image_range_valid(const struct pipe_image_view
*view
)
663 struct si_resource
*res
= si_resource(view
->resource
);
665 if (res
->b
.b
.target
!= PIPE_BUFFER
)
668 util_range_add(&res
->valid_buffer_range
,
670 view
->u
.buf
.offset
+ view
->u
.buf
.size
);
673 static void si_set_shader_image_desc(struct si_context
*ctx
,
674 const struct pipe_image_view
*view
,
675 bool skip_decompress
,
676 uint32_t *desc
, uint32_t *fmask_desc
)
678 struct si_screen
*screen
= ctx
->screen
;
679 struct si_resource
*res
;
681 res
= si_resource(view
->resource
);
683 if (res
->b
.b
.target
== PIPE_BUFFER
||
684 view
->shader_access
& SI_IMAGE_ACCESS_AS_BUFFER
) {
685 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
686 si_mark_image_range_valid(view
);
688 si_make_buffer_descriptor(screen
, res
,
691 view
->u
.buf
.size
, desc
);
692 si_set_buf_desc_address(res
, view
->u
.buf
.offset
, desc
+ 4);
694 static const unsigned char swizzle
[4] = { 0, 1, 2, 3 };
695 struct si_texture
*tex
= (struct si_texture
*)res
;
696 unsigned level
= view
->u
.tex
.level
;
697 unsigned width
, height
, depth
, hw_level
;
698 bool uses_dcc
= vi_dcc_enabled(tex
, level
);
699 unsigned access
= view
->access
;
701 /* Clear the write flag when writes can't occur.
702 * Note that DCC_DECOMPRESS for MSAA doesn't work in some cases,
703 * so we don't wanna trigger it.
706 (!fmask_desc
&& tex
->surface
.fmask_size
!= 0)) {
707 assert(!"Z/S and MSAA image stores are not supported");
708 access
&= ~PIPE_IMAGE_ACCESS_WRITE
;
711 assert(!tex
->is_depth
);
712 assert(fmask_desc
|| tex
->surface
.fmask_size
== 0);
714 if (uses_dcc
&& !skip_decompress
&&
715 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
||
716 !vi_dcc_formats_compatible(res
->b
.b
.format
, view
->format
))) {
717 /* If DCC can't be disabled, at least decompress it.
718 * The decompression is relatively cheap if the surface
719 * has been decompressed already.
721 if (!si_texture_disable_dcc(ctx
, tex
))
722 si_decompress_dcc(ctx
, tex
);
725 if (ctx
->chip_class
>= GFX9
) {
726 /* Always set the base address. The swizzle modes don't
727 * allow setting mipmap level offsets as the base.
729 width
= res
->b
.b
.width0
;
730 height
= res
->b
.b
.height0
;
731 depth
= res
->b
.b
.depth0
;
734 /* Always force the base level to the selected level.
736 * This is required for 3D textures, where otherwise
737 * selecting a single slice for non-layered bindings
738 * fails. It doesn't hurt the other targets.
740 width
= u_minify(res
->b
.b
.width0
, level
);
741 height
= u_minify(res
->b
.b
.height0
, level
);
742 depth
= u_minify(res
->b
.b
.depth0
, level
);
746 si_make_texture_descriptor(screen
, tex
,
747 false, res
->b
.b
.target
,
748 view
->format
, swizzle
,
750 view
->u
.tex
.first_layer
,
751 view
->u
.tex
.last_layer
,
752 width
, height
, depth
,
754 si_set_mutable_tex_desc_fields(screen
, tex
,
755 &tex
->surface
.u
.legacy
.level
[level
],
757 util_format_get_blockwidth(view
->format
),
762 static void si_set_shader_image(struct si_context
*ctx
,
764 unsigned slot
, const struct pipe_image_view
*view
,
765 bool skip_decompress
)
767 struct si_images
*images
= &ctx
->images
[shader
];
768 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
769 struct si_resource
*res
;
770 unsigned desc_slot
= si_get_image_slot(slot
);
771 uint32_t *desc
= descs
->list
+ desc_slot
* 8;
773 if (!view
|| !view
->resource
) {
774 si_disable_shader_image(ctx
, shader
, slot
);
778 res
= si_resource(view
->resource
);
780 if (&images
->views
[slot
] != view
)
781 util_copy_image_view(&images
->views
[slot
], view
);
783 si_set_shader_image_desc(ctx
, view
, skip_decompress
, desc
, NULL
);
785 if (res
->b
.b
.target
== PIPE_BUFFER
||
786 view
->shader_access
& SI_IMAGE_ACCESS_AS_BUFFER
) {
787 images
->needs_color_decompress_mask
&= ~(1 << slot
);
788 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
790 struct si_texture
*tex
= (struct si_texture
*)res
;
791 unsigned level
= view
->u
.tex
.level
;
793 if (color_needs_decompression(tex
)) {
794 images
->needs_color_decompress_mask
|= 1 << slot
;
796 images
->needs_color_decompress_mask
&= ~(1 << slot
);
799 if (vi_dcc_enabled(tex
, level
) &&
800 p_atomic_read(&tex
->framebuffers_bound
))
801 ctx
->need_check_render_feedback
= true;
804 images
->enabled_mask
|= 1u << slot
;
805 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
807 /* Since this can flush, it must be done after enabled_mask is updated. */
808 si_sampler_view_add_buffer(ctx
, &res
->b
.b
,
809 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
) ?
810 RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
,
815 si_set_shader_images(struct pipe_context
*pipe
,
816 enum pipe_shader_type shader
,
817 unsigned start_slot
, unsigned count
,
818 const struct pipe_image_view
*views
)
820 struct si_context
*ctx
= (struct si_context
*)pipe
;
823 assert(shader
< SI_NUM_SHADERS
);
828 assert(start_slot
+ count
<= SI_NUM_IMAGES
);
831 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
832 si_set_shader_image(ctx
, shader
, slot
, &views
[i
], false);
834 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
835 si_set_shader_image(ctx
, shader
, slot
, NULL
, false);
838 si_update_shader_needs_decompress_mask(ctx
, shader
);
842 si_images_update_needs_color_decompress_mask(struct si_images
*images
)
844 unsigned mask
= images
->enabled_mask
;
847 int i
= u_bit_scan(&mask
);
848 struct pipe_resource
*res
= images
->views
[i
].resource
;
850 if (res
&& res
->target
!= PIPE_BUFFER
) {
851 struct si_texture
*tex
= (struct si_texture
*)res
;
853 if (color_needs_decompression(tex
)) {
854 images
->needs_color_decompress_mask
|= 1 << i
;
856 images
->needs_color_decompress_mask
&= ~(1 << i
);
862 void si_update_ps_colorbuf0_slot(struct si_context
*sctx
)
864 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
865 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
866 unsigned slot
= SI_PS_IMAGE_COLORBUF0
;
867 struct pipe_surface
*surf
= NULL
;
869 /* si_texture_disable_dcc can get us here again. */
870 if (sctx
->blitter
->running
)
873 /* See whether FBFETCH is used and color buffer 0 is set. */
874 if (sctx
->ps_shader
.cso
&&
875 sctx
->ps_shader
.cso
->info
.opcode_count
[TGSI_OPCODE_FBFETCH
] &&
876 sctx
->framebuffer
.state
.nr_cbufs
&&
877 sctx
->framebuffer
.state
.cbufs
[0])
878 surf
= sctx
->framebuffer
.state
.cbufs
[0];
880 /* Return if FBFETCH transitions from disabled to disabled. */
881 if (!buffers
->buffers
[slot
] && !surf
)
884 sctx
->ps_uses_fbfetch
= surf
!= NULL
;
885 si_update_ps_iter_samples(sctx
);
888 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
889 struct pipe_image_view view
;
892 assert(!tex
->is_depth
);
894 /* Disable DCC, because the texture is used as both a sampler
897 si_texture_disable_dcc(sctx
, tex
);
899 if (tex
->buffer
.b
.b
.nr_samples
<= 1 && tex
->cmask_buffer
) {
901 assert(tex
->cmask_buffer
!= &tex
->buffer
);
902 si_eliminate_fast_color_clear(sctx
, tex
);
903 si_texture_discard_cmask(sctx
->screen
, tex
);
906 view
.resource
= surf
->texture
;
907 view
.format
= surf
->format
;
908 view
.access
= PIPE_IMAGE_ACCESS_READ
;
909 view
.u
.tex
.first_layer
= surf
->u
.tex
.first_layer
;
910 view
.u
.tex
.last_layer
= surf
->u
.tex
.last_layer
;
911 view
.u
.tex
.level
= surf
->u
.tex
.level
;
913 /* Set the descriptor. */
914 uint32_t *desc
= descs
->list
+ slot
*4;
915 memset(desc
, 0, 16 * 4);
916 si_set_shader_image_desc(sctx
, &view
, true, desc
, desc
+ 8);
918 pipe_resource_reference(&buffers
->buffers
[slot
], &tex
->buffer
.b
.b
);
919 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
920 &tex
->buffer
, RADEON_USAGE_READ
,
921 RADEON_PRIO_SHADER_RW_IMAGE
);
922 buffers
->enabled_mask
|= 1u << slot
;
924 /* Clear the descriptor. */
925 memset(descs
->list
+ slot
*4, 0, 8*4);
926 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
927 buffers
->enabled_mask
&= ~(1u << slot
);
930 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
935 static void si_bind_sampler_states(struct pipe_context
*ctx
,
936 enum pipe_shader_type shader
,
937 unsigned start
, unsigned count
, void **states
)
939 struct si_context
*sctx
= (struct si_context
*)ctx
;
940 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
941 struct si_descriptors
*desc
= si_sampler_and_image_descriptors(sctx
, shader
);
942 struct si_sampler_state
**sstates
= (struct si_sampler_state
**)states
;
945 if (!count
|| shader
>= SI_NUM_SHADERS
|| !sstates
)
948 for (i
= 0; i
< count
; i
++) {
949 unsigned slot
= start
+ i
;
950 unsigned desc_slot
= si_get_sampler_slot(slot
);
953 sstates
[i
] == samplers
->sampler_states
[slot
])
957 assert(sstates
[i
]->magic
== SI_SAMPLER_STATE_MAGIC
);
959 samplers
->sampler_states
[slot
] = sstates
[i
];
961 /* If FMASK is bound, don't overwrite it.
962 * The sampler state will be set after FMASK is unbound.
964 struct si_sampler_view
*sview
=
965 (struct si_sampler_view
*)samplers
->views
[slot
];
967 struct si_texture
*tex
= NULL
;
969 if (sview
&& sview
->base
.texture
&&
970 sview
->base
.texture
->target
!= PIPE_BUFFER
)
971 tex
= (struct si_texture
*)sview
->base
.texture
;
973 if (tex
&& tex
->surface
.fmask_size
)
976 si_set_sampler_state_desc(sstates
[i
], sview
, tex
,
977 desc
->list
+ desc_slot
* 16 + 12);
979 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
983 /* BUFFER RESOURCES */
985 static void si_init_buffer_resources(struct si_buffer_resources
*buffers
,
986 struct si_descriptors
*descs
,
987 unsigned num_buffers
,
988 short shader_userdata_rel_index
,
989 enum radeon_bo_priority priority
,
990 enum radeon_bo_priority priority_constbuf
)
992 buffers
->priority
= priority
;
993 buffers
->priority_constbuf
= priority_constbuf
;
994 buffers
->buffers
= CALLOC(num_buffers
, sizeof(struct pipe_resource
*));
995 buffers
->offsets
= CALLOC(num_buffers
, sizeof(buffers
->offsets
[0]));
997 si_init_descriptors(descs
, shader_userdata_rel_index
, 4, num_buffers
);
1000 static void si_release_buffer_resources(struct si_buffer_resources
*buffers
,
1001 struct si_descriptors
*descs
)
1005 for (i
= 0; i
< descs
->num_elements
; i
++) {
1006 pipe_resource_reference(&buffers
->buffers
[i
], NULL
);
1009 FREE(buffers
->buffers
);
1010 FREE(buffers
->offsets
);
1013 static void si_buffer_resources_begin_new_cs(struct si_context
*sctx
,
1014 struct si_buffer_resources
*buffers
)
1016 unsigned mask
= buffers
->enabled_mask
;
1018 /* Add buffers to the CS. */
1020 int i
= u_bit_scan(&mask
);
1022 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1023 si_resource(buffers
->buffers
[i
]),
1024 buffers
->writable_mask
& (1u << i
) ? RADEON_USAGE_READWRITE
:
1026 i
< SI_NUM_SHADER_BUFFERS
? buffers
->priority
:
1027 buffers
->priority_constbuf
);
1031 static void si_get_buffer_from_descriptors(struct si_buffer_resources
*buffers
,
1032 struct si_descriptors
*descs
,
1033 unsigned idx
, struct pipe_resource
**buf
,
1034 unsigned *offset
, unsigned *size
)
1036 pipe_resource_reference(buf
, buffers
->buffers
[idx
]);
1038 struct si_resource
*res
= si_resource(*buf
);
1039 const uint32_t *desc
= descs
->list
+ idx
* 4;
1044 assert(G_008F04_STRIDE(desc
[1]) == 0);
1045 va
= si_desc_extract_buffer_address(desc
);
1047 assert(va
>= res
->gpu_address
&& va
+ *size
<= res
->gpu_address
+ res
->bo_size
);
1048 *offset
= va
- res
->gpu_address
;
1052 /* VERTEX BUFFERS */
1054 static void si_vertex_buffers_begin_new_cs(struct si_context
*sctx
)
1056 int count
= sctx
->vertex_elements
? sctx
->vertex_elements
->count
: 0;
1059 for (i
= 0; i
< count
; i
++) {
1060 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1062 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1064 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1067 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1068 si_resource(sctx
->vertex_buffer
[vb
].buffer
.resource
),
1069 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1072 if (!sctx
->vb_descriptors_buffer
)
1074 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1075 sctx
->vb_descriptors_buffer
, RADEON_USAGE_READ
,
1076 RADEON_PRIO_DESCRIPTORS
);
1079 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
)
1081 struct si_vertex_elements
*velems
= sctx
->vertex_elements
;
1083 unsigned desc_list_byte_size
;
1084 unsigned first_vb_use_mask
;
1087 if (!sctx
->vertex_buffers_dirty
|| !velems
)
1090 count
= velems
->count
;
1095 desc_list_byte_size
= velems
->desc_list_byte_size
;
1096 first_vb_use_mask
= velems
->first_vb_use_mask
;
1098 /* Vertex buffer descriptors are the only ones which are uploaded
1099 * directly through a staging buffer and don't go through
1100 * the fine-grained upload path.
1102 u_upload_alloc(sctx
->b
.const_uploader
, 0,
1103 desc_list_byte_size
,
1104 si_optimal_tcc_alignment(sctx
, desc_list_byte_size
),
1105 &sctx
->vb_descriptors_offset
,
1106 (struct pipe_resource
**)&sctx
->vb_descriptors_buffer
,
1108 if (!sctx
->vb_descriptors_buffer
) {
1109 sctx
->vb_descriptors_offset
= 0;
1110 sctx
->vb_descriptors_gpu_list
= NULL
;
1114 sctx
->vb_descriptors_gpu_list
= ptr
;
1115 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1116 sctx
->vb_descriptors_buffer
, RADEON_USAGE_READ
,
1117 RADEON_PRIO_DESCRIPTORS
);
1119 assert(count
<= SI_MAX_ATTRIBS
);
1121 for (i
= 0; i
< count
; i
++) {
1122 struct pipe_vertex_buffer
*vb
;
1123 struct si_resource
*buf
;
1124 unsigned vbo_index
= velems
->vertex_buffer_index
[i
];
1125 uint32_t *desc
= &ptr
[i
*4];
1127 vb
= &sctx
->vertex_buffer
[vbo_index
];
1128 buf
= si_resource(vb
->buffer
.resource
);
1130 memset(desc
, 0, 16);
1134 int64_t offset
= (int64_t)((int)vb
->buffer_offset
) +
1135 velems
->src_offset
[i
];
1136 uint64_t va
= buf
->gpu_address
+ offset
;
1138 int64_t num_records
= (int64_t)buf
->b
.b
.width0
- offset
;
1139 if (sctx
->chip_class
!= GFX8
&& vb
->stride
) {
1140 /* Round up by rounding down and adding 1 */
1141 num_records
= (num_records
- velems
->format_size
[i
]) /
1144 assert(num_records
>= 0 && num_records
<= UINT_MAX
);
1147 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1148 S_008F04_STRIDE(vb
->stride
);
1149 desc
[2] = num_records
;
1150 desc
[3] = velems
->rsrc_word3
[i
];
1152 if (first_vb_use_mask
& (1 << i
)) {
1153 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1154 si_resource(vb
->buffer
.resource
),
1155 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1159 /* Don't flush the const cache. It would have a very negative effect
1160 * on performance (confirmed by testing). New descriptors are always
1161 * uploaded to a fresh new buffer, so I don't think flushing the const
1162 * cache is needed. */
1163 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
1164 sctx
->vertex_buffers_dirty
= false;
1165 sctx
->vertex_buffer_pointer_dirty
= true;
1166 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VBO_DESCRIPTORS
;
1171 /* CONSTANT BUFFERS */
1173 static struct si_descriptors
*
1174 si_const_and_shader_buffer_descriptors(struct si_context
*sctx
, unsigned shader
)
1176 return &sctx
->descriptors
[si_const_and_shader_buffer_descriptors_idx(shader
)];
1179 void si_upload_const_buffer(struct si_context
*sctx
, struct si_resource
**buf
,
1180 const uint8_t *ptr
, unsigned size
, uint32_t *const_offset
)
1184 u_upload_alloc(sctx
->b
.const_uploader
, 0, size
,
1185 si_optimal_tcc_alignment(sctx
, size
),
1187 (struct pipe_resource
**)buf
, &tmp
);
1189 util_memcpy_cpu_to_le32(tmp
, ptr
, size
);
1192 static void si_set_constant_buffer(struct si_context
*sctx
,
1193 struct si_buffer_resources
*buffers
,
1194 unsigned descriptors_idx
,
1195 uint slot
, const struct pipe_constant_buffer
*input
)
1197 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1198 assert(slot
< descs
->num_elements
);
1199 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1201 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1202 * with a NULL buffer). We need to use a dummy buffer instead. */
1203 if (sctx
->chip_class
== GFX7
&&
1204 (!input
|| (!input
->buffer
&& !input
->user_buffer
)))
1205 input
= &sctx
->null_const_buf
;
1207 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
1208 struct pipe_resource
*buffer
= NULL
;
1210 unsigned buffer_offset
;
1212 /* Upload the user buffer if needed. */
1213 if (input
->user_buffer
) {
1214 si_upload_const_buffer(sctx
,
1215 (struct si_resource
**)&buffer
, input
->user_buffer
,
1216 input
->buffer_size
, &buffer_offset
);
1218 /* Just unbind on failure. */
1219 si_set_constant_buffer(sctx
, buffers
, descriptors_idx
, slot
, NULL
);
1223 pipe_resource_reference(&buffer
, input
->buffer
);
1224 buffer_offset
= input
->buffer_offset
;
1227 va
= si_resource(buffer
)->gpu_address
+ buffer_offset
;
1229 /* Set the descriptor. */
1230 uint32_t *desc
= descs
->list
+ slot
*4;
1232 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1234 desc
[2] = input
->buffer_size
;
1235 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1236 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1237 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1238 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1239 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1240 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1242 buffers
->buffers
[slot
] = buffer
;
1243 buffers
->offsets
[slot
] = buffer_offset
;
1244 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1245 si_resource(buffer
),
1247 buffers
->priority_constbuf
, true);
1248 buffers
->enabled_mask
|= 1u << slot
;
1250 /* Clear the descriptor. */
1251 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1252 buffers
->enabled_mask
&= ~(1u << slot
);
1255 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1258 static void si_pipe_set_constant_buffer(struct pipe_context
*ctx
,
1259 enum pipe_shader_type shader
, uint slot
,
1260 const struct pipe_constant_buffer
*input
)
1262 struct si_context
*sctx
= (struct si_context
*)ctx
;
1264 if (shader
>= SI_NUM_SHADERS
)
1267 if (slot
== 0 && input
&& input
->buffer
&&
1268 !(si_resource(input
->buffer
)->flags
& RADEON_FLAG_32BIT
)) {
1269 assert(!"constant buffer 0 must have a 32-bit VM address, use const_uploader");
1273 if (input
&& input
->buffer
)
1274 si_resource(input
->buffer
)->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
1276 slot
= si_get_constbuf_slot(slot
);
1277 si_set_constant_buffer(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1278 si_const_and_shader_buffer_descriptors_idx(shader
),
1282 void si_get_pipe_constant_buffer(struct si_context
*sctx
, uint shader
,
1283 uint slot
, struct pipe_constant_buffer
*cbuf
)
1285 cbuf
->user_buffer
= NULL
;
1286 si_get_buffer_from_descriptors(
1287 &sctx
->const_and_shader_buffers
[shader
],
1288 si_const_and_shader_buffer_descriptors(sctx
, shader
),
1289 si_get_constbuf_slot(slot
),
1290 &cbuf
->buffer
, &cbuf
->buffer_offset
, &cbuf
->buffer_size
);
1293 /* SHADER BUFFERS */
1295 static void si_set_shader_buffer(struct si_context
*sctx
,
1296 struct si_buffer_resources
*buffers
,
1297 unsigned descriptors_idx
,
1298 uint slot
, const struct pipe_shader_buffer
*sbuffer
,
1299 bool writable
, enum radeon_bo_priority priority
)
1301 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1302 uint32_t *desc
= descs
->list
+ slot
* 4;
1304 if (!sbuffer
|| !sbuffer
->buffer
) {
1305 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1306 memset(desc
, 0, sizeof(uint32_t) * 4);
1307 buffers
->enabled_mask
&= ~(1u << slot
);
1308 buffers
->writable_mask
&= ~(1u << slot
);
1309 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1313 struct si_resource
*buf
= si_resource(sbuffer
->buffer
);
1314 uint64_t va
= buf
->gpu_address
+ sbuffer
->buffer_offset
;
1317 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1319 desc
[2] = sbuffer
->buffer_size
;
1320 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1321 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1322 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1323 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1324 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1325 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1327 pipe_resource_reference(&buffers
->buffers
[slot
], &buf
->b
.b
);
1328 buffers
->offsets
[slot
] = sbuffer
->buffer_offset
;
1329 radeon_add_to_gfx_buffer_list_check_mem(sctx
, buf
,
1330 writable
? RADEON_USAGE_READWRITE
:
1334 buffers
->writable_mask
|= 1u << slot
;
1336 buffers
->writable_mask
&= ~(1u << slot
);
1338 buffers
->enabled_mask
|= 1u << slot
;
1339 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1341 util_range_add(&buf
->valid_buffer_range
, sbuffer
->buffer_offset
,
1342 sbuffer
->buffer_offset
+ sbuffer
->buffer_size
);
1345 static void si_set_shader_buffers(struct pipe_context
*ctx
,
1346 enum pipe_shader_type shader
,
1347 unsigned start_slot
, unsigned count
,
1348 const struct pipe_shader_buffer
*sbuffers
,
1349 unsigned writable_bitmask
)
1351 struct si_context
*sctx
= (struct si_context
*)ctx
;
1352 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1353 unsigned descriptors_idx
= si_const_and_shader_buffer_descriptors_idx(shader
);
1356 assert(start_slot
+ count
<= SI_NUM_SHADER_BUFFERS
);
1358 for (i
= 0; i
< count
; ++i
) {
1359 const struct pipe_shader_buffer
*sbuffer
= sbuffers
? &sbuffers
[i
] : NULL
;
1360 unsigned slot
= si_get_shaderbuf_slot(start_slot
+ i
);
1362 if (sbuffer
&& sbuffer
->buffer
)
1363 si_resource(sbuffer
->buffer
)->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
1365 si_set_shader_buffer(sctx
, buffers
, descriptors_idx
, slot
, sbuffer
,
1366 !!(writable_bitmask
& (1u << i
)),
1371 void si_get_shader_buffers(struct si_context
*sctx
,
1372 enum pipe_shader_type shader
,
1373 uint start_slot
, uint count
,
1374 struct pipe_shader_buffer
*sbuf
)
1376 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1377 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1379 for (unsigned i
= 0; i
< count
; ++i
) {
1380 si_get_buffer_from_descriptors(
1382 si_get_shaderbuf_slot(start_slot
+ i
),
1383 &sbuf
[i
].buffer
, &sbuf
[i
].buffer_offset
,
1384 &sbuf
[i
].buffer_size
);
1390 void si_set_rw_buffer(struct si_context
*sctx
,
1391 uint slot
, const struct pipe_constant_buffer
*input
)
1393 si_set_constant_buffer(sctx
, &sctx
->rw_buffers
, SI_DESCS_RW_BUFFERS
,
1397 void si_set_rw_shader_buffer(struct si_context
*sctx
, uint slot
,
1398 const struct pipe_shader_buffer
*sbuffer
)
1400 si_set_shader_buffer(sctx
, &sctx
->rw_buffers
, SI_DESCS_RW_BUFFERS
,
1401 slot
, sbuffer
, true, RADEON_PRIO_SHADER_RW_BUFFER
);
1404 void si_set_ring_buffer(struct si_context
*sctx
, uint slot
,
1405 struct pipe_resource
*buffer
,
1406 unsigned stride
, unsigned num_records
,
1407 bool add_tid
, bool swizzle
,
1408 unsigned element_size
, unsigned index_stride
, uint64_t offset
)
1410 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1411 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1413 /* The stride field in the resource descriptor has 14 bits */
1414 assert(stride
< (1 << 14));
1416 assert(slot
< descs
->num_elements
);
1417 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1422 va
= si_resource(buffer
)->gpu_address
+ offset
;
1424 switch (element_size
) {
1426 assert(!"Unsupported ring buffer element size");
1442 switch (index_stride
) {
1444 assert(!"Unsupported ring buffer index stride");
1460 if (sctx
->chip_class
>= GFX8
&& stride
)
1461 num_records
*= stride
;
1463 /* Set the descriptor. */
1464 uint32_t *desc
= descs
->list
+ slot
*4;
1466 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1467 S_008F04_STRIDE(stride
) |
1468 S_008F04_SWIZZLE_ENABLE(swizzle
);
1469 desc
[2] = num_records
;
1470 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1471 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1472 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1473 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1474 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1475 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1476 S_008F0C_INDEX_STRIDE(index_stride
) |
1477 S_008F0C_ADD_TID_ENABLE(add_tid
);
1479 if (sctx
->chip_class
>= GFX9
)
1480 assert(!swizzle
|| element_size
== 1); /* always 4 bytes on GFX9 */
1482 desc
[3] |= S_008F0C_ELEMENT_SIZE(element_size
);
1484 pipe_resource_reference(&buffers
->buffers
[slot
], buffer
);
1485 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1486 si_resource(buffer
),
1487 RADEON_USAGE_READWRITE
, buffers
->priority
);
1488 buffers
->enabled_mask
|= 1u << slot
;
1490 /* Clear the descriptor. */
1491 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1492 buffers
->enabled_mask
&= ~(1u << slot
);
1495 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1498 /* INTERNAL CONST BUFFERS */
1500 static void si_set_polygon_stipple(struct pipe_context
*ctx
,
1501 const struct pipe_poly_stipple
*state
)
1503 struct si_context
*sctx
= (struct si_context
*)ctx
;
1504 struct pipe_constant_buffer cb
= {};
1505 unsigned stipple
[32];
1508 for (i
= 0; i
< 32; i
++)
1509 stipple
[i
] = util_bitreverse(state
->stipple
[i
]);
1511 cb
.user_buffer
= stipple
;
1512 cb
.buffer_size
= sizeof(stipple
);
1514 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
, &cb
);
1517 /* TEXTURE METADATA ENABLE/DISABLE */
1520 si_resident_handles_update_needs_color_decompress(struct si_context
*sctx
)
1522 util_dynarray_clear(&sctx
->resident_tex_needs_color_decompress
);
1523 util_dynarray_clear(&sctx
->resident_img_needs_color_decompress
);
1525 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1526 struct si_texture_handle
*, tex_handle
) {
1527 struct pipe_resource
*res
= (*tex_handle
)->view
->texture
;
1528 struct si_texture
*tex
;
1530 if (!res
|| res
->target
== PIPE_BUFFER
)
1533 tex
= (struct si_texture
*)res
;
1534 if (!color_needs_decompression(tex
))
1537 util_dynarray_append(&sctx
->resident_tex_needs_color_decompress
,
1538 struct si_texture_handle
*, *tex_handle
);
1541 util_dynarray_foreach(&sctx
->resident_img_handles
,
1542 struct si_image_handle
*, img_handle
) {
1543 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1544 struct pipe_resource
*res
= view
->resource
;
1545 struct si_texture
*tex
;
1547 if (!res
|| res
->target
== PIPE_BUFFER
)
1550 tex
= (struct si_texture
*)res
;
1551 if (!color_needs_decompression(tex
))
1554 util_dynarray_append(&sctx
->resident_img_needs_color_decompress
,
1555 struct si_image_handle
*, *img_handle
);
1559 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1560 * while the texture is bound, possibly by a different context. In that case,
1561 * call this function to update needs_*_decompress_masks.
1563 void si_update_needs_color_decompress_masks(struct si_context
*sctx
)
1565 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
1566 si_samplers_update_needs_color_decompress_mask(&sctx
->samplers
[i
]);
1567 si_images_update_needs_color_decompress_mask(&sctx
->images
[i
]);
1568 si_update_shader_needs_decompress_mask(sctx
, i
);
1571 si_resident_handles_update_needs_color_decompress(sctx
);
1574 /* BUFFER DISCARD/INVALIDATION */
1576 /* Reset descriptors of buffer resources after \p buf has been invalidated.
1577 * If buf == NULL, reset all descriptors.
1579 static void si_reset_buffer_resources(struct si_context
*sctx
,
1580 struct si_buffer_resources
*buffers
,
1581 unsigned descriptors_idx
,
1583 struct pipe_resource
*buf
,
1584 enum radeon_bo_priority priority
)
1586 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1587 unsigned mask
= buffers
->enabled_mask
& slot_mask
;
1590 unsigned i
= u_bit_scan(&mask
);
1591 struct pipe_resource
*buffer
= buffers
->buffers
[i
];
1593 if (buffer
&& (!buf
|| buffer
== buf
)) {
1594 si_set_buf_desc_address(si_resource(buffer
), buffers
->offsets
[i
],
1596 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1598 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1599 si_resource(buffer
),
1600 buffers
->writable_mask
& (1u << i
) ?
1601 RADEON_USAGE_READWRITE
:
1608 /* Update all buffer bindings where the buffer is bound, including
1609 * all resource descriptors. This is invalidate_buffer without
1612 * If buf == NULL, update all buffer bindings.
1614 void si_rebind_buffer(struct si_context
*sctx
, struct pipe_resource
*buf
)
1616 struct si_resource
*buffer
= si_resource(buf
);
1618 unsigned num_elems
= sctx
->vertex_elements
?
1619 sctx
->vertex_elements
->count
: 0;
1621 /* We changed the buffer, now we need to bind it where the old one
1622 * was bound. This consists of 2 things:
1623 * 1) Updating the resource descriptor and dirtying it.
1624 * 2) Adding a relocation to the CS, so that it's usable.
1627 /* Vertex buffers. */
1630 sctx
->vertex_buffers_dirty
= true;
1631 } else if (buffer
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
1632 for (i
= 0; i
< num_elems
; i
++) {
1633 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1635 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1637 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1640 if (sctx
->vertex_buffer
[vb
].buffer
.resource
== buf
) {
1641 sctx
->vertex_buffers_dirty
= true;
1647 /* Streamout buffers. (other internal buffers can't be invalidated) */
1648 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
1649 for (i
= SI_VS_STREAMOUT_BUF0
; i
<= SI_VS_STREAMOUT_BUF3
; i
++) {
1650 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1651 struct si_descriptors
*descs
=
1652 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1653 struct pipe_resource
*buffer
= buffers
->buffers
[i
];
1655 if (!buffer
|| (buf
&& buffer
!= buf
))
1658 si_set_buf_desc_address(si_resource(buffer
), buffers
->offsets
[i
],
1660 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1662 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1663 si_resource(buffer
),
1665 RADEON_PRIO_SHADER_RW_BUFFER
,
1668 /* Update the streamout state. */
1669 if (sctx
->streamout
.begin_emitted
)
1670 si_emit_streamout_end(sctx
);
1671 sctx
->streamout
.append_bitmask
=
1672 sctx
->streamout
.enabled_mask
;
1673 si_streamout_buffers_dirty(sctx
);
1677 /* Constant and shader buffers. */
1678 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1679 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1680 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1681 si_const_and_shader_buffer_descriptors_idx(shader
),
1682 u_bit_consecutive(SI_NUM_SHADER_BUFFERS
, SI_NUM_CONST_BUFFERS
),
1684 sctx
->const_and_shader_buffers
[shader
].priority_constbuf
);
1687 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
1688 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1689 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1690 si_const_and_shader_buffer_descriptors_idx(shader
),
1691 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS
),
1693 sctx
->const_and_shader_buffers
[shader
].priority
);
1696 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
1697 /* Texture buffers - update bindings. */
1698 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1699 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1700 struct si_descriptors
*descs
=
1701 si_sampler_and_image_descriptors(sctx
, shader
);
1702 unsigned mask
= samplers
->enabled_mask
;
1705 unsigned i
= u_bit_scan(&mask
);
1706 struct pipe_resource
*buffer
= samplers
->views
[i
]->texture
;
1708 if (buffer
&& (!buf
|| buffer
== buf
)) {
1709 unsigned desc_slot
= si_get_sampler_slot(i
);
1711 si_set_buf_desc_address(si_resource(buffer
),
1712 samplers
->views
[i
]->u
.buf
.offset
,
1713 descs
->list
+ desc_slot
* 16 + 4);
1714 sctx
->descriptors_dirty
|=
1715 1u << si_sampler_and_image_descriptors_idx(shader
);
1717 radeon_add_to_gfx_buffer_list_check_mem(
1718 sctx
, si_resource(buffer
),
1720 RADEON_PRIO_SAMPLER_BUFFER
, true);
1727 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
1728 for (shader
= 0; shader
< SI_NUM_SHADERS
; ++shader
) {
1729 struct si_images
*images
= &sctx
->images
[shader
];
1730 struct si_descriptors
*descs
=
1731 si_sampler_and_image_descriptors(sctx
, shader
);
1732 unsigned mask
= images
->enabled_mask
;
1735 unsigned i
= u_bit_scan(&mask
);
1736 struct pipe_resource
*buffer
= images
->views
[i
].resource
;
1738 if (buffer
&& (!buf
|| buffer
== buf
)) {
1739 unsigned desc_slot
= si_get_image_slot(i
);
1741 if (images
->views
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
)
1742 si_mark_image_range_valid(&images
->views
[i
]);
1744 si_set_buf_desc_address(si_resource(buffer
),
1745 images
->views
[i
].u
.buf
.offset
,
1746 descs
->list
+ desc_slot
* 8 + 4);
1747 sctx
->descriptors_dirty
|=
1748 1u << si_sampler_and_image_descriptors_idx(shader
);
1750 radeon_add_to_gfx_buffer_list_check_mem(
1751 sctx
, si_resource(buffer
),
1752 RADEON_USAGE_READWRITE
,
1753 RADEON_PRIO_SAMPLER_BUFFER
, true);
1759 /* Bindless texture handles */
1760 if (!buffer
|| buffer
->texture_handle_allocated
) {
1761 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1763 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1764 struct si_texture_handle
*, tex_handle
) {
1765 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
1766 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1767 struct pipe_resource
*buffer
= view
->texture
;
1769 if (buffer
&& (!buf
|| buffer
== buf
)) {
1770 si_set_buf_desc_address(si_resource(buffer
),
1773 desc_slot
* 16 + 4);
1775 (*tex_handle
)->desc_dirty
= true;
1776 sctx
->bindless_descriptors_dirty
= true;
1778 radeon_add_to_gfx_buffer_list_check_mem(
1779 sctx
, si_resource(buffer
),
1781 RADEON_PRIO_SAMPLER_BUFFER
, true);
1786 /* Bindless image handles */
1787 if (!buffer
|| buffer
->image_handle_allocated
) {
1788 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1790 util_dynarray_foreach(&sctx
->resident_img_handles
,
1791 struct si_image_handle
*, img_handle
) {
1792 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1793 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1794 struct pipe_resource
*buffer
= view
->resource
;
1796 if (buffer
&& (!buf
|| buffer
== buf
)) {
1797 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
1798 si_mark_image_range_valid(view
);
1800 si_set_buf_desc_address(si_resource(buffer
),
1803 desc_slot
* 16 + 4);
1805 (*img_handle
)->desc_dirty
= true;
1806 sctx
->bindless_descriptors_dirty
= true;
1808 radeon_add_to_gfx_buffer_list_check_mem(
1809 sctx
, si_resource(buffer
),
1810 RADEON_USAGE_READWRITE
,
1811 RADEON_PRIO_SAMPLER_BUFFER
, true);
1817 /* Do the same for other contexts. They will invoke this function
1818 * with buffer == NULL.
1820 unsigned new_counter
= p_atomic_inc_return(&sctx
->screen
->dirty_buf_counter
);
1822 /* Skip the update for the current context, because we have already updated
1823 * the buffer bindings.
1825 if (new_counter
== sctx
->last_dirty_buf_counter
+ 1)
1826 sctx
->last_dirty_buf_counter
= new_counter
;
1830 static void si_upload_bindless_descriptor(struct si_context
*sctx
,
1832 unsigned num_dwords
)
1834 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1835 unsigned desc_slot_offset
= desc_slot
* 16;
1839 data
= desc
->list
+ desc_slot_offset
;
1840 va
= desc
->gpu_address
+ desc_slot_offset
* 4;
1842 si_cp_write_data(sctx
, desc
->buffer
, va
- desc
->buffer
->gpu_address
,
1843 num_dwords
* 4, V_370_TC_L2
, V_370_ME
, data
);
1846 static void si_upload_bindless_descriptors(struct si_context
*sctx
)
1848 if (!sctx
->bindless_descriptors_dirty
)
1851 /* Wait for graphics/compute to be idle before updating the resident
1852 * descriptors directly in memory, in case the GPU is using them.
1854 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
1855 SI_CONTEXT_CS_PARTIAL_FLUSH
;
1856 si_emit_cache_flush(sctx
);
1858 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1859 struct si_texture_handle
*, tex_handle
) {
1860 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1862 if (!(*tex_handle
)->desc_dirty
)
1865 si_upload_bindless_descriptor(sctx
, desc_slot
, 16);
1866 (*tex_handle
)->desc_dirty
= false;
1869 util_dynarray_foreach(&sctx
->resident_img_handles
,
1870 struct si_image_handle
*, img_handle
) {
1871 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1873 if (!(*img_handle
)->desc_dirty
)
1876 si_upload_bindless_descriptor(sctx
, desc_slot
, 8);
1877 (*img_handle
)->desc_dirty
= false;
1880 /* Invalidate L1 because it doesn't know that L2 changed. */
1881 sctx
->flags
|= SI_CONTEXT_INV_SMEM_L1
;
1882 si_emit_cache_flush(sctx
);
1884 sctx
->bindless_descriptors_dirty
= false;
1887 /* Update mutable image descriptor fields of all resident textures. */
1888 static void si_update_bindless_texture_descriptor(struct si_context
*sctx
,
1889 struct si_texture_handle
*tex_handle
)
1891 struct si_sampler_view
*sview
= (struct si_sampler_view
*)tex_handle
->view
;
1892 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1893 unsigned desc_slot_offset
= tex_handle
->desc_slot
* 16;
1894 uint32_t desc_list
[16];
1896 if (sview
->base
.texture
->target
== PIPE_BUFFER
)
1899 memcpy(desc_list
, desc
->list
+ desc_slot_offset
, sizeof(desc_list
));
1900 si_set_sampler_view_desc(sctx
, sview
, &tex_handle
->sstate
,
1901 desc
->list
+ desc_slot_offset
);
1903 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1904 sizeof(desc_list
))) {
1905 tex_handle
->desc_dirty
= true;
1906 sctx
->bindless_descriptors_dirty
= true;
1910 static void si_update_bindless_image_descriptor(struct si_context
*sctx
,
1911 struct si_image_handle
*img_handle
)
1913 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1914 unsigned desc_slot_offset
= img_handle
->desc_slot
* 16;
1915 struct pipe_image_view
*view
= &img_handle
->view
;
1916 uint32_t desc_list
[8];
1918 if (view
->resource
->target
== PIPE_BUFFER
)
1921 memcpy(desc_list
, desc
->list
+ desc_slot_offset
,
1923 si_set_shader_image_desc(sctx
, view
, true,
1924 desc
->list
+ desc_slot_offset
, NULL
);
1926 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1927 sizeof(desc_list
))) {
1928 img_handle
->desc_dirty
= true;
1929 sctx
->bindless_descriptors_dirty
= true;
1933 static void si_update_all_resident_texture_descriptors(struct si_context
*sctx
)
1935 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1936 struct si_texture_handle
*, tex_handle
) {
1937 si_update_bindless_texture_descriptor(sctx
, *tex_handle
);
1940 util_dynarray_foreach(&sctx
->resident_img_handles
,
1941 struct si_image_handle
*, img_handle
) {
1942 si_update_bindless_image_descriptor(sctx
, *img_handle
);
1945 si_upload_bindless_descriptors(sctx
);
1948 /* Update mutable image descriptor fields of all bound textures. */
1949 void si_update_all_texture_descriptors(struct si_context
*sctx
)
1953 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1954 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1955 struct si_images
*images
= &sctx
->images
[shader
];
1959 mask
= images
->enabled_mask
;
1961 unsigned i
= u_bit_scan(&mask
);
1962 struct pipe_image_view
*view
= &images
->views
[i
];
1964 if (!view
->resource
||
1965 view
->resource
->target
== PIPE_BUFFER
)
1968 si_set_shader_image(sctx
, shader
, i
, view
, true);
1971 /* Sampler views. */
1972 mask
= samplers
->enabled_mask
;
1974 unsigned i
= u_bit_scan(&mask
);
1975 struct pipe_sampler_view
*view
= samplers
->views
[i
];
1979 view
->texture
->target
== PIPE_BUFFER
)
1982 si_set_sampler_view(sctx
, shader
, i
,
1983 samplers
->views
[i
], true);
1986 si_update_shader_needs_decompress_mask(sctx
, shader
);
1989 si_update_all_resident_texture_descriptors(sctx
);
1990 si_update_ps_colorbuf0_slot(sctx
);
1993 /* SHADER USER DATA */
1995 static void si_mark_shader_pointers_dirty(struct si_context
*sctx
,
1998 sctx
->shader_pointers_dirty
|=
1999 u_bit_consecutive(SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
,
2000 SI_NUM_SHADER_DESCS
);
2002 if (shader
== PIPE_SHADER_VERTEX
)
2003 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
2005 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
2008 static void si_shader_pointers_begin_new_cs(struct si_context
*sctx
)
2010 sctx
->shader_pointers_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2011 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
2012 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
2013 sctx
->graphics_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
2014 sctx
->compute_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
2017 /* Set a base register address for user data constants in the given shader.
2018 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
2020 static void si_set_user_data_base(struct si_context
*sctx
,
2021 unsigned shader
, uint32_t new_base
)
2023 uint32_t *base
= &sctx
->shader_pointers
.sh_base
[shader
];
2025 if (*base
!= new_base
) {
2029 si_mark_shader_pointers_dirty(sctx
, shader
);
2031 /* Any change in enabled shader stages requires re-emitting
2032 * the VS state SGPR, because it contains the clamp_vertex_color
2033 * state, which can be done in VS, TES, and GS.
2035 sctx
->last_vs_state
= ~0;
2039 /* This must be called when these shaders are changed from non-NULL to NULL
2042 * - tessellation control shader
2043 * - tessellation evaluation shader
2045 void si_shader_change_notify(struct si_context
*sctx
)
2047 /* VS can be bound as VS, ES, or LS. */
2048 if (sctx
->tes_shader
.cso
) {
2049 if (sctx
->chip_class
>= GFX9
) {
2050 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2051 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2053 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2054 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2056 } else if (sctx
->gs_shader
.cso
) {
2057 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2058 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2060 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2061 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2064 /* TES can be bound as ES, VS, or not bound. */
2065 if (sctx
->tes_shader
.cso
) {
2066 if (sctx
->gs_shader
.cso
)
2067 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
2068 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2070 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
2071 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2073 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, 0);
2077 static void si_emit_shader_pointer_head(struct radeon_cmdbuf
*cs
,
2079 unsigned pointer_count
)
2081 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
, 0));
2082 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
2085 static void si_emit_shader_pointer_body(struct si_screen
*sscreen
,
2086 struct radeon_cmdbuf
*cs
,
2089 radeon_emit(cs
, va
);
2091 assert(va
== 0 || (va
>> 32) == sscreen
->info
.address32_hi
);
2094 static void si_emit_shader_pointer(struct si_context
*sctx
,
2095 struct si_descriptors
*desc
,
2098 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2099 unsigned sh_offset
= sh_base
+ desc
->shader_userdata_offset
;
2101 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2102 si_emit_shader_pointer_body(sctx
->screen
, cs
, desc
->gpu_address
);
2105 static void si_emit_consecutive_shader_pointers(struct si_context
*sctx
,
2106 unsigned pointer_mask
,
2112 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2113 unsigned mask
= sctx
->shader_pointers_dirty
& pointer_mask
;
2117 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
2119 struct si_descriptors
*descs
= &sctx
->descriptors
[start
];
2120 unsigned sh_offset
= sh_base
+ descs
->shader_userdata_offset
;
2122 si_emit_shader_pointer_head(cs
, sh_offset
, count
);
2123 for (int i
= 0; i
< count
; i
++)
2124 si_emit_shader_pointer_body(sctx
->screen
, cs
,
2125 descs
[i
].gpu_address
);
2129 static void si_emit_global_shader_pointers(struct si_context
*sctx
,
2130 struct si_descriptors
*descs
)
2132 if (sctx
->chip_class
== GFX9
) {
2133 /* Broadcast it to all shader stages. */
2134 si_emit_shader_pointer(sctx
, descs
,
2135 R_00B530_SPI_SHADER_USER_DATA_COMMON_0
);
2139 si_emit_shader_pointer(sctx
, descs
,
2140 R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2141 si_emit_shader_pointer(sctx
, descs
,
2142 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2143 si_emit_shader_pointer(sctx
, descs
,
2144 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2145 si_emit_shader_pointer(sctx
, descs
,
2146 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2147 si_emit_shader_pointer(sctx
, descs
,
2148 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2149 si_emit_shader_pointer(sctx
, descs
,
2150 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2153 void si_emit_graphics_shader_pointers(struct si_context
*sctx
)
2155 uint32_t *sh_base
= sctx
->shader_pointers
.sh_base
;
2157 if (sctx
->shader_pointers_dirty
& (1 << SI_DESCS_RW_BUFFERS
)) {
2158 si_emit_global_shader_pointers(sctx
,
2159 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2162 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(VERTEX
),
2163 sh_base
[PIPE_SHADER_VERTEX
]);
2164 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_EVAL
),
2165 sh_base
[PIPE_SHADER_TESS_EVAL
]);
2166 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(FRAGMENT
),
2167 sh_base
[PIPE_SHADER_FRAGMENT
]);
2168 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_CTRL
),
2169 sh_base
[PIPE_SHADER_TESS_CTRL
]);
2170 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(GEOMETRY
),
2171 sh_base
[PIPE_SHADER_GEOMETRY
]);
2173 sctx
->shader_pointers_dirty
&=
2174 ~u_bit_consecutive(SI_DESCS_RW_BUFFERS
, SI_DESCS_FIRST_COMPUTE
);
2176 if (sctx
->vertex_buffer_pointer_dirty
) {
2177 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2179 /* Find the location of the VB descriptor pointer. */
2180 /* TODO: In the future, the pointer will be packed in unused
2181 * bits of the first 2 VB descriptors. */
2182 unsigned sh_dw_offset
= SI_VS_NUM_USER_SGPR
;
2183 if (sctx
->chip_class
>= GFX9
) {
2184 if (sctx
->tes_shader
.cso
)
2185 sh_dw_offset
= GFX9_TCS_NUM_USER_SGPR
;
2186 else if (sctx
->gs_shader
.cso
)
2187 sh_dw_offset
= GFX9_VSGS_NUM_USER_SGPR
;
2190 unsigned sh_offset
= sh_base
[PIPE_SHADER_VERTEX
] + sh_dw_offset
* 4;
2191 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2192 si_emit_shader_pointer_body(sctx
->screen
, cs
,
2193 sctx
->vb_descriptors_buffer
->gpu_address
+
2194 sctx
->vb_descriptors_offset
);
2195 sctx
->vertex_buffer_pointer_dirty
= false;
2198 if (sctx
->graphics_bindless_pointer_dirty
) {
2199 si_emit_global_shader_pointers(sctx
,
2200 &sctx
->bindless_descriptors
);
2201 sctx
->graphics_bindless_pointer_dirty
= false;
2205 void si_emit_compute_shader_pointers(struct si_context
*sctx
)
2207 unsigned base
= R_00B900_COMPUTE_USER_DATA_0
;
2209 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(COMPUTE
),
2210 R_00B900_COMPUTE_USER_DATA_0
);
2211 sctx
->shader_pointers_dirty
&= ~SI_DESCS_SHADER_MASK(COMPUTE
);
2213 if (sctx
->compute_bindless_pointer_dirty
) {
2214 si_emit_shader_pointer(sctx
, &sctx
->bindless_descriptors
, base
);
2215 sctx
->compute_bindless_pointer_dirty
= false;
2221 static void si_init_bindless_descriptors(struct si_context
*sctx
,
2222 struct si_descriptors
*desc
,
2223 short shader_userdata_rel_index
,
2224 unsigned num_elements
)
2226 MAYBE_UNUSED
unsigned desc_slot
;
2228 si_init_descriptors(desc
, shader_userdata_rel_index
, 16, num_elements
);
2229 sctx
->bindless_descriptors
.num_active_slots
= num_elements
;
2231 /* The first bindless descriptor is stored at slot 1, because 0 is not
2232 * considered to be a valid handle.
2234 sctx
->num_bindless_descriptors
= 1;
2236 /* Track which bindless slots are used (or not). */
2237 util_idalloc_init(&sctx
->bindless_used_slots
);
2238 util_idalloc_resize(&sctx
->bindless_used_slots
, num_elements
);
2240 /* Reserve slot 0 because it's an invalid handle for bindless. */
2241 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2242 assert(desc_slot
== 0);
2245 static void si_release_bindless_descriptors(struct si_context
*sctx
)
2247 si_release_descriptors(&sctx
->bindless_descriptors
);
2248 util_idalloc_fini(&sctx
->bindless_used_slots
);
2251 static unsigned si_get_first_free_bindless_slot(struct si_context
*sctx
)
2253 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2256 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2257 if (desc_slot
>= desc
->num_elements
) {
2258 /* The array of bindless descriptors is full, resize it. */
2259 unsigned slot_size
= desc
->element_dw_size
* 4;
2260 unsigned new_num_elements
= desc
->num_elements
* 2;
2262 desc
->list
= REALLOC(desc
->list
, desc
->num_elements
* slot_size
,
2263 new_num_elements
* slot_size
);
2264 desc
->num_elements
= new_num_elements
;
2265 desc
->num_active_slots
= new_num_elements
;
2273 si_create_bindless_descriptor(struct si_context
*sctx
, uint32_t *desc_list
,
2276 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2277 unsigned desc_slot
, desc_slot_offset
;
2279 /* Find a free slot. */
2280 desc_slot
= si_get_first_free_bindless_slot(sctx
);
2282 /* For simplicity, sampler and image bindless descriptors use fixed
2283 * 16-dword slots for now. Image descriptors only need 8-dword but this
2284 * doesn't really matter because no real apps use image handles.
2286 desc_slot_offset
= desc_slot
* 16;
2288 /* Copy the descriptor into the array. */
2289 memcpy(desc
->list
+ desc_slot_offset
, desc_list
, size
);
2291 /* Re-upload the whole array of bindless descriptors into a new buffer.
2293 if (!si_upload_descriptors(sctx
, desc
))
2296 /* Make sure to re-emit the shader pointers for all stages. */
2297 sctx
->graphics_bindless_pointer_dirty
= true;
2298 sctx
->compute_bindless_pointer_dirty
= true;
2303 static void si_update_bindless_buffer_descriptor(struct si_context
*sctx
,
2305 struct pipe_resource
*resource
,
2309 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2310 struct si_resource
*buf
= si_resource(resource
);
2311 unsigned desc_slot_offset
= desc_slot
* 16;
2312 uint32_t *desc_list
= desc
->list
+ desc_slot_offset
+ 4;
2313 uint64_t old_desc_va
;
2315 assert(resource
->target
== PIPE_BUFFER
);
2317 /* Retrieve the old buffer addr from the descriptor. */
2318 old_desc_va
= si_desc_extract_buffer_address(desc_list
);
2320 if (old_desc_va
!= buf
->gpu_address
+ offset
) {
2321 /* The buffer has been invalidated when the handle wasn't
2322 * resident, update the descriptor and the dirty flag.
2324 si_set_buf_desc_address(buf
, offset
, &desc_list
[0]);
2330 static uint64_t si_create_texture_handle(struct pipe_context
*ctx
,
2331 struct pipe_sampler_view
*view
,
2332 const struct pipe_sampler_state
*state
)
2334 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
2335 struct si_context
*sctx
= (struct si_context
*)ctx
;
2336 struct si_texture_handle
*tex_handle
;
2337 struct si_sampler_state
*sstate
;
2338 uint32_t desc_list
[16];
2341 tex_handle
= CALLOC_STRUCT(si_texture_handle
);
2345 memset(desc_list
, 0, sizeof(desc_list
));
2346 si_init_descriptor_list(&desc_list
[0], 16, 1, null_texture_descriptor
);
2348 sstate
= ctx
->create_sampler_state(ctx
, state
);
2354 si_set_sampler_view_desc(sctx
, sview
, sstate
, &desc_list
[0]);
2355 memcpy(&tex_handle
->sstate
, sstate
, sizeof(*sstate
));
2356 ctx
->delete_sampler_state(ctx
, sstate
);
2358 tex_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2360 if (!tex_handle
->desc_slot
) {
2365 handle
= tex_handle
->desc_slot
;
2367 if (!_mesa_hash_table_insert(sctx
->tex_handles
,
2368 (void *)(uintptr_t)handle
,
2374 pipe_sampler_view_reference(&tex_handle
->view
, view
);
2376 si_resource(sview
->base
.texture
)->texture_handle_allocated
= true;
2381 static void si_delete_texture_handle(struct pipe_context
*ctx
, uint64_t handle
)
2383 struct si_context
*sctx
= (struct si_context
*)ctx
;
2384 struct si_texture_handle
*tex_handle
;
2385 struct hash_entry
*entry
;
2387 entry
= _mesa_hash_table_search(sctx
->tex_handles
,
2388 (void *)(uintptr_t)handle
);
2392 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2394 /* Allow this descriptor slot to be re-used. */
2395 util_idalloc_free(&sctx
->bindless_used_slots
, tex_handle
->desc_slot
);
2397 pipe_sampler_view_reference(&tex_handle
->view
, NULL
);
2398 _mesa_hash_table_remove(sctx
->tex_handles
, entry
);
2402 static void si_make_texture_handle_resident(struct pipe_context
*ctx
,
2403 uint64_t handle
, bool resident
)
2405 struct si_context
*sctx
= (struct si_context
*)ctx
;
2406 struct si_texture_handle
*tex_handle
;
2407 struct si_sampler_view
*sview
;
2408 struct hash_entry
*entry
;
2410 entry
= _mesa_hash_table_search(sctx
->tex_handles
,
2411 (void *)(uintptr_t)handle
);
2415 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2416 sview
= (struct si_sampler_view
*)tex_handle
->view
;
2419 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2420 struct si_texture
*tex
=
2421 (struct si_texture
*)sview
->base
.texture
;
2423 if (depth_needs_decompression(tex
)) {
2424 util_dynarray_append(
2425 &sctx
->resident_tex_needs_depth_decompress
,
2426 struct si_texture_handle
*,
2430 if (color_needs_decompression(tex
)) {
2431 util_dynarray_append(
2432 &sctx
->resident_tex_needs_color_decompress
,
2433 struct si_texture_handle
*,
2437 if (tex
->dcc_offset
&&
2438 p_atomic_read(&tex
->framebuffers_bound
))
2439 sctx
->need_check_render_feedback
= true;
2441 si_update_bindless_texture_descriptor(sctx
, tex_handle
);
2443 si_update_bindless_buffer_descriptor(sctx
,
2444 tex_handle
->desc_slot
,
2445 sview
->base
.texture
,
2446 sview
->base
.u
.buf
.offset
,
2447 &tex_handle
->desc_dirty
);
2450 /* Re-upload the descriptor if it has been updated while it
2453 if (tex_handle
->desc_dirty
)
2454 sctx
->bindless_descriptors_dirty
= true;
2456 /* Add the texture handle to the per-context list. */
2457 util_dynarray_append(&sctx
->resident_tex_handles
,
2458 struct si_texture_handle
*, tex_handle
);
2460 /* Add the buffers to the current CS in case si_begin_new_cs()
2461 * is not going to be called.
2463 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2465 sview
->is_stencil_sampler
, false);
2467 /* Remove the texture handle from the per-context list. */
2468 util_dynarray_delete_unordered(&sctx
->resident_tex_handles
,
2469 struct si_texture_handle
*,
2472 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2473 util_dynarray_delete_unordered(
2474 &sctx
->resident_tex_needs_depth_decompress
,
2475 struct si_texture_handle
*, tex_handle
);
2477 util_dynarray_delete_unordered(
2478 &sctx
->resident_tex_needs_color_decompress
,
2479 struct si_texture_handle
*, tex_handle
);
2484 static uint64_t si_create_image_handle(struct pipe_context
*ctx
,
2485 const struct pipe_image_view
*view
)
2487 struct si_context
*sctx
= (struct si_context
*)ctx
;
2488 struct si_image_handle
*img_handle
;
2489 uint32_t desc_list
[8];
2492 if (!view
|| !view
->resource
)
2495 img_handle
= CALLOC_STRUCT(si_image_handle
);
2499 memset(desc_list
, 0, sizeof(desc_list
));
2500 si_init_descriptor_list(&desc_list
[0], 8, 1, null_image_descriptor
);
2502 si_set_shader_image_desc(sctx
, view
, false, &desc_list
[0], NULL
);
2504 img_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2506 if (!img_handle
->desc_slot
) {
2511 handle
= img_handle
->desc_slot
;
2513 if (!_mesa_hash_table_insert(sctx
->img_handles
,
2514 (void *)(uintptr_t)handle
,
2520 util_copy_image_view(&img_handle
->view
, view
);
2522 si_resource(view
->resource
)->image_handle_allocated
= true;
2527 static void si_delete_image_handle(struct pipe_context
*ctx
, uint64_t handle
)
2529 struct si_context
*sctx
= (struct si_context
*)ctx
;
2530 struct si_image_handle
*img_handle
;
2531 struct hash_entry
*entry
;
2533 entry
= _mesa_hash_table_search(sctx
->img_handles
,
2534 (void *)(uintptr_t)handle
);
2538 img_handle
= (struct si_image_handle
*)entry
->data
;
2540 util_copy_image_view(&img_handle
->view
, NULL
);
2541 _mesa_hash_table_remove(sctx
->img_handles
, entry
);
2545 static void si_make_image_handle_resident(struct pipe_context
*ctx
,
2546 uint64_t handle
, unsigned access
,
2549 struct si_context
*sctx
= (struct si_context
*)ctx
;
2550 struct si_image_handle
*img_handle
;
2551 struct pipe_image_view
*view
;
2552 struct si_resource
*res
;
2553 struct hash_entry
*entry
;
2555 entry
= _mesa_hash_table_search(sctx
->img_handles
,
2556 (void *)(uintptr_t)handle
);
2560 img_handle
= (struct si_image_handle
*)entry
->data
;
2561 view
= &img_handle
->view
;
2562 res
= si_resource(view
->resource
);
2565 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2566 struct si_texture
*tex
= (struct si_texture
*)res
;
2567 unsigned level
= view
->u
.tex
.level
;
2569 if (color_needs_decompression(tex
)) {
2570 util_dynarray_append(
2571 &sctx
->resident_img_needs_color_decompress
,
2572 struct si_image_handle
*,
2576 if (vi_dcc_enabled(tex
, level
) &&
2577 p_atomic_read(&tex
->framebuffers_bound
))
2578 sctx
->need_check_render_feedback
= true;
2580 si_update_bindless_image_descriptor(sctx
, img_handle
);
2582 si_update_bindless_buffer_descriptor(sctx
,
2583 img_handle
->desc_slot
,
2586 &img_handle
->desc_dirty
);
2589 /* Re-upload the descriptor if it has been updated while it
2592 if (img_handle
->desc_dirty
)
2593 sctx
->bindless_descriptors_dirty
= true;
2595 /* Add the image handle to the per-context list. */
2596 util_dynarray_append(&sctx
->resident_img_handles
,
2597 struct si_image_handle
*, img_handle
);
2599 /* Add the buffers to the current CS in case si_begin_new_cs()
2600 * is not going to be called.
2602 si_sampler_view_add_buffer(sctx
, view
->resource
,
2603 (access
& PIPE_IMAGE_ACCESS_WRITE
) ?
2604 RADEON_USAGE_READWRITE
:
2605 RADEON_USAGE_READ
, false, false);
2607 /* Remove the image handle from the per-context list. */
2608 util_dynarray_delete_unordered(&sctx
->resident_img_handles
,
2609 struct si_image_handle
*,
2612 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2613 util_dynarray_delete_unordered(
2614 &sctx
->resident_img_needs_color_decompress
,
2615 struct si_image_handle
*,
2621 static void si_resident_buffers_add_all_to_bo_list(struct si_context
*sctx
)
2623 unsigned num_resident_tex_handles
, num_resident_img_handles
;
2625 num_resident_tex_handles
= sctx
->resident_tex_handles
.size
/
2626 sizeof(struct si_texture_handle
*);
2627 num_resident_img_handles
= sctx
->resident_img_handles
.size
/
2628 sizeof(struct si_image_handle
*);
2630 /* Add all resident texture handles. */
2631 util_dynarray_foreach(&sctx
->resident_tex_handles
,
2632 struct si_texture_handle
*, tex_handle
) {
2633 struct si_sampler_view
*sview
=
2634 (struct si_sampler_view
*)(*tex_handle
)->view
;
2636 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2638 sview
->is_stencil_sampler
, false);
2641 /* Add all resident image handles. */
2642 util_dynarray_foreach(&sctx
->resident_img_handles
,
2643 struct si_image_handle
*, img_handle
) {
2644 struct pipe_image_view
*view
= &(*img_handle
)->view
;
2646 si_sampler_view_add_buffer(sctx
, view
->resource
,
2647 RADEON_USAGE_READWRITE
,
2651 sctx
->num_resident_handles
+= num_resident_tex_handles
+
2652 num_resident_img_handles
;
2653 assert(sctx
->bo_list_add_all_resident_resources
);
2654 sctx
->bo_list_add_all_resident_resources
= false;
2657 /* INIT/DEINIT/UPLOAD */
2659 void si_init_all_descriptors(struct si_context
*sctx
)
2662 unsigned first_shader
=
2663 sctx
->has_graphics
? 0 : PIPE_SHADER_COMPUTE
;
2665 for (i
= first_shader
; i
< SI_NUM_SHADERS
; i
++) {
2666 bool is_2nd
= sctx
->chip_class
>= GFX9
&&
2667 (i
== PIPE_SHADER_TESS_CTRL
||
2668 i
== PIPE_SHADER_GEOMETRY
);
2669 unsigned num_sampler_slots
= SI_NUM_IMAGES
/ 2 + SI_NUM_SAMPLERS
;
2670 unsigned num_buffer_slots
= SI_NUM_SHADER_BUFFERS
+ SI_NUM_CONST_BUFFERS
;
2672 struct si_descriptors
*desc
;
2675 if (i
== PIPE_SHADER_TESS_CTRL
) {
2676 rel_dw_offset
= (R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
-
2677 R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2678 } else { /* PIPE_SHADER_GEOMETRY */
2679 rel_dw_offset
= (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
-
2680 R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2683 rel_dw_offset
= SI_SGPR_CONST_AND_SHADER_BUFFERS
;
2685 desc
= si_const_and_shader_buffer_descriptors(sctx
, i
);
2686 si_init_buffer_resources(&sctx
->const_and_shader_buffers
[i
], desc
,
2687 num_buffer_slots
, rel_dw_offset
,
2688 RADEON_PRIO_SHADER_RW_BUFFER
,
2689 RADEON_PRIO_CONST_BUFFER
);
2690 desc
->slot_index_to_bind_directly
= si_get_constbuf_slot(0);
2693 if (i
== PIPE_SHADER_TESS_CTRL
) {
2694 rel_dw_offset
= (R_00B40C_SPI_SHADER_USER_DATA_ADDR_HI_HS
-
2695 R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2696 } else { /* PIPE_SHADER_GEOMETRY */
2697 rel_dw_offset
= (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS
-
2698 R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2701 rel_dw_offset
= SI_SGPR_SAMPLERS_AND_IMAGES
;
2704 desc
= si_sampler_and_image_descriptors(sctx
, i
);
2705 si_init_descriptors(desc
, rel_dw_offset
, 16, num_sampler_slots
);
2708 for (j
= 0; j
< SI_NUM_IMAGES
; j
++)
2709 memcpy(desc
->list
+ j
* 8, null_image_descriptor
, 8 * 4);
2710 for (; j
< SI_NUM_IMAGES
+ SI_NUM_SAMPLERS
* 2; j
++)
2711 memcpy(desc
->list
+ j
* 8, null_texture_descriptor
, 8 * 4);
2714 si_init_buffer_resources(&sctx
->rw_buffers
,
2715 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
],
2716 SI_NUM_RW_BUFFERS
, SI_SGPR_RW_BUFFERS
,
2717 /* The second priority is used by
2718 * const buffers in RW buffer slots. */
2719 RADEON_PRIO_SHADER_RINGS
, RADEON_PRIO_CONST_BUFFER
);
2720 sctx
->descriptors
[SI_DESCS_RW_BUFFERS
].num_active_slots
= SI_NUM_RW_BUFFERS
;
2722 /* Initialize an array of 1024 bindless descriptors, when the limit is
2723 * reached, just make it larger and re-upload the whole array.
2725 si_init_bindless_descriptors(sctx
, &sctx
->bindless_descriptors
,
2726 SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES
,
2729 sctx
->descriptors_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2731 /* Set pipe_context functions. */
2732 sctx
->b
.bind_sampler_states
= si_bind_sampler_states
;
2733 sctx
->b
.set_shader_images
= si_set_shader_images
;
2734 sctx
->b
.set_constant_buffer
= si_pipe_set_constant_buffer
;
2735 sctx
->b
.set_shader_buffers
= si_set_shader_buffers
;
2736 sctx
->b
.set_sampler_views
= si_set_sampler_views
;
2737 sctx
->b
.create_texture_handle
= si_create_texture_handle
;
2738 sctx
->b
.delete_texture_handle
= si_delete_texture_handle
;
2739 sctx
->b
.make_texture_handle_resident
= si_make_texture_handle_resident
;
2740 sctx
->b
.create_image_handle
= si_create_image_handle
;
2741 sctx
->b
.delete_image_handle
= si_delete_image_handle
;
2742 sctx
->b
.make_image_handle_resident
= si_make_image_handle_resident
;
2744 if (!sctx
->has_graphics
)
2747 sctx
->b
.set_polygon_stipple
= si_set_polygon_stipple
;
2749 /* Shader user data. */
2750 sctx
->atoms
.s
.shader_pointers
.emit
= si_emit_graphics_shader_pointers
;
2752 /* Set default and immutable mappings. */
2753 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2755 if (sctx
->chip_class
>= GFX9
) {
2756 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2757 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2758 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2759 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2761 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2762 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2763 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2764 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2766 si_set_user_data_base(sctx
, PIPE_SHADER_FRAGMENT
, R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2769 static bool si_upload_shader_descriptors(struct si_context
*sctx
, unsigned mask
)
2771 unsigned dirty
= sctx
->descriptors_dirty
& mask
;
2773 /* Assume nothing will go wrong: */
2774 sctx
->shader_pointers_dirty
|= dirty
;
2777 unsigned i
= u_bit_scan(&dirty
);
2779 if (!si_upload_descriptors(sctx
, &sctx
->descriptors
[i
]))
2783 sctx
->descriptors_dirty
&= ~mask
;
2785 si_upload_bindless_descriptors(sctx
);
2790 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
)
2792 const unsigned mask
= u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE
);
2793 return si_upload_shader_descriptors(sctx
, mask
);
2796 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
)
2798 /* Does not update rw_buffers as that is not needed for compute shaders
2799 * and the input buffer is using the same SGPR's anyway.
2801 const unsigned mask
= u_bit_consecutive(SI_DESCS_FIRST_COMPUTE
,
2802 SI_NUM_DESCS
- SI_DESCS_FIRST_COMPUTE
);
2803 return si_upload_shader_descriptors(sctx
, mask
);
2806 void si_release_all_descriptors(struct si_context
*sctx
)
2810 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2811 si_release_buffer_resources(&sctx
->const_and_shader_buffers
[i
],
2812 si_const_and_shader_buffer_descriptors(sctx
, i
));
2813 si_release_sampler_views(&sctx
->samplers
[i
]);
2814 si_release_image_views(&sctx
->images
[i
]);
2816 si_release_buffer_resources(&sctx
->rw_buffers
,
2817 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2818 for (i
= 0; i
< SI_NUM_VERTEX_BUFFERS
; i
++)
2819 pipe_vertex_buffer_unreference(&sctx
->vertex_buffer
[i
]);
2821 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2822 si_release_descriptors(&sctx
->descriptors
[i
]);
2824 si_resource_reference(&sctx
->vb_descriptors_buffer
, NULL
);
2825 sctx
->vb_descriptors_gpu_list
= NULL
; /* points into a mapped buffer */
2827 si_release_bindless_descriptors(sctx
);
2830 void si_gfx_resources_add_all_to_bo_list(struct si_context
*sctx
)
2832 for (unsigned i
= 0; i
< SI_NUM_GRAPHICS_SHADERS
; i
++) {
2833 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[i
]);
2834 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[i
]);
2835 si_image_views_begin_new_cs(sctx
, &sctx
->images
[i
]);
2837 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2838 si_vertex_buffers_begin_new_cs(sctx
);
2840 if (sctx
->bo_list_add_all_resident_resources
)
2841 si_resident_buffers_add_all_to_bo_list(sctx
);
2843 assert(sctx
->bo_list_add_all_gfx_resources
);
2844 sctx
->bo_list_add_all_gfx_resources
= false;
2847 void si_compute_resources_add_all_to_bo_list(struct si_context
*sctx
)
2849 unsigned sh
= PIPE_SHADER_COMPUTE
;
2851 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[sh
]);
2852 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[sh
]);
2853 si_image_views_begin_new_cs(sctx
, &sctx
->images
[sh
]);
2854 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2856 if (sctx
->bo_list_add_all_resident_resources
)
2857 si_resident_buffers_add_all_to_bo_list(sctx
);
2859 assert(sctx
->bo_list_add_all_compute_resources
);
2860 sctx
->bo_list_add_all_compute_resources
= false;
2863 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
)
2865 for (unsigned i
= 0; i
< SI_NUM_DESCS
; ++i
)
2866 si_descriptors_begin_new_cs(sctx
, &sctx
->descriptors
[i
]);
2867 si_descriptors_begin_new_cs(sctx
, &sctx
->bindless_descriptors
);
2869 si_shader_pointers_begin_new_cs(sctx
);
2871 sctx
->bo_list_add_all_resident_resources
= true;
2872 sctx
->bo_list_add_all_gfx_resources
= true;
2873 sctx
->bo_list_add_all_compute_resources
= true;
2876 void si_set_active_descriptors(struct si_context
*sctx
, unsigned desc_idx
,
2877 uint64_t new_active_mask
)
2879 struct si_descriptors
*desc
= &sctx
->descriptors
[desc_idx
];
2881 /* Ignore no-op updates and updates that disable all slots. */
2882 if (!new_active_mask
||
2883 new_active_mask
== u_bit_consecutive64(desc
->first_active_slot
,
2884 desc
->num_active_slots
))
2888 u_bit_scan_consecutive_range64(&new_active_mask
, &first
, &count
);
2889 assert(new_active_mask
== 0);
2891 /* Upload/dump descriptors if slots are being enabled. */
2892 if (first
< desc
->first_active_slot
||
2893 first
+ count
> desc
->first_active_slot
+ desc
->num_active_slots
)
2894 sctx
->descriptors_dirty
|= 1u << desc_idx
;
2896 desc
->first_active_slot
= first
;
2897 desc
->num_active_slots
= count
;
2900 void si_set_active_descriptors_for_shader(struct si_context
*sctx
,
2901 struct si_shader_selector
*sel
)
2906 si_set_active_descriptors(sctx
,
2907 si_const_and_shader_buffer_descriptors_idx(sel
->type
),
2908 sel
->active_const_and_shader_buffers
);
2909 si_set_active_descriptors(sctx
,
2910 si_sampler_and_image_descriptors_idx(sel
->type
),
2911 sel
->active_samplers_and_images
);