2 * Copyright 2013 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 /* Resource binding slots and sampler states (each described with 8 or
26 * 4 dwords) are stored in lists in memory which is accessed by shaders
27 * using scalar load instructions.
29 * This file is responsible for managing such lists. It keeps a copy of all
30 * descriptors in CPU memory and re-uploads a whole list if some slots have
33 * This code is also reponsible for updating shader pointers to those lists.
35 * Note that CP DMA can't be used for updating the lists, because a GPU hang
36 * could leave the list in a mid-IB state and the next IB would get wrong
37 * descriptors and the whole context would be unusable at that point.
38 * (Note: The register shadowing can't be used due to the same reason)
40 * Also, uploading descriptors to newly allocated memory doesn't require
44 * Possible scenarios for one 16 dword image+sampler slot:
46 * | Image | w/ FMASK | Buffer | NULL
47 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
48 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
49 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
50 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
52 * FMASK implies MSAA, therefore no sampler state.
53 * Sampler states are never unbound except when FMASK is bound.
59 #include "util/hash_table.h"
60 #include "util/u_idalloc.h"
61 #include "util/u_format.h"
62 #include "util/u_memory.h"
63 #include "util/u_upload_mgr.h"
66 /* NULL image and buffer descriptor for textures (alpha = 1) and images
69 * For images, all fields must be zero except for the swizzle, which
70 * supports arbitrary combinations of 0s and 1s. The texture type must be
71 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
73 * For buffers, all fields must be zero. If they are not, the hw hangs.
75 * This is the only reason why the buffer descriptor must be in words [4:7].
77 static uint32_t null_texture_descriptor
[8] = {
81 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1
) |
82 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
83 /* the rest must contain zeros, which is also used by the buffer
87 static uint32_t null_image_descriptor
[8] = {
91 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
92 /* the rest must contain zeros, which is also used by the buffer
96 static uint64_t si_desc_extract_buffer_address(const uint32_t *desc
)
98 uint64_t va
= desc
[0] |
99 ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc
[1]) << 32);
101 /* Sign-extend the 48-bit address. */
103 va
= (int64_t)va
>> 16;
107 static void si_init_descriptor_list(uint32_t *desc_list
,
108 unsigned element_dw_size
,
109 unsigned num_elements
,
110 const uint32_t *null_descriptor
)
114 /* Initialize the array to NULL descriptors if the element size is 8. */
115 if (null_descriptor
) {
116 assert(element_dw_size
% 8 == 0);
117 for (i
= 0; i
< num_elements
* element_dw_size
/ 8; i
++)
118 memcpy(desc_list
+ i
* 8, null_descriptor
, 8 * 4);
122 static void si_init_descriptors(struct si_descriptors
*desc
,
123 short shader_userdata_rel_index
,
124 unsigned element_dw_size
,
125 unsigned num_elements
)
127 desc
->list
= CALLOC(num_elements
, element_dw_size
* 4);
128 desc
->element_dw_size
= element_dw_size
;
129 desc
->num_elements
= num_elements
;
130 desc
->shader_userdata_offset
= shader_userdata_rel_index
* 4;
131 desc
->slot_index_to_bind_directly
= -1;
134 static void si_release_descriptors(struct si_descriptors
*desc
)
136 si_resource_reference(&desc
->buffer
, NULL
);
140 static bool si_upload_descriptors(struct si_context
*sctx
,
141 struct si_descriptors
*desc
)
143 unsigned slot_size
= desc
->element_dw_size
* 4;
144 unsigned first_slot_offset
= desc
->first_active_slot
* slot_size
;
145 unsigned upload_size
= desc
->num_active_slots
* slot_size
;
147 /* Skip the upload if no shader is using the descriptors. dirty_mask
148 * will stay dirty and the descriptors will be uploaded when there is
149 * a shader using them.
154 /* If there is just one active descriptor, bind it directly. */
155 if ((int)desc
->first_active_slot
== desc
->slot_index_to_bind_directly
&&
156 desc
->num_active_slots
== 1) {
157 uint32_t *descriptor
= &desc
->list
[desc
->slot_index_to_bind_directly
*
158 desc
->element_dw_size
];
160 /* The buffer is already in the buffer list. */
161 si_resource_reference(&desc
->buffer
, NULL
);
162 desc
->gpu_list
= NULL
;
163 desc
->gpu_address
= si_desc_extract_buffer_address(descriptor
);
164 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
169 unsigned buffer_offset
;
170 u_upload_alloc(sctx
->b
.const_uploader
, first_slot_offset
, upload_size
,
171 si_optimal_tcc_alignment(sctx
, upload_size
),
172 &buffer_offset
, (struct pipe_resource
**)&desc
->buffer
,
175 desc
->gpu_address
= 0;
176 return false; /* skip the draw call */
179 util_memcpy_cpu_to_le32(ptr
, (char*)desc
->list
+ first_slot_offset
,
181 desc
->gpu_list
= ptr
- first_slot_offset
/ 4;
183 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, desc
->buffer
,
184 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
186 /* The shader pointer should point to slot 0. */
187 buffer_offset
-= first_slot_offset
;
188 desc
->gpu_address
= desc
->buffer
->gpu_address
+ buffer_offset
;
190 assert(desc
->buffer
->flags
& RADEON_FLAG_32BIT
);
191 assert((desc
->buffer
->gpu_address
>> 32) == sctx
->screen
->info
.address32_hi
);
192 assert((desc
->gpu_address
>> 32) == sctx
->screen
->info
.address32_hi
);
194 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
199 si_descriptors_begin_new_cs(struct si_context
*sctx
, struct si_descriptors
*desc
)
204 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, desc
->buffer
,
205 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
210 static inline enum radeon_bo_priority
211 si_get_sampler_view_priority(struct si_resource
*res
)
213 if (res
->b
.b
.target
== PIPE_BUFFER
)
214 return RADEON_PRIO_SAMPLER_BUFFER
;
216 if (res
->b
.b
.nr_samples
> 1)
217 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA
;
219 return RADEON_PRIO_SAMPLER_TEXTURE
;
222 static struct si_descriptors
*
223 si_sampler_and_image_descriptors(struct si_context
*sctx
, unsigned shader
)
225 return &sctx
->descriptors
[si_sampler_and_image_descriptors_idx(shader
)];
228 static void si_release_sampler_views(struct si_samplers
*samplers
)
232 for (i
= 0; i
< ARRAY_SIZE(samplers
->views
); i
++) {
233 pipe_sampler_view_reference(&samplers
->views
[i
], NULL
);
237 static void si_sampler_view_add_buffer(struct si_context
*sctx
,
238 struct pipe_resource
*resource
,
239 enum radeon_bo_usage usage
,
240 bool is_stencil_sampler
,
243 struct si_texture
*tex
= (struct si_texture
*)resource
;
244 enum radeon_bo_priority priority
;
249 /* Use the flushed depth texture if direct sampling is unsupported. */
250 if (resource
->target
!= PIPE_BUFFER
&&
251 tex
->is_depth
&& !si_can_sample_zs(tex
, is_stencil_sampler
))
252 tex
= tex
->flushed_depth_texture
;
254 priority
= si_get_sampler_view_priority(&tex
->buffer
);
255 radeon_add_to_gfx_buffer_list_check_mem(sctx
, &tex
->buffer
, usage
, priority
,
258 if (resource
->target
== PIPE_BUFFER
)
261 /* Add separate DCC. */
262 if (tex
->dcc_separate_buffer
) {
263 radeon_add_to_gfx_buffer_list_check_mem(sctx
, tex
->dcc_separate_buffer
,
264 usage
, RADEON_PRIO_SEPARATE_META
, check_mem
);
268 static void si_sampler_views_begin_new_cs(struct si_context
*sctx
,
269 struct si_samplers
*samplers
)
271 unsigned mask
= samplers
->enabled_mask
;
273 /* Add buffers to the CS. */
275 int i
= u_bit_scan(&mask
);
276 struct si_sampler_view
*sview
= (struct si_sampler_view
*)samplers
->views
[i
];
278 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
280 sview
->is_stencil_sampler
, false);
284 /* Set buffer descriptor fields that can be changed by reallocations. */
285 static void si_set_buf_desc_address(struct si_resource
*buf
,
286 uint64_t offset
, uint32_t *state
)
288 uint64_t va
= buf
->gpu_address
+ offset
;
291 state
[1] &= C_008F04_BASE_ADDRESS_HI
;
292 state
[1] |= S_008F04_BASE_ADDRESS_HI(va
>> 32);
295 /* Set texture descriptor fields that can be changed by reallocations.
298 * \param base_level_info information of the level of BASE_ADDRESS
299 * \param base_level the level of BASE_ADDRESS
300 * \param first_level pipe_sampler_view.u.tex.first_level
301 * \param block_width util_format_get_blockwidth()
302 * \param is_stencil select between separate Z & Stencil
303 * \param state descriptor to update
305 void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen
,
306 struct si_texture
*tex
,
307 const struct legacy_surf_level
*base_level_info
,
308 unsigned base_level
, unsigned first_level
,
309 unsigned block_width
, bool is_stencil
,
312 uint64_t va
, meta_va
= 0;
314 if (tex
->is_depth
&& !si_can_sample_zs(tex
, is_stencil
)) {
315 tex
= tex
->flushed_depth_texture
;
319 va
= tex
->buffer
.gpu_address
;
321 if (sscreen
->info
.chip_class
>= GFX9
) {
322 /* Only stencil_offset needs to be added here. */
324 va
+= tex
->surface
.u
.gfx9
.stencil_offset
;
326 va
+= tex
->surface
.u
.gfx9
.surf_offset
;
328 va
+= base_level_info
->offset
;
332 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
333 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
335 /* Only macrotiled modes can set tile swizzle.
336 * GFX9 doesn't use (legacy) base_level_info.
338 if (sscreen
->info
.chip_class
>= GFX9
||
339 base_level_info
->mode
== RADEON_SURF_MODE_2D
)
340 state
[0] |= tex
->surface
.tile_swizzle
;
342 if (sscreen
->info
.chip_class
>= GFX8
) {
343 state
[6] &= C_008F28_COMPRESSION_EN
;
345 if (vi_dcc_enabled(tex
, first_level
)) {
346 meta_va
= (!tex
->dcc_separate_buffer
? tex
->buffer
.gpu_address
: 0) +
347 tex
->surface
.dcc_offset
;
349 if (sscreen
->info
.chip_class
== GFX8
) {
350 meta_va
+= base_level_info
->dcc_offset
;
351 assert(base_level_info
->mode
== RADEON_SURF_MODE_2D
);
354 unsigned dcc_tile_swizzle
= tex
->surface
.tile_swizzle
<< 8;
355 dcc_tile_swizzle
&= tex
->surface
.dcc_alignment
- 1;
356 meta_va
|= dcc_tile_swizzle
;
357 } else if (vi_tc_compat_htile_enabled(tex
, first_level
,
358 is_stencil
? PIPE_MASK_S
: PIPE_MASK_Z
)) {
359 meta_va
= tex
->buffer
.gpu_address
+ tex
->surface
.htile_offset
;
363 state
[6] |= S_008F28_COMPRESSION_EN(1);
366 if (sscreen
->info
.chip_class
>= GFX8
&& sscreen
->info
.chip_class
<= GFX9
)
367 state
[7] = meta_va
>> 8;
369 if (sscreen
->info
.chip_class
>= GFX10
) {
370 state
[3] &= C_00A00C_SW_MODE
;
373 state
[3] |= S_00A00C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
375 state
[3] |= S_00A00C_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
);
378 state
[6] &= C_00A018_META_DATA_ADDRESS_LO
&
379 C_00A018_META_PIPE_ALIGNED
;
382 struct gfx9_surf_meta_flags meta
;
384 if (tex
->surface
.dcc_offset
)
385 meta
= tex
->surface
.u
.gfx9
.dcc
;
387 meta
= tex
->surface
.u
.gfx9
.htile
;
389 state
[6] |= S_00A018_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
390 S_00A018_META_DATA_ADDRESS_LO(meta_va
>> 8);
393 state
[7] = meta_va
>> 16;
394 } else if (sscreen
->info
.chip_class
== GFX9
) {
395 state
[3] &= C_008F1C_SW_MODE
;
396 state
[4] &= C_008F20_PITCH
;
399 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
400 state
[4] |= S_008F20_PITCH(tex
->surface
.u
.gfx9
.stencil
.epitch
);
402 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
);
403 state
[4] |= S_008F20_PITCH(tex
->surface
.u
.gfx9
.surf
.epitch
);
406 state
[5] &= C_008F24_META_DATA_ADDRESS
&
407 C_008F24_META_PIPE_ALIGNED
&
408 C_008F24_META_RB_ALIGNED
;
410 struct gfx9_surf_meta_flags meta
;
412 if (tex
->surface
.dcc_offset
)
413 meta
= tex
->surface
.u
.gfx9
.dcc
;
415 meta
= tex
->surface
.u
.gfx9
.htile
;
417 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
418 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
419 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
423 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
424 unsigned index
= si_tile_mode_index(tex
, base_level
, is_stencil
);
426 state
[3] &= C_008F1C_TILING_INDEX
;
427 state
[3] |= S_008F1C_TILING_INDEX(index
);
428 state
[4] &= C_008F20_PITCH
;
429 state
[4] |= S_008F20_PITCH(pitch
- 1);
433 static void si_set_sampler_state_desc(struct si_sampler_state
*sstate
,
434 struct si_sampler_view
*sview
,
435 struct si_texture
*tex
,
438 if (sview
&& sview
->is_integer
)
439 memcpy(desc
, sstate
->integer_val
, 4*4);
440 else if (tex
&& tex
->upgraded_depth
&&
441 (!sview
|| !sview
->is_stencil_sampler
))
442 memcpy(desc
, sstate
->upgraded_depth_val
, 4*4);
444 memcpy(desc
, sstate
->val
, 4*4);
447 static void si_set_sampler_view_desc(struct si_context
*sctx
,
448 struct si_sampler_view
*sview
,
449 struct si_sampler_state
*sstate
,
452 struct pipe_sampler_view
*view
= &sview
->base
;
453 struct si_texture
*tex
= (struct si_texture
*)view
->texture
;
454 bool is_buffer
= tex
->buffer
.b
.b
.target
== PIPE_BUFFER
;
456 if (unlikely(!is_buffer
&& sview
->dcc_incompatible
)) {
457 if (vi_dcc_enabled(tex
, view
->u
.tex
.first_level
))
458 if (!si_texture_disable_dcc(sctx
, tex
))
459 si_decompress_dcc(sctx
, tex
);
461 sview
->dcc_incompatible
= false;
464 assert(tex
); /* views with texture == NULL aren't supported */
465 memcpy(desc
, sview
->state
, 8*4);
468 si_set_buf_desc_address(&tex
->buffer
,
469 sview
->base
.u
.buf
.offset
,
472 bool is_separate_stencil
= tex
->db_compatible
&&
473 sview
->is_stencil_sampler
;
475 si_set_mutable_tex_desc_fields(sctx
->screen
, tex
,
476 sview
->base_level_info
,
478 sview
->base
.u
.tex
.first_level
,
484 if (!is_buffer
&& tex
->surface
.fmask_size
) {
485 memcpy(desc
+ 8, sview
->fmask_state
, 8*4);
487 /* Disable FMASK and bind sampler state in [12:15]. */
488 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
491 si_set_sampler_state_desc(sstate
, sview
,
492 is_buffer
? NULL
: tex
,
497 static bool color_needs_decompression(struct si_texture
*tex
)
499 return tex
->surface
.fmask_size
||
500 (tex
->dirty_level_mask
&&
501 (tex
->cmask_buffer
|| tex
->surface
.dcc_offset
));
504 static bool depth_needs_decompression(struct si_texture
*tex
)
506 /* If the depth/stencil texture is TC-compatible, no decompression
507 * will be done. The decompression function will only flush DB caches
508 * to make it coherent with shaders. That's necessary because the driver
509 * doesn't flush DB caches in any other case.
511 return tex
->db_compatible
;
514 static void si_set_sampler_view(struct si_context
*sctx
,
516 unsigned slot
, struct pipe_sampler_view
*view
,
517 bool disallow_early_out
)
519 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
520 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
521 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(sctx
, shader
);
522 unsigned desc_slot
= si_get_sampler_slot(slot
);
523 uint32_t *desc
= descs
->list
+ desc_slot
* 16;
525 if (samplers
->views
[slot
] == view
&& !disallow_early_out
)
529 struct si_texture
*tex
= (struct si_texture
*)view
->texture
;
531 si_set_sampler_view_desc(sctx
, sview
,
532 samplers
->sampler_states
[slot
], desc
);
534 if (tex
->buffer
.b
.b
.target
== PIPE_BUFFER
) {
535 tex
->buffer
.bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
536 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
537 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
539 if (depth_needs_decompression(tex
)) {
540 samplers
->needs_depth_decompress_mask
|= 1u << slot
;
542 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
544 if (color_needs_decompression(tex
)) {
545 samplers
->needs_color_decompress_mask
|= 1u << slot
;
547 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
550 if (tex
->surface
.dcc_offset
&&
551 p_atomic_read(&tex
->framebuffers_bound
))
552 sctx
->need_check_render_feedback
= true;
555 pipe_sampler_view_reference(&samplers
->views
[slot
], view
);
556 samplers
->enabled_mask
|= 1u << slot
;
558 /* Since this can flush, it must be done after enabled_mask is
560 si_sampler_view_add_buffer(sctx
, view
->texture
,
562 sview
->is_stencil_sampler
, true);
564 pipe_sampler_view_reference(&samplers
->views
[slot
], NULL
);
565 memcpy(desc
, null_texture_descriptor
, 8*4);
566 /* Only clear the lower dwords of FMASK. */
567 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
568 /* Re-set the sampler state if we are transitioning from FMASK. */
569 if (samplers
->sampler_states
[slot
])
570 si_set_sampler_state_desc(samplers
->sampler_states
[slot
], NULL
, NULL
,
573 samplers
->enabled_mask
&= ~(1u << slot
);
574 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
575 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
578 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
581 static void si_update_shader_needs_decompress_mask(struct si_context
*sctx
,
584 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
585 unsigned shader_bit
= 1 << shader
;
587 if (samplers
->needs_depth_decompress_mask
||
588 samplers
->needs_color_decompress_mask
||
589 sctx
->images
[shader
].needs_color_decompress_mask
)
590 sctx
->shader_needs_decompress_mask
|= shader_bit
;
592 sctx
->shader_needs_decompress_mask
&= ~shader_bit
;
595 static void si_set_sampler_views(struct pipe_context
*ctx
,
596 enum pipe_shader_type shader
, unsigned start
,
598 struct pipe_sampler_view
**views
)
600 struct si_context
*sctx
= (struct si_context
*)ctx
;
603 if (!count
|| shader
>= SI_NUM_SHADERS
)
607 for (i
= 0; i
< count
; i
++)
608 si_set_sampler_view(sctx
, shader
, start
+ i
, views
[i
], false);
610 for (i
= 0; i
< count
; i
++)
611 si_set_sampler_view(sctx
, shader
, start
+ i
, NULL
, false);
614 si_update_shader_needs_decompress_mask(sctx
, shader
);
618 si_samplers_update_needs_color_decompress_mask(struct si_samplers
*samplers
)
620 unsigned mask
= samplers
->enabled_mask
;
623 int i
= u_bit_scan(&mask
);
624 struct pipe_resource
*res
= samplers
->views
[i
]->texture
;
626 if (res
&& res
->target
!= PIPE_BUFFER
) {
627 struct si_texture
*tex
= (struct si_texture
*)res
;
629 if (color_needs_decompression(tex
)) {
630 samplers
->needs_color_decompress_mask
|= 1u << i
;
632 samplers
->needs_color_decompress_mask
&= ~(1u << i
);
641 si_release_image_views(struct si_images
*images
)
645 for (i
= 0; i
< SI_NUM_IMAGES
; ++i
) {
646 struct pipe_image_view
*view
= &images
->views
[i
];
648 pipe_resource_reference(&view
->resource
, NULL
);
653 si_image_views_begin_new_cs(struct si_context
*sctx
, struct si_images
*images
)
655 uint mask
= images
->enabled_mask
;
657 /* Add buffers to the CS. */
659 int i
= u_bit_scan(&mask
);
660 struct pipe_image_view
*view
= &images
->views
[i
];
662 assert(view
->resource
);
664 si_sampler_view_add_buffer(sctx
, view
->resource
,
665 RADEON_USAGE_READWRITE
, false, false);
670 si_disable_shader_image(struct si_context
*ctx
, unsigned shader
, unsigned slot
)
672 struct si_images
*images
= &ctx
->images
[shader
];
674 if (images
->enabled_mask
& (1u << slot
)) {
675 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
676 unsigned desc_slot
= si_get_image_slot(slot
);
678 pipe_resource_reference(&images
->views
[slot
].resource
, NULL
);
679 images
->needs_color_decompress_mask
&= ~(1 << slot
);
681 memcpy(descs
->list
+ desc_slot
*8, null_image_descriptor
, 8*4);
682 images
->enabled_mask
&= ~(1u << slot
);
683 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
688 si_mark_image_range_valid(const struct pipe_image_view
*view
)
690 struct si_resource
*res
= si_resource(view
->resource
);
692 if (res
->b
.b
.target
!= PIPE_BUFFER
)
695 util_range_add(&res
->valid_buffer_range
,
697 view
->u
.buf
.offset
+ view
->u
.buf
.size
);
700 static void si_set_shader_image_desc(struct si_context
*ctx
,
701 const struct pipe_image_view
*view
,
702 bool skip_decompress
,
703 uint32_t *desc
, uint32_t *fmask_desc
)
705 struct si_screen
*screen
= ctx
->screen
;
706 struct si_resource
*res
;
708 res
= si_resource(view
->resource
);
710 if (res
->b
.b
.target
== PIPE_BUFFER
||
711 view
->shader_access
& SI_IMAGE_ACCESS_AS_BUFFER
) {
712 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
713 si_mark_image_range_valid(view
);
715 si_make_buffer_descriptor(screen
, res
,
718 view
->u
.buf
.size
, desc
);
719 si_set_buf_desc_address(res
, view
->u
.buf
.offset
, desc
+ 4);
721 static const unsigned char swizzle
[4] = { 0, 1, 2, 3 };
722 struct si_texture
*tex
= (struct si_texture
*)res
;
723 unsigned level
= view
->u
.tex
.level
;
724 unsigned width
, height
, depth
, hw_level
;
725 bool uses_dcc
= vi_dcc_enabled(tex
, level
);
726 unsigned access
= view
->access
;
728 /* Clear the write flag when writes can't occur.
729 * Note that DCC_DECOMPRESS for MSAA doesn't work in some cases,
730 * so we don't wanna trigger it.
733 (!fmask_desc
&& tex
->surface
.fmask_size
!= 0)) {
734 assert(!"Z/S and MSAA image stores are not supported");
735 access
&= ~PIPE_IMAGE_ACCESS_WRITE
;
738 assert(!tex
->is_depth
);
739 assert(fmask_desc
|| tex
->surface
.fmask_size
== 0);
741 if (uses_dcc
&& !skip_decompress
&&
742 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
||
743 !vi_dcc_formats_compatible(screen
, res
->b
.b
.format
, view
->format
))) {
744 /* If DCC can't be disabled, at least decompress it.
745 * The decompression is relatively cheap if the surface
746 * has been decompressed already.
748 if (!si_texture_disable_dcc(ctx
, tex
))
749 si_decompress_dcc(ctx
, tex
);
752 if (ctx
->chip_class
>= GFX9
) {
753 /* Always set the base address. The swizzle modes don't
754 * allow setting mipmap level offsets as the base.
756 width
= res
->b
.b
.width0
;
757 height
= res
->b
.b
.height0
;
758 depth
= res
->b
.b
.depth0
;
761 /* Always force the base level to the selected level.
763 * This is required for 3D textures, where otherwise
764 * selecting a single slice for non-layered bindings
765 * fails. It doesn't hurt the other targets.
767 width
= u_minify(res
->b
.b
.width0
, level
);
768 height
= u_minify(res
->b
.b
.height0
, level
);
769 depth
= u_minify(res
->b
.b
.depth0
, level
);
773 screen
->make_texture_descriptor(screen
, tex
,
774 false, res
->b
.b
.target
,
775 view
->format
, swizzle
,
777 view
->u
.tex
.first_layer
,
778 view
->u
.tex
.last_layer
,
779 width
, height
, depth
,
781 si_set_mutable_tex_desc_fields(screen
, tex
,
782 &tex
->surface
.u
.legacy
.level
[level
],
784 util_format_get_blockwidth(view
->format
),
789 static void si_set_shader_image(struct si_context
*ctx
,
791 unsigned slot
, const struct pipe_image_view
*view
,
792 bool skip_decompress
)
794 struct si_images
*images
= &ctx
->images
[shader
];
795 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
796 struct si_resource
*res
;
797 unsigned desc_slot
= si_get_image_slot(slot
);
798 uint32_t *desc
= descs
->list
+ desc_slot
* 8;
800 if (!view
|| !view
->resource
) {
801 si_disable_shader_image(ctx
, shader
, slot
);
805 res
= si_resource(view
->resource
);
807 if (&images
->views
[slot
] != view
)
808 util_copy_image_view(&images
->views
[slot
], view
);
810 si_set_shader_image_desc(ctx
, view
, skip_decompress
, desc
, NULL
);
812 if (res
->b
.b
.target
== PIPE_BUFFER
||
813 view
->shader_access
& SI_IMAGE_ACCESS_AS_BUFFER
) {
814 images
->needs_color_decompress_mask
&= ~(1 << slot
);
815 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
817 struct si_texture
*tex
= (struct si_texture
*)res
;
818 unsigned level
= view
->u
.tex
.level
;
820 if (color_needs_decompression(tex
)) {
821 images
->needs_color_decompress_mask
|= 1 << slot
;
823 images
->needs_color_decompress_mask
&= ~(1 << slot
);
826 if (vi_dcc_enabled(tex
, level
) &&
827 p_atomic_read(&tex
->framebuffers_bound
))
828 ctx
->need_check_render_feedback
= true;
831 images
->enabled_mask
|= 1u << slot
;
832 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
834 /* Since this can flush, it must be done after enabled_mask is updated. */
835 si_sampler_view_add_buffer(ctx
, &res
->b
.b
,
836 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
) ?
837 RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
,
842 si_set_shader_images(struct pipe_context
*pipe
,
843 enum pipe_shader_type shader
,
844 unsigned start_slot
, unsigned count
,
845 const struct pipe_image_view
*views
)
847 struct si_context
*ctx
= (struct si_context
*)pipe
;
850 assert(shader
< SI_NUM_SHADERS
);
855 assert(start_slot
+ count
<= SI_NUM_IMAGES
);
858 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
859 si_set_shader_image(ctx
, shader
, slot
, &views
[i
], false);
861 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
862 si_set_shader_image(ctx
, shader
, slot
, NULL
, false);
865 si_update_shader_needs_decompress_mask(ctx
, shader
);
869 si_images_update_needs_color_decompress_mask(struct si_images
*images
)
871 unsigned mask
= images
->enabled_mask
;
874 int i
= u_bit_scan(&mask
);
875 struct pipe_resource
*res
= images
->views
[i
].resource
;
877 if (res
&& res
->target
!= PIPE_BUFFER
) {
878 struct si_texture
*tex
= (struct si_texture
*)res
;
880 if (color_needs_decompression(tex
)) {
881 images
->needs_color_decompress_mask
|= 1 << i
;
883 images
->needs_color_decompress_mask
&= ~(1 << i
);
889 void si_update_ps_colorbuf0_slot(struct si_context
*sctx
)
891 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
892 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
893 unsigned slot
= SI_PS_IMAGE_COLORBUF0
;
894 struct pipe_surface
*surf
= NULL
;
896 /* si_texture_disable_dcc can get us here again. */
897 if (sctx
->blitter
->running
)
900 /* See whether FBFETCH is used and color buffer 0 is set. */
901 if (sctx
->ps_shader
.cso
&&
902 sctx
->ps_shader
.cso
->info
.uses_fbfetch
&&
903 sctx
->framebuffer
.state
.nr_cbufs
&&
904 sctx
->framebuffer
.state
.cbufs
[0])
905 surf
= sctx
->framebuffer
.state
.cbufs
[0];
907 /* Return if FBFETCH transitions from disabled to disabled. */
908 if (!buffers
->buffers
[slot
] && !surf
)
911 sctx
->ps_uses_fbfetch
= surf
!= NULL
;
912 si_update_ps_iter_samples(sctx
);
915 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
916 struct pipe_image_view view
;
919 assert(!tex
->is_depth
);
921 /* Disable DCC, because the texture is used as both a sampler
924 si_texture_disable_dcc(sctx
, tex
);
926 if (tex
->buffer
.b
.b
.nr_samples
<= 1 && tex
->cmask_buffer
) {
928 assert(tex
->cmask_buffer
!= &tex
->buffer
);
929 si_eliminate_fast_color_clear(sctx
, tex
);
930 si_texture_discard_cmask(sctx
->screen
, tex
);
933 view
.resource
= surf
->texture
;
934 view
.format
= surf
->format
;
935 view
.access
= PIPE_IMAGE_ACCESS_READ
;
936 view
.u
.tex
.first_layer
= surf
->u
.tex
.first_layer
;
937 view
.u
.tex
.last_layer
= surf
->u
.tex
.last_layer
;
938 view
.u
.tex
.level
= surf
->u
.tex
.level
;
940 /* Set the descriptor. */
941 uint32_t *desc
= descs
->list
+ slot
*4;
942 memset(desc
, 0, 16 * 4);
943 si_set_shader_image_desc(sctx
, &view
, true, desc
, desc
+ 8);
945 pipe_resource_reference(&buffers
->buffers
[slot
], &tex
->buffer
.b
.b
);
946 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
947 &tex
->buffer
, RADEON_USAGE_READ
,
948 RADEON_PRIO_SHADER_RW_IMAGE
);
949 buffers
->enabled_mask
|= 1u << slot
;
951 /* Clear the descriptor. */
952 memset(descs
->list
+ slot
*4, 0, 8*4);
953 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
954 buffers
->enabled_mask
&= ~(1u << slot
);
957 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
962 static void si_bind_sampler_states(struct pipe_context
*ctx
,
963 enum pipe_shader_type shader
,
964 unsigned start
, unsigned count
, void **states
)
966 struct si_context
*sctx
= (struct si_context
*)ctx
;
967 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
968 struct si_descriptors
*desc
= si_sampler_and_image_descriptors(sctx
, shader
);
969 struct si_sampler_state
**sstates
= (struct si_sampler_state
**)states
;
972 if (!count
|| shader
>= SI_NUM_SHADERS
|| !sstates
)
975 for (i
= 0; i
< count
; i
++) {
976 unsigned slot
= start
+ i
;
977 unsigned desc_slot
= si_get_sampler_slot(slot
);
980 sstates
[i
] == samplers
->sampler_states
[slot
])
984 assert(sstates
[i
]->magic
== SI_SAMPLER_STATE_MAGIC
);
986 samplers
->sampler_states
[slot
] = sstates
[i
];
988 /* If FMASK is bound, don't overwrite it.
989 * The sampler state will be set after FMASK is unbound.
991 struct si_sampler_view
*sview
=
992 (struct si_sampler_view
*)samplers
->views
[slot
];
994 struct si_texture
*tex
= NULL
;
996 if (sview
&& sview
->base
.texture
&&
997 sview
->base
.texture
->target
!= PIPE_BUFFER
)
998 tex
= (struct si_texture
*)sview
->base
.texture
;
1000 if (tex
&& tex
->surface
.fmask_size
)
1003 si_set_sampler_state_desc(sstates
[i
], sview
, tex
,
1004 desc
->list
+ desc_slot
* 16 + 12);
1006 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
1010 /* BUFFER RESOURCES */
1012 static void si_init_buffer_resources(struct si_buffer_resources
*buffers
,
1013 struct si_descriptors
*descs
,
1014 unsigned num_buffers
,
1015 short shader_userdata_rel_index
,
1016 enum radeon_bo_priority priority
,
1017 enum radeon_bo_priority priority_constbuf
)
1019 buffers
->priority
= priority
;
1020 buffers
->priority_constbuf
= priority_constbuf
;
1021 buffers
->buffers
= CALLOC(num_buffers
, sizeof(struct pipe_resource
*));
1022 buffers
->offsets
= CALLOC(num_buffers
, sizeof(buffers
->offsets
[0]));
1024 si_init_descriptors(descs
, shader_userdata_rel_index
, 4, num_buffers
);
1027 static void si_release_buffer_resources(struct si_buffer_resources
*buffers
,
1028 struct si_descriptors
*descs
)
1032 for (i
= 0; i
< descs
->num_elements
; i
++) {
1033 pipe_resource_reference(&buffers
->buffers
[i
], NULL
);
1036 FREE(buffers
->buffers
);
1037 FREE(buffers
->offsets
);
1040 static void si_buffer_resources_begin_new_cs(struct si_context
*sctx
,
1041 struct si_buffer_resources
*buffers
)
1043 unsigned mask
= buffers
->enabled_mask
;
1045 /* Add buffers to the CS. */
1047 int i
= u_bit_scan(&mask
);
1049 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1050 si_resource(buffers
->buffers
[i
]),
1051 buffers
->writable_mask
& (1u << i
) ? RADEON_USAGE_READWRITE
:
1053 i
< SI_NUM_SHADER_BUFFERS
? buffers
->priority
:
1054 buffers
->priority_constbuf
);
1058 static void si_get_buffer_from_descriptors(struct si_buffer_resources
*buffers
,
1059 struct si_descriptors
*descs
,
1060 unsigned idx
, struct pipe_resource
**buf
,
1061 unsigned *offset
, unsigned *size
)
1063 pipe_resource_reference(buf
, buffers
->buffers
[idx
]);
1065 struct si_resource
*res
= si_resource(*buf
);
1066 const uint32_t *desc
= descs
->list
+ idx
* 4;
1071 assert(G_008F04_STRIDE(desc
[1]) == 0);
1072 va
= si_desc_extract_buffer_address(desc
);
1074 assert(va
>= res
->gpu_address
&& va
+ *size
<= res
->gpu_address
+ res
->bo_size
);
1075 *offset
= va
- res
->gpu_address
;
1079 /* VERTEX BUFFERS */
1081 static void si_vertex_buffers_begin_new_cs(struct si_context
*sctx
)
1083 int count
= sctx
->vertex_elements
? sctx
->vertex_elements
->count
: 0;
1086 for (i
= 0; i
< count
; i
++) {
1087 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1089 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1091 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1094 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1095 si_resource(sctx
->vertex_buffer
[vb
].buffer
.resource
),
1096 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1099 if (!sctx
->vb_descriptors_buffer
)
1101 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1102 sctx
->vb_descriptors_buffer
, RADEON_USAGE_READ
,
1103 RADEON_PRIO_DESCRIPTORS
);
1106 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
)
1108 struct si_vertex_elements
*velems
= sctx
->vertex_elements
;
1110 unsigned desc_list_byte_size
;
1111 unsigned first_vb_use_mask
;
1114 if (!sctx
->vertex_buffers_dirty
|| !velems
)
1117 count
= velems
->count
;
1122 desc_list_byte_size
= velems
->desc_list_byte_size
;
1123 first_vb_use_mask
= velems
->first_vb_use_mask
;
1125 /* Vertex buffer descriptors are the only ones which are uploaded
1126 * directly through a staging buffer and don't go through
1127 * the fine-grained upload path.
1129 u_upload_alloc(sctx
->b
.const_uploader
, 0,
1130 desc_list_byte_size
,
1131 si_optimal_tcc_alignment(sctx
, desc_list_byte_size
),
1132 &sctx
->vb_descriptors_offset
,
1133 (struct pipe_resource
**)&sctx
->vb_descriptors_buffer
,
1135 if (!sctx
->vb_descriptors_buffer
) {
1136 sctx
->vb_descriptors_offset
= 0;
1137 sctx
->vb_descriptors_gpu_list
= NULL
;
1141 sctx
->vb_descriptors_gpu_list
= ptr
;
1142 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1143 sctx
->vb_descriptors_buffer
, RADEON_USAGE_READ
,
1144 RADEON_PRIO_DESCRIPTORS
);
1146 assert(count
<= SI_MAX_ATTRIBS
);
1148 for (i
= 0; i
< count
; i
++) {
1149 struct pipe_vertex_buffer
*vb
;
1150 struct si_resource
*buf
;
1151 unsigned vbo_index
= velems
->vertex_buffer_index
[i
];
1152 uint32_t *desc
= &ptr
[i
*4];
1154 vb
= &sctx
->vertex_buffer
[vbo_index
];
1155 buf
= si_resource(vb
->buffer
.resource
);
1157 memset(desc
, 0, 16);
1161 int64_t offset
= (int64_t)((int)vb
->buffer_offset
) +
1162 velems
->src_offset
[i
];
1164 if (offset
>= buf
->b
.b
.width0
) {
1165 assert(offset
< buf
->b
.b
.width0
);
1166 memset(desc
, 0, 16);
1170 uint64_t va
= buf
->gpu_address
+ offset
;
1172 int64_t num_records
= (int64_t)buf
->b
.b
.width0
- offset
;
1173 if (sctx
->chip_class
!= GFX8
&& vb
->stride
) {
1174 /* Round up by rounding down and adding 1 */
1175 num_records
= (num_records
- velems
->format_size
[i
]) /
1178 assert(num_records
>= 0 && num_records
<= UINT_MAX
);
1180 uint32_t rsrc_word3
= velems
->rsrc_word3
[i
];
1182 /* OOB_SELECT chooses the out-of-bounds check:
1183 * - 1: index >= NUM_RECORDS (Structured)
1184 * - 3: offset >= NUM_RECORDS (Raw)
1186 if (sctx
->chip_class
>= GFX10
)
1187 rsrc_word3
|= S_008F0C_OOB_SELECT(vb
->stride
? 1 : 3);
1190 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1191 S_008F04_STRIDE(vb
->stride
);
1192 desc
[2] = num_records
;
1193 desc
[3] = rsrc_word3
;
1195 if (first_vb_use_mask
& (1 << i
)) {
1196 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1197 si_resource(vb
->buffer
.resource
),
1198 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1202 /* Don't flush the const cache. It would have a very negative effect
1203 * on performance (confirmed by testing). New descriptors are always
1204 * uploaded to a fresh new buffer, so I don't think flushing the const
1205 * cache is needed. */
1206 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
1207 sctx
->vertex_buffers_dirty
= false;
1208 sctx
->vertex_buffer_pointer_dirty
= true;
1209 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VBO_DESCRIPTORS
;
1214 /* CONSTANT BUFFERS */
1216 static struct si_descriptors
*
1217 si_const_and_shader_buffer_descriptors(struct si_context
*sctx
, unsigned shader
)
1219 return &sctx
->descriptors
[si_const_and_shader_buffer_descriptors_idx(shader
)];
1222 void si_upload_const_buffer(struct si_context
*sctx
, struct si_resource
**buf
,
1223 const uint8_t *ptr
, unsigned size
, uint32_t *const_offset
)
1227 u_upload_alloc(sctx
->b
.const_uploader
, 0, size
,
1228 si_optimal_tcc_alignment(sctx
, size
),
1230 (struct pipe_resource
**)buf
, &tmp
);
1232 util_memcpy_cpu_to_le32(tmp
, ptr
, size
);
1235 static void si_set_constant_buffer(struct si_context
*sctx
,
1236 struct si_buffer_resources
*buffers
,
1237 unsigned descriptors_idx
,
1238 uint slot
, const struct pipe_constant_buffer
*input
)
1240 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1241 assert(slot
< descs
->num_elements
);
1242 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1244 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1245 * with a NULL buffer). We need to use a dummy buffer instead. */
1246 if (sctx
->chip_class
== GFX7
&&
1247 (!input
|| (!input
->buffer
&& !input
->user_buffer
)))
1248 input
= &sctx
->null_const_buf
;
1250 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
1251 struct pipe_resource
*buffer
= NULL
;
1253 unsigned buffer_offset
;
1255 /* Upload the user buffer if needed. */
1256 if (input
->user_buffer
) {
1257 si_upload_const_buffer(sctx
,
1258 (struct si_resource
**)&buffer
, input
->user_buffer
,
1259 input
->buffer_size
, &buffer_offset
);
1261 /* Just unbind on failure. */
1262 si_set_constant_buffer(sctx
, buffers
, descriptors_idx
, slot
, NULL
);
1266 pipe_resource_reference(&buffer
, input
->buffer
);
1267 buffer_offset
= input
->buffer_offset
;
1270 va
= si_resource(buffer
)->gpu_address
+ buffer_offset
;
1272 /* Set the descriptor. */
1273 uint32_t *desc
= descs
->list
+ slot
*4;
1275 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1277 desc
[2] = input
->buffer_size
;
1278 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1279 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1280 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1281 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
1283 if (sctx
->chip_class
>= GFX10
) {
1284 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
1285 S_008F0C_OOB_SELECT(3) |
1286 S_008F0C_RESOURCE_LEVEL(1);
1288 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1289 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1292 buffers
->buffers
[slot
] = buffer
;
1293 buffers
->offsets
[slot
] = buffer_offset
;
1294 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1295 si_resource(buffer
),
1297 buffers
->priority_constbuf
, true);
1298 buffers
->enabled_mask
|= 1u << slot
;
1300 /* Clear the descriptor. */
1301 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1302 buffers
->enabled_mask
&= ~(1u << slot
);
1305 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1308 static void si_pipe_set_constant_buffer(struct pipe_context
*ctx
,
1309 enum pipe_shader_type shader
, uint slot
,
1310 const struct pipe_constant_buffer
*input
)
1312 struct si_context
*sctx
= (struct si_context
*)ctx
;
1314 if (shader
>= SI_NUM_SHADERS
)
1317 if (slot
== 0 && input
&& input
->buffer
&&
1318 !(si_resource(input
->buffer
)->flags
& RADEON_FLAG_32BIT
)) {
1319 assert(!"constant buffer 0 must have a 32-bit VM address, use const_uploader");
1323 if (input
&& input
->buffer
)
1324 si_resource(input
->buffer
)->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
1326 slot
= si_get_constbuf_slot(slot
);
1327 si_set_constant_buffer(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1328 si_const_and_shader_buffer_descriptors_idx(shader
),
1332 void si_get_pipe_constant_buffer(struct si_context
*sctx
, uint shader
,
1333 uint slot
, struct pipe_constant_buffer
*cbuf
)
1335 cbuf
->user_buffer
= NULL
;
1336 si_get_buffer_from_descriptors(
1337 &sctx
->const_and_shader_buffers
[shader
],
1338 si_const_and_shader_buffer_descriptors(sctx
, shader
),
1339 si_get_constbuf_slot(slot
),
1340 &cbuf
->buffer
, &cbuf
->buffer_offset
, &cbuf
->buffer_size
);
1343 /* SHADER BUFFERS */
1345 static void si_set_shader_buffer(struct si_context
*sctx
,
1346 struct si_buffer_resources
*buffers
,
1347 unsigned descriptors_idx
,
1348 uint slot
, const struct pipe_shader_buffer
*sbuffer
,
1349 bool writable
, enum radeon_bo_priority priority
)
1351 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1352 uint32_t *desc
= descs
->list
+ slot
* 4;
1354 if (!sbuffer
|| !sbuffer
->buffer
) {
1355 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1356 memset(desc
, 0, sizeof(uint32_t) * 4);
1357 buffers
->enabled_mask
&= ~(1u << slot
);
1358 buffers
->writable_mask
&= ~(1u << slot
);
1359 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1363 struct si_resource
*buf
= si_resource(sbuffer
->buffer
);
1364 uint64_t va
= buf
->gpu_address
+ sbuffer
->buffer_offset
;
1367 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1369 desc
[2] = sbuffer
->buffer_size
;
1370 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1371 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1372 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1373 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
1375 if (sctx
->chip_class
>= GFX10
) {
1376 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
1377 S_008F0C_OOB_SELECT(3) |
1378 S_008F0C_RESOURCE_LEVEL(1);
1380 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1381 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1384 pipe_resource_reference(&buffers
->buffers
[slot
], &buf
->b
.b
);
1385 buffers
->offsets
[slot
] = sbuffer
->buffer_offset
;
1386 radeon_add_to_gfx_buffer_list_check_mem(sctx
, buf
,
1387 writable
? RADEON_USAGE_READWRITE
:
1391 buffers
->writable_mask
|= 1u << slot
;
1393 buffers
->writable_mask
&= ~(1u << slot
);
1395 buffers
->enabled_mask
|= 1u << slot
;
1396 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1398 util_range_add(&buf
->valid_buffer_range
, sbuffer
->buffer_offset
,
1399 sbuffer
->buffer_offset
+ sbuffer
->buffer_size
);
1402 static void si_set_shader_buffers(struct pipe_context
*ctx
,
1403 enum pipe_shader_type shader
,
1404 unsigned start_slot
, unsigned count
,
1405 const struct pipe_shader_buffer
*sbuffers
,
1406 unsigned writable_bitmask
)
1408 struct si_context
*sctx
= (struct si_context
*)ctx
;
1409 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1410 unsigned descriptors_idx
= si_const_and_shader_buffer_descriptors_idx(shader
);
1413 assert(start_slot
+ count
<= SI_NUM_SHADER_BUFFERS
);
1415 for (i
= 0; i
< count
; ++i
) {
1416 const struct pipe_shader_buffer
*sbuffer
= sbuffers
? &sbuffers
[i
] : NULL
;
1417 unsigned slot
= si_get_shaderbuf_slot(start_slot
+ i
);
1419 if (sbuffer
&& sbuffer
->buffer
)
1420 si_resource(sbuffer
->buffer
)->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
1422 si_set_shader_buffer(sctx
, buffers
, descriptors_idx
, slot
, sbuffer
,
1423 !!(writable_bitmask
& (1u << i
)),
1428 void si_get_shader_buffers(struct si_context
*sctx
,
1429 enum pipe_shader_type shader
,
1430 uint start_slot
, uint count
,
1431 struct pipe_shader_buffer
*sbuf
)
1433 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1434 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1436 for (unsigned i
= 0; i
< count
; ++i
) {
1437 si_get_buffer_from_descriptors(
1439 si_get_shaderbuf_slot(start_slot
+ i
),
1440 &sbuf
[i
].buffer
, &sbuf
[i
].buffer_offset
,
1441 &sbuf
[i
].buffer_size
);
1447 void si_set_rw_buffer(struct si_context
*sctx
,
1448 uint slot
, const struct pipe_constant_buffer
*input
)
1450 si_set_constant_buffer(sctx
, &sctx
->rw_buffers
, SI_DESCS_RW_BUFFERS
,
1454 void si_set_rw_shader_buffer(struct si_context
*sctx
, uint slot
,
1455 const struct pipe_shader_buffer
*sbuffer
)
1457 si_set_shader_buffer(sctx
, &sctx
->rw_buffers
, SI_DESCS_RW_BUFFERS
,
1458 slot
, sbuffer
, true, RADEON_PRIO_SHADER_RW_BUFFER
);
1461 void si_set_ring_buffer(struct si_context
*sctx
, uint slot
,
1462 struct pipe_resource
*buffer
,
1463 unsigned stride
, unsigned num_records
,
1464 bool add_tid
, bool swizzle
,
1465 unsigned element_size
, unsigned index_stride
, uint64_t offset
)
1467 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1468 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1470 /* The stride field in the resource descriptor has 14 bits */
1471 assert(stride
< (1 << 14));
1473 assert(slot
< descs
->num_elements
);
1474 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1479 va
= si_resource(buffer
)->gpu_address
+ offset
;
1481 switch (element_size
) {
1483 assert(!"Unsupported ring buffer element size");
1499 switch (index_stride
) {
1501 assert(!"Unsupported ring buffer index stride");
1517 if (sctx
->chip_class
>= GFX8
&& stride
)
1518 num_records
*= stride
;
1520 /* Set the descriptor. */
1521 uint32_t *desc
= descs
->list
+ slot
*4;
1523 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1524 S_008F04_STRIDE(stride
) |
1525 S_008F04_SWIZZLE_ENABLE(swizzle
);
1526 desc
[2] = num_records
;
1527 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1528 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1529 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1530 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1531 S_008F0C_INDEX_STRIDE(index_stride
) |
1532 S_008F0C_ADD_TID_ENABLE(add_tid
);
1534 if (sctx
->chip_class
>= GFX9
)
1535 assert(!swizzle
|| element_size
== 1); /* always 4 bytes on GFX9 */
1537 desc
[3] |= S_008F0C_ELEMENT_SIZE(element_size
);
1539 if (sctx
->chip_class
>= GFX10
) {
1540 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
1541 S_008F0C_OOB_SELECT(2) |
1542 S_008F0C_RESOURCE_LEVEL(1);
1544 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1545 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1548 pipe_resource_reference(&buffers
->buffers
[slot
], buffer
);
1549 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1550 si_resource(buffer
),
1551 RADEON_USAGE_READWRITE
, buffers
->priority
);
1552 buffers
->enabled_mask
|= 1u << slot
;
1554 /* Clear the descriptor. */
1555 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1556 buffers
->enabled_mask
&= ~(1u << slot
);
1559 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1562 /* INTERNAL CONST BUFFERS */
1564 static void si_set_polygon_stipple(struct pipe_context
*ctx
,
1565 const struct pipe_poly_stipple
*state
)
1567 struct si_context
*sctx
= (struct si_context
*)ctx
;
1568 struct pipe_constant_buffer cb
= {};
1569 unsigned stipple
[32];
1572 for (i
= 0; i
< 32; i
++)
1573 stipple
[i
] = util_bitreverse(state
->stipple
[i
]);
1575 cb
.user_buffer
= stipple
;
1576 cb
.buffer_size
= sizeof(stipple
);
1578 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
, &cb
);
1581 /* TEXTURE METADATA ENABLE/DISABLE */
1584 si_resident_handles_update_needs_color_decompress(struct si_context
*sctx
)
1586 util_dynarray_clear(&sctx
->resident_tex_needs_color_decompress
);
1587 util_dynarray_clear(&sctx
->resident_img_needs_color_decompress
);
1589 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1590 struct si_texture_handle
*, tex_handle
) {
1591 struct pipe_resource
*res
= (*tex_handle
)->view
->texture
;
1592 struct si_texture
*tex
;
1594 if (!res
|| res
->target
== PIPE_BUFFER
)
1597 tex
= (struct si_texture
*)res
;
1598 if (!color_needs_decompression(tex
))
1601 util_dynarray_append(&sctx
->resident_tex_needs_color_decompress
,
1602 struct si_texture_handle
*, *tex_handle
);
1605 util_dynarray_foreach(&sctx
->resident_img_handles
,
1606 struct si_image_handle
*, img_handle
) {
1607 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1608 struct pipe_resource
*res
= view
->resource
;
1609 struct si_texture
*tex
;
1611 if (!res
|| res
->target
== PIPE_BUFFER
)
1614 tex
= (struct si_texture
*)res
;
1615 if (!color_needs_decompression(tex
))
1618 util_dynarray_append(&sctx
->resident_img_needs_color_decompress
,
1619 struct si_image_handle
*, *img_handle
);
1623 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1624 * while the texture is bound, possibly by a different context. In that case,
1625 * call this function to update needs_*_decompress_masks.
1627 void si_update_needs_color_decompress_masks(struct si_context
*sctx
)
1629 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
1630 si_samplers_update_needs_color_decompress_mask(&sctx
->samplers
[i
]);
1631 si_images_update_needs_color_decompress_mask(&sctx
->images
[i
]);
1632 si_update_shader_needs_decompress_mask(sctx
, i
);
1635 si_resident_handles_update_needs_color_decompress(sctx
);
1638 /* BUFFER DISCARD/INVALIDATION */
1640 /* Reset descriptors of buffer resources after \p buf has been invalidated.
1641 * If buf == NULL, reset all descriptors.
1643 static void si_reset_buffer_resources(struct si_context
*sctx
,
1644 struct si_buffer_resources
*buffers
,
1645 unsigned descriptors_idx
,
1647 struct pipe_resource
*buf
,
1648 enum radeon_bo_priority priority
)
1650 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1651 unsigned mask
= buffers
->enabled_mask
& slot_mask
;
1654 unsigned i
= u_bit_scan(&mask
);
1655 struct pipe_resource
*buffer
= buffers
->buffers
[i
];
1657 if (buffer
&& (!buf
|| buffer
== buf
)) {
1658 si_set_buf_desc_address(si_resource(buffer
), buffers
->offsets
[i
],
1660 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1662 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1663 si_resource(buffer
),
1664 buffers
->writable_mask
& (1u << i
) ?
1665 RADEON_USAGE_READWRITE
:
1672 /* Update all buffer bindings where the buffer is bound, including
1673 * all resource descriptors. This is invalidate_buffer without
1676 * If buf == NULL, update all buffer bindings.
1678 void si_rebind_buffer(struct si_context
*sctx
, struct pipe_resource
*buf
)
1680 struct si_resource
*buffer
= si_resource(buf
);
1682 unsigned num_elems
= sctx
->vertex_elements
?
1683 sctx
->vertex_elements
->count
: 0;
1685 /* We changed the buffer, now we need to bind it where the old one
1686 * was bound. This consists of 2 things:
1687 * 1) Updating the resource descriptor and dirtying it.
1688 * 2) Adding a relocation to the CS, so that it's usable.
1691 /* Vertex buffers. */
1694 sctx
->vertex_buffers_dirty
= true;
1695 } else if (buffer
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
1696 for (i
= 0; i
< num_elems
; i
++) {
1697 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1699 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1701 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1704 if (sctx
->vertex_buffer
[vb
].buffer
.resource
== buf
) {
1705 sctx
->vertex_buffers_dirty
= true;
1711 /* Streamout buffers. (other internal buffers can't be invalidated) */
1712 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
1713 for (i
= SI_VS_STREAMOUT_BUF0
; i
<= SI_VS_STREAMOUT_BUF3
; i
++) {
1714 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1715 struct si_descriptors
*descs
=
1716 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1717 struct pipe_resource
*buffer
= buffers
->buffers
[i
];
1719 if (!buffer
|| (buf
&& buffer
!= buf
))
1722 si_set_buf_desc_address(si_resource(buffer
), buffers
->offsets
[i
],
1724 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1726 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1727 si_resource(buffer
),
1729 RADEON_PRIO_SHADER_RW_BUFFER
,
1732 /* Update the streamout state. */
1733 if (sctx
->streamout
.begin_emitted
)
1734 si_emit_streamout_end(sctx
);
1735 sctx
->streamout
.append_bitmask
=
1736 sctx
->streamout
.enabled_mask
;
1737 si_streamout_buffers_dirty(sctx
);
1741 /* Constant and shader buffers. */
1742 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1743 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1744 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1745 si_const_and_shader_buffer_descriptors_idx(shader
),
1746 u_bit_consecutive(SI_NUM_SHADER_BUFFERS
, SI_NUM_CONST_BUFFERS
),
1748 sctx
->const_and_shader_buffers
[shader
].priority_constbuf
);
1751 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
1752 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1753 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1754 si_const_and_shader_buffer_descriptors_idx(shader
),
1755 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS
),
1757 sctx
->const_and_shader_buffers
[shader
].priority
);
1760 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
1761 /* Texture buffers - update bindings. */
1762 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1763 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1764 struct si_descriptors
*descs
=
1765 si_sampler_and_image_descriptors(sctx
, shader
);
1766 unsigned mask
= samplers
->enabled_mask
;
1769 unsigned i
= u_bit_scan(&mask
);
1770 struct pipe_resource
*buffer
= samplers
->views
[i
]->texture
;
1772 if (buffer
&& buffer
->target
== PIPE_BUFFER
&&
1773 (!buf
|| buffer
== buf
)) {
1774 unsigned desc_slot
= si_get_sampler_slot(i
);
1776 si_set_buf_desc_address(si_resource(buffer
),
1777 samplers
->views
[i
]->u
.buf
.offset
,
1778 descs
->list
+ desc_slot
* 16 + 4);
1779 sctx
->descriptors_dirty
|=
1780 1u << si_sampler_and_image_descriptors_idx(shader
);
1782 radeon_add_to_gfx_buffer_list_check_mem(
1783 sctx
, si_resource(buffer
),
1785 RADEON_PRIO_SAMPLER_BUFFER
, true);
1792 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
1793 for (shader
= 0; shader
< SI_NUM_SHADERS
; ++shader
) {
1794 struct si_images
*images
= &sctx
->images
[shader
];
1795 struct si_descriptors
*descs
=
1796 si_sampler_and_image_descriptors(sctx
, shader
);
1797 unsigned mask
= images
->enabled_mask
;
1800 unsigned i
= u_bit_scan(&mask
);
1801 struct pipe_resource
*buffer
= images
->views
[i
].resource
;
1803 if (buffer
&& buffer
->target
== PIPE_BUFFER
&&
1804 (!buf
|| buffer
== buf
)) {
1805 unsigned desc_slot
= si_get_image_slot(i
);
1807 if (images
->views
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
)
1808 si_mark_image_range_valid(&images
->views
[i
]);
1810 si_set_buf_desc_address(si_resource(buffer
),
1811 images
->views
[i
].u
.buf
.offset
,
1812 descs
->list
+ desc_slot
* 8 + 4);
1813 sctx
->descriptors_dirty
|=
1814 1u << si_sampler_and_image_descriptors_idx(shader
);
1816 radeon_add_to_gfx_buffer_list_check_mem(
1817 sctx
, si_resource(buffer
),
1818 RADEON_USAGE_READWRITE
,
1819 RADEON_PRIO_SAMPLER_BUFFER
, true);
1825 /* Bindless texture handles */
1826 if (!buffer
|| buffer
->texture_handle_allocated
) {
1827 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1829 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1830 struct si_texture_handle
*, tex_handle
) {
1831 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
1832 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1833 struct pipe_resource
*buffer
= view
->texture
;
1835 if (buffer
&& buffer
->target
== PIPE_BUFFER
&&
1836 (!buf
|| buffer
== buf
)) {
1837 si_set_buf_desc_address(si_resource(buffer
),
1840 desc_slot
* 16 + 4);
1842 (*tex_handle
)->desc_dirty
= true;
1843 sctx
->bindless_descriptors_dirty
= true;
1845 radeon_add_to_gfx_buffer_list_check_mem(
1846 sctx
, si_resource(buffer
),
1848 RADEON_PRIO_SAMPLER_BUFFER
, true);
1853 /* Bindless image handles */
1854 if (!buffer
|| buffer
->image_handle_allocated
) {
1855 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1857 util_dynarray_foreach(&sctx
->resident_img_handles
,
1858 struct si_image_handle
*, img_handle
) {
1859 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1860 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1861 struct pipe_resource
*buffer
= view
->resource
;
1863 if (buffer
&& buffer
->target
== PIPE_BUFFER
&&
1864 (!buf
|| buffer
== buf
)) {
1865 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
1866 si_mark_image_range_valid(view
);
1868 si_set_buf_desc_address(si_resource(buffer
),
1871 desc_slot
* 16 + 4);
1873 (*img_handle
)->desc_dirty
= true;
1874 sctx
->bindless_descriptors_dirty
= true;
1876 radeon_add_to_gfx_buffer_list_check_mem(
1877 sctx
, si_resource(buffer
),
1878 RADEON_USAGE_READWRITE
,
1879 RADEON_PRIO_SAMPLER_BUFFER
, true);
1885 /* Do the same for other contexts. They will invoke this function
1886 * with buffer == NULL.
1888 unsigned new_counter
= p_atomic_inc_return(&sctx
->screen
->dirty_buf_counter
);
1890 /* Skip the update for the current context, because we have already updated
1891 * the buffer bindings.
1893 if (new_counter
== sctx
->last_dirty_buf_counter
+ 1)
1894 sctx
->last_dirty_buf_counter
= new_counter
;
1898 static void si_upload_bindless_descriptor(struct si_context
*sctx
,
1900 unsigned num_dwords
)
1902 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1903 unsigned desc_slot_offset
= desc_slot
* 16;
1907 data
= desc
->list
+ desc_slot_offset
;
1908 va
= desc
->gpu_address
+ desc_slot_offset
* 4;
1910 si_cp_write_data(sctx
, desc
->buffer
, va
- desc
->buffer
->gpu_address
,
1911 num_dwords
* 4, V_370_TC_L2
, V_370_ME
, data
);
1914 static void si_upload_bindless_descriptors(struct si_context
*sctx
)
1916 if (!sctx
->bindless_descriptors_dirty
)
1919 /* Wait for graphics/compute to be idle before updating the resident
1920 * descriptors directly in memory, in case the GPU is using them.
1922 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
1923 SI_CONTEXT_CS_PARTIAL_FLUSH
;
1924 sctx
->emit_cache_flush(sctx
);
1926 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1927 struct si_texture_handle
*, tex_handle
) {
1928 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1930 if (!(*tex_handle
)->desc_dirty
)
1933 si_upload_bindless_descriptor(sctx
, desc_slot
, 16);
1934 (*tex_handle
)->desc_dirty
= false;
1937 util_dynarray_foreach(&sctx
->resident_img_handles
,
1938 struct si_image_handle
*, img_handle
) {
1939 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1941 if (!(*img_handle
)->desc_dirty
)
1944 si_upload_bindless_descriptor(sctx
, desc_slot
, 8);
1945 (*img_handle
)->desc_dirty
= false;
1948 /* Invalidate L1 because it doesn't know that L2 changed. */
1949 sctx
->flags
|= SI_CONTEXT_INV_SCACHE
;
1950 sctx
->emit_cache_flush(sctx
);
1952 sctx
->bindless_descriptors_dirty
= false;
1955 /* Update mutable image descriptor fields of all resident textures. */
1956 static void si_update_bindless_texture_descriptor(struct si_context
*sctx
,
1957 struct si_texture_handle
*tex_handle
)
1959 struct si_sampler_view
*sview
= (struct si_sampler_view
*)tex_handle
->view
;
1960 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1961 unsigned desc_slot_offset
= tex_handle
->desc_slot
* 16;
1962 uint32_t desc_list
[16];
1964 if (sview
->base
.texture
->target
== PIPE_BUFFER
)
1967 memcpy(desc_list
, desc
->list
+ desc_slot_offset
, sizeof(desc_list
));
1968 si_set_sampler_view_desc(sctx
, sview
, &tex_handle
->sstate
,
1969 desc
->list
+ desc_slot_offset
);
1971 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1972 sizeof(desc_list
))) {
1973 tex_handle
->desc_dirty
= true;
1974 sctx
->bindless_descriptors_dirty
= true;
1978 static void si_update_bindless_image_descriptor(struct si_context
*sctx
,
1979 struct si_image_handle
*img_handle
)
1981 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1982 unsigned desc_slot_offset
= img_handle
->desc_slot
* 16;
1983 struct pipe_image_view
*view
= &img_handle
->view
;
1984 uint32_t desc_list
[8];
1986 if (view
->resource
->target
== PIPE_BUFFER
)
1989 memcpy(desc_list
, desc
->list
+ desc_slot_offset
,
1991 si_set_shader_image_desc(sctx
, view
, true,
1992 desc
->list
+ desc_slot_offset
, NULL
);
1994 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1995 sizeof(desc_list
))) {
1996 img_handle
->desc_dirty
= true;
1997 sctx
->bindless_descriptors_dirty
= true;
2001 static void si_update_all_resident_texture_descriptors(struct si_context
*sctx
)
2003 util_dynarray_foreach(&sctx
->resident_tex_handles
,
2004 struct si_texture_handle
*, tex_handle
) {
2005 si_update_bindless_texture_descriptor(sctx
, *tex_handle
);
2008 util_dynarray_foreach(&sctx
->resident_img_handles
,
2009 struct si_image_handle
*, img_handle
) {
2010 si_update_bindless_image_descriptor(sctx
, *img_handle
);
2013 si_upload_bindless_descriptors(sctx
);
2016 /* Update mutable image descriptor fields of all bound textures. */
2017 void si_update_all_texture_descriptors(struct si_context
*sctx
)
2021 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
2022 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
2023 struct si_images
*images
= &sctx
->images
[shader
];
2027 mask
= images
->enabled_mask
;
2029 unsigned i
= u_bit_scan(&mask
);
2030 struct pipe_image_view
*view
= &images
->views
[i
];
2032 if (!view
->resource
||
2033 view
->resource
->target
== PIPE_BUFFER
)
2036 si_set_shader_image(sctx
, shader
, i
, view
, true);
2039 /* Sampler views. */
2040 mask
= samplers
->enabled_mask
;
2042 unsigned i
= u_bit_scan(&mask
);
2043 struct pipe_sampler_view
*view
= samplers
->views
[i
];
2047 view
->texture
->target
== PIPE_BUFFER
)
2050 si_set_sampler_view(sctx
, shader
, i
,
2051 samplers
->views
[i
], true);
2054 si_update_shader_needs_decompress_mask(sctx
, shader
);
2057 si_update_all_resident_texture_descriptors(sctx
);
2058 si_update_ps_colorbuf0_slot(sctx
);
2061 /* SHADER USER DATA */
2063 static void si_mark_shader_pointers_dirty(struct si_context
*sctx
,
2066 sctx
->shader_pointers_dirty
|=
2067 u_bit_consecutive(SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
,
2068 SI_NUM_SHADER_DESCS
);
2070 if (shader
== PIPE_SHADER_VERTEX
)
2071 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
2073 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
2076 static void si_shader_pointers_begin_new_cs(struct si_context
*sctx
)
2078 sctx
->shader_pointers_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2079 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
2080 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
2081 sctx
->graphics_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
2082 sctx
->compute_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
2085 /* Set a base register address for user data constants in the given shader.
2086 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
2088 static void si_set_user_data_base(struct si_context
*sctx
,
2089 unsigned shader
, uint32_t new_base
)
2091 uint32_t *base
= &sctx
->shader_pointers
.sh_base
[shader
];
2093 if (*base
!= new_base
) {
2097 si_mark_shader_pointers_dirty(sctx
, shader
);
2099 /* Any change in enabled shader stages requires re-emitting
2100 * the VS state SGPR, because it contains the clamp_vertex_color
2101 * state, which can be done in VS, TES, and GS.
2103 sctx
->last_vs_state
= ~0;
2107 /* This must be called when these are changed between enabled and disabled
2109 * - tessellation evaluation shader
2112 void si_shader_change_notify(struct si_context
*sctx
)
2114 /* VS can be bound as VS, ES, or LS. */
2115 if (sctx
->tes_shader
.cso
) {
2116 if (sctx
->chip_class
>= GFX10
) {
2117 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2118 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2119 } else if (sctx
->chip_class
== GFX9
) {
2120 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2121 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2123 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2124 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2126 } else if (sctx
->chip_class
>= GFX10
) {
2127 if (sctx
->ngg
|| sctx
->gs_shader
.cso
) {
2128 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2129 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2131 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2132 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2134 } else if (sctx
->gs_shader
.cso
) {
2135 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2136 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2138 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2139 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2142 /* TES can be bound as ES, VS, or not bound. */
2143 if (sctx
->tes_shader
.cso
) {
2144 if (sctx
->chip_class
>= GFX10
) {
2145 if (sctx
->ngg
|| sctx
->gs_shader
.cso
) {
2146 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
2147 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2149 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
2150 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2152 } else if (sctx
->gs_shader
.cso
) {
2153 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
2154 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2156 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
2157 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2160 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, 0);
2164 static void si_emit_shader_pointer_head(struct radeon_cmdbuf
*cs
,
2166 unsigned pointer_count
)
2168 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
, 0));
2169 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
2172 static void si_emit_shader_pointer_body(struct si_screen
*sscreen
,
2173 struct radeon_cmdbuf
*cs
,
2176 radeon_emit(cs
, va
);
2178 assert(va
== 0 || (va
>> 32) == sscreen
->info
.address32_hi
);
2181 static void si_emit_shader_pointer(struct si_context
*sctx
,
2182 struct si_descriptors
*desc
,
2185 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2186 unsigned sh_offset
= sh_base
+ desc
->shader_userdata_offset
;
2188 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2189 si_emit_shader_pointer_body(sctx
->screen
, cs
, desc
->gpu_address
);
2192 static void si_emit_consecutive_shader_pointers(struct si_context
*sctx
,
2193 unsigned pointer_mask
,
2199 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2200 unsigned mask
= sctx
->shader_pointers_dirty
& pointer_mask
;
2204 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
2206 struct si_descriptors
*descs
= &sctx
->descriptors
[start
];
2207 unsigned sh_offset
= sh_base
+ descs
->shader_userdata_offset
;
2209 si_emit_shader_pointer_head(cs
, sh_offset
, count
);
2210 for (int i
= 0; i
< count
; i
++)
2211 si_emit_shader_pointer_body(sctx
->screen
, cs
,
2212 descs
[i
].gpu_address
);
2216 static void si_emit_global_shader_pointers(struct si_context
*sctx
,
2217 struct si_descriptors
*descs
)
2219 if (sctx
->chip_class
>= GFX10
) {
2220 si_emit_shader_pointer(sctx
, descs
,
2221 R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2222 /* HW VS stage only used in non-NGG mode. */
2223 si_emit_shader_pointer(sctx
, descs
,
2224 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2225 si_emit_shader_pointer(sctx
, descs
,
2226 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2227 si_emit_shader_pointer(sctx
, descs
,
2228 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2230 } else if (sctx
->chip_class
== GFX9
) {
2231 /* Broadcast it to all shader stages. */
2232 si_emit_shader_pointer(sctx
, descs
,
2233 R_00B530_SPI_SHADER_USER_DATA_COMMON_0
);
2237 si_emit_shader_pointer(sctx
, descs
,
2238 R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2239 si_emit_shader_pointer(sctx
, descs
,
2240 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2241 si_emit_shader_pointer(sctx
, descs
,
2242 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2243 si_emit_shader_pointer(sctx
, descs
,
2244 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2245 si_emit_shader_pointer(sctx
, descs
,
2246 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2247 si_emit_shader_pointer(sctx
, descs
,
2248 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2251 void si_emit_graphics_shader_pointers(struct si_context
*sctx
)
2253 uint32_t *sh_base
= sctx
->shader_pointers
.sh_base
;
2255 if (sctx
->shader_pointers_dirty
& (1 << SI_DESCS_RW_BUFFERS
)) {
2256 si_emit_global_shader_pointers(sctx
,
2257 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2260 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(VERTEX
),
2261 sh_base
[PIPE_SHADER_VERTEX
]);
2262 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_EVAL
),
2263 sh_base
[PIPE_SHADER_TESS_EVAL
]);
2264 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(FRAGMENT
),
2265 sh_base
[PIPE_SHADER_FRAGMENT
]);
2266 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_CTRL
),
2267 sh_base
[PIPE_SHADER_TESS_CTRL
]);
2268 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(GEOMETRY
),
2269 sh_base
[PIPE_SHADER_GEOMETRY
]);
2271 sctx
->shader_pointers_dirty
&=
2272 ~u_bit_consecutive(SI_DESCS_RW_BUFFERS
, SI_DESCS_FIRST_COMPUTE
);
2274 if (sctx
->vertex_buffer_pointer_dirty
) {
2275 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2277 /* Find the location of the VB descriptor pointer. */
2278 /* TODO: In the future, the pointer will be packed in unused
2279 * bits of the first 2 VB descriptors. */
2280 unsigned sh_dw_offset
= SI_VS_NUM_USER_SGPR
;
2281 if (sctx
->chip_class
>= GFX9
) {
2282 if (sctx
->tes_shader
.cso
)
2283 sh_dw_offset
= GFX9_TCS_NUM_USER_SGPR
;
2284 else if (sctx
->gs_shader
.cso
)
2285 sh_dw_offset
= GFX9_VSGS_NUM_USER_SGPR
;
2288 unsigned sh_offset
= sh_base
[PIPE_SHADER_VERTEX
] + sh_dw_offset
* 4;
2289 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2290 si_emit_shader_pointer_body(sctx
->screen
, cs
,
2291 sctx
->vb_descriptors_buffer
->gpu_address
+
2292 sctx
->vb_descriptors_offset
);
2293 sctx
->vertex_buffer_pointer_dirty
= false;
2296 if (sctx
->graphics_bindless_pointer_dirty
) {
2297 si_emit_global_shader_pointers(sctx
,
2298 &sctx
->bindless_descriptors
);
2299 sctx
->graphics_bindless_pointer_dirty
= false;
2303 void si_emit_compute_shader_pointers(struct si_context
*sctx
)
2305 unsigned base
= R_00B900_COMPUTE_USER_DATA_0
;
2307 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(COMPUTE
),
2308 R_00B900_COMPUTE_USER_DATA_0
);
2309 sctx
->shader_pointers_dirty
&= ~SI_DESCS_SHADER_MASK(COMPUTE
);
2311 if (sctx
->compute_bindless_pointer_dirty
) {
2312 si_emit_shader_pointer(sctx
, &sctx
->bindless_descriptors
, base
);
2313 sctx
->compute_bindless_pointer_dirty
= false;
2319 static void si_init_bindless_descriptors(struct si_context
*sctx
,
2320 struct si_descriptors
*desc
,
2321 short shader_userdata_rel_index
,
2322 unsigned num_elements
)
2324 ASSERTED
unsigned desc_slot
;
2326 si_init_descriptors(desc
, shader_userdata_rel_index
, 16, num_elements
);
2327 sctx
->bindless_descriptors
.num_active_slots
= num_elements
;
2329 /* The first bindless descriptor is stored at slot 1, because 0 is not
2330 * considered to be a valid handle.
2332 sctx
->num_bindless_descriptors
= 1;
2334 /* Track which bindless slots are used (or not). */
2335 util_idalloc_init(&sctx
->bindless_used_slots
);
2336 util_idalloc_resize(&sctx
->bindless_used_slots
, num_elements
);
2338 /* Reserve slot 0 because it's an invalid handle for bindless. */
2339 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2340 assert(desc_slot
== 0);
2343 static void si_release_bindless_descriptors(struct si_context
*sctx
)
2345 si_release_descriptors(&sctx
->bindless_descriptors
);
2346 util_idalloc_fini(&sctx
->bindless_used_slots
);
2349 static unsigned si_get_first_free_bindless_slot(struct si_context
*sctx
)
2351 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2354 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2355 if (desc_slot
>= desc
->num_elements
) {
2356 /* The array of bindless descriptors is full, resize it. */
2357 unsigned slot_size
= desc
->element_dw_size
* 4;
2358 unsigned new_num_elements
= desc
->num_elements
* 2;
2360 desc
->list
= REALLOC(desc
->list
, desc
->num_elements
* slot_size
,
2361 new_num_elements
* slot_size
);
2362 desc
->num_elements
= new_num_elements
;
2363 desc
->num_active_slots
= new_num_elements
;
2371 si_create_bindless_descriptor(struct si_context
*sctx
, uint32_t *desc_list
,
2374 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2375 unsigned desc_slot
, desc_slot_offset
;
2377 /* Find a free slot. */
2378 desc_slot
= si_get_first_free_bindless_slot(sctx
);
2380 /* For simplicity, sampler and image bindless descriptors use fixed
2381 * 16-dword slots for now. Image descriptors only need 8-dword but this
2382 * doesn't really matter because no real apps use image handles.
2384 desc_slot_offset
= desc_slot
* 16;
2386 /* Copy the descriptor into the array. */
2387 memcpy(desc
->list
+ desc_slot_offset
, desc_list
, size
);
2389 /* Re-upload the whole array of bindless descriptors into a new buffer.
2391 if (!si_upload_descriptors(sctx
, desc
))
2394 /* Make sure to re-emit the shader pointers for all stages. */
2395 sctx
->graphics_bindless_pointer_dirty
= true;
2396 sctx
->compute_bindless_pointer_dirty
= true;
2401 static void si_update_bindless_buffer_descriptor(struct si_context
*sctx
,
2403 struct pipe_resource
*resource
,
2407 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2408 struct si_resource
*buf
= si_resource(resource
);
2409 unsigned desc_slot_offset
= desc_slot
* 16;
2410 uint32_t *desc_list
= desc
->list
+ desc_slot_offset
+ 4;
2411 uint64_t old_desc_va
;
2413 assert(resource
->target
== PIPE_BUFFER
);
2415 /* Retrieve the old buffer addr from the descriptor. */
2416 old_desc_va
= si_desc_extract_buffer_address(desc_list
);
2418 if (old_desc_va
!= buf
->gpu_address
+ offset
) {
2419 /* The buffer has been invalidated when the handle wasn't
2420 * resident, update the descriptor and the dirty flag.
2422 si_set_buf_desc_address(buf
, offset
, &desc_list
[0]);
2428 static uint64_t si_create_texture_handle(struct pipe_context
*ctx
,
2429 struct pipe_sampler_view
*view
,
2430 const struct pipe_sampler_state
*state
)
2432 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
2433 struct si_context
*sctx
= (struct si_context
*)ctx
;
2434 struct si_texture_handle
*tex_handle
;
2435 struct si_sampler_state
*sstate
;
2436 uint32_t desc_list
[16];
2439 tex_handle
= CALLOC_STRUCT(si_texture_handle
);
2443 memset(desc_list
, 0, sizeof(desc_list
));
2444 si_init_descriptor_list(&desc_list
[0], 16, 1, null_texture_descriptor
);
2446 sstate
= ctx
->create_sampler_state(ctx
, state
);
2452 si_set_sampler_view_desc(sctx
, sview
, sstate
, &desc_list
[0]);
2453 memcpy(&tex_handle
->sstate
, sstate
, sizeof(*sstate
));
2454 ctx
->delete_sampler_state(ctx
, sstate
);
2456 tex_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2458 if (!tex_handle
->desc_slot
) {
2463 handle
= tex_handle
->desc_slot
;
2465 if (!_mesa_hash_table_insert(sctx
->tex_handles
,
2466 (void *)(uintptr_t)handle
,
2472 pipe_sampler_view_reference(&tex_handle
->view
, view
);
2474 si_resource(sview
->base
.texture
)->texture_handle_allocated
= true;
2479 static void si_delete_texture_handle(struct pipe_context
*ctx
, uint64_t handle
)
2481 struct si_context
*sctx
= (struct si_context
*)ctx
;
2482 struct si_texture_handle
*tex_handle
;
2483 struct hash_entry
*entry
;
2485 entry
= _mesa_hash_table_search(sctx
->tex_handles
,
2486 (void *)(uintptr_t)handle
);
2490 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2492 /* Allow this descriptor slot to be re-used. */
2493 util_idalloc_free(&sctx
->bindless_used_slots
, tex_handle
->desc_slot
);
2495 pipe_sampler_view_reference(&tex_handle
->view
, NULL
);
2496 _mesa_hash_table_remove(sctx
->tex_handles
, entry
);
2500 static void si_make_texture_handle_resident(struct pipe_context
*ctx
,
2501 uint64_t handle
, bool resident
)
2503 struct si_context
*sctx
= (struct si_context
*)ctx
;
2504 struct si_texture_handle
*tex_handle
;
2505 struct si_sampler_view
*sview
;
2506 struct hash_entry
*entry
;
2508 entry
= _mesa_hash_table_search(sctx
->tex_handles
,
2509 (void *)(uintptr_t)handle
);
2513 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2514 sview
= (struct si_sampler_view
*)tex_handle
->view
;
2517 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2518 struct si_texture
*tex
=
2519 (struct si_texture
*)sview
->base
.texture
;
2521 if (depth_needs_decompression(tex
)) {
2522 util_dynarray_append(
2523 &sctx
->resident_tex_needs_depth_decompress
,
2524 struct si_texture_handle
*,
2528 if (color_needs_decompression(tex
)) {
2529 util_dynarray_append(
2530 &sctx
->resident_tex_needs_color_decompress
,
2531 struct si_texture_handle
*,
2535 if (tex
->surface
.dcc_offset
&&
2536 p_atomic_read(&tex
->framebuffers_bound
))
2537 sctx
->need_check_render_feedback
= true;
2539 si_update_bindless_texture_descriptor(sctx
, tex_handle
);
2541 si_update_bindless_buffer_descriptor(sctx
,
2542 tex_handle
->desc_slot
,
2543 sview
->base
.texture
,
2544 sview
->base
.u
.buf
.offset
,
2545 &tex_handle
->desc_dirty
);
2548 /* Re-upload the descriptor if it has been updated while it
2551 if (tex_handle
->desc_dirty
)
2552 sctx
->bindless_descriptors_dirty
= true;
2554 /* Add the texture handle to the per-context list. */
2555 util_dynarray_append(&sctx
->resident_tex_handles
,
2556 struct si_texture_handle
*, tex_handle
);
2558 /* Add the buffers to the current CS in case si_begin_new_cs()
2559 * is not going to be called.
2561 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2563 sview
->is_stencil_sampler
, false);
2565 /* Remove the texture handle from the per-context list. */
2566 util_dynarray_delete_unordered(&sctx
->resident_tex_handles
,
2567 struct si_texture_handle
*,
2570 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2571 util_dynarray_delete_unordered(
2572 &sctx
->resident_tex_needs_depth_decompress
,
2573 struct si_texture_handle
*, tex_handle
);
2575 util_dynarray_delete_unordered(
2576 &sctx
->resident_tex_needs_color_decompress
,
2577 struct si_texture_handle
*, tex_handle
);
2582 static uint64_t si_create_image_handle(struct pipe_context
*ctx
,
2583 const struct pipe_image_view
*view
)
2585 struct si_context
*sctx
= (struct si_context
*)ctx
;
2586 struct si_image_handle
*img_handle
;
2587 uint32_t desc_list
[8];
2590 if (!view
|| !view
->resource
)
2593 img_handle
= CALLOC_STRUCT(si_image_handle
);
2597 memset(desc_list
, 0, sizeof(desc_list
));
2598 si_init_descriptor_list(&desc_list
[0], 8, 1, null_image_descriptor
);
2600 si_set_shader_image_desc(sctx
, view
, false, &desc_list
[0], NULL
);
2602 img_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2604 if (!img_handle
->desc_slot
) {
2609 handle
= img_handle
->desc_slot
;
2611 if (!_mesa_hash_table_insert(sctx
->img_handles
,
2612 (void *)(uintptr_t)handle
,
2618 util_copy_image_view(&img_handle
->view
, view
);
2620 si_resource(view
->resource
)->image_handle_allocated
= true;
2625 static void si_delete_image_handle(struct pipe_context
*ctx
, uint64_t handle
)
2627 struct si_context
*sctx
= (struct si_context
*)ctx
;
2628 struct si_image_handle
*img_handle
;
2629 struct hash_entry
*entry
;
2631 entry
= _mesa_hash_table_search(sctx
->img_handles
,
2632 (void *)(uintptr_t)handle
);
2636 img_handle
= (struct si_image_handle
*)entry
->data
;
2638 util_copy_image_view(&img_handle
->view
, NULL
);
2639 _mesa_hash_table_remove(sctx
->img_handles
, entry
);
2643 static void si_make_image_handle_resident(struct pipe_context
*ctx
,
2644 uint64_t handle
, unsigned access
,
2647 struct si_context
*sctx
= (struct si_context
*)ctx
;
2648 struct si_image_handle
*img_handle
;
2649 struct pipe_image_view
*view
;
2650 struct si_resource
*res
;
2651 struct hash_entry
*entry
;
2653 entry
= _mesa_hash_table_search(sctx
->img_handles
,
2654 (void *)(uintptr_t)handle
);
2658 img_handle
= (struct si_image_handle
*)entry
->data
;
2659 view
= &img_handle
->view
;
2660 res
= si_resource(view
->resource
);
2663 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2664 struct si_texture
*tex
= (struct si_texture
*)res
;
2665 unsigned level
= view
->u
.tex
.level
;
2667 if (color_needs_decompression(tex
)) {
2668 util_dynarray_append(
2669 &sctx
->resident_img_needs_color_decompress
,
2670 struct si_image_handle
*,
2674 if (vi_dcc_enabled(tex
, level
) &&
2675 p_atomic_read(&tex
->framebuffers_bound
))
2676 sctx
->need_check_render_feedback
= true;
2678 si_update_bindless_image_descriptor(sctx
, img_handle
);
2680 si_update_bindless_buffer_descriptor(sctx
,
2681 img_handle
->desc_slot
,
2684 &img_handle
->desc_dirty
);
2687 /* Re-upload the descriptor if it has been updated while it
2690 if (img_handle
->desc_dirty
)
2691 sctx
->bindless_descriptors_dirty
= true;
2693 /* Add the image handle to the per-context list. */
2694 util_dynarray_append(&sctx
->resident_img_handles
,
2695 struct si_image_handle
*, img_handle
);
2697 /* Add the buffers to the current CS in case si_begin_new_cs()
2698 * is not going to be called.
2700 si_sampler_view_add_buffer(sctx
, view
->resource
,
2701 (access
& PIPE_IMAGE_ACCESS_WRITE
) ?
2702 RADEON_USAGE_READWRITE
:
2703 RADEON_USAGE_READ
, false, false);
2705 /* Remove the image handle from the per-context list. */
2706 util_dynarray_delete_unordered(&sctx
->resident_img_handles
,
2707 struct si_image_handle
*,
2710 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2711 util_dynarray_delete_unordered(
2712 &sctx
->resident_img_needs_color_decompress
,
2713 struct si_image_handle
*,
2719 static void si_resident_buffers_add_all_to_bo_list(struct si_context
*sctx
)
2721 unsigned num_resident_tex_handles
, num_resident_img_handles
;
2723 num_resident_tex_handles
= sctx
->resident_tex_handles
.size
/
2724 sizeof(struct si_texture_handle
*);
2725 num_resident_img_handles
= sctx
->resident_img_handles
.size
/
2726 sizeof(struct si_image_handle
*);
2728 /* Add all resident texture handles. */
2729 util_dynarray_foreach(&sctx
->resident_tex_handles
,
2730 struct si_texture_handle
*, tex_handle
) {
2731 struct si_sampler_view
*sview
=
2732 (struct si_sampler_view
*)(*tex_handle
)->view
;
2734 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2736 sview
->is_stencil_sampler
, false);
2739 /* Add all resident image handles. */
2740 util_dynarray_foreach(&sctx
->resident_img_handles
,
2741 struct si_image_handle
*, img_handle
) {
2742 struct pipe_image_view
*view
= &(*img_handle
)->view
;
2744 si_sampler_view_add_buffer(sctx
, view
->resource
,
2745 RADEON_USAGE_READWRITE
,
2749 sctx
->num_resident_handles
+= num_resident_tex_handles
+
2750 num_resident_img_handles
;
2751 assert(sctx
->bo_list_add_all_resident_resources
);
2752 sctx
->bo_list_add_all_resident_resources
= false;
2755 /* INIT/DEINIT/UPLOAD */
2757 void si_init_all_descriptors(struct si_context
*sctx
)
2760 unsigned first_shader
=
2761 sctx
->has_graphics
? 0 : PIPE_SHADER_COMPUTE
;
2763 for (i
= first_shader
; i
< SI_NUM_SHADERS
; i
++) {
2764 bool is_2nd
= sctx
->chip_class
>= GFX9
&&
2765 (i
== PIPE_SHADER_TESS_CTRL
||
2766 i
== PIPE_SHADER_GEOMETRY
);
2767 unsigned num_sampler_slots
= SI_NUM_IMAGES
/ 2 + SI_NUM_SAMPLERS
;
2768 unsigned num_buffer_slots
= SI_NUM_SHADER_BUFFERS
+ SI_NUM_CONST_BUFFERS
;
2770 struct si_descriptors
*desc
;
2773 if (i
== PIPE_SHADER_TESS_CTRL
) {
2774 rel_dw_offset
= (R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
-
2775 R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2776 } else if (sctx
->chip_class
>= GFX10
) { /* PIPE_SHADER_GEOMETRY */
2777 rel_dw_offset
= (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
-
2778 R_00B230_SPI_SHADER_USER_DATA_GS_0
) / 4;
2780 rel_dw_offset
= (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
-
2781 R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2784 rel_dw_offset
= SI_SGPR_CONST_AND_SHADER_BUFFERS
;
2786 desc
= si_const_and_shader_buffer_descriptors(sctx
, i
);
2787 si_init_buffer_resources(&sctx
->const_and_shader_buffers
[i
], desc
,
2788 num_buffer_slots
, rel_dw_offset
,
2789 RADEON_PRIO_SHADER_RW_BUFFER
,
2790 RADEON_PRIO_CONST_BUFFER
);
2791 desc
->slot_index_to_bind_directly
= si_get_constbuf_slot(0);
2794 if (i
== PIPE_SHADER_TESS_CTRL
) {
2795 rel_dw_offset
= (R_00B40C_SPI_SHADER_USER_DATA_ADDR_HI_HS
-
2796 R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2797 } else if (sctx
->chip_class
>= GFX10
) { /* PIPE_SHADER_GEOMETRY */
2798 rel_dw_offset
= (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS
-
2799 R_00B230_SPI_SHADER_USER_DATA_GS_0
) / 4;
2801 rel_dw_offset
= (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS
-
2802 R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2805 rel_dw_offset
= SI_SGPR_SAMPLERS_AND_IMAGES
;
2808 desc
= si_sampler_and_image_descriptors(sctx
, i
);
2809 si_init_descriptors(desc
, rel_dw_offset
, 16, num_sampler_slots
);
2812 for (j
= 0; j
< SI_NUM_IMAGES
; j
++)
2813 memcpy(desc
->list
+ j
* 8, null_image_descriptor
, 8 * 4);
2814 for (; j
< SI_NUM_IMAGES
+ SI_NUM_SAMPLERS
* 2; j
++)
2815 memcpy(desc
->list
+ j
* 8, null_texture_descriptor
, 8 * 4);
2818 si_init_buffer_resources(&sctx
->rw_buffers
,
2819 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
],
2820 SI_NUM_RW_BUFFERS
, SI_SGPR_RW_BUFFERS
,
2821 /* The second priority is used by
2822 * const buffers in RW buffer slots. */
2823 RADEON_PRIO_SHADER_RINGS
, RADEON_PRIO_CONST_BUFFER
);
2824 sctx
->descriptors
[SI_DESCS_RW_BUFFERS
].num_active_slots
= SI_NUM_RW_BUFFERS
;
2826 /* Initialize an array of 1024 bindless descriptors, when the limit is
2827 * reached, just make it larger and re-upload the whole array.
2829 si_init_bindless_descriptors(sctx
, &sctx
->bindless_descriptors
,
2830 SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES
,
2833 sctx
->descriptors_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2835 /* Set pipe_context functions. */
2836 sctx
->b
.bind_sampler_states
= si_bind_sampler_states
;
2837 sctx
->b
.set_shader_images
= si_set_shader_images
;
2838 sctx
->b
.set_constant_buffer
= si_pipe_set_constant_buffer
;
2839 sctx
->b
.set_shader_buffers
= si_set_shader_buffers
;
2840 sctx
->b
.set_sampler_views
= si_set_sampler_views
;
2841 sctx
->b
.create_texture_handle
= si_create_texture_handle
;
2842 sctx
->b
.delete_texture_handle
= si_delete_texture_handle
;
2843 sctx
->b
.make_texture_handle_resident
= si_make_texture_handle_resident
;
2844 sctx
->b
.create_image_handle
= si_create_image_handle
;
2845 sctx
->b
.delete_image_handle
= si_delete_image_handle
;
2846 sctx
->b
.make_image_handle_resident
= si_make_image_handle_resident
;
2848 if (!sctx
->has_graphics
)
2851 sctx
->b
.set_polygon_stipple
= si_set_polygon_stipple
;
2853 /* Shader user data. */
2854 sctx
->atoms
.s
.shader_pointers
.emit
= si_emit_graphics_shader_pointers
;
2856 /* Set default and immutable mappings. */
2858 assert(sctx
->chip_class
>= GFX10
);
2859 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2861 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2864 if (sctx
->chip_class
== GFX9
) {
2865 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2866 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2867 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2868 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2870 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2871 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2872 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2873 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2875 si_set_user_data_base(sctx
, PIPE_SHADER_FRAGMENT
, R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2878 static bool si_upload_shader_descriptors(struct si_context
*sctx
, unsigned mask
)
2880 unsigned dirty
= sctx
->descriptors_dirty
& mask
;
2882 /* Assume nothing will go wrong: */
2883 sctx
->shader_pointers_dirty
|= dirty
;
2886 unsigned i
= u_bit_scan(&dirty
);
2888 if (!si_upload_descriptors(sctx
, &sctx
->descriptors
[i
]))
2892 sctx
->descriptors_dirty
&= ~mask
;
2894 si_upload_bindless_descriptors(sctx
);
2899 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
)
2901 const unsigned mask
= u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE
);
2902 return si_upload_shader_descriptors(sctx
, mask
);
2905 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
)
2907 /* Does not update rw_buffers as that is not needed for compute shaders
2908 * and the input buffer is using the same SGPR's anyway.
2910 const unsigned mask
= u_bit_consecutive(SI_DESCS_FIRST_COMPUTE
,
2911 SI_NUM_DESCS
- SI_DESCS_FIRST_COMPUTE
);
2912 return si_upload_shader_descriptors(sctx
, mask
);
2915 void si_release_all_descriptors(struct si_context
*sctx
)
2919 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2920 si_release_buffer_resources(&sctx
->const_and_shader_buffers
[i
],
2921 si_const_and_shader_buffer_descriptors(sctx
, i
));
2922 si_release_sampler_views(&sctx
->samplers
[i
]);
2923 si_release_image_views(&sctx
->images
[i
]);
2925 si_release_buffer_resources(&sctx
->rw_buffers
,
2926 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2927 for (i
= 0; i
< SI_NUM_VERTEX_BUFFERS
; i
++)
2928 pipe_vertex_buffer_unreference(&sctx
->vertex_buffer
[i
]);
2930 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2931 si_release_descriptors(&sctx
->descriptors
[i
]);
2933 si_resource_reference(&sctx
->vb_descriptors_buffer
, NULL
);
2934 sctx
->vb_descriptors_gpu_list
= NULL
; /* points into a mapped buffer */
2936 si_release_bindless_descriptors(sctx
);
2939 void si_gfx_resources_add_all_to_bo_list(struct si_context
*sctx
)
2941 for (unsigned i
= 0; i
< SI_NUM_GRAPHICS_SHADERS
; i
++) {
2942 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[i
]);
2943 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[i
]);
2944 si_image_views_begin_new_cs(sctx
, &sctx
->images
[i
]);
2946 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2947 si_vertex_buffers_begin_new_cs(sctx
);
2949 if (sctx
->bo_list_add_all_resident_resources
)
2950 si_resident_buffers_add_all_to_bo_list(sctx
);
2952 assert(sctx
->bo_list_add_all_gfx_resources
);
2953 sctx
->bo_list_add_all_gfx_resources
= false;
2956 void si_compute_resources_add_all_to_bo_list(struct si_context
*sctx
)
2958 unsigned sh
= PIPE_SHADER_COMPUTE
;
2960 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[sh
]);
2961 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[sh
]);
2962 si_image_views_begin_new_cs(sctx
, &sctx
->images
[sh
]);
2963 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2965 if (sctx
->bo_list_add_all_resident_resources
)
2966 si_resident_buffers_add_all_to_bo_list(sctx
);
2968 assert(sctx
->bo_list_add_all_compute_resources
);
2969 sctx
->bo_list_add_all_compute_resources
= false;
2972 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
)
2974 for (unsigned i
= 0; i
< SI_NUM_DESCS
; ++i
)
2975 si_descriptors_begin_new_cs(sctx
, &sctx
->descriptors
[i
]);
2976 si_descriptors_begin_new_cs(sctx
, &sctx
->bindless_descriptors
);
2978 si_shader_pointers_begin_new_cs(sctx
);
2980 sctx
->bo_list_add_all_resident_resources
= true;
2981 sctx
->bo_list_add_all_gfx_resources
= true;
2982 sctx
->bo_list_add_all_compute_resources
= true;
2985 void si_set_active_descriptors(struct si_context
*sctx
, unsigned desc_idx
,
2986 uint64_t new_active_mask
)
2988 struct si_descriptors
*desc
= &sctx
->descriptors
[desc_idx
];
2990 /* Ignore no-op updates and updates that disable all slots. */
2991 if (!new_active_mask
||
2992 new_active_mask
== u_bit_consecutive64(desc
->first_active_slot
,
2993 desc
->num_active_slots
))
2997 u_bit_scan_consecutive_range64(&new_active_mask
, &first
, &count
);
2998 assert(new_active_mask
== 0);
3000 /* Upload/dump descriptors if slots are being enabled. */
3001 if (first
< desc
->first_active_slot
||
3002 first
+ count
> desc
->first_active_slot
+ desc
->num_active_slots
)
3003 sctx
->descriptors_dirty
|= 1u << desc_idx
;
3005 desc
->first_active_slot
= first
;
3006 desc
->num_active_slots
= count
;
3009 void si_set_active_descriptors_for_shader(struct si_context
*sctx
,
3010 struct si_shader_selector
*sel
)
3015 si_set_active_descriptors(sctx
,
3016 si_const_and_shader_buffer_descriptors_idx(sel
->type
),
3017 sel
->active_const_and_shader_buffers
);
3018 si_set_active_descriptors(sctx
,
3019 si_sampler_and_image_descriptors_idx(sel
->type
),
3020 sel
->active_samplers_and_images
);