src/gallium/drivers/radeonsi/si_get.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "compiler/nir/nir.h"
  26 #include "radeon/radeon_uvd_enc.h"
  27 #include "radeon/radeon_vce.h"
  28 #include "radeon/radeon_video.h"
  29 #include "si_pipe.h"
  30 #include "util/u_screen.h"
  31 #include "util/u_video.h"
  32 #include "vl/vl_decoder.h"
  33 #include "vl/vl_video_buffer.h"
  34 #include <sys/utsname.h>
  35
  36 static const char *si_get_vendor(struct pipe_screen *pscreen)
  37 {
  38    /* Don't change this. Games such as Alien Isolation are broken if this
  39     * returns "Advanced Micro Devices, Inc."
  40     */
  41    return "X.Org";
  42 }
  43
  44 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
  45 {
  46    return "AMD";
  47 }
  48
  49 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  50 {
  51    struct si_screen *sscreen = (struct si_screen *)pscreen;
  52
  53    switch (param) {
  54    /* Supported features (boolean caps). */
  55    case PIPE_CAP_ACCELERATED:
  56    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  57    case PIPE_CAP_ANISOTROPIC_FILTER:
  58    case PIPE_CAP_POINT_SPRITE:
  59    case PIPE_CAP_OCCLUSION_QUERY:
  60    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  61    case PIPE_CAP_TEXTURE_SHADOW_LOD:
  62    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
  63    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  64    case PIPE_CAP_TEXTURE_SWIZZLE:
  65    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  66    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
  67    case PIPE_CAP_SHADER_STENCIL_EXPORT:
  68    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
  69    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  70    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  71    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  72    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  73    case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
  74    case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
  75    case PIPE_CAP_VERTEX_SHADER_SATURATE:
  76    case PIPE_CAP_SEAMLESS_CUBE_MAP:
  77    case PIPE_CAP_PRIMITIVE_RESTART:
  78    case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
  79    case PIPE_CAP_CONDITIONAL_RENDER:
  80    case PIPE_CAP_TEXTURE_BARRIER:
  81    case PIPE_CAP_INDEP_BLEND_ENABLE:
  82    case PIPE_CAP_INDEP_BLEND_FUNC:
  83    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  84    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
  85    case PIPE_CAP_START_INSTANCE:
  86    case PIPE_CAP_NPOT_TEXTURES:
  87    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  88    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
  89    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
  90    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
  91    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  92    case PIPE_CAP_TGSI_INSTANCEID:
  93    case PIPE_CAP_COMPUTE:
  94    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
  95    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
  96    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
  97    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  98    case PIPE_CAP_CUBE_MAP_ARRAY:
  99    case PIPE_CAP_SAMPLE_SHADING:
 100    case PIPE_CAP_DRAW_INDIRECT:
 101    case PIPE_CAP_CLIP_HALFZ:
 102    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 103    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 104    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 105    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 106    case PIPE_CAP_TGSI_TEXCOORD:
 107    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 108    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 109    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 110    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 111    case PIPE_CAP_SHAREABLE_SHADERS:
 112    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 113    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 114    case PIPE_CAP_TEXTURE_QUERY_LOD:
 115    case PIPE_CAP_TEXTURE_GATHER_SM5:
 116    case PIPE_CAP_TGSI_TXQS:
 117    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 118    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 119    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 120    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 121    case PIPE_CAP_INVALIDATE_BUFFER:
 122    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 123    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 124    case PIPE_CAP_QUERY_MEMORY_INFO:
 125    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 126    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 127    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 128    case PIPE_CAP_GENERATE_MIPMAP:
 129    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 130    case PIPE_CAP_STRING_MARKER:
 131    case PIPE_CAP_CLEAR_TEXTURE:
 132    case PIPE_CAP_CULL_DISTANCE:
 133    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 134    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 135    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 136    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 137    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 138    case PIPE_CAP_DOUBLES:
 139    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 140    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 141    case PIPE_CAP_BINDLESS_TEXTURE:
 142    case PIPE_CAP_QUERY_TIMESTAMP:
 143    case PIPE_CAP_QUERY_TIME_ELAPSED:
 144    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 145    case PIPE_CAP_MEMOBJ:
 146    case PIPE_CAP_LOAD_CONSTBUF:
 147    case PIPE_CAP_INT64:
 148    case PIPE_CAP_INT64_DIVMOD:
 149    case PIPE_CAP_TGSI_CLOCK:
 150    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 151    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 152    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 153    case PIPE_CAP_TGSI_BALLOT:
 154    case PIPE_CAP_TGSI_VOTE:
 155    case PIPE_CAP_FBFETCH:
 156    case PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK:
 157    case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 158    case PIPE_CAP_PREFER_COMPUTE_FOR_MULTIMEDIA:
 159    case PIPE_CAP_TGSI_DIV:
 160    case PIPE_CAP_PACKED_UNIFORMS:
 161    case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
 162    case PIPE_CAP_GL_SPIRV:
 163    case PIPE_CAP_DRAW_INFO_START_WITH_USER_INDICES:
 164    case PIPE_CAP_ALPHA_TO_COVERAGE_DITHER_CONTROL:
 165    case PIPE_CAP_MAP_UNSYNCHRONIZED_THREAD_SAFE:
 166       return 1;
 167
 168    case PIPE_CAP_GLSL_ZERO_INIT:
 169       return 2;
 170
 171    case PIPE_CAP_QUERY_SO_OVERFLOW:
 172       return !sscreen->use_ngg_streamout;
 173
 174    case PIPE_CAP_POST_DEPTH_COVERAGE:
 175       return sscreen->info.chip_class >= GFX10;
 176
 177    case PIPE_CAP_GRAPHICS:
 178       return sscreen->info.has_graphics;
 179
 180    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 181       return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 182
 183    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 184       return sscreen->info.has_gpu_reset_status_query;
 185
 186    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 187       return sscreen->info.has_2d_tiling;
 188
 189    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 190       return SI_MAP_BUFFER_ALIGNMENT;
 191
 192    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 193    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 194    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 195    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 196    case PIPE_CAP_MAX_VERTEX_STREAMS:
 197    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 198    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 199       return 4;
 200
 201    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 202    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 203       if (!sscreen->info.has_indirect_compute_dispatch)
 204          return 420;
 205       return 460;
 206
 207    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 208       /* Optimal number for good TexSubImage performance on Polaris10. */
 209       return 64 * 1024 * 1024;
 210
 211    case PIPE_CAP_GL_BEGIN_END_BUFFER_SIZE:
 212       return 4096 * 1024;
 213
 214    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 215    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 216       /* Align it down to 256 bytes. I've chosen the number randomly. */
 217       return ROUND_DOWN_TO(MIN2(sscreen->info.max_alloc_size, INT_MAX), 256);
 218
 219    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 220    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 221    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 222       return LLVM_VERSION_MAJOR < 9 && !sscreen->info.has_unaligned_shader_loads;
 223
 224    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 225       return sscreen->info.has_sparse_vm_mappings ? RADEON_SPARSE_PAGE_SIZE : 0;
 226
 227    case PIPE_CAP_UMA:
 228    case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF:
 229       return 0;
 230
 231    case PIPE_CAP_FENCE_SIGNAL:
 232       return sscreen->info.has_syncobj;
 233
 234    case PIPE_CAP_CONSTBUF0_FLAGS:
 235       return SI_RESOURCE_FLAG_32BIT;
 236
 237    case PIPE_CAP_NATIVE_FENCE_FD:
 238       return sscreen->info.has_fence_to_handle;
 239
 240    case PIPE_CAP_DRAW_PARAMETERS:
 241    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 242    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 243       return sscreen->has_draw_indirect_multi;
 244
 245    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 246       return 30;
 247
 248    case PIPE_CAP_MAX_VARYINGS:
 249       return 32;
 250
 251    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 252       return sscreen->info.chip_class <= GFX8 ? PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 253
 254    /* Stream output. */
 255    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 256    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 257       return 32 * 4;
 258
 259    /* Geometry shader output. */
 260    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 261       /* gfx9 has to report 256 to make piglit/gs-max-output pass.
 262        * gfx8 and earlier can do 1024.
 263        */
 264       return 256;
 265    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 266       return 4095;
 267    case PIPE_CAP_MAX_GS_INVOCATIONS:
 268       /* Even though the hw supports more, we officially wanna expose only 32. */
 269       return 32;
 270
 271    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 272       return 2048;
 273
 274    /* Texturing. */
 275    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 276       return 16384;
 277    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 278       return 15; /* 16384 */
 279    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 280       if (sscreen->info.chip_class >= GFX10)
 281          return 14;
 282       /* textures support 8192, but layered rendering supports 2048 */
 283       return 12;
 284    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 285       if (sscreen->info.chip_class >= GFX10)
 286          return 8192;
 287       /* textures support 8192, but layered rendering supports 2048 */
 288       return 2048;
 289
 290    /* Viewports and render targets. */
 291    case PIPE_CAP_MAX_VIEWPORTS:
 292       return SI_MAX_VIEWPORTS;
 293    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 294    case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 295    case PIPE_CAP_MAX_RENDER_TARGETS:
 296       return 8;
 297    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 298       return sscreen->info.has_eqaa_surface_allocator ? 2 : 0;
 299
 300    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 301    case PIPE_CAP_MIN_TEXEL_OFFSET:
 302       return -32;
 303
 304    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 305    case PIPE_CAP_MAX_TEXEL_OFFSET:
 306       return 31;
 307
 308    case PIPE_CAP_ENDIANNESS:
 309       return PIPE_ENDIAN_LITTLE;
 310
 311    case PIPE_CAP_VENDOR_ID:
 312       return ATI_VENDOR_ID;
 313    case PIPE_CAP_DEVICE_ID:
 314       return sscreen->info.pci_id;
 315    case PIPE_CAP_VIDEO_MEMORY:
 316       return sscreen->info.vram_size >> 20;
 317    case PIPE_CAP_PCI_GROUP:
 318       return sscreen->info.pci_domain;
 319    case PIPE_CAP_PCI_BUS:
 320       return sscreen->info.pci_bus;
 321    case PIPE_CAP_PCI_DEVICE:
 322       return sscreen->info.pci_dev;
 323    case PIPE_CAP_PCI_FUNCTION:
 324       return sscreen->info.pci_func;
 325    case PIPE_CAP_TGSI_ATOMINC_WRAP:
 326       return LLVM_VERSION_MAJOR >= 10;
 327
 328    default:
 329       return u_pipe_screen_get_param_defaults(pscreen, param);
 330    }
 331 }
 332
 333 static float si_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 334 {
 335    switch (param) {
 336    case PIPE_CAPF_MAX_LINE_WIDTH:
 337    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 338       /* This depends on the quant mode, though the precise interactions
 339        * are unknown. */
 340       return 2048;
 341    case PIPE_CAPF_MAX_POINT_WIDTH:
 342    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 343       return SI_MAX_POINT_SIZE;
 344    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 345       return 16.0f;
 346    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 347       return 16.0f;
 348    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 349    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 350    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 351       return 0.0f;
 352    }
 353    return 0.0f;
 354 }
 355
 356 static int si_get_shader_param(struct pipe_screen *pscreen, enum pipe_shader_type shader,
 357                                enum pipe_shader_cap param)
 358 {
 359    struct si_screen *sscreen = (struct si_screen *)pscreen;
 360
 361    switch (shader) {
 362    case PIPE_SHADER_FRAGMENT:
 363    case PIPE_SHADER_VERTEX:
 364    case PIPE_SHADER_GEOMETRY:
 365    case PIPE_SHADER_TESS_CTRL:
 366    case PIPE_SHADER_TESS_EVAL:
 367       break;
 368    case PIPE_SHADER_COMPUTE:
 369       switch (param) {
 370       case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 371          int ir = 1 << PIPE_SHADER_IR_NATIVE;
 372
 373          if (sscreen->info.has_indirect_compute_dispatch)
 374             ir |= 1 << PIPE_SHADER_IR_NIR;
 375
 376          return ir;
 377       }
 378       default:
 379          /* If compute shaders don't require a special value
 380           * for this cap, we can return the same value we
 381           * do for other shader types. */
 382          break;
 383       }
 384       break;
 385    default:
 386       return 0;
 387    }
 388
 389    switch (param) {
 390    /* Shader limits. */
 391    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 392    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 393    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 394    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 395    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 396       return 16384;
 397    case PIPE_SHADER_CAP_MAX_INPUTS:
 398       return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 399    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 400       return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 401    case PIPE_SHADER_CAP_MAX_TEMPS:
 402       return 256; /* Max native temporaries. */
 403    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 404       return si_get_param(pscreen, PIPE_CAP_MAX_SHADER_BUFFER_SIZE);
 405    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 406       return SI_NUM_CONST_BUFFERS;
 407    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 408    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 409       return SI_NUM_SAMPLERS;
 410    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 411       return SI_NUM_SHADER_BUFFERS;
 412    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 413       return SI_NUM_IMAGES;
 414    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 415       return 0;
 416    case PIPE_SHADER_CAP_PREFERRED_IR:
 417       return PIPE_SHADER_IR_NIR;
 418    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 419       return 4;
 420
 421    /* Supported boolean features. */
 422    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 423    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 424    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 425    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 426    case PIPE_SHADER_CAP_INTEGERS:
 427    case PIPE_SHADER_CAP_INT64_ATOMICS:
 428    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 429    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 430    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 431    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 432    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 433    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 434       return 1;
 435
 436    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 437       /* TODO: Indirect indexing of GS inputs is unimplemented. */
 438       if (shader == PIPE_SHADER_GEOMETRY)
 439          return 0;
 440
 441       if (shader == PIPE_SHADER_VERTEX && !sscreen->llvm_has_working_vgpr_indexing)
 442          return 0;
 443
 444       /* TCS and TES load inputs directly from LDS or offchip
 445        * memory, so indirect indexing is always supported.
 446        * PS has to support indirect indexing, because we can't
 447        * lower that to TEMPs for INTERP instructions.
 448        */
 449       return 1;
 450
 451    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 452       return sscreen->llvm_has_working_vgpr_indexing ||
 453              /* TCS stores outputs directly to memory. */
 454              shader == PIPE_SHADER_TESS_CTRL;
 455
 456    /* Unsupported boolean features. */
 457    case PIPE_SHADER_CAP_FP16:
 458    case PIPE_SHADER_CAP_FP16_DERIVATIVES:
 459    case PIPE_SHADER_CAP_INT16:
 460    case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
 461    case PIPE_SHADER_CAP_SUBROUTINES:
 462    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 463    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 464    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 465       return 0;
 466    }
 467    return 0;
 468 }
 469
 470 static const struct nir_shader_compiler_options nir_options = {
 471    .lower_scmp = true,
 472    .lower_flrp32 = true,
 473    .lower_flrp64 = true,
 474    .lower_fsat = true,
 475    .lower_fdiv = true,
 476    .lower_bitfield_insert_to_bitfield_select = true,
 477    .lower_bitfield_extract = true,
 478    .lower_sub = true,
 479    .fuse_ffma = true,
 480    .lower_fmod = true,
 481    .lower_pack_snorm_4x8 = true,
 482    .lower_pack_unorm_4x8 = true,
 483    .lower_unpack_snorm_2x16 = true,
 484    .lower_unpack_snorm_4x8 = true,
 485    .lower_unpack_unorm_2x16 = true,
 486    .lower_unpack_unorm_4x8 = true,
 487    .lower_extract_byte = true,
 488    .lower_extract_word = true,
 489    .lower_rotate = true,
 490    .lower_to_scalar = true,
 491    .optimize_sample_mask_in = true,
 492    .max_unroll_iterations = 32,
 493    .use_interpolated_input_intrinsics = true,
 494 };
 495
 496 static const void *si_get_compiler_options(struct pipe_screen *screen, enum pipe_shader_ir ir,
 497                                            enum pipe_shader_type shader)
 498 {
 499    assert(ir == PIPE_SHADER_IR_NIR);
 500    return &nir_options;
 501 }
 502
 503 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 504 {
 505    ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 506 }
 507
 508 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 509 {
 510    struct si_screen *sscreen = (struct si_screen *)pscreen;
 511
 512    ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
 513 }
 514
 515 static const char *si_get_name(struct pipe_screen *pscreen)
 516 {
 517    struct si_screen *sscreen = (struct si_screen *)pscreen;
 518
 519    return sscreen->renderer_string;
 520 }
 521
 522 static int si_get_video_param_no_decode(struct pipe_screen *screen, enum pipe_video_profile profile,
 523                                         enum pipe_video_entrypoint entrypoint,
 524                                         enum pipe_video_cap param)
 525 {
 526    switch (param) {
 527    case PIPE_VIDEO_CAP_SUPPORTED:
 528       return vl_profile_supported(screen, profile, entrypoint);
 529    case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 530       return 1;
 531    case PIPE_VIDEO_CAP_MAX_WIDTH:
 532    case PIPE_VIDEO_CAP_MAX_HEIGHT:
 533       return vl_video_buffer_max_size(screen);
 534    case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 535       return PIPE_FORMAT_NV12;
 536    case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 537       return false;
 538    case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 539       return false;
 540    case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 541       return true;
 542    case PIPE_VIDEO_CAP_MAX_LEVEL:
 543       return vl_level_supported(screen, profile);
 544    default:
 545       return 0;
 546    }
 547 }
 548
 549 static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profile profile,
 550                               enum pipe_video_entrypoint entrypoint, enum pipe_video_cap param)
 551 {
 552    struct si_screen *sscreen = (struct si_screen *)screen;
 553    enum pipe_video_format codec = u_reduce_video_profile(profile);
 554
 555    if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 556       switch (param) {
 557       case PIPE_VIDEO_CAP_SUPPORTED:
 558          return (
 559             (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 560              (sscreen->info.family >= CHIP_RAVEN || si_vce_is_fw_version_supported(sscreen))) ||
 561             (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
 562              (sscreen->info.family >= CHIP_RAVEN || si_radeon_uvd_enc_supported(sscreen))) ||
 563             (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 && sscreen->info.family >= CHIP_RENOIR));
 564       case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 565          return 1;
 566       case PIPE_VIDEO_CAP_MAX_WIDTH:
 567          return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 568       case PIPE_VIDEO_CAP_MAX_HEIGHT:
 569          return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
 570       case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 571          return PIPE_FORMAT_NV12;
 572       case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 573          return false;
 574       case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 575          return false;
 576       case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 577          return true;
 578       case PIPE_VIDEO_CAP_STACKED_FRAMES:
 579          return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
 580       default:
 581          return 0;
 582       }
 583    }
 584
 585    switch (param) {
 586    case PIPE_VIDEO_CAP_SUPPORTED:
 587       switch (codec) {
 588       case PIPE_VIDEO_FORMAT_MPEG12:
 589          return profile != PIPE_VIDEO_PROFILE_MPEG1;
 590       case PIPE_VIDEO_FORMAT_MPEG4:
 591          return 1;
 592       case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 593          if ((sscreen->info.family == CHIP_POLARIS10 || sscreen->info.family == CHIP_POLARIS11) &&
 594              sscreen->info.uvd_fw_version < UVD_FW_1_66_16) {
 595             RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 596             return false;
 597          }
 598          return true;
 599       case PIPE_VIDEO_FORMAT_VC1:
 600          return true;
 601       case PIPE_VIDEO_FORMAT_HEVC:
 602          /* Carrizo only supports HEVC Main */
 603          if (sscreen->info.family >= CHIP_STONEY)
 604             return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 605                     profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 606          else if (sscreen->info.family >= CHIP_CARRIZO)
 607             return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 608          return false;
 609       case PIPE_VIDEO_FORMAT_JPEG:
 610          if (sscreen->info.family >= CHIP_RAVEN)
 611             return true;
 612          if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
 613             return false;
 614          if (!(sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 19)) {
 615             RVID_ERR("No MJPEG support for the kernel version\n");
 616             return false;
 617          }
 618          return true;
 619       case PIPE_VIDEO_FORMAT_VP9:
 620          if (sscreen->info.family < CHIP_RAVEN)
 621             return false;
 622          return true;
 623       default:
 624          return false;
 625       }
 626    case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 627       return 1;
 628    case PIPE_VIDEO_CAP_MAX_WIDTH:
 629       switch (codec) {
 630       case PIPE_VIDEO_FORMAT_HEVC:
 631       case PIPE_VIDEO_FORMAT_VP9:
 632          return (sscreen->info.family < CHIP_RENOIR)
 633                    ? ((sscreen->info.family < CHIP_TONGA) ? 2048 : 4096)
 634                    : 8192;
 635       default:
 636          return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 637       }
 638    case PIPE_VIDEO_CAP_MAX_HEIGHT:
 639       switch (codec) {
 640       case PIPE_VIDEO_FORMAT_HEVC:
 641       case PIPE_VIDEO_FORMAT_VP9:
 642          return (sscreen->info.family < CHIP_RENOIR)
 643                    ? ((sscreen->info.family < CHIP_TONGA) ? 1152 : 4096)
 644                    : 4352;
 645       default:
 646          return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
 647       }
 648    case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 649       if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 650          return PIPE_FORMAT_P010;
 651       else if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 652          return PIPE_FORMAT_P010;
 653       else
 654          return PIPE_FORMAT_NV12;
 655
 656    case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 657    case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 658       enum pipe_video_format format = u_reduce_video_profile(profile);
 659
 660       if (format == PIPE_VIDEO_FORMAT_HEVC)
 661          return false; // The firmware doesn't support interlaced HEVC.
 662       else if (format == PIPE_VIDEO_FORMAT_JPEG)
 663          return false;
 664       else if (format == PIPE_VIDEO_FORMAT_VP9)
 665          return false;
 666       return true;
 667    }
 668    case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 669       return true;
 670    case PIPE_VIDEO_CAP_MAX_LEVEL:
 671       switch (profile) {
 672       case PIPE_VIDEO_PROFILE_MPEG1:
 673          return 0;
 674       case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 675       case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 676          return 3;
 677       case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 678          return 3;
 679       case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 680          return 5;
 681       case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 682          return 1;
 683       case PIPE_VIDEO_PROFILE_VC1_MAIN:
 684          return 2;
 685       case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 686          return 4;
 687       case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 688       case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 689       case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 690          return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
 691       case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 692       case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 693          return 186;
 694       default:
 695          return 0;
 696       }
 697    default:
 698       return 0;
 699    }
 700 }
 701
 702 static bool si_vid_is_format_supported(struct pipe_screen *screen, enum pipe_format format,
 703                                        enum pipe_video_profile profile,
 704                                        enum pipe_video_entrypoint entrypoint)
 705 {
 706    /* HEVC 10 bit decoding should use P010 instead of NV12 if possible */
 707    if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 708       return (format == PIPE_FORMAT_NV12) || (format == PIPE_FORMAT_P010) ||
 709              (format == PIPE_FORMAT_P016);
 710
 711    /* Vp9 profile 2 supports 10 bit decoding using P016 */
 712    if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 713       return (format == PIPE_FORMAT_P010) || (format == PIPE_FORMAT_P016);
 714
 715    /* we can only handle this one with UVD */
 716    if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 717       return format == PIPE_FORMAT_NV12;
 718
 719    return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 720 }
 721
 722 static unsigned get_max_threads_per_block(struct si_screen *screen, enum pipe_shader_ir ir_type)
 723 {
 724    if (ir_type == PIPE_SHADER_IR_NATIVE)
 725       return 256;
 726
 727    /* LLVM 10 only supports 1024 threads per block. */
 728    return 1024;
 729 }
 730
 731 static int si_get_compute_param(struct pipe_screen *screen, enum pipe_shader_ir ir_type,
 732                                 enum pipe_compute_cap param, void *ret)
 733 {
 734    struct si_screen *sscreen = (struct si_screen *)screen;
 735
 736    // TODO: select these params by asic
 737    switch (param) {
 738    case PIPE_COMPUTE_CAP_IR_TARGET: {
 739       const char *gpu, *triple;
 740
 741       triple = "amdgcn-mesa-mesa3d";
 742       gpu = ac_get_llvm_processor_name(sscreen->info.family);
 743       if (ret) {
 744          sprintf(ret, "%s-%s", gpu, triple);
 745       }
 746       /* +2 for dash and terminating NIL byte */
 747       return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 748    }
 749    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 750       if (ret) {
 751          uint64_t *grid_dimension = ret;
 752          grid_dimension[0] = 3;
 753       }
 754       return 1 * sizeof(uint64_t);
 755
 756    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 757       if (ret) {
 758          uint64_t *grid_size = ret;
 759          grid_size[0] = 65535;
 760          grid_size[1] = 65535;
 761          grid_size[2] = 65535;
 762       }
 763       return 3 * sizeof(uint64_t);
 764
 765    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 766       if (ret) {
 767          uint64_t *block_size = ret;
 768          unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 769          block_size[0] = threads_per_block;
 770          block_size[1] = threads_per_block;
 771          block_size[2] = threads_per_block;
 772       }
 773       return 3 * sizeof(uint64_t);
 774
 775    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 776       if (ret) {
 777          uint64_t *max_threads_per_block = ret;
 778          *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 779       }
 780       return sizeof(uint64_t);
 781    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 782       if (ret) {
 783          uint32_t *address_bits = ret;
 784          address_bits[0] = 64;
 785       }
 786       return 1 * sizeof(uint32_t);
 787
 788    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 789       if (ret) {
 790          uint64_t *max_global_size = ret;
 791          uint64_t max_mem_alloc_size;
 792
 793          si_get_compute_param(screen, ir_type, PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 794                               &max_mem_alloc_size);
 795
 796          /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 797           * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 798           * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 799           * make sure we never report more than
 800           * 4 * MAX_MEM_ALLOC_SIZE.
 801           */
 802          *max_global_size =
 803             MIN2(4 * max_mem_alloc_size, MAX2(sscreen->info.gart_size, sscreen->info.vram_size));
 804       }
 805       return sizeof(uint64_t);
 806
 807    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 808       if (ret) {
 809          uint64_t *max_local_size = ret;
 810          /* Value reported by the closed source driver. */
 811          *max_local_size = 32768;
 812       }
 813       return sizeof(uint64_t);
 814
 815    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 816       if (ret) {
 817          uint64_t *max_input_size = ret;
 818          /* Value reported by the closed source driver. */
 819          *max_input_size = 1024;
 820       }
 821       return sizeof(uint64_t);
 822
 823    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 824       if (ret) {
 825          uint64_t *max_mem_alloc_size = ret;
 826
 827          *max_mem_alloc_size = sscreen->info.max_alloc_size;
 828       }
 829       return sizeof(uint64_t);
 830
 831    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 832       if (ret) {
 833          uint32_t *max_clock_frequency = ret;
 834          *max_clock_frequency = sscreen->info.max_shader_clock;
 835       }
 836       return sizeof(uint32_t);
 837
 838    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 839       if (ret) {
 840          uint32_t *max_compute_units = ret;
 841          *max_compute_units = sscreen->info.num_good_compute_units;
 842       }
 843       return sizeof(uint32_t);
 844
 845    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 846       if (ret) {
 847          uint32_t *images_supported = ret;
 848          *images_supported = 0;
 849       }
 850       return sizeof(uint32_t);
 851    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 852       break; /* unused */
 853    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 854       if (ret) {
 855          uint32_t *subgroup_size = ret;
 856          *subgroup_size = sscreen->compute_wave_size;
 857       }
 858       return sizeof(uint32_t);
 859    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 860       if (ret) {
 861          uint64_t *max_variable_threads_per_block = ret;
 862          if (ir_type == PIPE_SHADER_IR_NATIVE)
 863             *max_variable_threads_per_block = 0;
 864          else
 865             *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
 866       }
 867       return sizeof(uint64_t);
 868    }
 869
 870    fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 871    return 0;
 872 }
 873
 874 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 875 {
 876    struct si_screen *sscreen = (struct si_screen *)screen;
 877
 878    return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
 879           sscreen->info.clock_crystal_freq;
 880 }
 881
 882 static void si_query_memory_info(struct pipe_screen *screen, struct pipe_memory_info *info)
 883 {
 884    struct si_screen *sscreen = (struct si_screen *)screen;
 885    struct radeon_winsys *ws = sscreen->ws;
 886    unsigned vram_usage, gtt_usage;
 887
 888    info->total_device_memory = sscreen->info.vram_size / 1024;
 889    info->total_staging_memory = sscreen->info.gart_size / 1024;
 890
 891    /* The real TTM memory usage is somewhat random, because:
 892     *
 893     * 1) TTM delays freeing memory, because it can only free it after
 894     *    fences expire.
 895     *
 896     * 2) The memory usage can be really low if big VRAM evictions are
 897     *    taking place, but the real usage is well above the size of VRAM.
 898     *
 899     * Instead, return statistics of this process.
 900     */
 901    vram_usage = ws->query_value(ws, RADEON_VRAM_USAGE) / 1024;
 902    gtt_usage = ws->query_value(ws, RADEON_GTT_USAGE) / 1024;
 903
 904    info->avail_device_memory =
 905       vram_usage <= info->total_device_memory ? info->total_device_memory - vram_usage : 0;
 906    info->avail_staging_memory =
 907       gtt_usage <= info->total_staging_memory ? info->total_staging_memory - gtt_usage : 0;
 908
 909    info->device_memory_evicted = ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 910
 911    if (sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 4)
 912       info->nr_device_memory_evictions = ws->query_value(ws, RADEON_NUM_EVICTIONS);
 913    else
 914       /* Just return the number of evicted 64KB pages. */
 915       info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 916 }
 917
 918 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 919 {
 920    struct si_screen *sscreen = (struct si_screen *)pscreen;
 921
 922    return sscreen->disk_shader_cache;
 923 }
 924
 925 static void si_init_renderer_string(struct si_screen *sscreen)
 926 {
 927    char first_name[256], second_name[32] = {}, kernel_version[128] = {};
 928    struct utsname uname_data;
 929
 930    if (sscreen->info.marketing_name) {
 931       snprintf(first_name, sizeof(first_name), "%s", sscreen->info.marketing_name);
 932       snprintf(second_name, sizeof(second_name), "%s, ", sscreen->info.name);
 933    } else {
 934       snprintf(first_name, sizeof(first_name), "AMD %s", sscreen->info.name);
 935    }
 936
 937    if (uname(&uname_data) == 0)
 938       snprintf(kernel_version, sizeof(kernel_version), ", %s", uname_data.release);
 939
 940    snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
 941             "%s (%sDRM %i.%i.%i%s, LLVM " MESA_LLVM_VERSION_STRING ")", first_name, second_name,
 942             sscreen->info.drm_major, sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
 943             kernel_version);
 944 }
 945
 946 void si_init_screen_get_functions(struct si_screen *sscreen)
 947 {
 948    sscreen->b.get_name = si_get_name;
 949    sscreen->b.get_vendor = si_get_vendor;
 950    sscreen->b.get_device_vendor = si_get_device_vendor;
 951    sscreen->b.get_param = si_get_param;
 952    sscreen->b.get_paramf = si_get_paramf;
 953    sscreen->b.get_compute_param = si_get_compute_param;
 954    sscreen->b.get_timestamp = si_get_timestamp;
 955    sscreen->b.get_shader_param = si_get_shader_param;
 956    sscreen->b.get_compiler_options = si_get_compiler_options;
 957    sscreen->b.get_device_uuid = si_get_device_uuid;
 958    sscreen->b.get_driver_uuid = si_get_driver_uuid;
 959    sscreen->b.query_memory_info = si_query_memory_info;
 960    sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
 961
 962    if (sscreen->info.has_hw_decode) {
 963       sscreen->b.get_video_param = si_get_video_param;
 964       sscreen->b.is_video_format_supported = si_vid_is_format_supported;
 965    } else {
 966       sscreen->b.get_video_param = si_get_video_param_no_decode;
 967       sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
 968    }
 969
 970    si_init_renderer_string(sscreen);
 971 }