src/gallium/drivers/radeonsi/si_get.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "si_pipe.h"
  26 #include "radeon/radeon_video.h"
  27 #include "radeon/radeon_vce.h"
  28 #include "radeon/radeon_uvd_enc.h"
  29 #include "ac_llvm_util.h"
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32 #include "util/u_screen.h"
  33 #include "util/u_video.h"
  34 #include "compiler/nir/nir.h"
  35
  36 #include <sys/utsname.h>
  37
  38 static const char *si_get_vendor(struct pipe_screen *pscreen)
  39 {
  40         /* Don't change this. Games such as Alien Isolation are broken if this
  41          * returns "Advanced Micro Devices, Inc."
  42          */
  43         return "X.Org";
  44 }
  45
  46 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
  47 {
  48         return "AMD";
  49 }
  50
  51 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  52 {
  53         struct si_screen *sscreen = (struct si_screen *)pscreen;
  54
  55         switch (param) {
  56         /* Supported features (boolean caps). */
  57         case PIPE_CAP_ACCELERATED:
  58         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  59         case PIPE_CAP_ANISOTROPIC_FILTER:
  60         case PIPE_CAP_POINT_SPRITE:
  61         case PIPE_CAP_OCCLUSION_QUERY:
  62         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  63         case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
  64         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  65         case PIPE_CAP_TEXTURE_SWIZZLE:
  66         case PIPE_CAP_DEPTH_CLIP_DISABLE:
  67         case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
  68         case PIPE_CAP_SHADER_STENCIL_EXPORT:
  69         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
  70         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  71         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  72         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  73         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  74         case PIPE_CAP_SM3:
  75         case PIPE_CAP_SEAMLESS_CUBE_MAP:
  76         case PIPE_CAP_PRIMITIVE_RESTART:
  77         case PIPE_CAP_CONDITIONAL_RENDER:
  78         case PIPE_CAP_TEXTURE_BARRIER:
  79         case PIPE_CAP_INDEP_BLEND_ENABLE:
  80         case PIPE_CAP_INDEP_BLEND_FUNC:
  81         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  82         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
  83         case PIPE_CAP_START_INSTANCE:
  84         case PIPE_CAP_NPOT_TEXTURES:
  85         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  86         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
  87         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
  88         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
  89         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  90         case PIPE_CAP_TGSI_INSTANCEID:
  91         case PIPE_CAP_COMPUTE:
  92         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
  93         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
  94         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
  95         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  96         case PIPE_CAP_CUBE_MAP_ARRAY:
  97         case PIPE_CAP_SAMPLE_SHADING:
  98         case PIPE_CAP_DRAW_INDIRECT:
  99         case PIPE_CAP_CLIP_HALFZ:
 100         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 101         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 102         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 103         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 104         case PIPE_CAP_TGSI_TEXCOORD:
 105         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 106         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 107         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 108         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 109         case PIPE_CAP_SHAREABLE_SHADERS:
 110         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 111         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 112         case PIPE_CAP_TEXTURE_QUERY_LOD:
 113         case PIPE_CAP_TEXTURE_GATHER_SM5:
 114         case PIPE_CAP_TGSI_TXQS:
 115         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 116         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 117         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 118         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 119         case PIPE_CAP_INVALIDATE_BUFFER:
 120         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 121         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 122         case PIPE_CAP_QUERY_MEMORY_INFO:
 123         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 124         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 125         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 126         case PIPE_CAP_GENERATE_MIPMAP:
 127         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 128         case PIPE_CAP_STRING_MARKER:
 129         case PIPE_CAP_CLEAR_TEXTURE:
 130         case PIPE_CAP_CULL_DISTANCE:
 131         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 132         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 133         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 134         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 135         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 136         case PIPE_CAP_DOUBLES:
 137         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 138         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 139         case PIPE_CAP_BINDLESS_TEXTURE:
 140         case PIPE_CAP_QUERY_TIMESTAMP:
 141         case PIPE_CAP_QUERY_TIME_ELAPSED:
 142         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 143         case PIPE_CAP_QUERY_SO_OVERFLOW:
 144         case PIPE_CAP_MEMOBJ:
 145         case PIPE_CAP_LOAD_CONSTBUF:
 146         case PIPE_CAP_INT64:
 147         case PIPE_CAP_INT64_DIVMOD:
 148         case PIPE_CAP_TGSI_CLOCK:
 149         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 150         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 151         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 152         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 153         case PIPE_CAP_TGSI_BALLOT:
 154         case PIPE_CAP_TGSI_VOTE:
 155         case PIPE_CAP_FBFETCH:
 156         case PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK:
 157         case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 158         case PIPE_CAP_PREFER_COMPUTE_BLIT_FOR_MULTIMEDIA:
 159         case PIPE_CAP_TGSI_DIV:
 160                 return 1;
 161
 162         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 163                 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 164
 165         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 166                 return sscreen->info.has_gpu_reset_status_query;
 167
 168         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 169                 return sscreen->info.has_2d_tiling;
 170
 171         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 172                 return SI_MAP_BUFFER_ALIGNMENT;
 173
 174         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 175         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 176         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 177         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 178         case PIPE_CAP_MAX_VERTEX_STREAMS:
 179         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 180         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 181                 return 4;
 182
 183         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 184         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 185                 if (sscreen->info.has_indirect_compute_dispatch)
 186                                 return 450;
 187                 return 420;
 188
 189         case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 190                 /* Optimal number for good TexSubImage performance on Polaris10. */
 191                 return 64 * 1024 * 1024;
 192
 193         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 194         case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 195                 return MIN2(sscreen->info.max_alloc_size, INT_MAX);
 196
 197         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 198         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 199         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 200                 return HAVE_LLVM < 0x0900 && !sscreen->info.has_unaligned_shader_loads;
 201
 202         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 203                 return sscreen->info.has_sparse_vm_mappings ?
 204                                 RADEON_SPARSE_PAGE_SIZE : 0;
 205
 206         case PIPE_CAP_PACKED_UNIFORMS:
 207                 if (sscreen->options.enable_nir)
 208                         return 1;
 209                 return 0;
 210
 211         /* Unsupported features. */
 212         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 213         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 214         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 215         case PIPE_CAP_USER_VERTEX_BUFFERS:
 216         case PIPE_CAP_FAKE_SW_MSAA:
 217         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 218         case PIPE_CAP_VERTEXID_NOBASE:
 219         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 220         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 221         case PIPE_CAP_UMA:
 222         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 223         case PIPE_CAP_POST_DEPTH_COVERAGE:
 224         case PIPE_CAP_TILE_RASTER_ORDER:
 225         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 226         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 227         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 228         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 229         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 230         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 231         case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 232         case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 233         case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 234                 return 0;
 235
 236         case PIPE_CAP_FENCE_SIGNAL:
 237                 return sscreen->info.has_syncobj;
 238
 239         case PIPE_CAP_CONSTBUF0_FLAGS:
 240                 return SI_RESOURCE_FLAG_32BIT;
 241
 242         case PIPE_CAP_NATIVE_FENCE_FD:
 243                 return sscreen->info.has_fence_to_handle;
 244
 245         case PIPE_CAP_DRAW_PARAMETERS:
 246         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 247         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 248                 return sscreen->has_draw_indirect_multi;
 249
 250         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 251                 return 30;
 252
 253         case PIPE_CAP_MAX_VARYINGS:
 254                 return 32;
 255
 256         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 257                 return sscreen->info.chip_class <= GFX8 ?
 258                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 259
 260         /* Stream output. */
 261         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 262         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 263                 return 32*4;
 264
 265         /* Geometry shader output. */
 266         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 267                 /* gfx9 has to report 256 to make piglit/gs-max-output pass.
 268                  * gfx8 and earlier can do 1024.
 269                  */
 270                 return 256;
 271         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 272                 return 4095;
 273         case PIPE_CAP_MAX_GS_INVOCATIONS:
 274                 /* The closed driver exposes 127, but 125 is the greatest
 275                  * number that works. */
 276                 return 125;
 277
 278         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 279                 return 2048;
 280
 281         /* Texturing. */
 282         case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 283                 return 16384;
 284         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 285                 return 15; /* 16384 */
 286         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 287                 /* textures support 8192, but layered rendering supports 2048 */
 288                 return 12;
 289         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 290                 /* textures support 8192, but layered rendering supports 2048 */
 291                 return 2048;
 292
 293         /* Viewports and render targets. */
 294         case PIPE_CAP_MAX_VIEWPORTS:
 295                 return SI_MAX_VIEWPORTS;
 296         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 297         case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 298         case PIPE_CAP_MAX_RENDER_TARGETS:
 299                 return 8;
 300         case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 301                 return sscreen->info.has_eqaa_surface_allocator ? 2 : 0;
 302
 303         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 304         case PIPE_CAP_MIN_TEXEL_OFFSET:
 305                 return -32;
 306
 307         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 308         case PIPE_CAP_MAX_TEXEL_OFFSET:
 309                 return 31;
 310
 311         case PIPE_CAP_ENDIANNESS:
 312                 return PIPE_ENDIAN_LITTLE;
 313
 314         case PIPE_CAP_VENDOR_ID:
 315                 return ATI_VENDOR_ID;
 316         case PIPE_CAP_DEVICE_ID:
 317                 return sscreen->info.pci_id;
 318         case PIPE_CAP_VIDEO_MEMORY:
 319                 return sscreen->info.vram_size >> 20;
 320         case PIPE_CAP_PCI_GROUP:
 321                 return sscreen->info.pci_domain;
 322         case PIPE_CAP_PCI_BUS:
 323                 return sscreen->info.pci_bus;
 324         case PIPE_CAP_PCI_DEVICE:
 325                 return sscreen->info.pci_dev;
 326         case PIPE_CAP_PCI_FUNCTION:
 327                 return sscreen->info.pci_func;
 328
 329         default:
 330                 return u_pipe_screen_get_param_defaults(pscreen, param);
 331         }
 332 }
 333
 334 static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
 335 {
 336         switch (param) {
 337         case PIPE_CAPF_MAX_LINE_WIDTH:
 338         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 339                 /* This depends on the quant mode, though the precise interactions
 340                  * are unknown. */
 341                 return 2048;
 342         case PIPE_CAPF_MAX_POINT_WIDTH:
 343         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 344                 return SI_MAX_POINT_SIZE;
 345         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 346                 return 16.0f;
 347         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 348                 return 16.0f;
 349         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 350         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 351         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 352                 return 0.0f;
 353         }
 354         return 0.0f;
 355 }
 356
 357 static int si_get_shader_param(struct pipe_screen* pscreen,
 358                                enum pipe_shader_type shader,
 359                                enum pipe_shader_cap param)
 360 {
 361         struct si_screen *sscreen = (struct si_screen *)pscreen;
 362
 363         switch(shader)
 364         {
 365         case PIPE_SHADER_FRAGMENT:
 366         case PIPE_SHADER_VERTEX:
 367         case PIPE_SHADER_GEOMETRY:
 368         case PIPE_SHADER_TESS_CTRL:
 369         case PIPE_SHADER_TESS_EVAL:
 370                 break;
 371         case PIPE_SHADER_COMPUTE:
 372                 switch (param) {
 373                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 374                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 375
 376                         if (sscreen->info.has_indirect_compute_dispatch)
 377                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 378
 379                         return ir;
 380                 }
 381
 382                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 383                         uint64_t max_const_buffer_size;
 384                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 385                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 386                                 &max_const_buffer_size);
 387                         return MIN2(max_const_buffer_size, INT_MAX);
 388                 }
 389                 default:
 390                         /* If compute shaders don't require a special value
 391                          * for this cap, we can return the same value we
 392                          * do for other shader types. */
 393                         break;
 394                 }
 395                 break;
 396         default:
 397                 return 0;
 398         }
 399
 400         switch (param) {
 401         /* Shader limits. */
 402         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 403         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 404         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 405         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 406         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 407                 return 16384;
 408         case PIPE_SHADER_CAP_MAX_INPUTS:
 409                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 410         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 411                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 412         case PIPE_SHADER_CAP_MAX_TEMPS:
 413                 return 256; /* Max native temporaries. */
 414         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 415                 return MIN2(sscreen->info.max_alloc_size, INT_MAX - 3); /* aligned to 4 */
 416         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 417                 return SI_NUM_CONST_BUFFERS;
 418         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 419         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 420                 return SI_NUM_SAMPLERS;
 421         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 422                 return SI_NUM_SHADER_BUFFERS;
 423         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 424                 return SI_NUM_IMAGES;
 425         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 426                 if (sscreen->options.enable_nir)
 427                         return 0;
 428                 return 32;
 429         case PIPE_SHADER_CAP_PREFERRED_IR:
 430                 if (sscreen->options.enable_nir)
 431                         return PIPE_SHADER_IR_NIR;
 432                 return PIPE_SHADER_IR_TGSI;
 433         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 434                 return 4;
 435
 436         /* Supported boolean features. */
 437         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 438         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 439         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 440         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 441         case PIPE_SHADER_CAP_INTEGERS:
 442         case PIPE_SHADER_CAP_INT64_ATOMICS:
 443         case PIPE_SHADER_CAP_FP16:
 444         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 445         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 446         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 447         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 448         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 449         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 450                 return 1;
 451
 452         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 453                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 454                 if (shader == PIPE_SHADER_GEOMETRY)
 455                         return 0;
 456
 457                 if (shader == PIPE_SHADER_VERTEX &&
 458                     !sscreen->llvm_has_working_vgpr_indexing)
 459                         return 0;
 460
 461                 /* TCS and TES load inputs directly from LDS or offchip
 462                  * memory, so indirect indexing is always supported.
 463                  * PS has to support indirect indexing, because we can't
 464                  * lower that to TEMPs for INTERP instructions.
 465                  */
 466                 return 1;
 467
 468         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 469                 return sscreen->llvm_has_working_vgpr_indexing ||
 470                        /* TCS stores outputs directly to memory. */
 471                        shader == PIPE_SHADER_TESS_CTRL;
 472
 473         /* Unsupported boolean features. */
 474         case PIPE_SHADER_CAP_SUBROUTINES:
 475         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 476         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 477         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 478                 return 0;
 479         case PIPE_SHADER_CAP_SCALAR_ISA:
 480                 return 1;
 481         }
 482         return 0;
 483 }
 484
 485 static const struct nir_shader_compiler_options nir_options = {
 486         .lower_scmp = true,
 487         .lower_flrp32 = true,
 488         .lower_flrp64 = true,
 489         .lower_fsat = true,
 490         .lower_fdiv = true,
 491         .lower_bitfield_insert_to_bitfield_select = true,
 492         .lower_bitfield_extract = true,
 493         .lower_sub = true,
 494         .lower_ffma = true,
 495         .lower_fmod = true,
 496         .lower_pack_snorm_2x16 = true,
 497         .lower_pack_snorm_4x8 = true,
 498         .lower_pack_unorm_2x16 = true,
 499         .lower_pack_unorm_4x8 = true,
 500         .lower_unpack_snorm_2x16 = true,
 501         .lower_unpack_snorm_4x8 = true,
 502         .lower_unpack_unorm_2x16 = true,
 503         .lower_unpack_unorm_4x8 = true,
 504         .lower_extract_byte = true,
 505         .lower_extract_word = true,
 506         .lower_rotate = true,
 507         .optimize_sample_mask_in = true,
 508         .max_unroll_iterations = 32,
 509 };
 510
 511 static const void *
 512 si_get_compiler_options(struct pipe_screen *screen,
 513                         enum pipe_shader_ir ir,
 514                         enum pipe_shader_type shader)
 515 {
 516         assert(ir == PIPE_SHADER_IR_NIR);
 517         return &nir_options;
 518 }
 519
 520 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 521 {
 522         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 523 }
 524
 525 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 526 {
 527         struct si_screen *sscreen = (struct si_screen *)pscreen;
 528
 529         ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
 530 }
 531
 532 static const char* si_get_name(struct pipe_screen *pscreen)
 533 {
 534         struct si_screen *sscreen = (struct si_screen*)pscreen;
 535
 536         return sscreen->renderer_string;
 537 }
 538
 539 static int si_get_video_param_no_decode(struct pipe_screen *screen,
 540                                         enum pipe_video_profile profile,
 541                                         enum pipe_video_entrypoint entrypoint,
 542                                         enum pipe_video_cap param)
 543 {
 544         switch (param) {
 545         case PIPE_VIDEO_CAP_SUPPORTED:
 546                 return vl_profile_supported(screen, profile, entrypoint);
 547         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 548                 return 1;
 549         case PIPE_VIDEO_CAP_MAX_WIDTH:
 550         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 551                 return vl_video_buffer_max_size(screen);
 552         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 553                 return PIPE_FORMAT_NV12;
 554         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 555                 return false;
 556         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 557                 return false;
 558         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 559                 return true;
 560         case PIPE_VIDEO_CAP_MAX_LEVEL:
 561                 return vl_level_supported(screen, profile);
 562         default:
 563                 return 0;
 564         }
 565 }
 566
 567 static int si_get_video_param(struct pipe_screen *screen,
 568                               enum pipe_video_profile profile,
 569                               enum pipe_video_entrypoint entrypoint,
 570                               enum pipe_video_cap param)
 571 {
 572         struct si_screen *sscreen = (struct si_screen *)screen;
 573         enum pipe_video_format codec = u_reduce_video_profile(profile);
 574
 575         if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 576                 switch (param) {
 577                 case PIPE_VIDEO_CAP_SUPPORTED:
 578                         return (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 579                                 (si_vce_is_fw_version_supported(sscreen) ||
 580                                  sscreen->info.family == CHIP_RAVEN ||
 581                                  sscreen->info.family == CHIP_RAVEN2)) ||
 582                                 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
 583                                 (sscreen->info.family == CHIP_RAVEN ||
 584                                  sscreen->info.family == CHIP_RAVEN2 ||
 585                                  si_radeon_uvd_enc_supported(sscreen)));
 586                 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 587                         return 1;
 588                 case PIPE_VIDEO_CAP_MAX_WIDTH:
 589                         return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 590                 case PIPE_VIDEO_CAP_MAX_HEIGHT:
 591                         return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
 592                 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 593                         return PIPE_FORMAT_NV12;
 594                 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 595                         return false;
 596                 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 597                         return false;
 598                 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 599                         return true;
 600                 case PIPE_VIDEO_CAP_STACKED_FRAMES:
 601                         return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
 602                 default:
 603                         return 0;
 604                 }
 605         }
 606
 607         switch (param) {
 608         case PIPE_VIDEO_CAP_SUPPORTED:
 609                 switch (codec) {
 610                 case PIPE_VIDEO_FORMAT_MPEG12:
 611                         return profile != PIPE_VIDEO_PROFILE_MPEG1;
 612                 case PIPE_VIDEO_FORMAT_MPEG4:
 613                         return 1;
 614                 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 615                         if ((sscreen->info.family == CHIP_POLARIS10 ||
 616                              sscreen->info.family == CHIP_POLARIS11) &&
 617                             sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
 618                                 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 619                                 return false;
 620                         }
 621                         return true;
 622                 case PIPE_VIDEO_FORMAT_VC1:
 623                         return true;
 624                 case PIPE_VIDEO_FORMAT_HEVC:
 625                         /* Carrizo only supports HEVC Main */
 626                         if (sscreen->info.family >= CHIP_STONEY)
 627                                 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 628                                         profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 629                         else if (sscreen->info.family >= CHIP_CARRIZO)
 630                                 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 631                         return false;
 632                 case PIPE_VIDEO_FORMAT_JPEG:
 633                         if (sscreen->info.family == CHIP_RAVEN ||
 634                             sscreen->info.family == CHIP_RAVEN2)
 635                                 return true;
 636                         if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
 637                                 return false;
 638                         if (!(sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 19)) {
 639                                 RVID_ERR("No MJPEG support for the kernel version\n");
 640                                 return false;
 641                         }
 642                         return true;
 643                 case PIPE_VIDEO_FORMAT_VP9:
 644                         if (sscreen->info.family < CHIP_RAVEN)
 645                                 return false;
 646                         return true;
 647                 default:
 648                         return false;
 649                 }
 650         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 651                 return 1;
 652         case PIPE_VIDEO_CAP_MAX_WIDTH:
 653                 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 654         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 655                 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
 656         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 657                 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 ||
 658                     profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 659                         return PIPE_FORMAT_P016;
 660                 else
 661                         return PIPE_FORMAT_NV12;
 662
 663         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 664         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 665                 enum pipe_video_format format = u_reduce_video_profile(profile);
 666
 667                 if (format == PIPE_VIDEO_FORMAT_HEVC)
 668                         return false; //The firmware doesn't support interlaced HEVC.
 669                 else if (format == PIPE_VIDEO_FORMAT_JPEG)
 670                         return false;
 671                 else if (format == PIPE_VIDEO_FORMAT_VP9)
 672                         return false;
 673                 return true;
 674         }
 675         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 676                 return true;
 677         case PIPE_VIDEO_CAP_MAX_LEVEL:
 678                 switch (profile) {
 679                 case PIPE_VIDEO_PROFILE_MPEG1:
 680                         return 0;
 681                 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 682                 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 683                         return 3;
 684                 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 685                         return 3;
 686                 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 687                         return 5;
 688                 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 689                         return 1;
 690                 case PIPE_VIDEO_PROFILE_VC1_MAIN:
 691                         return 2;
 692                 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 693                         return 4;
 694                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 695                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 696                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 697                         return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
 698                 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 699                 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 700                         return 186;
 701                 default:
 702                         return 0;
 703                 }
 704         default:
 705                 return 0;
 706         }
 707 }
 708
 709 static boolean si_vid_is_format_supported(struct pipe_screen *screen,
 710                                           enum pipe_format format,
 711                                           enum pipe_video_profile profile,
 712                                           enum pipe_video_entrypoint entrypoint)
 713 {
 714         /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
 715         if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 716                 return (format == PIPE_FORMAT_NV12) ||
 717                         (format == PIPE_FORMAT_P016);
 718
 719         /* we can only handle this one with UVD */
 720         if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 721                 return format == PIPE_FORMAT_NV12;
 722
 723         return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 724 }
 725
 726 static unsigned get_max_threads_per_block(struct si_screen *screen,
 727                                           enum pipe_shader_ir ir_type)
 728 {
 729         if (ir_type == PIPE_SHADER_IR_NATIVE)
 730                 return 256;
 731
 732         /* Only 16 waves per thread-group on gfx9. */
 733         if (screen->info.chip_class >= GFX9)
 734                 return 1024;
 735
 736         /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
 737          * round number.
 738          */
 739         return 2048;
 740 }
 741
 742 static int si_get_compute_param(struct pipe_screen *screen,
 743                                 enum pipe_shader_ir ir_type,
 744                                 enum pipe_compute_cap param,
 745                                 void *ret)
 746 {
 747         struct si_screen *sscreen = (struct si_screen *)screen;
 748
 749         //TODO: select these params by asic
 750         switch (param) {
 751         case PIPE_COMPUTE_CAP_IR_TARGET: {
 752                 const char *gpu, *triple;
 753
 754                 triple = "amdgcn-mesa-mesa3d";
 755                 gpu = ac_get_llvm_processor_name(sscreen->info.family);
 756                 if (ret) {
 757                         sprintf(ret, "%s-%s", gpu, triple);
 758                 }
 759                 /* +2 for dash and terminating NIL byte */
 760                 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 761         }
 762         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 763                 if (ret) {
 764                         uint64_t *grid_dimension = ret;
 765                         grid_dimension[0] = 3;
 766                 }
 767                 return 1 * sizeof(uint64_t);
 768
 769         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 770                 if (ret) {
 771                         uint64_t *grid_size = ret;
 772                         grid_size[0] = 65535;
 773                         grid_size[1] = 65535;
 774                         grid_size[2] = 65535;
 775                 }
 776                 return 3 * sizeof(uint64_t) ;
 777
 778         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 779                 if (ret) {
 780                         uint64_t *block_size = ret;
 781                         unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 782                         block_size[0] = threads_per_block;
 783                         block_size[1] = threads_per_block;
 784                         block_size[2] = threads_per_block;
 785                 }
 786                 return 3 * sizeof(uint64_t);
 787
 788         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 789                 if (ret) {
 790                         uint64_t *max_threads_per_block = ret;
 791                         *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 792                 }
 793                 return sizeof(uint64_t);
 794         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 795                 if (ret) {
 796                         uint32_t *address_bits = ret;
 797                         address_bits[0] = 64;
 798                 }
 799                 return 1 * sizeof(uint32_t);
 800
 801         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 802                 if (ret) {
 803                         uint64_t *max_global_size = ret;
 804                         uint64_t max_mem_alloc_size;
 805
 806                         si_get_compute_param(screen, ir_type,
 807                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 808                                 &max_mem_alloc_size);
 809
 810                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 811                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 812                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 813                          * make sure we never report more than
 814                          * 4 * MAX_MEM_ALLOC_SIZE.
 815                          */
 816                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 817                                                 MAX2(sscreen->info.gart_size,
 818                                                      sscreen->info.vram_size));
 819                 }
 820                 return sizeof(uint64_t);
 821
 822         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 823                 if (ret) {
 824                         uint64_t *max_local_size = ret;
 825                         /* Value reported by the closed source driver. */
 826                         *max_local_size = 32768;
 827                 }
 828                 return sizeof(uint64_t);
 829
 830         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 831                 if (ret) {
 832                         uint64_t *max_input_size = ret;
 833                         /* Value reported by the closed source driver. */
 834                         *max_input_size = 1024;
 835                 }
 836                 return sizeof(uint64_t);
 837
 838         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 839                 if (ret) {
 840                         uint64_t *max_mem_alloc_size = ret;
 841
 842                         *max_mem_alloc_size = sscreen->info.max_alloc_size;
 843                 }
 844                 return sizeof(uint64_t);
 845
 846         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 847                 if (ret) {
 848                         uint32_t *max_clock_frequency = ret;
 849                         *max_clock_frequency = sscreen->info.max_shader_clock;
 850                 }
 851                 return sizeof(uint32_t);
 852
 853         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 854                 if (ret) {
 855                         uint32_t *max_compute_units = ret;
 856                         *max_compute_units = sscreen->info.num_good_compute_units;
 857                 }
 858                 return sizeof(uint32_t);
 859
 860         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 861                 if (ret) {
 862                         uint32_t *images_supported = ret;
 863                         *images_supported = 0;
 864                 }
 865                 return sizeof(uint32_t);
 866         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 867                 break; /* unused */
 868         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 869                 if (ret) {
 870                         uint32_t *subgroup_size = ret;
 871                         *subgroup_size = 64;
 872                 }
 873                 return sizeof(uint32_t);
 874         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 875                 if (ret) {
 876                         uint64_t *max_variable_threads_per_block = ret;
 877                         if (ir_type == PIPE_SHADER_IR_NATIVE)
 878                                 *max_variable_threads_per_block = 0;
 879                         else
 880                                 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
 881                 }
 882                 return sizeof(uint64_t);
 883         }
 884
 885         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 886         return 0;
 887 }
 888
 889 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 890 {
 891         struct si_screen *sscreen = (struct si_screen*)screen;
 892
 893         return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
 894                         sscreen->info.clock_crystal_freq;
 895 }
 896
 897 static void si_query_memory_info(struct pipe_screen *screen,
 898                                  struct pipe_memory_info *info)
 899 {
 900         struct si_screen *sscreen = (struct si_screen*)screen;
 901         struct radeon_winsys *ws = sscreen->ws;
 902         unsigned vram_usage, gtt_usage;
 903
 904         info->total_device_memory = sscreen->info.vram_size / 1024;
 905         info->total_staging_memory = sscreen->info.gart_size / 1024;
 906
 907         /* The real TTM memory usage is somewhat random, because:
 908          *
 909          * 1) TTM delays freeing memory, because it can only free it after
 910          *    fences expire.
 911          *
 912          * 2) The memory usage can be really low if big VRAM evictions are
 913          *    taking place, but the real usage is well above the size of VRAM.
 914          *
 915          * Instead, return statistics of this process.
 916          */
 917         vram_usage = ws->query_value(ws, RADEON_VRAM_USAGE) / 1024;
 918         gtt_usage =  ws->query_value(ws, RADEON_GTT_USAGE) / 1024;
 919
 920         info->avail_device_memory =
 921                 vram_usage <= info->total_device_memory ?
 922                                 info->total_device_memory - vram_usage : 0;
 923         info->avail_staging_memory =
 924                 gtt_usage <= info->total_staging_memory ?
 925                                 info->total_staging_memory - gtt_usage : 0;
 926
 927         info->device_memory_evicted =
 928                 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 929
 930         if (sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 4)
 931                 info->nr_device_memory_evictions =
 932                         ws->query_value(ws, RADEON_NUM_EVICTIONS);
 933         else
 934                 /* Just return the number of evicted 64KB pages. */
 935                 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 936 }
 937
 938 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 939 {
 940         struct si_screen *sscreen = (struct si_screen*)pscreen;
 941
 942         return sscreen->disk_shader_cache;
 943 }
 944
 945 static void si_init_renderer_string(struct si_screen *sscreen)
 946 {
 947         char first_name[256], second_name[32] = {}, kernel_version[128] = {};
 948         struct utsname uname_data;
 949
 950         if (sscreen->info.marketing_name) {
 951                 snprintf(first_name, sizeof(first_name), "%s",
 952                          sscreen->info.marketing_name);
 953                 snprintf(second_name, sizeof(second_name), "%s, ",
 954                          sscreen->info.name);
 955         } else {
 956                 snprintf(first_name, sizeof(first_name), "AMD %s",
 957                          sscreen->info.name);
 958         }
 959
 960         if (uname(&uname_data) == 0)
 961                 snprintf(kernel_version, sizeof(kernel_version),
 962                          ", %s", uname_data.release);
 963
 964         snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
 965                  "%s (%sDRM %i.%i.%i%s, LLVM " MESA_LLVM_VERSION_STRING ")",
 966                  first_name, second_name, sscreen->info.drm_major,
 967                  sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
 968                  kernel_version);
 969 }
 970
 971 void si_init_screen_get_functions(struct si_screen *sscreen)
 972 {
 973         sscreen->b.get_name = si_get_name;
 974         sscreen->b.get_vendor = si_get_vendor;
 975         sscreen->b.get_device_vendor = si_get_device_vendor;
 976         sscreen->b.get_param = si_get_param;
 977         sscreen->b.get_paramf = si_get_paramf;
 978         sscreen->b.get_compute_param = si_get_compute_param;
 979         sscreen->b.get_timestamp = si_get_timestamp;
 980         sscreen->b.get_shader_param = si_get_shader_param;
 981         sscreen->b.get_compiler_options = si_get_compiler_options;
 982         sscreen->b.get_device_uuid = si_get_device_uuid;
 983         sscreen->b.get_driver_uuid = si_get_driver_uuid;
 984         sscreen->b.query_memory_info = si_query_memory_info;
 985         sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
 986
 987         if (sscreen->info.has_hw_decode) {
 988                 sscreen->b.get_video_param = si_get_video_param;
 989                 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
 990         } else {
 991                 sscreen->b.get_video_param = si_get_video_param_no_decode;
 992                 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
 993         }
 994
 995         si_init_renderer_string(sscreen);
 996 }