2 * Copyright 2017 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "radeon/radeon_video.h"
27 #include "radeon/radeon_vce.h"
28 #include "radeon/radeon_uvd_enc.h"
29 #include "ac_llvm_util.h"
30 #include "vl/vl_decoder.h"
31 #include "vl/vl_video_buffer.h"
32 #include "util/u_screen.h"
33 #include "util/u_video.h"
34 #include "compiler/nir/nir.h"
36 #include <llvm/Config/llvm-config.h>
37 #include <sys/utsname.h>
39 static const char *si_get_vendor(struct pipe_screen
*pscreen
)
41 /* Don't change this. Games such as Alien Isolation are broken if this
42 * returns "Advanced Micro Devices, Inc."
47 static const char *si_get_device_vendor(struct pipe_screen
*pscreen
)
52 static int si_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
54 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
57 /* Supported features (boolean caps). */
58 case PIPE_CAP_ACCELERATED
:
59 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
60 case PIPE_CAP_ANISOTROPIC_FILTER
:
61 case PIPE_CAP_POINT_SPRITE
:
62 case PIPE_CAP_OCCLUSION_QUERY
:
63 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
64 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE
:
65 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
66 case PIPE_CAP_TEXTURE_SWIZZLE
:
67 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
68 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE
:
69 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
70 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
71 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
72 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
73 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
74 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
75 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD
:
76 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES
:
77 case PIPE_CAP_VERTEX_SHADER_SATURATE
:
78 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
79 case PIPE_CAP_PRIMITIVE_RESTART
:
80 case PIPE_CAP_CONDITIONAL_RENDER
:
81 case PIPE_CAP_TEXTURE_BARRIER
:
82 case PIPE_CAP_INDEP_BLEND_ENABLE
:
83 case PIPE_CAP_INDEP_BLEND_FUNC
:
84 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
85 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
86 case PIPE_CAP_START_INSTANCE
:
87 case PIPE_CAP_NPOT_TEXTURES
:
88 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
89 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
90 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
91 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
92 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
93 case PIPE_CAP_TGSI_INSTANCEID
:
94 case PIPE_CAP_COMPUTE
:
95 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
96 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
97 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
98 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
99 case PIPE_CAP_CUBE_MAP_ARRAY
:
100 case PIPE_CAP_SAMPLE_SHADING
:
101 case PIPE_CAP_DRAW_INDIRECT
:
102 case PIPE_CAP_CLIP_HALFZ
:
103 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
104 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
105 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
106 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
107 case PIPE_CAP_TGSI_TEXCOORD
:
108 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
109 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
110 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
111 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
112 case PIPE_CAP_SHAREABLE_SHADERS
:
113 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
114 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
115 case PIPE_CAP_TEXTURE_QUERY_LOD
:
116 case PIPE_CAP_TEXTURE_GATHER_SM5
:
117 case PIPE_CAP_TGSI_TXQS
:
118 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
119 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
120 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
121 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
122 case PIPE_CAP_INVALIDATE_BUFFER
:
123 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
124 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
125 case PIPE_CAP_QUERY_MEMORY_INFO
:
126 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
127 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
128 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
129 case PIPE_CAP_GENERATE_MIPMAP
:
130 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
131 case PIPE_CAP_STRING_MARKER
:
132 case PIPE_CAP_CLEAR_TEXTURE
:
133 case PIPE_CAP_CULL_DISTANCE
:
134 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
135 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
136 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
137 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
138 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
139 case PIPE_CAP_DOUBLES
:
140 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
141 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
142 case PIPE_CAP_BINDLESS_TEXTURE
:
143 case PIPE_CAP_QUERY_TIMESTAMP
:
144 case PIPE_CAP_QUERY_TIME_ELAPSED
:
145 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF
:
146 case PIPE_CAP_MEMOBJ
:
147 case PIPE_CAP_LOAD_CONSTBUF
:
149 case PIPE_CAP_INT64_DIVMOD
:
150 case PIPE_CAP_TGSI_CLOCK
:
151 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX
:
152 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
153 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
:
154 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
:
155 case PIPE_CAP_TGSI_BALLOT
:
156 case PIPE_CAP_TGSI_VOTE
:
157 case PIPE_CAP_FBFETCH
:
158 case PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK
:
159 case PIPE_CAP_IMAGE_LOAD_FORMATTED
:
160 case PIPE_CAP_PREFER_COMPUTE_FOR_MULTIMEDIA
:
161 case PIPE_CAP_TGSI_DIV
:
164 case PIPE_CAP_QUERY_SO_OVERFLOW
:
165 return !sscreen
->use_ngg_streamout
;
167 case PIPE_CAP_POST_DEPTH_COVERAGE
:
168 return sscreen
->info
.chip_class
>= GFX10
;
170 case PIPE_CAP_GRAPHICS
:
171 return sscreen
->info
.has_graphics
;
173 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
174 return !SI_BIG_ENDIAN
&& sscreen
->info
.has_userptr
;
176 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
177 return sscreen
->info
.has_gpu_reset_status_query
;
179 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
180 return sscreen
->info
.has_2d_tiling
;
182 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
183 return SI_MAP_BUFFER_ALIGNMENT
;
185 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
186 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
187 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
188 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
189 case PIPE_CAP_MAX_VERTEX_STREAMS
:
190 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
191 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
194 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
195 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
196 if (sscreen
->info
.has_indirect_compute_dispatch
)
200 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET
:
201 /* Optimal number for good TexSubImage performance on Polaris10. */
202 return 64 * 1024 * 1024;
204 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
205 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE
:
206 return MIN2(sscreen
->info
.max_alloc_size
, INT_MAX
);
208 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
209 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
210 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
211 return LLVM_VERSION_MAJOR
< 9 && !sscreen
->info
.has_unaligned_shader_loads
;
213 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE
:
214 return sscreen
->info
.has_sparse_vm_mappings
?
215 RADEON_SPARSE_PAGE_SIZE
: 0;
217 case PIPE_CAP_PACKED_UNIFORMS
:
218 case PIPE_CAP_SHADER_SAMPLES_IDENTICAL
:
219 if (sscreen
->options
.enable_nir
)
223 case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF
:
224 if (sscreen
->options
.enable_nir
)
228 /* Unsupported features. */
229 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
230 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
231 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
232 case PIPE_CAP_USER_VERTEX_BUFFERS
:
233 case PIPE_CAP_FAKE_SW_MSAA
:
234 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
235 case PIPE_CAP_VERTEXID_NOBASE
:
236 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
237 case PIPE_CAP_TGSI_MUL_ZERO_WINS
:
239 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE
:
240 case PIPE_CAP_TILE_RASTER_ORDER
:
241 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES
:
242 case PIPE_CAP_CONTEXT_PRIORITY_MASK
:
243 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES
:
244 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES
:
245 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES
:
246 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES
:
247 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE
:
248 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS
:
249 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS
:
252 case PIPE_CAP_FENCE_SIGNAL
:
253 return sscreen
->info
.has_syncobj
;
255 case PIPE_CAP_CONSTBUF0_FLAGS
:
256 return SI_RESOURCE_FLAG_32BIT
;
258 case PIPE_CAP_NATIVE_FENCE_FD
:
259 return sscreen
->info
.has_fence_to_handle
;
261 case PIPE_CAP_DRAW_PARAMETERS
:
262 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
263 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
264 return sscreen
->has_draw_indirect_multi
;
266 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
269 case PIPE_CAP_MAX_VARYINGS
:
272 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
273 return sscreen
->info
.chip_class
<= GFX8
?
274 PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600
: 0;
277 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
278 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
281 /* Geometry shader output. */
282 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
283 /* gfx9 has to report 256 to make piglit/gs-max-output pass.
284 * gfx8 and earlier can do 1024.
287 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
289 case PIPE_CAP_MAX_GS_INVOCATIONS
:
290 /* The closed driver exposes 127, but 125 is the greatest
291 * number that works. */
294 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
298 case PIPE_CAP_MAX_TEXTURE_2D_SIZE
:
300 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
301 return 15; /* 16384 */
302 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
303 if (sscreen
->info
.chip_class
>= GFX10
)
305 /* textures support 8192, but layered rendering supports 2048 */
307 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
308 if (sscreen
->info
.chip_class
>= GFX10
)
310 /* textures support 8192, but layered rendering supports 2048 */
313 /* Viewports and render targets. */
314 case PIPE_CAP_MAX_VIEWPORTS
:
315 return SI_MAX_VIEWPORTS
;
316 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
317 case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS
:
318 case PIPE_CAP_MAX_RENDER_TARGETS
:
320 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS
:
321 return sscreen
->info
.has_eqaa_surface_allocator
? 2 : 0;
323 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
324 case PIPE_CAP_MIN_TEXEL_OFFSET
:
327 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
328 case PIPE_CAP_MAX_TEXEL_OFFSET
:
331 case PIPE_CAP_ENDIANNESS
:
332 return PIPE_ENDIAN_LITTLE
;
334 case PIPE_CAP_VENDOR_ID
:
335 return ATI_VENDOR_ID
;
336 case PIPE_CAP_DEVICE_ID
:
337 return sscreen
->info
.pci_id
;
338 case PIPE_CAP_VIDEO_MEMORY
:
339 return sscreen
->info
.vram_size
>> 20;
340 case PIPE_CAP_PCI_GROUP
:
341 return sscreen
->info
.pci_domain
;
342 case PIPE_CAP_PCI_BUS
:
343 return sscreen
->info
.pci_bus
;
344 case PIPE_CAP_PCI_DEVICE
:
345 return sscreen
->info
.pci_dev
;
346 case PIPE_CAP_PCI_FUNCTION
:
347 return sscreen
->info
.pci_func
;
348 case PIPE_CAP_TGSI_ATOMINC_WRAP
:
349 return LLVM_VERSION_MAJOR
>= 10;
352 return u_pipe_screen_get_param_defaults(pscreen
, param
);
356 static float si_get_paramf(struct pipe_screen
* pscreen
, enum pipe_capf param
)
359 case PIPE_CAPF_MAX_LINE_WIDTH
:
360 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
361 /* This depends on the quant mode, though the precise interactions
364 case PIPE_CAPF_MAX_POINT_WIDTH
:
365 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
366 return SI_MAX_POINT_SIZE
;
367 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
369 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
371 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
372 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
373 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
379 static int si_get_shader_param(struct pipe_screen
* pscreen
,
380 enum pipe_shader_type shader
,
381 enum pipe_shader_cap param
)
383 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
387 case PIPE_SHADER_FRAGMENT
:
388 case PIPE_SHADER_VERTEX
:
389 case PIPE_SHADER_GEOMETRY
:
390 case PIPE_SHADER_TESS_CTRL
:
391 case PIPE_SHADER_TESS_EVAL
:
393 case PIPE_SHADER_COMPUTE
:
395 case PIPE_SHADER_CAP_SUPPORTED_IRS
: {
396 int ir
= 1 << PIPE_SHADER_IR_NATIVE
;
398 if (sscreen
->info
.has_indirect_compute_dispatch
)
399 ir
|= 1 << PIPE_SHADER_IR_TGSI
;
404 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
: {
405 uint64_t max_const_buffer_size
;
406 pscreen
->get_compute_param(pscreen
, PIPE_SHADER_IR_TGSI
,
407 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
408 &max_const_buffer_size
);
409 return MIN2(max_const_buffer_size
, INT_MAX
);
412 /* If compute shaders don't require a special value
413 * for this cap, we can return the same value we
414 * do for other shader types. */
424 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
425 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
426 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
427 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
428 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
430 case PIPE_SHADER_CAP_MAX_INPUTS
:
431 return shader
== PIPE_SHADER_VERTEX
? SI_MAX_ATTRIBS
: 32;
432 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
433 return shader
== PIPE_SHADER_FRAGMENT
? 8 : 32;
434 case PIPE_SHADER_CAP_MAX_TEMPS
:
435 return 256; /* Max native temporaries. */
436 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
437 return MIN2(sscreen
->info
.max_alloc_size
, INT_MAX
- 3); /* aligned to 4 */
438 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
439 return SI_NUM_CONST_BUFFERS
;
440 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
441 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
442 return SI_NUM_SAMPLERS
;
443 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
444 return SI_NUM_SHADER_BUFFERS
;
445 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
446 return SI_NUM_IMAGES
;
447 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
448 if (sscreen
->options
.enable_nir
)
451 case PIPE_SHADER_CAP_PREFERRED_IR
:
452 if (sscreen
->options
.enable_nir
)
453 return PIPE_SHADER_IR_NIR
;
454 return PIPE_SHADER_IR_TGSI
;
455 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
458 /* Supported boolean features. */
459 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
460 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
461 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
462 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
463 case PIPE_SHADER_CAP_INTEGERS
:
464 case PIPE_SHADER_CAP_INT64_ATOMICS
:
465 case PIPE_SHADER_CAP_FP16
:
466 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
467 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
468 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
469 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
470 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
471 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
474 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
475 /* TODO: Indirect indexing of GS inputs is unimplemented. */
476 if (shader
== PIPE_SHADER_GEOMETRY
)
479 if (shader
== PIPE_SHADER_VERTEX
&&
480 !sscreen
->llvm_has_working_vgpr_indexing
)
483 /* TCS and TES load inputs directly from LDS or offchip
484 * memory, so indirect indexing is always supported.
485 * PS has to support indirect indexing, because we can't
486 * lower that to TEMPs for INTERP instructions.
490 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
491 return sscreen
->llvm_has_working_vgpr_indexing
||
492 /* TCS stores outputs directly to memory. */
493 shader
== PIPE_SHADER_TESS_CTRL
;
495 /* Unsupported boolean features. */
496 case PIPE_SHADER_CAP_SUBROUTINES
:
497 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
498 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
499 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
501 case PIPE_SHADER_CAP_SCALAR_ISA
:
507 static const struct nir_shader_compiler_options nir_options
= {
509 .lower_flrp32
= true,
510 .lower_flrp64
= true,
513 .lower_bitfield_insert_to_bitfield_select
= true,
514 .lower_bitfield_extract
= true,
518 .lower_pack_snorm_4x8
= true,
519 .lower_pack_unorm_4x8
= true,
520 .lower_unpack_snorm_2x16
= true,
521 .lower_unpack_snorm_4x8
= true,
522 .lower_unpack_unorm_2x16
= true,
523 .lower_unpack_unorm_4x8
= true,
524 .lower_extract_byte
= true,
525 .lower_extract_word
= true,
526 .lower_rotate
= true,
527 .lower_to_scalar
= true,
528 .optimize_sample_mask_in
= true,
529 .max_unroll_iterations
= 32,
530 .use_interpolated_input_intrinsics
= true,
534 si_get_compiler_options(struct pipe_screen
*screen
,
535 enum pipe_shader_ir ir
,
536 enum pipe_shader_type shader
)
538 assert(ir
== PIPE_SHADER_IR_NIR
);
542 static void si_get_driver_uuid(struct pipe_screen
*pscreen
, char *uuid
)
544 ac_compute_driver_uuid(uuid
, PIPE_UUID_SIZE
);
547 static void si_get_device_uuid(struct pipe_screen
*pscreen
, char *uuid
)
549 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
551 ac_compute_device_uuid(&sscreen
->info
, uuid
, PIPE_UUID_SIZE
);
554 static const char* si_get_name(struct pipe_screen
*pscreen
)
556 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
558 return sscreen
->renderer_string
;
561 static int si_get_video_param_no_decode(struct pipe_screen
*screen
,
562 enum pipe_video_profile profile
,
563 enum pipe_video_entrypoint entrypoint
,
564 enum pipe_video_cap param
)
567 case PIPE_VIDEO_CAP_SUPPORTED
:
568 return vl_profile_supported(screen
, profile
, entrypoint
);
569 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
571 case PIPE_VIDEO_CAP_MAX_WIDTH
:
572 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
573 return vl_video_buffer_max_size(screen
);
574 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
575 return PIPE_FORMAT_NV12
;
576 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
578 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
580 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
582 case PIPE_VIDEO_CAP_MAX_LEVEL
:
583 return vl_level_supported(screen
, profile
);
589 static int si_get_video_param(struct pipe_screen
*screen
,
590 enum pipe_video_profile profile
,
591 enum pipe_video_entrypoint entrypoint
,
592 enum pipe_video_cap param
)
594 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
595 enum pipe_video_format codec
= u_reduce_video_profile(profile
);
597 if (entrypoint
== PIPE_VIDEO_ENTRYPOINT_ENCODE
) {
599 case PIPE_VIDEO_CAP_SUPPORTED
:
600 return (codec
== PIPE_VIDEO_FORMAT_MPEG4_AVC
&&
601 (si_vce_is_fw_version_supported(sscreen
) ||
602 sscreen
->info
.family
>= CHIP_RAVEN
)) ||
603 (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN
&&
604 (sscreen
->info
.family
>= CHIP_RAVEN
||
605 si_radeon_uvd_enc_supported(sscreen
)));
606 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
608 case PIPE_VIDEO_CAP_MAX_WIDTH
:
609 return (sscreen
->info
.family
< CHIP_TONGA
) ? 2048 : 4096;
610 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
611 return (sscreen
->info
.family
< CHIP_TONGA
) ? 1152 : 2304;
612 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
613 return PIPE_FORMAT_NV12
;
614 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
616 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
618 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
620 case PIPE_VIDEO_CAP_STACKED_FRAMES
:
621 return (sscreen
->info
.family
< CHIP_TONGA
) ? 1 : 2;
628 case PIPE_VIDEO_CAP_SUPPORTED
:
630 case PIPE_VIDEO_FORMAT_MPEG12
:
631 return profile
!= PIPE_VIDEO_PROFILE_MPEG1
;
632 case PIPE_VIDEO_FORMAT_MPEG4
:
634 case PIPE_VIDEO_FORMAT_MPEG4_AVC
:
635 if ((sscreen
->info
.family
== CHIP_POLARIS10
||
636 sscreen
->info
.family
== CHIP_POLARIS11
) &&
637 sscreen
->info
.uvd_fw_version
< UVD_FW_1_66_16
) {
638 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
642 case PIPE_VIDEO_FORMAT_VC1
:
644 case PIPE_VIDEO_FORMAT_HEVC
:
645 /* Carrizo only supports HEVC Main */
646 if (sscreen
->info
.family
>= CHIP_STONEY
)
647 return (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN
||
648 profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN_10
);
649 else if (sscreen
->info
.family
>= CHIP_CARRIZO
)
650 return profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN
;
652 case PIPE_VIDEO_FORMAT_JPEG
:
653 if (sscreen
->info
.family
>= CHIP_RAVEN
)
655 if (sscreen
->info
.family
< CHIP_CARRIZO
|| sscreen
->info
.family
>= CHIP_VEGA10
)
657 if (!(sscreen
->info
.is_amdgpu
&& sscreen
->info
.drm_minor
>= 19)) {
658 RVID_ERR("No MJPEG support for the kernel version\n");
662 case PIPE_VIDEO_FORMAT_VP9
:
663 if (sscreen
->info
.family
< CHIP_RAVEN
)
669 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
671 case PIPE_VIDEO_CAP_MAX_WIDTH
:
672 return (sscreen
->info
.family
< CHIP_TONGA
) ? 2048 : 4096;
673 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
674 return (sscreen
->info
.family
< CHIP_TONGA
) ? 1152 : 4096;
675 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
676 if (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN_10
||
677 profile
== PIPE_VIDEO_PROFILE_VP9_PROFILE2
)
678 return PIPE_FORMAT_P016
;
680 return PIPE_FORMAT_NV12
;
682 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
683 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
: {
684 enum pipe_video_format format
= u_reduce_video_profile(profile
);
686 if (format
== PIPE_VIDEO_FORMAT_HEVC
)
687 return false; //The firmware doesn't support interlaced HEVC.
688 else if (format
== PIPE_VIDEO_FORMAT_JPEG
)
690 else if (format
== PIPE_VIDEO_FORMAT_VP9
)
694 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
696 case PIPE_VIDEO_CAP_MAX_LEVEL
:
698 case PIPE_VIDEO_PROFILE_MPEG1
:
700 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE
:
701 case PIPE_VIDEO_PROFILE_MPEG2_MAIN
:
703 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE
:
705 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE
:
707 case PIPE_VIDEO_PROFILE_VC1_SIMPLE
:
709 case PIPE_VIDEO_PROFILE_VC1_MAIN
:
711 case PIPE_VIDEO_PROFILE_VC1_ADVANCED
:
713 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE
:
714 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN
:
715 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH
:
716 return (sscreen
->info
.family
< CHIP_TONGA
) ? 41 : 52;
717 case PIPE_VIDEO_PROFILE_HEVC_MAIN
:
718 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10
:
728 static bool si_vid_is_format_supported(struct pipe_screen
*screen
,
729 enum pipe_format format
,
730 enum pipe_video_profile profile
,
731 enum pipe_video_entrypoint entrypoint
)
733 /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
734 if (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN_10
)
735 return (format
== PIPE_FORMAT_NV12
) ||
736 (format
== PIPE_FORMAT_P016
);
738 /* Vp9 profile 2 supports 10 bit decoding using P016 */
739 if (profile
== PIPE_VIDEO_PROFILE_VP9_PROFILE2
)
740 return format
== PIPE_FORMAT_P016
;
743 /* we can only handle this one with UVD */
744 if (profile
!= PIPE_VIDEO_PROFILE_UNKNOWN
)
745 return format
== PIPE_FORMAT_NV12
;
747 return vl_video_buffer_is_format_supported(screen
, format
, profile
, entrypoint
);
750 static unsigned get_max_threads_per_block(struct si_screen
*screen
,
751 enum pipe_shader_ir ir_type
)
753 if (ir_type
== PIPE_SHADER_IR_NATIVE
)
756 /* LLVM 10 only supports 1024 threads per block. */
760 static int si_get_compute_param(struct pipe_screen
*screen
,
761 enum pipe_shader_ir ir_type
,
762 enum pipe_compute_cap param
,
765 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
767 //TODO: select these params by asic
769 case PIPE_COMPUTE_CAP_IR_TARGET
: {
770 const char *gpu
, *triple
;
772 triple
= "amdgcn-mesa-mesa3d";
773 gpu
= ac_get_llvm_processor_name(sscreen
->info
.family
);
775 sprintf(ret
, "%s-%s", gpu
, triple
);
777 /* +2 for dash and terminating NIL byte */
778 return (strlen(triple
) + strlen(gpu
) + 2) * sizeof(char);
780 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
782 uint64_t *grid_dimension
= ret
;
783 grid_dimension
[0] = 3;
785 return 1 * sizeof(uint64_t);
787 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
789 uint64_t *grid_size
= ret
;
790 grid_size
[0] = 65535;
791 grid_size
[1] = 65535;
792 grid_size
[2] = 65535;
794 return 3 * sizeof(uint64_t) ;
796 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
798 uint64_t *block_size
= ret
;
799 unsigned threads_per_block
= get_max_threads_per_block(sscreen
, ir_type
);
800 block_size
[0] = threads_per_block
;
801 block_size
[1] = threads_per_block
;
802 block_size
[2] = threads_per_block
;
804 return 3 * sizeof(uint64_t);
806 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
808 uint64_t *max_threads_per_block
= ret
;
809 *max_threads_per_block
= get_max_threads_per_block(sscreen
, ir_type
);
811 return sizeof(uint64_t);
812 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
814 uint32_t *address_bits
= ret
;
815 address_bits
[0] = 64;
817 return 1 * sizeof(uint32_t);
819 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
821 uint64_t *max_global_size
= ret
;
822 uint64_t max_mem_alloc_size
;
824 si_get_compute_param(screen
, ir_type
,
825 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
826 &max_mem_alloc_size
);
828 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
829 * 1/4 of the MAX_GLOBAL_SIZE. Since the
830 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
831 * make sure we never report more than
832 * 4 * MAX_MEM_ALLOC_SIZE.
834 *max_global_size
= MIN2(4 * max_mem_alloc_size
,
835 MAX2(sscreen
->info
.gart_size
,
836 sscreen
->info
.vram_size
));
838 return sizeof(uint64_t);
840 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
842 uint64_t *max_local_size
= ret
;
843 /* Value reported by the closed source driver. */
844 *max_local_size
= 32768;
846 return sizeof(uint64_t);
848 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
850 uint64_t *max_input_size
= ret
;
851 /* Value reported by the closed source driver. */
852 *max_input_size
= 1024;
854 return sizeof(uint64_t);
856 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
858 uint64_t *max_mem_alloc_size
= ret
;
860 *max_mem_alloc_size
= sscreen
->info
.max_alloc_size
;
862 return sizeof(uint64_t);
864 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
866 uint32_t *max_clock_frequency
= ret
;
867 *max_clock_frequency
= sscreen
->info
.max_shader_clock
;
869 return sizeof(uint32_t);
871 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
873 uint32_t *max_compute_units
= ret
;
874 *max_compute_units
= sscreen
->info
.num_good_compute_units
;
876 return sizeof(uint32_t);
878 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
880 uint32_t *images_supported
= ret
;
881 *images_supported
= 0;
883 return sizeof(uint32_t);
884 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
886 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
888 uint32_t *subgroup_size
= ret
;
889 *subgroup_size
= sscreen
->compute_wave_size
;
891 return sizeof(uint32_t);
892 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
894 uint64_t *max_variable_threads_per_block
= ret
;
895 if (ir_type
== PIPE_SHADER_IR_NATIVE
)
896 *max_variable_threads_per_block
= 0;
898 *max_variable_threads_per_block
= SI_MAX_VARIABLE_THREADS_PER_BLOCK
;
900 return sizeof(uint64_t);
903 fprintf(stderr
, "unknown PIPE_COMPUTE_CAP %d\n", param
);
907 static uint64_t si_get_timestamp(struct pipe_screen
*screen
)
909 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
911 return 1000000 * sscreen
->ws
->query_value(sscreen
->ws
, RADEON_TIMESTAMP
) /
912 sscreen
->info
.clock_crystal_freq
;
915 static void si_query_memory_info(struct pipe_screen
*screen
,
916 struct pipe_memory_info
*info
)
918 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
919 struct radeon_winsys
*ws
= sscreen
->ws
;
920 unsigned vram_usage
, gtt_usage
;
922 info
->total_device_memory
= sscreen
->info
.vram_size
/ 1024;
923 info
->total_staging_memory
= sscreen
->info
.gart_size
/ 1024;
925 /* The real TTM memory usage is somewhat random, because:
927 * 1) TTM delays freeing memory, because it can only free it after
930 * 2) The memory usage can be really low if big VRAM evictions are
931 * taking place, but the real usage is well above the size of VRAM.
933 * Instead, return statistics of this process.
935 vram_usage
= ws
->query_value(ws
, RADEON_VRAM_USAGE
) / 1024;
936 gtt_usage
= ws
->query_value(ws
, RADEON_GTT_USAGE
) / 1024;
938 info
->avail_device_memory
=
939 vram_usage
<= info
->total_device_memory
?
940 info
->total_device_memory
- vram_usage
: 0;
941 info
->avail_staging_memory
=
942 gtt_usage
<= info
->total_staging_memory
?
943 info
->total_staging_memory
- gtt_usage
: 0;
945 info
->device_memory_evicted
=
946 ws
->query_value(ws
, RADEON_NUM_BYTES_MOVED
) / 1024;
948 if (sscreen
->info
.is_amdgpu
&& sscreen
->info
.drm_minor
>= 4)
949 info
->nr_device_memory_evictions
=
950 ws
->query_value(ws
, RADEON_NUM_EVICTIONS
);
952 /* Just return the number of evicted 64KB pages. */
953 info
->nr_device_memory_evictions
= info
->device_memory_evicted
/ 64;
956 static struct disk_cache
*si_get_disk_shader_cache(struct pipe_screen
*pscreen
)
958 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
960 return sscreen
->disk_shader_cache
;
963 static void si_init_renderer_string(struct si_screen
*sscreen
)
965 char first_name
[256], second_name
[32] = {}, kernel_version
[128] = {};
966 struct utsname uname_data
;
968 if (sscreen
->info
.marketing_name
) {
969 snprintf(first_name
, sizeof(first_name
), "%s",
970 sscreen
->info
.marketing_name
);
971 snprintf(second_name
, sizeof(second_name
), "%s, ",
974 snprintf(first_name
, sizeof(first_name
), "AMD %s",
978 if (uname(&uname_data
) == 0)
979 snprintf(kernel_version
, sizeof(kernel_version
),
980 ", %s", uname_data
.release
);
982 snprintf(sscreen
->renderer_string
, sizeof(sscreen
->renderer_string
),
983 "%s (%sDRM %i.%i.%i%s, LLVM " MESA_LLVM_VERSION_STRING
")",
984 first_name
, second_name
, sscreen
->info
.drm_major
,
985 sscreen
->info
.drm_minor
, sscreen
->info
.drm_patchlevel
,
989 void si_init_screen_get_functions(struct si_screen
*sscreen
)
991 sscreen
->b
.get_name
= si_get_name
;
992 sscreen
->b
.get_vendor
= si_get_vendor
;
993 sscreen
->b
.get_device_vendor
= si_get_device_vendor
;
994 sscreen
->b
.get_param
= si_get_param
;
995 sscreen
->b
.get_paramf
= si_get_paramf
;
996 sscreen
->b
.get_compute_param
= si_get_compute_param
;
997 sscreen
->b
.get_timestamp
= si_get_timestamp
;
998 sscreen
->b
.get_shader_param
= si_get_shader_param
;
999 sscreen
->b
.get_compiler_options
= si_get_compiler_options
;
1000 sscreen
->b
.get_device_uuid
= si_get_device_uuid
;
1001 sscreen
->b
.get_driver_uuid
= si_get_driver_uuid
;
1002 sscreen
->b
.query_memory_info
= si_query_memory_info
;
1003 sscreen
->b
.get_disk_shader_cache
= si_get_disk_shader_cache
;
1005 if (sscreen
->info
.has_hw_decode
) {
1006 sscreen
->b
.get_video_param
= si_get_video_param
;
1007 sscreen
->b
.is_video_format_supported
= si_vid_is_format_supported
;
1009 sscreen
->b
.get_video_param
= si_get_video_param_no_decode
;
1010 sscreen
->b
.is_video_format_supported
= vl_video_buffer_is_format_supported
;
1013 si_init_renderer_string(sscreen
);