src/gallium/drivers/radeonsi/si_get.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "si_pipe.h"
  26 #include "radeon/radeon_video.h"
  27 #include "radeon/radeon_vce.h"
  28 #include "radeon/radeon_uvd_enc.h"
  29 #include "ac_llvm_util.h"
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32 #include "util/u_video.h"
  33 #include "compiler/nir/nir.h"
  34
  35 #include <sys/utsname.h>
  36
  37 static const char *si_get_vendor(struct pipe_screen *pscreen)
  38 {
  39         /* Don't change this. Games such as Alien Isolation are broken if this
  40          * returns "Advanced Micro Devices, Inc."
  41          */
  42         return "X.Org";
  43 }
  44
  45 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
  46 {
  47         return "AMD";
  48 }
  49
  50 static const char *si_get_marketing_name(struct radeon_winsys *ws)
  51 {
  52         if (!ws->get_chip_name)
  53                 return NULL;
  54         return ws->get_chip_name(ws);
  55 }
  56
  57 const char *si_get_family_name(const struct si_screen *sscreen)
  58 {
  59         switch (sscreen->info.family) {
  60         case CHIP_TAHITI: return "AMD TAHITI";
  61         case CHIP_PITCAIRN: return "AMD PITCAIRN";
  62         case CHIP_VERDE: return "AMD CAPE VERDE";
  63         case CHIP_OLAND: return "AMD OLAND";
  64         case CHIP_HAINAN: return "AMD HAINAN";
  65         case CHIP_BONAIRE: return "AMD BONAIRE";
  66         case CHIP_KAVERI: return "AMD KAVERI";
  67         case CHIP_KABINI: return "AMD KABINI";
  68         case CHIP_HAWAII: return "AMD HAWAII";
  69         case CHIP_MULLINS: return "AMD MULLINS";
  70         case CHIP_TONGA: return "AMD TONGA";
  71         case CHIP_ICELAND: return "AMD ICELAND";
  72         case CHIP_CARRIZO: return "AMD CARRIZO";
  73         case CHIP_FIJI: return "AMD FIJI";
  74         case CHIP_POLARIS10: return "AMD POLARIS10";
  75         case CHIP_POLARIS11: return "AMD POLARIS11";
  76         case CHIP_POLARIS12: return "AMD POLARIS12";
  77         case CHIP_STONEY: return "AMD STONEY";
  78         case CHIP_VEGA10: return "AMD VEGA10";
  79         case CHIP_VEGA12: return "AMD VEGA12";
  80         case CHIP_RAVEN: return "AMD RAVEN";
  81         default: return "AMD unknown";
  82         }
  83 }
  84
  85 static bool si_have_tgsi_compute(struct si_screen *sscreen)
  86 {
  87         /* Old kernels disallowed some register writes for SI
  88          * that are used for indirect dispatches. */
  89         return (sscreen->info.chip_class >= CIK ||
  90                 sscreen->info.drm_major == 3 ||
  91                 (sscreen->info.drm_major == 2 &&
  92                  sscreen->info.drm_minor >= 45));
  93 }
  94
  95 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  96 {
  97         struct si_screen *sscreen = (struct si_screen *)pscreen;
  98
  99         switch (param) {
 100         /* Supported features (boolean caps). */
 101         case PIPE_CAP_ACCELERATED:
 102         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 103         case PIPE_CAP_ANISOTROPIC_FILTER:
 104         case PIPE_CAP_POINT_SPRITE:
 105         case PIPE_CAP_OCCLUSION_QUERY:
 106         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 107         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 108         case PIPE_CAP_TEXTURE_SWIZZLE:
 109         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 110         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 111         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 112         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 113         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 114         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 115         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 116         case PIPE_CAP_SM3:
 117         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 118         case PIPE_CAP_PRIMITIVE_RESTART:
 119         case PIPE_CAP_CONDITIONAL_RENDER:
 120         case PIPE_CAP_TEXTURE_BARRIER:
 121         case PIPE_CAP_INDEP_BLEND_ENABLE:
 122         case PIPE_CAP_INDEP_BLEND_FUNC:
 123         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 124         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 125         case PIPE_CAP_START_INSTANCE:
 126         case PIPE_CAP_NPOT_TEXTURES:
 127         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 128         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 129         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 130         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 131         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 132         case PIPE_CAP_TGSI_INSTANCEID:
 133         case PIPE_CAP_COMPUTE:
 134         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 135         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 136         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 137         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 138         case PIPE_CAP_CUBE_MAP_ARRAY:
 139         case PIPE_CAP_SAMPLE_SHADING:
 140         case PIPE_CAP_DRAW_INDIRECT:
 141         case PIPE_CAP_CLIP_HALFZ:
 142         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 143         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 144         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 145         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 146         case PIPE_CAP_TGSI_TEXCOORD:
 147         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 148         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 149         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 150         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 151         case PIPE_CAP_SHAREABLE_SHADERS:
 152         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 153         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 154         case PIPE_CAP_TEXTURE_QUERY_LOD:
 155         case PIPE_CAP_TEXTURE_GATHER_SM5:
 156         case PIPE_CAP_TGSI_TXQS:
 157         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 158         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 159         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 160         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 161         case PIPE_CAP_INVALIDATE_BUFFER:
 162         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 163         case PIPE_CAP_QUERY_MEMORY_INFO:
 164         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 165         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 166         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 167         case PIPE_CAP_GENERATE_MIPMAP:
 168         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 169         case PIPE_CAP_STRING_MARKER:
 170         case PIPE_CAP_CLEAR_TEXTURE:
 171         case PIPE_CAP_CULL_DISTANCE:
 172         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 173         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 174         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 175         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 176         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 177         case PIPE_CAP_DOUBLES:
 178         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 179         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 180         case PIPE_CAP_BINDLESS_TEXTURE:
 181         case PIPE_CAP_QUERY_TIMESTAMP:
 182         case PIPE_CAP_QUERY_TIME_ELAPSED:
 183         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 184         case PIPE_CAP_QUERY_SO_OVERFLOW:
 185         case PIPE_CAP_MEMOBJ:
 186         case PIPE_CAP_LOAD_CONSTBUF:
 187         case PIPE_CAP_INT64:
 188         case PIPE_CAP_INT64_DIVMOD:
 189         case PIPE_CAP_TGSI_CLOCK:
 190         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 191         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 192         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 193         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 194         case PIPE_CAP_TGSI_VOTE:
 195         case PIPE_CAP_TGSI_FS_FBFETCH:
 196                 return 1;
 197
 198         case PIPE_CAP_TGSI_BALLOT:
 199                 return HAVE_LLVM >= 0x0500;
 200
 201         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 202                 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 203
 204         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 205                 return (sscreen->info.drm_major == 2 &&
 206                         sscreen->info.drm_minor >= 43) ||
 207                        sscreen->info.drm_major == 3;
 208
 209         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 210                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 211                 return sscreen->info.chip_class < CIK ||
 212                        (sscreen->info.drm_major == 2 &&
 213                         sscreen->info.drm_minor >= 35) ||
 214                        sscreen->info.drm_major == 3;
 215
 216         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 217                 return SI_MAP_BUFFER_ALIGNMENT;
 218
 219         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 220         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 221         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 222         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 223         case PIPE_CAP_MAX_VERTEX_STREAMS:
 224         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 225                 return 4;
 226
 227         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 228                 if (si_have_tgsi_compute(sscreen))
 229                         return 450;
 230                 return 420;
 231
 232         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 233                 return MIN2(sscreen->info.max_alloc_size, INT_MAX);
 234
 235         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 236         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 237         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 238                 /* SI doesn't support unaligned loads.
 239                  * CIK needs DRM 2.50.0 on radeon. */
 240                 return sscreen->info.chip_class == SI ||
 241                        (sscreen->info.drm_major == 2 &&
 242                         sscreen->info.drm_minor < 50);
 243
 244         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 245                 /* TODO: GFX9 hangs. */
 246                 if (sscreen->info.chip_class >= GFX9)
 247                         return 0;
 248                 /* Disable on SI due to VM faults in CP DMA. Enable once these
 249                  * faults are mitigated in software.
 250                  */
 251                 if (sscreen->info.chip_class >= CIK &&
 252                     sscreen->info.drm_major == 3 &&
 253                     sscreen->info.drm_minor >= 13)
 254                         return RADEON_SPARSE_PAGE_SIZE;
 255                 return 0;
 256
 257         case PIPE_CAP_PACKED_UNIFORMS:
 258                 if (sscreen->debug_flags & DBG(NIR))
 259                         return 1;
 260                 return 0;
 261
 262         /* Unsupported features. */
 263         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 264         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 265         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 266         case PIPE_CAP_USER_VERTEX_BUFFERS:
 267         case PIPE_CAP_FAKE_SW_MSAA:
 268         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 269         case PIPE_CAP_VERTEXID_NOBASE:
 270         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 271         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 272         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 273         case PIPE_CAP_UMA:
 274         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 275         case PIPE_CAP_POST_DEPTH_COVERAGE:
 276         case PIPE_CAP_TILE_RASTER_ORDER:
 277         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 278         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 279                 return 0;
 280
 281         case PIPE_CAP_FENCE_SIGNAL:
 282                 return sscreen->info.has_syncobj;
 283
 284         case PIPE_CAP_CONSTBUF0_FLAGS:
 285                 return SI_RESOURCE_FLAG_32BIT;
 286
 287         case PIPE_CAP_NATIVE_FENCE_FD:
 288                 return sscreen->info.has_fence_to_handle;
 289
 290         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 291                 return si_have_tgsi_compute(sscreen);
 292
 293         case PIPE_CAP_DRAW_PARAMETERS:
 294         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 295         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 296                 return sscreen->has_draw_indirect_multi;
 297
 298         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 299                 return 30;
 300
 301         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 302                 return sscreen->info.chip_class <= VI ?
 303                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 304
 305         /* Stream output. */
 306         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 307         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 308                 return 32*4;
 309
 310         /* Geometry shader output. */
 311         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 312                 return 1024;
 313         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 314                 return 4095;
 315
 316         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 317                 return 2048;
 318
 319         /* Texturing. */
 320         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 321         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 322                 return 15; /* 16384 */
 323         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 324                 /* textures support 8192, but layered rendering supports 2048 */
 325                 return 12;
 326         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 327                 /* textures support 8192, but layered rendering supports 2048 */
 328                 return 2048;
 329
 330         /* Viewports and render targets. */
 331         case PIPE_CAP_MAX_VIEWPORTS:
 332                 return SI_MAX_VIEWPORTS;
 333         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 334         case PIPE_CAP_MAX_RENDER_TARGETS:
 335                 return 8;
 336
 337         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 338         case PIPE_CAP_MIN_TEXEL_OFFSET:
 339                 return -32;
 340
 341         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 342         case PIPE_CAP_MAX_TEXEL_OFFSET:
 343                 return 31;
 344
 345         case PIPE_CAP_ENDIANNESS:
 346                 return PIPE_ENDIAN_LITTLE;
 347
 348         case PIPE_CAP_VENDOR_ID:
 349                 return ATI_VENDOR_ID;
 350         case PIPE_CAP_DEVICE_ID:
 351                 return sscreen->info.pci_id;
 352         case PIPE_CAP_VIDEO_MEMORY:
 353                 return sscreen->info.vram_size >> 20;
 354         case PIPE_CAP_PCI_GROUP:
 355                 return sscreen->info.pci_domain;
 356         case PIPE_CAP_PCI_BUS:
 357                 return sscreen->info.pci_bus;
 358         case PIPE_CAP_PCI_DEVICE:
 359                 return sscreen->info.pci_dev;
 360         case PIPE_CAP_PCI_FUNCTION:
 361                 return sscreen->info.pci_func;
 362         }
 363         return 0;
 364 }
 365
 366 static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
 367 {
 368         switch (param) {
 369         case PIPE_CAPF_MAX_LINE_WIDTH:
 370         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 371         case PIPE_CAPF_MAX_POINT_WIDTH:
 372         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 373                 return 8192.0f;
 374         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 375                 return 16.0f;
 376         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 377                 return 16.0f;
 378         }
 379         return 0.0f;
 380 }
 381
 382 static int si_get_shader_param(struct pipe_screen* pscreen,
 383                                enum pipe_shader_type shader,
 384                                enum pipe_shader_cap param)
 385 {
 386         struct si_screen *sscreen = (struct si_screen *)pscreen;
 387
 388         switch(shader)
 389         {
 390         case PIPE_SHADER_FRAGMENT:
 391         case PIPE_SHADER_VERTEX:
 392         case PIPE_SHADER_GEOMETRY:
 393         case PIPE_SHADER_TESS_CTRL:
 394         case PIPE_SHADER_TESS_EVAL:
 395                 break;
 396         case PIPE_SHADER_COMPUTE:
 397                 switch (param) {
 398                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 399                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 400
 401                         if (si_have_tgsi_compute(sscreen))
 402                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 403
 404                         return ir;
 405                 }
 406
 407                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 408                         uint64_t max_const_buffer_size;
 409                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 410                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 411                                 &max_const_buffer_size);
 412                         return MIN2(max_const_buffer_size, INT_MAX);
 413                 }
 414                 default:
 415                         /* If compute shaders don't require a special value
 416                          * for this cap, we can return the same value we
 417                          * do for other shader types. */
 418                         break;
 419                 }
 420                 break;
 421         default:
 422                 return 0;
 423         }
 424
 425         switch (param) {
 426         /* Shader limits. */
 427         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 428         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 429         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 430         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 431         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 432                 return 16384;
 433         case PIPE_SHADER_CAP_MAX_INPUTS:
 434                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 435         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 436                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 437         case PIPE_SHADER_CAP_MAX_TEMPS:
 438                 return 256; /* Max native temporaries. */
 439         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 440                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 441         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 442                 return SI_NUM_CONST_BUFFERS;
 443         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 444         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 445                 return SI_NUM_SAMPLERS;
 446         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 447                 return SI_NUM_SHADER_BUFFERS;
 448         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 449                 return SI_NUM_IMAGES;
 450         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 451                 if (sscreen->debug_flags & DBG(NIR))
 452                         return 0;
 453                 return 32;
 454         case PIPE_SHADER_CAP_PREFERRED_IR:
 455                 if (sscreen->debug_flags & DBG(NIR))
 456                         return PIPE_SHADER_IR_NIR;
 457                 return PIPE_SHADER_IR_TGSI;
 458         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 459                 return 4;
 460
 461         /* Supported boolean features. */
 462         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 463         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 464         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 465         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 466         case PIPE_SHADER_CAP_INTEGERS:
 467         case PIPE_SHADER_CAP_INT64_ATOMICS:
 468         case PIPE_SHADER_CAP_FP16:
 469         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 470         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 471         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 472         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 473         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 474         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 475                 return 1;
 476
 477         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 478                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 479                 return shader != PIPE_SHADER_GEOMETRY &&
 480                        (sscreen->llvm_has_working_vgpr_indexing ||
 481                         /* TCS and TES load inputs directly from LDS or
 482                          * offchip memory, so indirect indexing is trivial. */
 483                         shader == PIPE_SHADER_TESS_CTRL ||
 484                         shader == PIPE_SHADER_TESS_EVAL);
 485
 486         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 487                 return sscreen->llvm_has_working_vgpr_indexing ||
 488                        /* TCS stores outputs directly to memory. */
 489                        shader == PIPE_SHADER_TESS_CTRL;
 490
 491         /* Unsupported boolean features. */
 492         case PIPE_SHADER_CAP_SUBROUTINES:
 493         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 494         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 495         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 496                 return 0;
 497         }
 498         return 0;
 499 }
 500
 501 static const struct nir_shader_compiler_options nir_options = {
 502         .lower_scmp = true,
 503         .lower_flrp32 = true,
 504         .lower_flrp64 = true,
 505         .lower_fpow = true,
 506         .lower_fsat = true,
 507         .lower_fdiv = true,
 508         .lower_sub = true,
 509         .lower_ffma = true,
 510         .lower_pack_snorm_2x16 = true,
 511         .lower_pack_snorm_4x8 = true,
 512         .lower_pack_unorm_2x16 = true,
 513         .lower_pack_unorm_4x8 = true,
 514         .lower_unpack_snorm_2x16 = true,
 515         .lower_unpack_snorm_4x8 = true,
 516         .lower_unpack_unorm_2x16 = true,
 517         .lower_unpack_unorm_4x8 = true,
 518         .lower_extract_byte = true,
 519         .lower_extract_word = true,
 520         .max_unroll_iterations = 32,
 521         .native_integers = true,
 522 };
 523
 524 static const void *
 525 si_get_compiler_options(struct pipe_screen *screen,
 526                         enum pipe_shader_ir ir,
 527                         enum pipe_shader_type shader)
 528 {
 529         assert(ir == PIPE_SHADER_IR_NIR);
 530         return &nir_options;
 531 }
 532
 533 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 534 {
 535         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 536 }
 537
 538 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 539 {
 540         struct si_screen *sscreen = (struct si_screen *)pscreen;
 541
 542         ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
 543 }
 544
 545 static const char* si_get_name(struct pipe_screen *pscreen)
 546 {
 547         struct si_screen *sscreen = (struct si_screen*)pscreen;
 548
 549         return sscreen->renderer_string;
 550 }
 551
 552 static int si_get_video_param_no_decode(struct pipe_screen *screen,
 553                                         enum pipe_video_profile profile,
 554                                         enum pipe_video_entrypoint entrypoint,
 555                                         enum pipe_video_cap param)
 556 {
 557         switch (param) {
 558         case PIPE_VIDEO_CAP_SUPPORTED:
 559                 return vl_profile_supported(screen, profile, entrypoint);
 560         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 561                 return 1;
 562         case PIPE_VIDEO_CAP_MAX_WIDTH:
 563         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 564                 return vl_video_buffer_max_size(screen);
 565         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 566                 return PIPE_FORMAT_NV12;
 567         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 568                 return false;
 569         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 570                 return false;
 571         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 572                 return true;
 573         case PIPE_VIDEO_CAP_MAX_LEVEL:
 574                 return vl_level_supported(screen, profile);
 575         default:
 576                 return 0;
 577         }
 578 }
 579
 580 static int si_get_video_param(struct pipe_screen *screen,
 581                               enum pipe_video_profile profile,
 582                               enum pipe_video_entrypoint entrypoint,
 583                               enum pipe_video_cap param)
 584 {
 585         struct si_screen *sscreen = (struct si_screen *)screen;
 586         enum pipe_video_format codec = u_reduce_video_profile(profile);
 587
 588         if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 589                 switch (param) {
 590                 case PIPE_VIDEO_CAP_SUPPORTED:
 591                         return (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 592                                 (si_vce_is_fw_version_supported(sscreen) ||
 593                                 sscreen->info.family == CHIP_RAVEN)) ||
 594                                 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
 595                                 (sscreen->info.family == CHIP_RAVEN ||
 596                                 si_radeon_uvd_enc_supported(sscreen)));
 597                 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 598                         return 1;
 599                 case PIPE_VIDEO_CAP_MAX_WIDTH:
 600                         return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 601                 case PIPE_VIDEO_CAP_MAX_HEIGHT:
 602                         return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
 603                 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 604                         return PIPE_FORMAT_NV12;
 605                 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 606                         return false;
 607                 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 608                         return false;
 609                 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 610                         return true;
 611                 case PIPE_VIDEO_CAP_STACKED_FRAMES:
 612                         return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
 613                 default:
 614                         return 0;
 615                 }
 616         }
 617
 618         switch (param) {
 619         case PIPE_VIDEO_CAP_SUPPORTED:
 620                 switch (codec) {
 621                 case PIPE_VIDEO_FORMAT_MPEG12:
 622                         return profile != PIPE_VIDEO_PROFILE_MPEG1;
 623                 case PIPE_VIDEO_FORMAT_MPEG4:
 624                         return 1;
 625                 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 626                         if ((sscreen->info.family == CHIP_POLARIS10 ||
 627                              sscreen->info.family == CHIP_POLARIS11) &&
 628                             sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
 629                                 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 630                                 return false;
 631                         }
 632                         return true;
 633                 case PIPE_VIDEO_FORMAT_VC1:
 634                         return true;
 635                 case PIPE_VIDEO_FORMAT_HEVC:
 636                         /* Carrizo only supports HEVC Main */
 637                         if (sscreen->info.family >= CHIP_STONEY)
 638                                 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 639                                         profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 640                         else if (sscreen->info.family >= CHIP_CARRIZO)
 641                                 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 642                         return false;
 643                 case PIPE_VIDEO_FORMAT_JPEG:
 644                         if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
 645                                 return false;
 646                         if (!(sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 19)) {
 647                                 RVID_ERR("No MJPEG support for the kernel version\n");
 648                                 return false;
 649                         }
 650                         return true;
 651                 case PIPE_VIDEO_FORMAT_VP9:
 652                         if (sscreen->info.family < CHIP_RAVEN)
 653                                 return false;
 654                         return true;
 655                 default:
 656                         return false;
 657                 }
 658         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 659                 return 1;
 660         case PIPE_VIDEO_CAP_MAX_WIDTH:
 661                 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 662         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 663                 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
 664         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 665                 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 ||
 666                     profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 667                         return PIPE_FORMAT_P016;
 668                 else
 669                         return PIPE_FORMAT_NV12;
 670
 671         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 672         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 673                 enum pipe_video_format format = u_reduce_video_profile(profile);
 674
 675                 if (format == PIPE_VIDEO_FORMAT_HEVC)
 676                         return false; //The firmware doesn't support interlaced HEVC.
 677                 else if (format == PIPE_VIDEO_FORMAT_JPEG)
 678                         return false;
 679                 else if (format == PIPE_VIDEO_FORMAT_VP9)
 680                         return false;
 681                 return true;
 682         }
 683         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 684                 return true;
 685         case PIPE_VIDEO_CAP_MAX_LEVEL:
 686                 switch (profile) {
 687                 case PIPE_VIDEO_PROFILE_MPEG1:
 688                         return 0;
 689                 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 690                 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 691                         return 3;
 692                 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 693                         return 3;
 694                 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 695                         return 5;
 696                 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 697                         return 1;
 698                 case PIPE_VIDEO_PROFILE_VC1_MAIN:
 699                         return 2;
 700                 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 701                         return 4;
 702                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 703                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 704                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 705                         return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
 706                 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 707                 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 708                         return 186;
 709                 default:
 710                         return 0;
 711                 }
 712         default:
 713                 return 0;
 714         }
 715 }
 716
 717 static boolean si_vid_is_format_supported(struct pipe_screen *screen,
 718                                           enum pipe_format format,
 719                                           enum pipe_video_profile profile,
 720                                           enum pipe_video_entrypoint entrypoint)
 721 {
 722         /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
 723         if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 724                 return (format == PIPE_FORMAT_NV12) ||
 725                         (format == PIPE_FORMAT_P016);
 726
 727         /* we can only handle this one with UVD */
 728         if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 729                 return format == PIPE_FORMAT_NV12;
 730
 731         return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 732 }
 733
 734 static unsigned get_max_threads_per_block(struct si_screen *screen,
 735                                           enum pipe_shader_ir ir_type)
 736 {
 737         if (ir_type == PIPE_SHADER_IR_NATIVE)
 738                 return 256;
 739
 740         /* Only 16 waves per thread-group on gfx9. */
 741         if (screen->info.chip_class >= GFX9)
 742                 return 1024;
 743
 744         /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
 745          * round number.
 746          */
 747         return 2048;
 748 }
 749
 750 static int si_get_compute_param(struct pipe_screen *screen,
 751                                 enum pipe_shader_ir ir_type,
 752                                 enum pipe_compute_cap param,
 753                                 void *ret)
 754 {
 755         struct si_screen *sscreen = (struct si_screen *)screen;
 756
 757         //TODO: select these params by asic
 758         switch (param) {
 759         case PIPE_COMPUTE_CAP_IR_TARGET: {
 760                 const char *gpu, *triple;
 761
 762                 triple = "amdgcn-mesa-mesa3d";
 763                 gpu = ac_get_llvm_processor_name(sscreen->info.family);
 764                 if (ret) {
 765                         sprintf(ret, "%s-%s", gpu, triple);
 766                 }
 767                 /* +2 for dash and terminating NIL byte */
 768                 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 769         }
 770         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 771                 if (ret) {
 772                         uint64_t *grid_dimension = ret;
 773                         grid_dimension[0] = 3;
 774                 }
 775                 return 1 * sizeof(uint64_t);
 776
 777         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 778                 if (ret) {
 779                         uint64_t *grid_size = ret;
 780                         grid_size[0] = 65535;
 781                         grid_size[1] = 65535;
 782                         grid_size[2] = 65535;
 783                 }
 784                 return 3 * sizeof(uint64_t) ;
 785
 786         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 787                 if (ret) {
 788                         uint64_t *block_size = ret;
 789                         unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 790                         block_size[0] = threads_per_block;
 791                         block_size[1] = threads_per_block;
 792                         block_size[2] = threads_per_block;
 793                 }
 794                 return 3 * sizeof(uint64_t);
 795
 796         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 797                 if (ret) {
 798                         uint64_t *max_threads_per_block = ret;
 799                         *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 800                 }
 801                 return sizeof(uint64_t);
 802         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 803                 if (ret) {
 804                         uint32_t *address_bits = ret;
 805                         address_bits[0] = 64;
 806                 }
 807                 return 1 * sizeof(uint32_t);
 808
 809         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 810                 if (ret) {
 811                         uint64_t *max_global_size = ret;
 812                         uint64_t max_mem_alloc_size;
 813
 814                         si_get_compute_param(screen, ir_type,
 815                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 816                                 &max_mem_alloc_size);
 817
 818                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 819                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 820                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 821                          * make sure we never report more than
 822                          * 4 * MAX_MEM_ALLOC_SIZE.
 823                          */
 824                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 825                                                 MAX2(sscreen->info.gart_size,
 826                                                      sscreen->info.vram_size));
 827                 }
 828                 return sizeof(uint64_t);
 829
 830         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 831                 if (ret) {
 832                         uint64_t *max_local_size = ret;
 833                         /* Value reported by the closed source driver. */
 834                         *max_local_size = 32768;
 835                 }
 836                 return sizeof(uint64_t);
 837
 838         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 839                 if (ret) {
 840                         uint64_t *max_input_size = ret;
 841                         /* Value reported by the closed source driver. */
 842                         *max_input_size = 1024;
 843                 }
 844                 return sizeof(uint64_t);
 845
 846         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 847                 if (ret) {
 848                         uint64_t *max_mem_alloc_size = ret;
 849
 850                         *max_mem_alloc_size = sscreen->info.max_alloc_size;
 851                 }
 852                 return sizeof(uint64_t);
 853
 854         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 855                 if (ret) {
 856                         uint32_t *max_clock_frequency = ret;
 857                         *max_clock_frequency = sscreen->info.max_shader_clock;
 858                 }
 859                 return sizeof(uint32_t);
 860
 861         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 862                 if (ret) {
 863                         uint32_t *max_compute_units = ret;
 864                         *max_compute_units = sscreen->info.num_good_compute_units;
 865                 }
 866                 return sizeof(uint32_t);
 867
 868         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 869                 if (ret) {
 870                         uint32_t *images_supported = ret;
 871                         *images_supported = 0;
 872                 }
 873                 return sizeof(uint32_t);
 874         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 875                 break; /* unused */
 876         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 877                 if (ret) {
 878                         uint32_t *subgroup_size = ret;
 879                         *subgroup_size = 64;
 880                 }
 881                 return sizeof(uint32_t);
 882         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 883                 if (ret) {
 884                         uint64_t *max_variable_threads_per_block = ret;
 885                         if (ir_type == PIPE_SHADER_IR_NATIVE)
 886                                 *max_variable_threads_per_block = 0;
 887                         else
 888                                 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
 889                 }
 890                 return sizeof(uint64_t);
 891         }
 892
 893         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 894         return 0;
 895 }
 896
 897 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 898 {
 899         struct si_screen *sscreen = (struct si_screen*)screen;
 900
 901         return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
 902                         sscreen->info.clock_crystal_freq;
 903 }
 904
 905 static void si_query_memory_info(struct pipe_screen *screen,
 906                                  struct pipe_memory_info *info)
 907 {
 908         struct si_screen *sscreen = (struct si_screen*)screen;
 909         struct radeon_winsys *ws = sscreen->ws;
 910         unsigned vram_usage, gtt_usage;
 911
 912         info->total_device_memory = sscreen->info.vram_size / 1024;
 913         info->total_staging_memory = sscreen->info.gart_size / 1024;
 914
 915         /* The real TTM memory usage is somewhat random, because:
 916          *
 917          * 1) TTM delays freeing memory, because it can only free it after
 918          *    fences expire.
 919          *
 920          * 2) The memory usage can be really low if big VRAM evictions are
 921          *    taking place, but the real usage is well above the size of VRAM.
 922          *
 923          * Instead, return statistics of this process.
 924          */
 925         vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
 926         gtt_usage =  ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
 927
 928         info->avail_device_memory =
 929                 vram_usage <= info->total_device_memory ?
 930                                 info->total_device_memory - vram_usage : 0;
 931         info->avail_staging_memory =
 932                 gtt_usage <= info->total_staging_memory ?
 933                                 info->total_staging_memory - gtt_usage : 0;
 934
 935         info->device_memory_evicted =
 936                 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 937
 938         if (sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 4)
 939                 info->nr_device_memory_evictions =
 940                         ws->query_value(ws, RADEON_NUM_EVICTIONS);
 941         else
 942                 /* Just return the number of evicted 64KB pages. */
 943                 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 944 }
 945
 946 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 947 {
 948         struct si_screen *sscreen = (struct si_screen*)pscreen;
 949
 950         return sscreen->disk_shader_cache;
 951 }
 952
 953 static void si_init_renderer_string(struct si_screen *sscreen)
 954 {
 955         struct radeon_winsys *ws = sscreen->ws;
 956         char family_name[32] = {}, kernel_version[128] = {};
 957         struct utsname uname_data;
 958
 959         const char *chip_name = si_get_marketing_name(ws);
 960
 961         if (chip_name)
 962                 snprintf(family_name, sizeof(family_name), "%s, ",
 963                          si_get_family_name(sscreen) + 4);
 964         else
 965                 chip_name = si_get_family_name(sscreen);
 966
 967         if (uname(&uname_data) == 0)
 968                 snprintf(kernel_version, sizeof(kernel_version),
 969                          ", %s", uname_data.release);
 970
 971         snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
 972                  "%s (%sDRM %i.%i.%i%s, LLVM %i.%i.%i)",
 973                  chip_name, family_name, sscreen->info.drm_major,
 974                  sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
 975                  kernel_version,
 976                  (HAVE_LLVM >> 8) & 0xff,
 977                  HAVE_LLVM & 0xff,
 978                  MESA_LLVM_VERSION_PATCH);
 979 }
 980
 981 void si_init_screen_get_functions(struct si_screen *sscreen)
 982 {
 983         sscreen->b.get_name = si_get_name;
 984         sscreen->b.get_vendor = si_get_vendor;
 985         sscreen->b.get_device_vendor = si_get_device_vendor;
 986         sscreen->b.get_param = si_get_param;
 987         sscreen->b.get_paramf = si_get_paramf;
 988         sscreen->b.get_compute_param = si_get_compute_param;
 989         sscreen->b.get_timestamp = si_get_timestamp;
 990         sscreen->b.get_shader_param = si_get_shader_param;
 991         sscreen->b.get_compiler_options = si_get_compiler_options;
 992         sscreen->b.get_device_uuid = si_get_device_uuid;
 993         sscreen->b.get_driver_uuid = si_get_driver_uuid;
 994         sscreen->b.query_memory_info = si_query_memory_info;
 995         sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
 996
 997         if (sscreen->info.has_hw_decode) {
 998                 sscreen->b.get_video_param = si_get_video_param;
 999                 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
1000         } else {
1001                 sscreen->b.get_video_param = si_get_video_param_no_decode;
1002                 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1003         }
1004
1005         si_init_renderer_string(sscreen);
1006 }