src/gallium/drivers/radeonsi/si_get.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "si_pipe.h"
  26 #include "radeon/radeon_video.h"
  27 #include "radeon/radeon_vce.h"
  28 #include "radeon/radeon_uvd_enc.h"
  29 #include "ac_llvm_util.h"
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32 #include "util/u_screen.h"
  33 #include "util/u_video.h"
  34 #include "compiler/nir/nir.h"
  35
  36 #include <sys/utsname.h>
  37
  38 static const char *si_get_vendor(struct pipe_screen *pscreen)
  39 {
  40         /* Don't change this. Games such as Alien Isolation are broken if this
  41          * returns "Advanced Micro Devices, Inc."
  42          */
  43         return "X.Org";
  44 }
  45
  46 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
  47 {
  48         return "AMD";
  49 }
  50
  51 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  52 {
  53         struct si_screen *sscreen = (struct si_screen *)pscreen;
  54
  55         switch (param) {
  56         /* Supported features (boolean caps). */
  57         case PIPE_CAP_ACCELERATED:
  58         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  59         case PIPE_CAP_ANISOTROPIC_FILTER:
  60         case PIPE_CAP_POINT_SPRITE:
  61         case PIPE_CAP_OCCLUSION_QUERY:
  62         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  63         case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
  64         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  65         case PIPE_CAP_TEXTURE_SWIZZLE:
  66         case PIPE_CAP_DEPTH_CLIP_DISABLE:
  67         case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
  68         case PIPE_CAP_SHADER_STENCIL_EXPORT:
  69         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
  70         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  71         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  72         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  73         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  74         case PIPE_CAP_SM3:
  75         case PIPE_CAP_SEAMLESS_CUBE_MAP:
  76         case PIPE_CAP_PRIMITIVE_RESTART:
  77         case PIPE_CAP_CONDITIONAL_RENDER:
  78         case PIPE_CAP_TEXTURE_BARRIER:
  79         case PIPE_CAP_INDEP_BLEND_ENABLE:
  80         case PIPE_CAP_INDEP_BLEND_FUNC:
  81         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  82         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
  83         case PIPE_CAP_START_INSTANCE:
  84         case PIPE_CAP_NPOT_TEXTURES:
  85         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  86         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
  87         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
  88         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
  89         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  90         case PIPE_CAP_TGSI_INSTANCEID:
  91         case PIPE_CAP_COMPUTE:
  92         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
  93         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
  94         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
  95         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  96         case PIPE_CAP_CUBE_MAP_ARRAY:
  97         case PIPE_CAP_SAMPLE_SHADING:
  98         case PIPE_CAP_DRAW_INDIRECT:
  99         case PIPE_CAP_CLIP_HALFZ:
 100         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 101         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 102         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 103         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 104         case PIPE_CAP_TGSI_TEXCOORD:
 105         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 106         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 107         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 108         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 109         case PIPE_CAP_SHAREABLE_SHADERS:
 110         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 111         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 112         case PIPE_CAP_TEXTURE_QUERY_LOD:
 113         case PIPE_CAP_TEXTURE_GATHER_SM5:
 114         case PIPE_CAP_TGSI_TXQS:
 115         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 116         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 117         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 118         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 119         case PIPE_CAP_INVALIDATE_BUFFER:
 120         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 121         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 122         case PIPE_CAP_QUERY_MEMORY_INFO:
 123         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 124         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 125         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 126         case PIPE_CAP_GENERATE_MIPMAP:
 127         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 128         case PIPE_CAP_STRING_MARKER:
 129         case PIPE_CAP_CLEAR_TEXTURE:
 130         case PIPE_CAP_CULL_DISTANCE:
 131         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 132         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 133         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 134         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 135         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 136         case PIPE_CAP_DOUBLES:
 137         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 138         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 139         case PIPE_CAP_BINDLESS_TEXTURE:
 140         case PIPE_CAP_QUERY_TIMESTAMP:
 141         case PIPE_CAP_QUERY_TIME_ELAPSED:
 142         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 143         case PIPE_CAP_QUERY_SO_OVERFLOW:
 144         case PIPE_CAP_MEMOBJ:
 145         case PIPE_CAP_LOAD_CONSTBUF:
 146         case PIPE_CAP_INT64:
 147         case PIPE_CAP_INT64_DIVMOD:
 148         case PIPE_CAP_TGSI_CLOCK:
 149         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 150         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 151         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 152         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 153         case PIPE_CAP_TGSI_BALLOT:
 154         case PIPE_CAP_TGSI_VOTE:
 155         case PIPE_CAP_TGSI_FS_FBFETCH:
 156         case PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK:
 157         case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 158         case PIPE_CAP_PREFER_COMPUTE_BLIT_FOR_MULTIMEDIA:
 159                 return 1;
 160
 161         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 162                 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 163
 164         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 165                 return sscreen->info.has_gpu_reset_status_query ||
 166                        sscreen->info.has_gpu_reset_counter_query;
 167
 168         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 169                 return sscreen->info.has_2d_tiling;
 170
 171         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 172                 return SI_MAP_BUFFER_ALIGNMENT;
 173
 174         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 175         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 176         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 177         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 178         case PIPE_CAP_MAX_VERTEX_STREAMS:
 179         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 180         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 181                 return 4;
 182
 183         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 184         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 185                 if (sscreen->info.has_indirect_compute_dispatch)
 186                                 return 450;
 187                 return 420;
 188
 189         case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 190                 /* Optimal number for good TexSubImage performance on Polaris10. */
 191                 return 64 * 1024 * 1024;
 192
 193         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 194         case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 195                 return MIN2(sscreen->info.max_alloc_size, INT_MAX);
 196
 197         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 198         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 199         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 200                 return !sscreen->info.has_unaligned_shader_loads;
 201
 202         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 203                 return sscreen->info.has_sparse_vm_mappings ?
 204                                 RADEON_SPARSE_PAGE_SIZE : 0;
 205
 206         case PIPE_CAP_PACKED_UNIFORMS:
 207                 if (sscreen->options.enable_nir)
 208                         return 1;
 209                 return 0;
 210
 211         /* Unsupported features. */
 212         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 213         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 214         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 215         case PIPE_CAP_USER_VERTEX_BUFFERS:
 216         case PIPE_CAP_FAKE_SW_MSAA:
 217         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 218         case PIPE_CAP_VERTEXID_NOBASE:
 219         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 220         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 221         case PIPE_CAP_UMA:
 222         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 223         case PIPE_CAP_POST_DEPTH_COVERAGE:
 224         case PIPE_CAP_TILE_RASTER_ORDER:
 225         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 226         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 227         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 228         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 229         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 230         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 231         case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 232         case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 233         case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 234                 return 0;
 235
 236         case PIPE_CAP_FENCE_SIGNAL:
 237                 return sscreen->info.has_syncobj;
 238
 239         case PIPE_CAP_CONSTBUF0_FLAGS:
 240                 return SI_RESOURCE_FLAG_32BIT;
 241
 242         case PIPE_CAP_NATIVE_FENCE_FD:
 243                 return sscreen->info.has_fence_to_handle;
 244
 245         case PIPE_CAP_DRAW_PARAMETERS:
 246         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 247         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 248                 return sscreen->has_draw_indirect_multi;
 249
 250         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 251                 return 30;
 252
 253         case PIPE_CAP_MAX_VARYINGS:
 254                 return 32;
 255
 256         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 257                 return sscreen->info.chip_class <= VI ?
 258                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 259
 260         /* Stream output. */
 261         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 262         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 263                 return 32*4;
 264
 265         /* Geometry shader output. */
 266         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 267                 return 1024;
 268         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 269                 return 4095;
 270         case PIPE_CAP_MAX_GS_INVOCATIONS:
 271                 /* The closed driver exposes 127, but 125 is the greatest
 272                  * number that works. */
 273                 return 125;
 274
 275         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 276                 return 2048;
 277
 278         /* Texturing. */
 279         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 280         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 281                 return 15; /* 16384 */
 282         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 283                 /* textures support 8192, but layered rendering supports 2048 */
 284                 return 12;
 285         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 286                 /* textures support 8192, but layered rendering supports 2048 */
 287                 return 2048;
 288
 289         /* Viewports and render targets. */
 290         case PIPE_CAP_MAX_VIEWPORTS:
 291                 return SI_MAX_VIEWPORTS;
 292         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 293         case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 294         case PIPE_CAP_MAX_RENDER_TARGETS:
 295                 return 8;
 296         case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 297                 return sscreen->info.has_eqaa_surface_allocator ? 2 : 0;
 298
 299         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 300         case PIPE_CAP_MIN_TEXEL_OFFSET:
 301                 return -32;
 302
 303         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 304         case PIPE_CAP_MAX_TEXEL_OFFSET:
 305                 return 31;
 306
 307         case PIPE_CAP_ENDIANNESS:
 308                 return PIPE_ENDIAN_LITTLE;
 309
 310         case PIPE_CAP_VENDOR_ID:
 311                 return ATI_VENDOR_ID;
 312         case PIPE_CAP_DEVICE_ID:
 313                 return sscreen->info.pci_id;
 314         case PIPE_CAP_VIDEO_MEMORY:
 315                 return sscreen->info.vram_size >> 20;
 316         case PIPE_CAP_PCI_GROUP:
 317                 return sscreen->info.pci_domain;
 318         case PIPE_CAP_PCI_BUS:
 319                 return sscreen->info.pci_bus;
 320         case PIPE_CAP_PCI_DEVICE:
 321                 return sscreen->info.pci_dev;
 322         case PIPE_CAP_PCI_FUNCTION:
 323                 return sscreen->info.pci_func;
 324
 325         default:
 326                 return u_pipe_screen_get_param_defaults(pscreen, param);
 327         }
 328 }
 329
 330 static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
 331 {
 332         switch (param) {
 333         case PIPE_CAPF_MAX_LINE_WIDTH:
 334         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 335                 /* This depends on the quant mode, though the precise interactions
 336                  * are unknown. */
 337                 return 2048;
 338         case PIPE_CAPF_MAX_POINT_WIDTH:
 339         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 340                 return SI_MAX_POINT_SIZE;
 341         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 342                 return 16.0f;
 343         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 344                 return 16.0f;
 345         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 346         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 347         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 348                 return 0.0f;
 349         }
 350         return 0.0f;
 351 }
 352
 353 static int si_get_shader_param(struct pipe_screen* pscreen,
 354                                enum pipe_shader_type shader,
 355                                enum pipe_shader_cap param)
 356 {
 357         struct si_screen *sscreen = (struct si_screen *)pscreen;
 358
 359         switch(shader)
 360         {
 361         case PIPE_SHADER_FRAGMENT:
 362         case PIPE_SHADER_VERTEX:
 363         case PIPE_SHADER_GEOMETRY:
 364         case PIPE_SHADER_TESS_CTRL:
 365         case PIPE_SHADER_TESS_EVAL:
 366                 break;
 367         case PIPE_SHADER_COMPUTE:
 368                 switch (param) {
 369                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 370                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 371
 372                         if (sscreen->info.has_indirect_compute_dispatch)
 373                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 374
 375                         return ir;
 376                 }
 377
 378                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 379                         uint64_t max_const_buffer_size;
 380                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 381                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 382                                 &max_const_buffer_size);
 383                         return MIN2(max_const_buffer_size, INT_MAX);
 384                 }
 385                 default:
 386                         /* If compute shaders don't require a special value
 387                          * for this cap, we can return the same value we
 388                          * do for other shader types. */
 389                         break;
 390                 }
 391                 break;
 392         default:
 393                 return 0;
 394         }
 395
 396         switch (param) {
 397         /* Shader limits. */
 398         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 399         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 400         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 401         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 402         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 403                 return 16384;
 404         case PIPE_SHADER_CAP_MAX_INPUTS:
 405                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 406         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 407                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 408         case PIPE_SHADER_CAP_MAX_TEMPS:
 409                 return 256; /* Max native temporaries. */
 410         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 411                 return MIN2(sscreen->info.max_alloc_size, INT_MAX - 3); /* aligned to 4 */
 412         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 413                 return SI_NUM_CONST_BUFFERS;
 414         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 415         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 416                 return SI_NUM_SAMPLERS;
 417         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 418                 return SI_NUM_SHADER_BUFFERS;
 419         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 420                 return SI_NUM_IMAGES;
 421         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 422                 if (sscreen->options.enable_nir)
 423                         return 0;
 424                 return 32;
 425         case PIPE_SHADER_CAP_PREFERRED_IR:
 426                 if (sscreen->options.enable_nir)
 427                         return PIPE_SHADER_IR_NIR;
 428                 return PIPE_SHADER_IR_TGSI;
 429         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 430                 return 4;
 431
 432         /* Supported boolean features. */
 433         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 434         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 435         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 436         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 437         case PIPE_SHADER_CAP_INTEGERS:
 438         case PIPE_SHADER_CAP_INT64_ATOMICS:
 439         case PIPE_SHADER_CAP_FP16:
 440         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 441         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 442         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 443         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 444         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 445         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 446                 return 1;
 447
 448         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 449                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 450                 if (shader == PIPE_SHADER_GEOMETRY)
 451                         return 0;
 452
 453                 if (shader == PIPE_SHADER_VERTEX &&
 454                     !sscreen->llvm_has_working_vgpr_indexing)
 455                         return 0;
 456
 457                 /* TCS and TES load inputs directly from LDS or offchip
 458                  * memory, so indirect indexing is always supported.
 459                  * PS has to support indirect indexing, because we can't
 460                  * lower that to TEMPs for INTERP instructions.
 461                  */
 462                 return 1;
 463
 464         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 465                 return sscreen->llvm_has_working_vgpr_indexing ||
 466                        /* TCS stores outputs directly to memory. */
 467                        shader == PIPE_SHADER_TESS_CTRL;
 468
 469         /* Unsupported boolean features. */
 470         case PIPE_SHADER_CAP_SUBROUTINES:
 471         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 472         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 473         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 474                 return 0;
 475         case PIPE_SHADER_CAP_SCALAR_ISA:
 476                 return 1;
 477         }
 478         return 0;
 479 }
 480
 481 static const struct nir_shader_compiler_options nir_options = {
 482         .lower_scmp = true,
 483         .lower_flrp32 = true,
 484         .lower_flrp64 = true,
 485         .lower_fsat = true,
 486         .lower_fdiv = true,
 487         .lower_sub = true,
 488         .lower_ffma = true,
 489         .lower_pack_snorm_2x16 = true,
 490         .lower_pack_snorm_4x8 = true,
 491         .lower_pack_unorm_2x16 = true,
 492         .lower_pack_unorm_4x8 = true,
 493         .lower_unpack_snorm_2x16 = true,
 494         .lower_unpack_snorm_4x8 = true,
 495         .lower_unpack_unorm_2x16 = true,
 496         .lower_unpack_unorm_4x8 = true,
 497         .lower_extract_byte = true,
 498         .lower_extract_word = true,
 499         .optimize_sample_mask_in = true,
 500         .max_unroll_iterations = 32,
 501 };
 502
 503 static const void *
 504 si_get_compiler_options(struct pipe_screen *screen,
 505                         enum pipe_shader_ir ir,
 506                         enum pipe_shader_type shader)
 507 {
 508         assert(ir == PIPE_SHADER_IR_NIR);
 509         return &nir_options;
 510 }
 511
 512 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 513 {
 514         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 515 }
 516
 517 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 518 {
 519         struct si_screen *sscreen = (struct si_screen *)pscreen;
 520
 521         ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
 522 }
 523
 524 static const char* si_get_name(struct pipe_screen *pscreen)
 525 {
 526         struct si_screen *sscreen = (struct si_screen*)pscreen;
 527
 528         return sscreen->renderer_string;
 529 }
 530
 531 static int si_get_video_param_no_decode(struct pipe_screen *screen,
 532                                         enum pipe_video_profile profile,
 533                                         enum pipe_video_entrypoint entrypoint,
 534                                         enum pipe_video_cap param)
 535 {
 536         switch (param) {
 537         case PIPE_VIDEO_CAP_SUPPORTED:
 538                 return vl_profile_supported(screen, profile, entrypoint);
 539         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 540                 return 1;
 541         case PIPE_VIDEO_CAP_MAX_WIDTH:
 542         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 543                 return vl_video_buffer_max_size(screen);
 544         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 545                 return PIPE_FORMAT_NV12;
 546         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 547                 return false;
 548         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 549                 return false;
 550         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 551                 return true;
 552         case PIPE_VIDEO_CAP_MAX_LEVEL:
 553                 return vl_level_supported(screen, profile);
 554         default:
 555                 return 0;
 556         }
 557 }
 558
 559 static int si_get_video_param(struct pipe_screen *screen,
 560                               enum pipe_video_profile profile,
 561                               enum pipe_video_entrypoint entrypoint,
 562                               enum pipe_video_cap param)
 563 {
 564         struct si_screen *sscreen = (struct si_screen *)screen;
 565         enum pipe_video_format codec = u_reduce_video_profile(profile);
 566
 567         if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 568                 switch (param) {
 569                 case PIPE_VIDEO_CAP_SUPPORTED:
 570                         return (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 571                                 (si_vce_is_fw_version_supported(sscreen) ||
 572                                  sscreen->info.family == CHIP_RAVEN ||
 573                                  sscreen->info.family == CHIP_RAVEN2)) ||
 574                                 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
 575                                 (sscreen->info.family == CHIP_RAVEN ||
 576                                  sscreen->info.family == CHIP_RAVEN2 ||
 577                                  si_radeon_uvd_enc_supported(sscreen)));
 578                 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 579                         return 1;
 580                 case PIPE_VIDEO_CAP_MAX_WIDTH:
 581                         return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 582                 case PIPE_VIDEO_CAP_MAX_HEIGHT:
 583                         return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
 584                 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 585                         return PIPE_FORMAT_NV12;
 586                 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 587                         return false;
 588                 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 589                         return false;
 590                 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 591                         return true;
 592                 case PIPE_VIDEO_CAP_STACKED_FRAMES:
 593                         return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
 594                 default:
 595                         return 0;
 596                 }
 597         }
 598
 599         switch (param) {
 600         case PIPE_VIDEO_CAP_SUPPORTED:
 601                 switch (codec) {
 602                 case PIPE_VIDEO_FORMAT_MPEG12:
 603                         return profile != PIPE_VIDEO_PROFILE_MPEG1;
 604                 case PIPE_VIDEO_FORMAT_MPEG4:
 605                         return 1;
 606                 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 607                         if ((sscreen->info.family == CHIP_POLARIS10 ||
 608                              sscreen->info.family == CHIP_POLARIS11) &&
 609                             sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
 610                                 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 611                                 return false;
 612                         }
 613                         return true;
 614                 case PIPE_VIDEO_FORMAT_VC1:
 615                         return true;
 616                 case PIPE_VIDEO_FORMAT_HEVC:
 617                         /* Carrizo only supports HEVC Main */
 618                         if (sscreen->info.family >= CHIP_STONEY)
 619                                 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 620                                         profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 621                         else if (sscreen->info.family >= CHIP_CARRIZO)
 622                                 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 623                         return false;
 624                 case PIPE_VIDEO_FORMAT_JPEG:
 625                         if (sscreen->info.family == CHIP_RAVEN ||
 626                             sscreen->info.family == CHIP_RAVEN2)
 627                                 return true;
 628                         if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
 629                                 return false;
 630                         if (!(sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 19)) {
 631                                 RVID_ERR("No MJPEG support for the kernel version\n");
 632                                 return false;
 633                         }
 634                         return true;
 635                 case PIPE_VIDEO_FORMAT_VP9:
 636                         if (sscreen->info.family < CHIP_RAVEN)
 637                                 return false;
 638                         return true;
 639                 default:
 640                         return false;
 641                 }
 642         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 643                 return 1;
 644         case PIPE_VIDEO_CAP_MAX_WIDTH:
 645                 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 646         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 647                 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
 648         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 649                 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 ||
 650                     profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 651                         return PIPE_FORMAT_P016;
 652                 else
 653                         return PIPE_FORMAT_NV12;
 654
 655         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 656         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 657                 enum pipe_video_format format = u_reduce_video_profile(profile);
 658
 659                 if (format == PIPE_VIDEO_FORMAT_HEVC)
 660                         return false; //The firmware doesn't support interlaced HEVC.
 661                 else if (format == PIPE_VIDEO_FORMAT_JPEG)
 662                         return false;
 663                 else if (format == PIPE_VIDEO_FORMAT_VP9)
 664                         return false;
 665                 return true;
 666         }
 667         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 668                 return true;
 669         case PIPE_VIDEO_CAP_MAX_LEVEL:
 670                 switch (profile) {
 671                 case PIPE_VIDEO_PROFILE_MPEG1:
 672                         return 0;
 673                 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 674                 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 675                         return 3;
 676                 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 677                         return 3;
 678                 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 679                         return 5;
 680                 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 681                         return 1;
 682                 case PIPE_VIDEO_PROFILE_VC1_MAIN:
 683                         return 2;
 684                 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 685                         return 4;
 686                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 687                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 688                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 689                         return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
 690                 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 691                 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 692                         return 186;
 693                 default:
 694                         return 0;
 695                 }
 696         default:
 697                 return 0;
 698         }
 699 }
 700
 701 static boolean si_vid_is_format_supported(struct pipe_screen *screen,
 702                                           enum pipe_format format,
 703                                           enum pipe_video_profile profile,
 704                                           enum pipe_video_entrypoint entrypoint)
 705 {
 706         /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
 707         if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 708                 return (format == PIPE_FORMAT_NV12) ||
 709                         (format == PIPE_FORMAT_P016);
 710
 711         /* we can only handle this one with UVD */
 712         if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 713                 return format == PIPE_FORMAT_NV12;
 714
 715         return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 716 }
 717
 718 static unsigned get_max_threads_per_block(struct si_screen *screen,
 719                                           enum pipe_shader_ir ir_type)
 720 {
 721         if (ir_type == PIPE_SHADER_IR_NATIVE)
 722                 return 256;
 723
 724         /* Only 16 waves per thread-group on gfx9. */
 725         if (screen->info.chip_class >= GFX9)
 726                 return 1024;
 727
 728         /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
 729          * round number.
 730          */
 731         return 2048;
 732 }
 733
 734 static int si_get_compute_param(struct pipe_screen *screen,
 735                                 enum pipe_shader_ir ir_type,
 736                                 enum pipe_compute_cap param,
 737                                 void *ret)
 738 {
 739         struct si_screen *sscreen = (struct si_screen *)screen;
 740
 741         //TODO: select these params by asic
 742         switch (param) {
 743         case PIPE_COMPUTE_CAP_IR_TARGET: {
 744                 const char *gpu, *triple;
 745
 746                 triple = "amdgcn-mesa-mesa3d";
 747                 gpu = ac_get_llvm_processor_name(sscreen->info.family);
 748                 if (ret) {
 749                         sprintf(ret, "%s-%s", gpu, triple);
 750                 }
 751                 /* +2 for dash and terminating NIL byte */
 752                 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 753         }
 754         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 755                 if (ret) {
 756                         uint64_t *grid_dimension = ret;
 757                         grid_dimension[0] = 3;
 758                 }
 759                 return 1 * sizeof(uint64_t);
 760
 761         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 762                 if (ret) {
 763                         uint64_t *grid_size = ret;
 764                         grid_size[0] = 65535;
 765                         grid_size[1] = 65535;
 766                         grid_size[2] = 65535;
 767                 }
 768                 return 3 * sizeof(uint64_t) ;
 769
 770         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 771                 if (ret) {
 772                         uint64_t *block_size = ret;
 773                         unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 774                         block_size[0] = threads_per_block;
 775                         block_size[1] = threads_per_block;
 776                         block_size[2] = threads_per_block;
 777                 }
 778                 return 3 * sizeof(uint64_t);
 779
 780         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 781                 if (ret) {
 782                         uint64_t *max_threads_per_block = ret;
 783                         *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 784                 }
 785                 return sizeof(uint64_t);
 786         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 787                 if (ret) {
 788                         uint32_t *address_bits = ret;
 789                         address_bits[0] = 64;
 790                 }
 791                 return 1 * sizeof(uint32_t);
 792
 793         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 794                 if (ret) {
 795                         uint64_t *max_global_size = ret;
 796                         uint64_t max_mem_alloc_size;
 797
 798                         si_get_compute_param(screen, ir_type,
 799                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 800                                 &max_mem_alloc_size);
 801
 802                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 803                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 804                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 805                          * make sure we never report more than
 806                          * 4 * MAX_MEM_ALLOC_SIZE.
 807                          */
 808                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 809                                                 MAX2(sscreen->info.gart_size,
 810                                                      sscreen->info.vram_size));
 811                 }
 812                 return sizeof(uint64_t);
 813
 814         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 815                 if (ret) {
 816                         uint64_t *max_local_size = ret;
 817                         /* Value reported by the closed source driver. */
 818                         *max_local_size = 32768;
 819                 }
 820                 return sizeof(uint64_t);
 821
 822         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 823                 if (ret) {
 824                         uint64_t *max_input_size = ret;
 825                         /* Value reported by the closed source driver. */
 826                         *max_input_size = 1024;
 827                 }
 828                 return sizeof(uint64_t);
 829
 830         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 831                 if (ret) {
 832                         uint64_t *max_mem_alloc_size = ret;
 833
 834                         *max_mem_alloc_size = sscreen->info.max_alloc_size;
 835                 }
 836                 return sizeof(uint64_t);
 837
 838         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 839                 if (ret) {
 840                         uint32_t *max_clock_frequency = ret;
 841                         *max_clock_frequency = sscreen->info.max_shader_clock;
 842                 }
 843                 return sizeof(uint32_t);
 844
 845         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 846                 if (ret) {
 847                         uint32_t *max_compute_units = ret;
 848                         *max_compute_units = sscreen->info.num_good_compute_units;
 849                 }
 850                 return sizeof(uint32_t);
 851
 852         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 853                 if (ret) {
 854                         uint32_t *images_supported = ret;
 855                         *images_supported = 0;
 856                 }
 857                 return sizeof(uint32_t);
 858         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 859                 break; /* unused */
 860         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 861                 if (ret) {
 862                         uint32_t *subgroup_size = ret;
 863                         *subgroup_size = 64;
 864                 }
 865                 return sizeof(uint32_t);
 866         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 867                 if (ret) {
 868                         uint64_t *max_variable_threads_per_block = ret;
 869                         if (ir_type == PIPE_SHADER_IR_NATIVE)
 870                                 *max_variable_threads_per_block = 0;
 871                         else
 872                                 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
 873                 }
 874                 return sizeof(uint64_t);
 875         }
 876
 877         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 878         return 0;
 879 }
 880
 881 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 882 {
 883         struct si_screen *sscreen = (struct si_screen*)screen;
 884
 885         return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
 886                         sscreen->info.clock_crystal_freq;
 887 }
 888
 889 static void si_query_memory_info(struct pipe_screen *screen,
 890                                  struct pipe_memory_info *info)
 891 {
 892         struct si_screen *sscreen = (struct si_screen*)screen;
 893         struct radeon_winsys *ws = sscreen->ws;
 894         unsigned vram_usage, gtt_usage;
 895
 896         info->total_device_memory = sscreen->info.vram_size / 1024;
 897         info->total_staging_memory = sscreen->info.gart_size / 1024;
 898
 899         /* The real TTM memory usage is somewhat random, because:
 900          *
 901          * 1) TTM delays freeing memory, because it can only free it after
 902          *    fences expire.
 903          *
 904          * 2) The memory usage can be really low if big VRAM evictions are
 905          *    taking place, but the real usage is well above the size of VRAM.
 906          *
 907          * Instead, return statistics of this process.
 908          */
 909         vram_usage = ws->query_value(ws, RADEON_VRAM_USAGE) / 1024;
 910         gtt_usage =  ws->query_value(ws, RADEON_GTT_USAGE) / 1024;
 911
 912         info->avail_device_memory =
 913                 vram_usage <= info->total_device_memory ?
 914                                 info->total_device_memory - vram_usage : 0;
 915         info->avail_staging_memory =
 916                 gtt_usage <= info->total_staging_memory ?
 917                                 info->total_staging_memory - gtt_usage : 0;
 918
 919         info->device_memory_evicted =
 920                 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 921
 922         if (sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 4)
 923                 info->nr_device_memory_evictions =
 924                         ws->query_value(ws, RADEON_NUM_EVICTIONS);
 925         else
 926                 /* Just return the number of evicted 64KB pages. */
 927                 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 928 }
 929
 930 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 931 {
 932         struct si_screen *sscreen = (struct si_screen*)pscreen;
 933
 934         return sscreen->disk_shader_cache;
 935 }
 936
 937 static void si_init_renderer_string(struct si_screen *sscreen)
 938 {
 939         char first_name[256], second_name[32] = {}, kernel_version[128] = {};
 940         struct utsname uname_data;
 941
 942         if (sscreen->info.marketing_name) {
 943                 snprintf(first_name, sizeof(first_name), "%s",
 944                          sscreen->info.marketing_name);
 945                 snprintf(second_name, sizeof(second_name), "%s, ",
 946                          sscreen->info.name);
 947         } else {
 948                 snprintf(first_name, sizeof(first_name), "AMD %s",
 949                          sscreen->info.name);
 950         }
 951
 952         if (uname(&uname_data) == 0)
 953                 snprintf(kernel_version, sizeof(kernel_version),
 954                          ", %s", uname_data.release);
 955
 956         snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
 957                  "%s (%sDRM %i.%i.%i%s, LLVM " MESA_LLVM_VERSION_STRING ")",
 958                  first_name, second_name, sscreen->info.drm_major,
 959                  sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
 960                  kernel_version);
 961 }
 962
 963 void si_init_screen_get_functions(struct si_screen *sscreen)
 964 {
 965         sscreen->b.get_name = si_get_name;
 966         sscreen->b.get_vendor = si_get_vendor;
 967         sscreen->b.get_device_vendor = si_get_device_vendor;
 968         sscreen->b.get_param = si_get_param;
 969         sscreen->b.get_paramf = si_get_paramf;
 970         sscreen->b.get_compute_param = si_get_compute_param;
 971         sscreen->b.get_timestamp = si_get_timestamp;
 972         sscreen->b.get_shader_param = si_get_shader_param;
 973         sscreen->b.get_compiler_options = si_get_compiler_options;
 974         sscreen->b.get_device_uuid = si_get_device_uuid;
 975         sscreen->b.get_driver_uuid = si_get_driver_uuid;
 976         sscreen->b.query_memory_info = si_query_memory_info;
 977         sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
 978
 979         if (sscreen->info.has_hw_decode) {
 980                 sscreen->b.get_video_param = si_get_video_param;
 981                 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
 982         } else {
 983                 sscreen->b.get_video_param = si_get_video_param_no_decode;
 984                 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
 985         }
 986
 987         si_init_renderer_string(sscreen);
 988 }