src/gallium/drivers/radeonsi/si_get.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "radeon/radeon_video.h"
  26 #include "radeon/radeon_vce.h"
  27 #include "ac_llvm_util.h"
  28 #include "vl/vl_decoder.h"
  29 #include "vl/vl_video_buffer.h"
  30 #include "util/u_video.h"
  31 #include "compiler/nir/nir.h"
  32
  33 #include <sys/utsname.h>
  34
  35 static const char *si_get_vendor(struct pipe_screen *pscreen)
  36 {
  37         /* Don't change this. Games such as Alien Isolation are broken if this
  38          * returns "Advanced Micro Devices, Inc."
  39          */
  40         return "X.Org";
  41 }
  42
  43 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
  44 {
  45         return "AMD";
  46 }
  47
  48 static const char *si_get_marketing_name(struct radeon_winsys *ws)
  49 {
  50         if (!ws->get_chip_name)
  51                 return NULL;
  52         return ws->get_chip_name(ws);
  53 }
  54
  55 const char *si_get_family_name(const struct si_screen *sscreen)
  56 {
  57         switch (sscreen->info.family) {
  58         case CHIP_TAHITI: return "AMD TAHITI";
  59         case CHIP_PITCAIRN: return "AMD PITCAIRN";
  60         case CHIP_VERDE: return "AMD CAPE VERDE";
  61         case CHIP_OLAND: return "AMD OLAND";
  62         case CHIP_HAINAN: return "AMD HAINAN";
  63         case CHIP_BONAIRE: return "AMD BONAIRE";
  64         case CHIP_KAVERI: return "AMD KAVERI";
  65         case CHIP_KABINI: return "AMD KABINI";
  66         case CHIP_HAWAII: return "AMD HAWAII";
  67         case CHIP_MULLINS: return "AMD MULLINS";
  68         case CHIP_TONGA: return "AMD TONGA";
  69         case CHIP_ICELAND: return "AMD ICELAND";
  70         case CHIP_CARRIZO: return "AMD CARRIZO";
  71         case CHIP_FIJI: return "AMD FIJI";
  72         case CHIP_POLARIS10: return "AMD POLARIS10";
  73         case CHIP_POLARIS11: return "AMD POLARIS11";
  74         case CHIP_POLARIS12: return "AMD POLARIS12";
  75         case CHIP_STONEY: return "AMD STONEY";
  76         case CHIP_VEGA10: return "AMD VEGA10";
  77         case CHIP_RAVEN: return "AMD RAVEN";
  78         default: return "AMD unknown";
  79         }
  80 }
  81
  82 static bool si_have_tgsi_compute(struct si_screen *sscreen)
  83 {
  84         /* Old kernels disallowed some register writes for SI
  85          * that are used for indirect dispatches. */
  86         return (sscreen->info.chip_class >= CIK ||
  87                 sscreen->info.drm_major == 3 ||
  88                 (sscreen->info.drm_major == 2 &&
  89                  sscreen->info.drm_minor >= 45));
  90 }
  91
  92 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  93 {
  94         struct si_screen *sscreen = (struct si_screen *)pscreen;
  95
  96         switch (param) {
  97         /* Supported features (boolean caps). */
  98         case PIPE_CAP_ACCELERATED:
  99         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 100         case PIPE_CAP_ANISOTROPIC_FILTER:
 101         case PIPE_CAP_POINT_SPRITE:
 102         case PIPE_CAP_OCCLUSION_QUERY:
 103         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 104         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 105         case PIPE_CAP_TEXTURE_SWIZZLE:
 106         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 107         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 108         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 109         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 110         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 111         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 112         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 113         case PIPE_CAP_SM3:
 114         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 115         case PIPE_CAP_PRIMITIVE_RESTART:
 116         case PIPE_CAP_CONDITIONAL_RENDER:
 117         case PIPE_CAP_TEXTURE_BARRIER:
 118         case PIPE_CAP_INDEP_BLEND_ENABLE:
 119         case PIPE_CAP_INDEP_BLEND_FUNC:
 120         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 121         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 122         case PIPE_CAP_START_INSTANCE:
 123         case PIPE_CAP_NPOT_TEXTURES:
 124         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 125         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 126         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 127         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 128         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 129         case PIPE_CAP_TGSI_INSTANCEID:
 130         case PIPE_CAP_COMPUTE:
 131         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 132         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 133         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 134         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 135         case PIPE_CAP_CUBE_MAP_ARRAY:
 136         case PIPE_CAP_SAMPLE_SHADING:
 137         case PIPE_CAP_DRAW_INDIRECT:
 138         case PIPE_CAP_CLIP_HALFZ:
 139         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 140         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 141         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 142         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 143         case PIPE_CAP_TGSI_TEXCOORD:
 144         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 145         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 146         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 147         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 148         case PIPE_CAP_SHAREABLE_SHADERS:
 149         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 150         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 151         case PIPE_CAP_TEXTURE_QUERY_LOD:
 152         case PIPE_CAP_TEXTURE_GATHER_SM5:
 153         case PIPE_CAP_TGSI_TXQS:
 154         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 155         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 156         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 157         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 158         case PIPE_CAP_INVALIDATE_BUFFER:
 159         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 160         case PIPE_CAP_QUERY_MEMORY_INFO:
 161         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 162         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 163         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 164         case PIPE_CAP_GENERATE_MIPMAP:
 165         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 166         case PIPE_CAP_STRING_MARKER:
 167         case PIPE_CAP_CLEAR_TEXTURE:
 168         case PIPE_CAP_CULL_DISTANCE:
 169         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 170         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 171         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 172         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 173         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 174         case PIPE_CAP_DOUBLES:
 175         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 176         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 177         case PIPE_CAP_BINDLESS_TEXTURE:
 178         case PIPE_CAP_QUERY_TIMESTAMP:
 179         case PIPE_CAP_QUERY_TIME_ELAPSED:
 180         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 181         case PIPE_CAP_QUERY_SO_OVERFLOW:
 182         case PIPE_CAP_MEMOBJ:
 183         case PIPE_CAP_LOAD_CONSTBUF:
 184         case PIPE_CAP_INT64:
 185         case PIPE_CAP_INT64_DIVMOD:
 186         case PIPE_CAP_TGSI_CLOCK:
 187         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 188         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 189         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 190         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 191                 return 1;
 192
 193         case PIPE_CAP_TGSI_VOTE:
 194                 return HAVE_LLVM >= 0x0400;
 195
 196         case PIPE_CAP_TGSI_BALLOT:
 197                 return HAVE_LLVM >= 0x0500;
 198
 199         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 200                 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 201
 202         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 203                 return (sscreen->info.drm_major == 2 &&
 204                         sscreen->info.drm_minor >= 43) ||
 205                        sscreen->info.drm_major == 3;
 206
 207         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 208                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 209                 return sscreen->info.chip_class < CIK ||
 210                        (sscreen->info.drm_major == 2 &&
 211                         sscreen->info.drm_minor >= 35) ||
 212                        sscreen->info.drm_major == 3;
 213
 214         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 215                 return R600_MAP_BUFFER_ALIGNMENT;
 216
 217         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 218         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 219         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 220         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 221         case PIPE_CAP_MAX_VERTEX_STREAMS:
 222         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 223                 return 4;
 224
 225         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 226                 if (si_have_tgsi_compute(sscreen))
 227                         return 450;
 228                 return 420;
 229
 230         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 231                 return MIN2(sscreen->info.max_alloc_size, INT_MAX);
 232
 233         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 234         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 235         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 236                 /* SI doesn't support unaligned loads.
 237                  * CIK needs DRM 2.50.0 on radeon. */
 238                 return sscreen->info.chip_class == SI ||
 239                        (sscreen->info.drm_major == 2 &&
 240                         sscreen->info.drm_minor < 50);
 241
 242         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 243                 /* TODO: GFX9 hangs. */
 244                 if (sscreen->info.chip_class >= GFX9)
 245                         return 0;
 246                 /* Disable on SI due to VM faults in CP DMA. Enable once these
 247                  * faults are mitigated in software.
 248                  */
 249                 if (sscreen->info.chip_class >= CIK &&
 250                     sscreen->info.drm_major == 3 &&
 251                     sscreen->info.drm_minor >= 13)
 252                         return RADEON_SPARSE_PAGE_SIZE;
 253                 return 0;
 254
 255         /* Unsupported features. */
 256         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 257         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 258         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 259         case PIPE_CAP_USER_VERTEX_BUFFERS:
 260         case PIPE_CAP_FAKE_SW_MSAA:
 261         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 262         case PIPE_CAP_VERTEXID_NOBASE:
 263         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 264         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 265         case PIPE_CAP_TGSI_FS_FBFETCH:
 266         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 267         case PIPE_CAP_UMA:
 268         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 269         case PIPE_CAP_POST_DEPTH_COVERAGE:
 270         case PIPE_CAP_TILE_RASTER_ORDER:
 271         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 272         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 273                 return 0;
 274
 275         case PIPE_CAP_FENCE_SIGNAL:
 276                 return sscreen->info.has_syncobj;
 277
 278         case PIPE_CAP_NATIVE_FENCE_FD:
 279                 return sscreen->info.has_fence_to_handle;
 280
 281         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 282                 return si_have_tgsi_compute(sscreen);
 283
 284         case PIPE_CAP_DRAW_PARAMETERS:
 285         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 286         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 287                 return sscreen->has_draw_indirect_multi;
 288
 289         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 290                 return 30;
 291
 292         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 293                 return sscreen->info.chip_class <= VI ?
 294                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 295
 296         /* Stream output. */
 297         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 298         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 299                 return 32*4;
 300
 301         /* Geometry shader output. */
 302         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 303                 return 1024;
 304         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 305                 return 4095;
 306
 307         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 308                 return 2048;
 309
 310         /* Texturing. */
 311         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 312         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 313                 return 15; /* 16384 */
 314         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 315                 /* textures support 8192, but layered rendering supports 2048 */
 316                 return 12;
 317         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 318                 /* textures support 8192, but layered rendering supports 2048 */
 319                 return 2048;
 320
 321         /* Viewports and render targets. */
 322         case PIPE_CAP_MAX_VIEWPORTS:
 323                 return SI_MAX_VIEWPORTS;
 324         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 325         case PIPE_CAP_MAX_RENDER_TARGETS:
 326                 return 8;
 327
 328         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 329         case PIPE_CAP_MIN_TEXEL_OFFSET:
 330                 return -32;
 331
 332         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 333         case PIPE_CAP_MAX_TEXEL_OFFSET:
 334                 return 31;
 335
 336         case PIPE_CAP_ENDIANNESS:
 337                 return PIPE_ENDIAN_LITTLE;
 338
 339         case PIPE_CAP_VENDOR_ID:
 340                 return ATI_VENDOR_ID;
 341         case PIPE_CAP_DEVICE_ID:
 342                 return sscreen->info.pci_id;
 343         case PIPE_CAP_VIDEO_MEMORY:
 344                 return sscreen->info.vram_size >> 20;
 345         case PIPE_CAP_PCI_GROUP:
 346                 return sscreen->info.pci_domain;
 347         case PIPE_CAP_PCI_BUS:
 348                 return sscreen->info.pci_bus;
 349         case PIPE_CAP_PCI_DEVICE:
 350                 return sscreen->info.pci_dev;
 351         case PIPE_CAP_PCI_FUNCTION:
 352                 return sscreen->info.pci_func;
 353         }
 354         return 0;
 355 }
 356
 357 static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
 358 {
 359         switch (param) {
 360         case PIPE_CAPF_MAX_LINE_WIDTH:
 361         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 362         case PIPE_CAPF_MAX_POINT_WIDTH:
 363         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 364                 return 8192.0f;
 365         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 366                 return 16.0f;
 367         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 368                 return 16.0f;
 369         case PIPE_CAPF_GUARD_BAND_LEFT:
 370         case PIPE_CAPF_GUARD_BAND_TOP:
 371         case PIPE_CAPF_GUARD_BAND_RIGHT:
 372         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 373                 return 0.0f;
 374         }
 375         return 0.0f;
 376 }
 377
 378 static int si_get_shader_param(struct pipe_screen* pscreen,
 379                                enum pipe_shader_type shader,
 380                                enum pipe_shader_cap param)
 381 {
 382         struct si_screen *sscreen = (struct si_screen *)pscreen;
 383
 384         switch(shader)
 385         {
 386         case PIPE_SHADER_FRAGMENT:
 387         case PIPE_SHADER_VERTEX:
 388         case PIPE_SHADER_GEOMETRY:
 389         case PIPE_SHADER_TESS_CTRL:
 390         case PIPE_SHADER_TESS_EVAL:
 391                 break;
 392         case PIPE_SHADER_COMPUTE:
 393                 switch (param) {
 394                 case PIPE_SHADER_CAP_PREFERRED_IR:
 395                         return PIPE_SHADER_IR_NATIVE;
 396
 397                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 398                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 399
 400                         if (si_have_tgsi_compute(sscreen))
 401                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 402
 403                         return ir;
 404                 }
 405
 406                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 407                         uint64_t max_const_buffer_size;
 408                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 409                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 410                                 &max_const_buffer_size);
 411                         return MIN2(max_const_buffer_size, INT_MAX);
 412                 }
 413                 default:
 414                         /* If compute shaders don't require a special value
 415                          * for this cap, we can return the same value we
 416                          * do for other shader types. */
 417                         break;
 418                 }
 419                 break;
 420         default:
 421                 return 0;
 422         }
 423
 424         switch (param) {
 425         /* Shader limits. */
 426         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 427         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 428         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 429         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 430         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 431                 return 16384;
 432         case PIPE_SHADER_CAP_MAX_INPUTS:
 433                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 434         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 435                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 436         case PIPE_SHADER_CAP_MAX_TEMPS:
 437                 return 256; /* Max native temporaries. */
 438         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 439                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 440         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 441                 return SI_NUM_CONST_BUFFERS;
 442         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 443         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 444                 return SI_NUM_SAMPLERS;
 445         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 446                 return SI_NUM_SHADER_BUFFERS;
 447         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 448                 return SI_NUM_IMAGES;
 449         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 450                 return 32;
 451         case PIPE_SHADER_CAP_PREFERRED_IR:
 452                 if (sscreen->debug_flags & DBG(NIR))
 453                         return PIPE_SHADER_IR_NIR;
 454                 return PIPE_SHADER_IR_TGSI;
 455         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 456                 return 4;
 457
 458         /* Supported boolean features. */
 459         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 460         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 461         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 462         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 463         case PIPE_SHADER_CAP_INTEGERS:
 464         case PIPE_SHADER_CAP_INT64_ATOMICS:
 465         case PIPE_SHADER_CAP_FP16:
 466         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 467         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 468         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 469         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 470         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 471         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 472                 return 1;
 473
 474         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 475                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 476                 return shader != PIPE_SHADER_GEOMETRY &&
 477                        (sscreen->llvm_has_working_vgpr_indexing ||
 478                         /* TCS and TES load inputs directly from LDS or
 479                          * offchip memory, so indirect indexing is trivial. */
 480                         shader == PIPE_SHADER_TESS_CTRL ||
 481                         shader == PIPE_SHADER_TESS_EVAL);
 482
 483         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 484                 return sscreen->llvm_has_working_vgpr_indexing ||
 485                        /* TCS stores outputs directly to memory. */
 486                        shader == PIPE_SHADER_TESS_CTRL;
 487
 488         /* Unsupported boolean features. */
 489         case PIPE_SHADER_CAP_SUBROUTINES:
 490         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 491         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 492         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 493                 return 0;
 494         }
 495         return 0;
 496 }
 497
 498 static const struct nir_shader_compiler_options nir_options = {
 499         .vertex_id_zero_based = true,
 500         .lower_scmp = true,
 501         .lower_flrp32 = true,
 502         .lower_flrp64 = true,
 503         .lower_fsat = true,
 504         .lower_fdiv = true,
 505         .lower_sub = true,
 506         .lower_ffma = true,
 507         .lower_pack_snorm_2x16 = true,
 508         .lower_pack_snorm_4x8 = true,
 509         .lower_pack_unorm_2x16 = true,
 510         .lower_pack_unorm_4x8 = true,
 511         .lower_unpack_snorm_2x16 = true,
 512         .lower_unpack_snorm_4x8 = true,
 513         .lower_unpack_unorm_2x16 = true,
 514         .lower_unpack_unorm_4x8 = true,
 515         .lower_extract_byte = true,
 516         .lower_extract_word = true,
 517         .max_unroll_iterations = 32,
 518         .native_integers = true,
 519 };
 520
 521 static const void *
 522 si_get_compiler_options(struct pipe_screen *screen,
 523                         enum pipe_shader_ir ir,
 524                         enum pipe_shader_type shader)
 525 {
 526         assert(ir == PIPE_SHADER_IR_NIR);
 527         return &nir_options;
 528 }
 529
 530 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 531 {
 532         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 533 }
 534
 535 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 536 {
 537         struct si_screen *sscreen = (struct si_screen *)pscreen;
 538
 539         ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
 540 }
 541
 542 static const char* si_get_name(struct pipe_screen *pscreen)
 543 {
 544         struct si_screen *sscreen = (struct si_screen*)pscreen;
 545
 546         return sscreen->renderer_string;
 547 }
 548
 549 static int si_get_video_param_no_decode(struct pipe_screen *screen,
 550                                         enum pipe_video_profile profile,
 551                                         enum pipe_video_entrypoint entrypoint,
 552                                         enum pipe_video_cap param)
 553 {
 554         switch (param) {
 555         case PIPE_VIDEO_CAP_SUPPORTED:
 556                 return vl_profile_supported(screen, profile, entrypoint);
 557         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 558                 return 1;
 559         case PIPE_VIDEO_CAP_MAX_WIDTH:
 560         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 561                 return vl_video_buffer_max_size(screen);
 562         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 563                 return PIPE_FORMAT_NV12;
 564         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 565                 return false;
 566         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 567                 return false;
 568         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 569                 return true;
 570         case PIPE_VIDEO_CAP_MAX_LEVEL:
 571                 return vl_level_supported(screen, profile);
 572         default:
 573                 return 0;
 574         }
 575 }
 576
 577 static int si_get_video_param(struct pipe_screen *screen,
 578                               enum pipe_video_profile profile,
 579                               enum pipe_video_entrypoint entrypoint,
 580                               enum pipe_video_cap param)
 581 {
 582         struct si_screen *sscreen = (struct si_screen *)screen;
 583         enum pipe_video_format codec = u_reduce_video_profile(profile);
 584
 585         if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 586                 switch (param) {
 587                 case PIPE_VIDEO_CAP_SUPPORTED:
 588                         return codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 589                                 (si_vce_is_fw_version_supported(sscreen) ||
 590                                 sscreen->info.family == CHIP_RAVEN);
 591                 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 592                         return 1;
 593                 case PIPE_VIDEO_CAP_MAX_WIDTH:
 594                         return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 595                 case PIPE_VIDEO_CAP_MAX_HEIGHT:
 596                         return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
 597                 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 598                         return PIPE_FORMAT_NV12;
 599                 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 600                         return false;
 601                 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 602                         return false;
 603                 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 604                         return true;
 605                 case PIPE_VIDEO_CAP_STACKED_FRAMES:
 606                         return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
 607                 default:
 608                         return 0;
 609                 }
 610         }
 611
 612         switch (param) {
 613         case PIPE_VIDEO_CAP_SUPPORTED:
 614                 switch (codec) {
 615                 case PIPE_VIDEO_FORMAT_MPEG12:
 616                         return profile != PIPE_VIDEO_PROFILE_MPEG1;
 617                 case PIPE_VIDEO_FORMAT_MPEG4:
 618                         return 1;
 619                 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 620                         if ((sscreen->info.family == CHIP_POLARIS10 ||
 621                              sscreen->info.family == CHIP_POLARIS11) &&
 622                             sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
 623                                 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 624                                 return false;
 625                         }
 626                         return true;
 627                 case PIPE_VIDEO_FORMAT_VC1:
 628                         return true;
 629                 case PIPE_VIDEO_FORMAT_HEVC:
 630                         /* Carrizo only supports HEVC Main */
 631                         if (sscreen->info.family >= CHIP_STONEY)
 632                                 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 633                                         profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 634                         else if (sscreen->info.family >= CHIP_CARRIZO)
 635                                 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 636                         return false;
 637                 case PIPE_VIDEO_FORMAT_JPEG:
 638                         if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
 639                                 return false;
 640                         if (!(sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 19)) {
 641                                 RVID_ERR("No MJPEG support for the kernel version\n");
 642                                 return false;
 643                         }
 644                         return true;
 645                 default:
 646                         return false;
 647                 }
 648         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 649                 return 1;
 650         case PIPE_VIDEO_CAP_MAX_WIDTH:
 651                 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 652         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 653                 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
 654         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 655                 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 656                         return PIPE_FORMAT_P016;
 657                 else
 658                         return PIPE_FORMAT_NV12;
 659
 660         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 661         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 662                 enum pipe_video_format format = u_reduce_video_profile(profile);
 663
 664                 if (format == PIPE_VIDEO_FORMAT_HEVC)
 665                         return false; //The firmware doesn't support interlaced HEVC.
 666                 else if (format == PIPE_VIDEO_FORMAT_JPEG)
 667                         return false;
 668                 return true;
 669         }
 670         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 671                 return true;
 672         case PIPE_VIDEO_CAP_MAX_LEVEL:
 673                 switch (profile) {
 674                 case PIPE_VIDEO_PROFILE_MPEG1:
 675                         return 0;
 676                 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 677                 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 678                         return 3;
 679                 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 680                         return 3;
 681                 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 682                         return 5;
 683                 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 684                         return 1;
 685                 case PIPE_VIDEO_PROFILE_VC1_MAIN:
 686                         return 2;
 687                 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 688                         return 4;
 689                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 690                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 691                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 692                         return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
 693                 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 694                 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 695                         return 186;
 696                 default:
 697                         return 0;
 698                 }
 699         default:
 700                 return 0;
 701         }
 702 }
 703
 704 static boolean si_vid_is_format_supported(struct pipe_screen *screen,
 705                                           enum pipe_format format,
 706                                           enum pipe_video_profile profile,
 707                                           enum pipe_video_entrypoint entrypoint)
 708 {
 709         /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
 710         if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 711                 return (format == PIPE_FORMAT_NV12) ||
 712                         (format == PIPE_FORMAT_P016);
 713
 714         /* we can only handle this one with UVD */
 715         if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 716                 return format == PIPE_FORMAT_NV12;
 717
 718         return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 719 }
 720
 721 static unsigned get_max_threads_per_block(struct si_screen *screen,
 722                                           enum pipe_shader_ir ir_type)
 723 {
 724         if (ir_type != PIPE_SHADER_IR_TGSI)
 725                 return 256;
 726
 727         /* Only 16 waves per thread-group on gfx9. */
 728         if (screen->info.chip_class >= GFX9)
 729                 return 1024;
 730
 731         /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
 732          * round number.
 733          */
 734         return 2048;
 735 }
 736
 737 static int si_get_compute_param(struct pipe_screen *screen,
 738                                 enum pipe_shader_ir ir_type,
 739                                 enum pipe_compute_cap param,
 740                                 void *ret)
 741 {
 742         struct si_screen *sscreen = (struct si_screen *)screen;
 743
 744         //TODO: select these params by asic
 745         switch (param) {
 746         case PIPE_COMPUTE_CAP_IR_TARGET: {
 747                 const char *gpu;
 748                 const char *triple;
 749
 750                 if (HAVE_LLVM < 0x0400)
 751                         triple = "amdgcn--";
 752                 else
 753                         triple = "amdgcn-mesa-mesa3d";
 754
 755                 gpu = ac_get_llvm_processor_name(sscreen->info.family);
 756                 if (ret) {
 757                         sprintf(ret, "%s-%s", gpu, triple);
 758                 }
 759                 /* +2 for dash and terminating NIL byte */
 760                 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 761         }
 762         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 763                 if (ret) {
 764                         uint64_t *grid_dimension = ret;
 765                         grid_dimension[0] = 3;
 766                 }
 767                 return 1 * sizeof(uint64_t);
 768
 769         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 770                 if (ret) {
 771                         uint64_t *grid_size = ret;
 772                         grid_size[0] = 65535;
 773                         grid_size[1] = 65535;
 774                         grid_size[2] = 65535;
 775                 }
 776                 return 3 * sizeof(uint64_t) ;
 777
 778         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 779                 if (ret) {
 780                         uint64_t *block_size = ret;
 781                         unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 782                         block_size[0] = threads_per_block;
 783                         block_size[1] = threads_per_block;
 784                         block_size[2] = threads_per_block;
 785                 }
 786                 return 3 * sizeof(uint64_t);
 787
 788         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 789                 if (ret) {
 790                         uint64_t *max_threads_per_block = ret;
 791                         *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 792                 }
 793                 return sizeof(uint64_t);
 794         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 795                 if (ret) {
 796                         uint32_t *address_bits = ret;
 797                         address_bits[0] = 64;
 798                 }
 799                 return 1 * sizeof(uint32_t);
 800
 801         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 802                 if (ret) {
 803                         uint64_t *max_global_size = ret;
 804                         uint64_t max_mem_alloc_size;
 805
 806                         si_get_compute_param(screen, ir_type,
 807                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 808                                 &max_mem_alloc_size);
 809
 810                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 811                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 812                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 813                          * make sure we never report more than
 814                          * 4 * MAX_MEM_ALLOC_SIZE.
 815                          */
 816                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 817                                                 MAX2(sscreen->info.gart_size,
 818                                                      sscreen->info.vram_size));
 819                 }
 820                 return sizeof(uint64_t);
 821
 822         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 823                 if (ret) {
 824                         uint64_t *max_local_size = ret;
 825                         /* Value reported by the closed source driver. */
 826                         *max_local_size = 32768;
 827                 }
 828                 return sizeof(uint64_t);
 829
 830         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 831                 if (ret) {
 832                         uint64_t *max_input_size = ret;
 833                         /* Value reported by the closed source driver. */
 834                         *max_input_size = 1024;
 835                 }
 836                 return sizeof(uint64_t);
 837
 838         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 839                 if (ret) {
 840                         uint64_t *max_mem_alloc_size = ret;
 841
 842                         *max_mem_alloc_size = sscreen->info.max_alloc_size;
 843                 }
 844                 return sizeof(uint64_t);
 845
 846         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 847                 if (ret) {
 848                         uint32_t *max_clock_frequency = ret;
 849                         *max_clock_frequency = sscreen->info.max_shader_clock;
 850                 }
 851                 return sizeof(uint32_t);
 852
 853         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 854                 if (ret) {
 855                         uint32_t *max_compute_units = ret;
 856                         *max_compute_units = sscreen->info.num_good_compute_units;
 857                 }
 858                 return sizeof(uint32_t);
 859
 860         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 861                 if (ret) {
 862                         uint32_t *images_supported = ret;
 863                         *images_supported = 0;
 864                 }
 865                 return sizeof(uint32_t);
 866         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 867                 break; /* unused */
 868         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 869                 if (ret) {
 870                         uint32_t *subgroup_size = ret;
 871                         *subgroup_size = 64;
 872                 }
 873                 return sizeof(uint32_t);
 874         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 875                 if (ret) {
 876                         uint64_t *max_variable_threads_per_block = ret;
 877                         if (ir_type == PIPE_SHADER_IR_TGSI)
 878                                 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
 879                         else
 880                                 *max_variable_threads_per_block = 0;
 881                 }
 882                 return sizeof(uint64_t);
 883         }
 884
 885         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 886         return 0;
 887 }
 888
 889 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 890 {
 891         struct si_screen *sscreen = (struct si_screen*)screen;
 892
 893         return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
 894                         sscreen->info.clock_crystal_freq;
 895 }
 896
 897 static void si_query_memory_info(struct pipe_screen *screen,
 898                                  struct pipe_memory_info *info)
 899 {
 900         struct si_screen *sscreen = (struct si_screen*)screen;
 901         struct radeon_winsys *ws = sscreen->ws;
 902         unsigned vram_usage, gtt_usage;
 903
 904         info->total_device_memory = sscreen->info.vram_size / 1024;
 905         info->total_staging_memory = sscreen->info.gart_size / 1024;
 906
 907         /* The real TTM memory usage is somewhat random, because:
 908          *
 909          * 1) TTM delays freeing memory, because it can only free it after
 910          *    fences expire.
 911          *
 912          * 2) The memory usage can be really low if big VRAM evictions are
 913          *    taking place, but the real usage is well above the size of VRAM.
 914          *
 915          * Instead, return statistics of this process.
 916          */
 917         vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
 918         gtt_usage =  ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
 919
 920         info->avail_device_memory =
 921                 vram_usage <= info->total_device_memory ?
 922                                 info->total_device_memory - vram_usage : 0;
 923         info->avail_staging_memory =
 924                 gtt_usage <= info->total_staging_memory ?
 925                                 info->total_staging_memory - gtt_usage : 0;
 926
 927         info->device_memory_evicted =
 928                 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 929
 930         if (sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 4)
 931                 info->nr_device_memory_evictions =
 932                         ws->query_value(ws, RADEON_NUM_EVICTIONS);
 933         else
 934                 /* Just return the number of evicted 64KB pages. */
 935                 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 936 }
 937
 938 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 939 {
 940         struct si_screen *sscreen = (struct si_screen*)pscreen;
 941
 942         return sscreen->disk_shader_cache;
 943 }
 944
 945 static void si_init_renderer_string(struct si_screen *sscreen)
 946 {
 947         struct radeon_winsys *ws = sscreen->ws;
 948         char family_name[32] = {}, llvm_string[32] = {}, kernel_version[128] = {};
 949         struct utsname uname_data;
 950
 951         const char *chip_name = si_get_marketing_name(ws);
 952
 953         if (chip_name)
 954                 snprintf(family_name, sizeof(family_name), "%s / ",
 955                          si_get_family_name(sscreen) + 4);
 956         else
 957                 chip_name = si_get_family_name(sscreen);
 958
 959         if (uname(&uname_data) == 0)
 960                 snprintf(kernel_version, sizeof(kernel_version),
 961                          " / %s", uname_data.release);
 962
 963         if (HAVE_LLVM > 0) {
 964                 snprintf(llvm_string, sizeof(llvm_string),
 965                          ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
 966                          HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
 967         }
 968
 969         snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
 970                  "%s (%sDRM %i.%i.%i%s%s)",
 971                  chip_name, family_name, sscreen->info.drm_major,
 972                  sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
 973                  kernel_version, llvm_string);
 974 }
 975
 976 void si_init_screen_get_functions(struct si_screen *sscreen)
 977 {
 978         sscreen->b.get_name = si_get_name;
 979         sscreen->b.get_vendor = si_get_vendor;
 980         sscreen->b.get_device_vendor = si_get_device_vendor;
 981         sscreen->b.get_param = si_get_param;
 982         sscreen->b.get_paramf = si_get_paramf;
 983         sscreen->b.get_compute_param = si_get_compute_param;
 984         sscreen->b.get_timestamp = si_get_timestamp;
 985         sscreen->b.get_shader_param = si_get_shader_param;
 986         sscreen->b.get_compiler_options = si_get_compiler_options;
 987         sscreen->b.get_device_uuid = si_get_device_uuid;
 988         sscreen->b.get_driver_uuid = si_get_driver_uuid;
 989         sscreen->b.query_memory_info = si_query_memory_info;
 990         sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
 991
 992         if (sscreen->info.has_hw_decode) {
 993                 sscreen->b.get_video_param = si_get_video_param;
 994                 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
 995         } else {
 996                 sscreen->b.get_video_param = si_get_video_param_no_decode;
 997                 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
 998         }
 999
1000         si_init_renderer_string(sscreen);
1001 }