src/gallium/drivers/radeonsi/si_get.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "si_pipe.h"
  26 #include "radeon/radeon_video.h"
  27 #include "radeon/radeon_vce.h"
  28 #include "radeon/radeon_uvd_enc.h"
  29 #include "ac_llvm_util.h"
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32 #include "util/u_video.h"
  33 #include "compiler/nir/nir.h"
  34
  35 #include <sys/utsname.h>
  36
  37 static const char *si_get_vendor(struct pipe_screen *pscreen)
  38 {
  39         /* Don't change this. Games such as Alien Isolation are broken if this
  40          * returns "Advanced Micro Devices, Inc."
  41          */
  42         return "X.Org";
  43 }
  44
  45 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
  46 {
  47         return "AMD";
  48 }
  49
  50 static const char *si_get_marketing_name(struct radeon_winsys *ws)
  51 {
  52         if (!ws->get_chip_name)
  53                 return NULL;
  54         return ws->get_chip_name(ws);
  55 }
  56
  57 const char *si_get_family_name(const struct si_screen *sscreen)
  58 {
  59         switch (sscreen->info.family) {
  60         case CHIP_TAHITI: return "AMD TAHITI";
  61         case CHIP_PITCAIRN: return "AMD PITCAIRN";
  62         case CHIP_VERDE: return "AMD CAPE VERDE";
  63         case CHIP_OLAND: return "AMD OLAND";
  64         case CHIP_HAINAN: return "AMD HAINAN";
  65         case CHIP_BONAIRE: return "AMD BONAIRE";
  66         case CHIP_KAVERI: return "AMD KAVERI";
  67         case CHIP_KABINI: return "AMD KABINI";
  68         case CHIP_HAWAII: return "AMD HAWAII";
  69         case CHIP_MULLINS: return "AMD MULLINS";
  70         case CHIP_TONGA: return "AMD TONGA";
  71         case CHIP_ICELAND: return "AMD ICELAND";
  72         case CHIP_CARRIZO: return "AMD CARRIZO";
  73         case CHIP_FIJI: return "AMD FIJI";
  74         case CHIP_STONEY: return "AMD STONEY";
  75         case CHIP_POLARIS10: return "AMD POLARIS10";
  76         case CHIP_POLARIS11: return "AMD POLARIS11";
  77         case CHIP_POLARIS12: return "AMD POLARIS12";
  78         case CHIP_VEGAM: return "AMD VEGAM";
  79         case CHIP_VEGA10: return "AMD VEGA10";
  80         case CHIP_VEGA12: return "AMD VEGA12";
  81         case CHIP_RAVEN: return "AMD RAVEN";
  82         default: return "AMD unknown";
  83         }
  84 }
  85
  86 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  87 {
  88         struct si_screen *sscreen = (struct si_screen *)pscreen;
  89
  90         switch (param) {
  91         /* Supported features (boolean caps). */
  92         case PIPE_CAP_ACCELERATED:
  93         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  94         case PIPE_CAP_ANISOTROPIC_FILTER:
  95         case PIPE_CAP_POINT_SPRITE:
  96         case PIPE_CAP_OCCLUSION_QUERY:
  97         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  98         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  99         case PIPE_CAP_TEXTURE_SWIZZLE:
 100         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 101         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 102         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 103         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 104         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 105         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 106         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 107         case PIPE_CAP_SM3:
 108         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 109         case PIPE_CAP_PRIMITIVE_RESTART:
 110         case PIPE_CAP_CONDITIONAL_RENDER:
 111         case PIPE_CAP_TEXTURE_BARRIER:
 112         case PIPE_CAP_INDEP_BLEND_ENABLE:
 113         case PIPE_CAP_INDEP_BLEND_FUNC:
 114         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 115         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 116         case PIPE_CAP_START_INSTANCE:
 117         case PIPE_CAP_NPOT_TEXTURES:
 118         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 119         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 120         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 121         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 122         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 123         case PIPE_CAP_TGSI_INSTANCEID:
 124         case PIPE_CAP_COMPUTE:
 125         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 126         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 127         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 128         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 129         case PIPE_CAP_CUBE_MAP_ARRAY:
 130         case PIPE_CAP_SAMPLE_SHADING:
 131         case PIPE_CAP_DRAW_INDIRECT:
 132         case PIPE_CAP_CLIP_HALFZ:
 133         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 134         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 135         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 136         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 137         case PIPE_CAP_TGSI_TEXCOORD:
 138         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 139         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 140         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 141         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 142         case PIPE_CAP_SHAREABLE_SHADERS:
 143         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 144         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 145         case PIPE_CAP_TEXTURE_QUERY_LOD:
 146         case PIPE_CAP_TEXTURE_GATHER_SM5:
 147         case PIPE_CAP_TGSI_TXQS:
 148         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 149         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 150         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 151         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 152         case PIPE_CAP_INVALIDATE_BUFFER:
 153         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 154         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 155         case PIPE_CAP_QUERY_MEMORY_INFO:
 156         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 157         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 158         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 159         case PIPE_CAP_GENERATE_MIPMAP:
 160         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 161         case PIPE_CAP_STRING_MARKER:
 162         case PIPE_CAP_CLEAR_TEXTURE:
 163         case PIPE_CAP_CULL_DISTANCE:
 164         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 165         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 166         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 167         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 168         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 169         case PIPE_CAP_DOUBLES:
 170         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 171         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 172         case PIPE_CAP_BINDLESS_TEXTURE:
 173         case PIPE_CAP_QUERY_TIMESTAMP:
 174         case PIPE_CAP_QUERY_TIME_ELAPSED:
 175         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 176         case PIPE_CAP_QUERY_SO_OVERFLOW:
 177         case PIPE_CAP_MEMOBJ:
 178         case PIPE_CAP_LOAD_CONSTBUF:
 179         case PIPE_CAP_INT64:
 180         case PIPE_CAP_INT64_DIVMOD:
 181         case PIPE_CAP_TGSI_CLOCK:
 182         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 183         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 184         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 185         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 186         case PIPE_CAP_TGSI_BALLOT:
 187         case PIPE_CAP_TGSI_VOTE:
 188         case PIPE_CAP_TGSI_FS_FBFETCH:
 189                 return 1;
 190
 191         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 192                 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 193
 194         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 195                 return sscreen->info.has_gpu_reset_status_query ||
 196                        sscreen->info.has_gpu_reset_counter_query;
 197
 198         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 199                 return sscreen->info.has_2d_tiling;
 200
 201         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 202                 return SI_MAP_BUFFER_ALIGNMENT;
 203
 204         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 205         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 206         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 207         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 208         case PIPE_CAP_MAX_VERTEX_STREAMS:
 209         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 210                 return 4;
 211
 212         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 213                 if (sscreen->info.has_indirect_compute_dispatch)
 214                         return 450;
 215                 return 420;
 216
 217         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 218                 return 330;
 219
 220         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 221                 return MIN2(sscreen->info.max_alloc_size, INT_MAX);
 222
 223         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 224         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 225         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 226                 return !sscreen->info.has_unaligned_shader_loads;
 227
 228         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 229                 return sscreen->info.has_sparse_vm_mappings ?
 230                                 RADEON_SPARSE_PAGE_SIZE : 0;
 231
 232         case PIPE_CAP_PACKED_UNIFORMS:
 233                 if (sscreen->debug_flags & DBG(NIR))
 234                         return 1;
 235                 return 0;
 236
 237         /* Unsupported features. */
 238         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 239         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 240         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 241         case PIPE_CAP_USER_VERTEX_BUFFERS:
 242         case PIPE_CAP_FAKE_SW_MSAA:
 243         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 244         case PIPE_CAP_VERTEXID_NOBASE:
 245         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 246         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 247         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 248         case PIPE_CAP_UMA:
 249         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 250         case PIPE_CAP_POST_DEPTH_COVERAGE:
 251         case PIPE_CAP_TILE_RASTER_ORDER:
 252         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 253         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 254         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 255         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 256         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 257         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 258         case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 259         case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 260         case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 261                 return 0;
 262
 263         case PIPE_CAP_FENCE_SIGNAL:
 264                 return sscreen->info.has_syncobj;
 265
 266         case PIPE_CAP_CONSTBUF0_FLAGS:
 267                 return SI_RESOURCE_FLAG_32BIT;
 268
 269         case PIPE_CAP_NATIVE_FENCE_FD:
 270                 return sscreen->info.has_fence_to_handle;
 271
 272         case PIPE_CAP_DRAW_PARAMETERS:
 273         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 274         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 275                 return sscreen->has_draw_indirect_multi;
 276
 277         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 278                 return 30;
 279
 280         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 281                 return sscreen->info.chip_class <= VI ?
 282                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 283
 284         /* Stream output. */
 285         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 286         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 287                 return 32*4;
 288
 289         /* Geometry shader output. */
 290         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 291                 return 1024;
 292         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 293                 return 4095;
 294
 295         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 296                 return 2048;
 297
 298         /* Texturing. */
 299         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 300         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 301                 return 15; /* 16384 */
 302         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 303                 /* textures support 8192, but layered rendering supports 2048 */
 304                 return 12;
 305         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 306                 /* textures support 8192, but layered rendering supports 2048 */
 307                 return 2048;
 308
 309         /* Viewports and render targets. */
 310         case PIPE_CAP_MAX_VIEWPORTS:
 311                 return SI_MAX_VIEWPORTS;
 312         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 313         case PIPE_CAP_MAX_RENDER_TARGETS:
 314                 return 8;
 315
 316         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 317         case PIPE_CAP_MIN_TEXEL_OFFSET:
 318                 return -32;
 319
 320         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 321         case PIPE_CAP_MAX_TEXEL_OFFSET:
 322                 return 31;
 323
 324         case PIPE_CAP_ENDIANNESS:
 325                 return PIPE_ENDIAN_LITTLE;
 326
 327         case PIPE_CAP_VENDOR_ID:
 328                 return ATI_VENDOR_ID;
 329         case PIPE_CAP_DEVICE_ID:
 330                 return sscreen->info.pci_id;
 331         case PIPE_CAP_VIDEO_MEMORY:
 332                 return sscreen->info.vram_size >> 20;
 333         case PIPE_CAP_PCI_GROUP:
 334                 return sscreen->info.pci_domain;
 335         case PIPE_CAP_PCI_BUS:
 336                 return sscreen->info.pci_bus;
 337         case PIPE_CAP_PCI_DEVICE:
 338                 return sscreen->info.pci_dev;
 339         case PIPE_CAP_PCI_FUNCTION:
 340                 return sscreen->info.pci_func;
 341         }
 342         return 0;
 343 }
 344
 345 static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
 346 {
 347         switch (param) {
 348         case PIPE_CAPF_MAX_LINE_WIDTH:
 349         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 350         case PIPE_CAPF_MAX_POINT_WIDTH:
 351         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 352                 return 8192.0f;
 353         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 354                 return 16.0f;
 355         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 356                 return 16.0f;
 357         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 358         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 359         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 360                 return 0.0f;
 361         }
 362         return 0.0f;
 363 }
 364
 365 static int si_get_shader_param(struct pipe_screen* pscreen,
 366                                enum pipe_shader_type shader,
 367                                enum pipe_shader_cap param)
 368 {
 369         struct si_screen *sscreen = (struct si_screen *)pscreen;
 370
 371         switch(shader)
 372         {
 373         case PIPE_SHADER_FRAGMENT:
 374         case PIPE_SHADER_VERTEX:
 375         case PIPE_SHADER_GEOMETRY:
 376         case PIPE_SHADER_TESS_CTRL:
 377         case PIPE_SHADER_TESS_EVAL:
 378                 break;
 379         case PIPE_SHADER_COMPUTE:
 380                 switch (param) {
 381                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 382                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 383
 384                         if (sscreen->info.has_indirect_compute_dispatch)
 385                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 386
 387                         return ir;
 388                 }
 389
 390                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 391                         uint64_t max_const_buffer_size;
 392                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 393                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 394                                 &max_const_buffer_size);
 395                         return MIN2(max_const_buffer_size, INT_MAX);
 396                 }
 397                 default:
 398                         /* If compute shaders don't require a special value
 399                          * for this cap, we can return the same value we
 400                          * do for other shader types. */
 401                         break;
 402                 }
 403                 break;
 404         default:
 405                 return 0;
 406         }
 407
 408         switch (param) {
 409         /* Shader limits. */
 410         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 411         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 412         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 413         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 414         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 415                 return 16384;
 416         case PIPE_SHADER_CAP_MAX_INPUTS:
 417                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 418         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 419                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 420         case PIPE_SHADER_CAP_MAX_TEMPS:
 421                 return 256; /* Max native temporaries. */
 422         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 423                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 424         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 425                 return SI_NUM_CONST_BUFFERS;
 426         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 427         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 428                 return SI_NUM_SAMPLERS;
 429         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 430                 return SI_NUM_SHADER_BUFFERS;
 431         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 432                 return SI_NUM_IMAGES;
 433         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 434                 if (sscreen->debug_flags & DBG(NIR))
 435                         return 0;
 436                 return 32;
 437         case PIPE_SHADER_CAP_PREFERRED_IR:
 438                 if (sscreen->debug_flags & DBG(NIR))
 439                         return PIPE_SHADER_IR_NIR;
 440                 return PIPE_SHADER_IR_TGSI;
 441         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 442                 return 4;
 443
 444         /* Supported boolean features. */
 445         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 446         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 447         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 448         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 449         case PIPE_SHADER_CAP_INTEGERS:
 450         case PIPE_SHADER_CAP_INT64_ATOMICS:
 451         case PIPE_SHADER_CAP_FP16:
 452         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 453         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 454         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 455         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 456         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 457         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 458                 return 1;
 459
 460         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 461                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 462                 if (shader == PIPE_SHADER_GEOMETRY)
 463                         return 0;
 464
 465                 if (shader == PIPE_SHADER_VERTEX &&
 466                     !sscreen->llvm_has_working_vgpr_indexing)
 467                         return 0;
 468
 469                 /* Doing indirect indexing on GFX9 with LLVM 6.0 hangs.
 470                  * This means we don't support INTERP instructions with
 471                  * indirect indexing on inputs.
 472                  */
 473                 if (shader == PIPE_SHADER_FRAGMENT &&
 474                     !sscreen->llvm_has_working_vgpr_indexing &&
 475                     HAVE_LLVM < 0x0700)
 476                         return 0;
 477
 478                 /* TCS and TES load inputs directly from LDS or offchip
 479                  * memory, so indirect indexing is always supported.
 480                  * PS has to support indirect indexing, because we can't
 481                  * lower that to TEMPs for INTERP instructions.
 482                  */
 483                 return 1;
 484
 485         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 486                 return sscreen->llvm_has_working_vgpr_indexing ||
 487                        /* TCS stores outputs directly to memory. */
 488                        shader == PIPE_SHADER_TESS_CTRL;
 489
 490         /* Unsupported boolean features. */
 491         case PIPE_SHADER_CAP_SUBROUTINES:
 492         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 493         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 494         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 495                 return 0;
 496         }
 497         return 0;
 498 }
 499
 500 static const struct nir_shader_compiler_options nir_options = {
 501         .lower_scmp = true,
 502         .lower_flrp32 = true,
 503         .lower_flrp64 = true,
 504         .lower_fpow = true,
 505         .lower_fsat = true,
 506         .lower_fdiv = true,
 507         .lower_sub = true,
 508         .lower_ffma = true,
 509         .lower_pack_snorm_2x16 = true,
 510         .lower_pack_snorm_4x8 = true,
 511         .lower_pack_unorm_2x16 = true,
 512         .lower_pack_unorm_4x8 = true,
 513         .lower_unpack_snorm_2x16 = true,
 514         .lower_unpack_snorm_4x8 = true,
 515         .lower_unpack_unorm_2x16 = true,
 516         .lower_unpack_unorm_4x8 = true,
 517         .lower_extract_byte = true,
 518         .lower_extract_word = true,
 519         .max_unroll_iterations = 32,
 520         .native_integers = true,
 521 };
 522
 523 static const void *
 524 si_get_compiler_options(struct pipe_screen *screen,
 525                         enum pipe_shader_ir ir,
 526                         enum pipe_shader_type shader)
 527 {
 528         assert(ir == PIPE_SHADER_IR_NIR);
 529         return &nir_options;
 530 }
 531
 532 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 533 {
 534         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 535 }
 536
 537 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 538 {
 539         struct si_screen *sscreen = (struct si_screen *)pscreen;
 540
 541         ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
 542 }
 543
 544 static const char* si_get_name(struct pipe_screen *pscreen)
 545 {
 546         struct si_screen *sscreen = (struct si_screen*)pscreen;
 547
 548         return sscreen->renderer_string;
 549 }
 550
 551 static int si_get_video_param_no_decode(struct pipe_screen *screen,
 552                                         enum pipe_video_profile profile,
 553                                         enum pipe_video_entrypoint entrypoint,
 554                                         enum pipe_video_cap param)
 555 {
 556         switch (param) {
 557         case PIPE_VIDEO_CAP_SUPPORTED:
 558                 return vl_profile_supported(screen, profile, entrypoint);
 559         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 560                 return 1;
 561         case PIPE_VIDEO_CAP_MAX_WIDTH:
 562         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 563                 return vl_video_buffer_max_size(screen);
 564         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 565                 return PIPE_FORMAT_NV12;
 566         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 567                 return false;
 568         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 569                 return false;
 570         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 571                 return true;
 572         case PIPE_VIDEO_CAP_MAX_LEVEL:
 573                 return vl_level_supported(screen, profile);
 574         default:
 575                 return 0;
 576         }
 577 }
 578
 579 static int si_get_video_param(struct pipe_screen *screen,
 580                               enum pipe_video_profile profile,
 581                               enum pipe_video_entrypoint entrypoint,
 582                               enum pipe_video_cap param)
 583 {
 584         struct si_screen *sscreen = (struct si_screen *)screen;
 585         enum pipe_video_format codec = u_reduce_video_profile(profile);
 586
 587         if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 588                 switch (param) {
 589                 case PIPE_VIDEO_CAP_SUPPORTED:
 590                         return (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 591                                 (si_vce_is_fw_version_supported(sscreen) ||
 592                                 sscreen->info.family == CHIP_RAVEN)) ||
 593                                 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
 594                                 (sscreen->info.family == CHIP_RAVEN ||
 595                                 si_radeon_uvd_enc_supported(sscreen)));
 596                 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 597                         return 1;
 598                 case PIPE_VIDEO_CAP_MAX_WIDTH:
 599                         return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 600                 case PIPE_VIDEO_CAP_MAX_HEIGHT:
 601                         return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
 602                 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 603                         return PIPE_FORMAT_NV12;
 604                 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 605                         return false;
 606                 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 607                         return false;
 608                 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 609                         return true;
 610                 case PIPE_VIDEO_CAP_STACKED_FRAMES:
 611                         return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
 612                 default:
 613                         return 0;
 614                 }
 615         }
 616
 617         switch (param) {
 618         case PIPE_VIDEO_CAP_SUPPORTED:
 619                 switch (codec) {
 620                 case PIPE_VIDEO_FORMAT_MPEG12:
 621                         return profile != PIPE_VIDEO_PROFILE_MPEG1;
 622                 case PIPE_VIDEO_FORMAT_MPEG4:
 623                         return 1;
 624                 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 625                         if ((sscreen->info.family == CHIP_POLARIS10 ||
 626                              sscreen->info.family == CHIP_POLARIS11) &&
 627                             sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
 628                                 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 629                                 return false;
 630                         }
 631                         return true;
 632                 case PIPE_VIDEO_FORMAT_VC1:
 633                         return true;
 634                 case PIPE_VIDEO_FORMAT_HEVC:
 635                         /* Carrizo only supports HEVC Main */
 636                         if (sscreen->info.family >= CHIP_STONEY)
 637                                 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 638                                         profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 639                         else if (sscreen->info.family >= CHIP_CARRIZO)
 640                                 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 641                         return false;
 642                 case PIPE_VIDEO_FORMAT_JPEG:
 643                         if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
 644                                 return false;
 645                         if (!(sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 19)) {
 646                                 RVID_ERR("No MJPEG support for the kernel version\n");
 647                                 return false;
 648                         }
 649                         return true;
 650                 case PIPE_VIDEO_FORMAT_VP9:
 651                         if (sscreen->info.family < CHIP_RAVEN)
 652                                 return false;
 653                         return true;
 654                 default:
 655                         return false;
 656                 }
 657         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 658                 return 1;
 659         case PIPE_VIDEO_CAP_MAX_WIDTH:
 660                 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 661         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 662                 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
 663         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 664                 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 ||
 665                     profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 666                         return PIPE_FORMAT_P016;
 667                 else
 668                         return PIPE_FORMAT_NV12;
 669
 670         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 671         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 672                 enum pipe_video_format format = u_reduce_video_profile(profile);
 673
 674                 if (format == PIPE_VIDEO_FORMAT_HEVC)
 675                         return false; //The firmware doesn't support interlaced HEVC.
 676                 else if (format == PIPE_VIDEO_FORMAT_JPEG)
 677                         return false;
 678                 else if (format == PIPE_VIDEO_FORMAT_VP9)
 679                         return false;
 680                 return true;
 681         }
 682         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 683                 return true;
 684         case PIPE_VIDEO_CAP_MAX_LEVEL:
 685                 switch (profile) {
 686                 case PIPE_VIDEO_PROFILE_MPEG1:
 687                         return 0;
 688                 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 689                 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 690                         return 3;
 691                 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 692                         return 3;
 693                 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 694                         return 5;
 695                 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 696                         return 1;
 697                 case PIPE_VIDEO_PROFILE_VC1_MAIN:
 698                         return 2;
 699                 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 700                         return 4;
 701                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 702                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 703                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 704                         return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
 705                 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 706                 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 707                         return 186;
 708                 default:
 709                         return 0;
 710                 }
 711         default:
 712                 return 0;
 713         }
 714 }
 715
 716 static boolean si_vid_is_format_supported(struct pipe_screen *screen,
 717                                           enum pipe_format format,
 718                                           enum pipe_video_profile profile,
 719                                           enum pipe_video_entrypoint entrypoint)
 720 {
 721         /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
 722         if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 723                 return (format == PIPE_FORMAT_NV12) ||
 724                         (format == PIPE_FORMAT_P016);
 725
 726         /* we can only handle this one with UVD */
 727         if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 728                 return format == PIPE_FORMAT_NV12;
 729
 730         return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 731 }
 732
 733 static unsigned get_max_threads_per_block(struct si_screen *screen,
 734                                           enum pipe_shader_ir ir_type)
 735 {
 736         if (ir_type == PIPE_SHADER_IR_NATIVE)
 737                 return 256;
 738
 739         /* Only 16 waves per thread-group on gfx9. */
 740         if (screen->info.chip_class >= GFX9)
 741                 return 1024;
 742
 743         /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
 744          * round number.
 745          */
 746         return 2048;
 747 }
 748
 749 static int si_get_compute_param(struct pipe_screen *screen,
 750                                 enum pipe_shader_ir ir_type,
 751                                 enum pipe_compute_cap param,
 752                                 void *ret)
 753 {
 754         struct si_screen *sscreen = (struct si_screen *)screen;
 755
 756         //TODO: select these params by asic
 757         switch (param) {
 758         case PIPE_COMPUTE_CAP_IR_TARGET: {
 759                 const char *gpu, *triple;
 760
 761                 triple = "amdgcn-mesa-mesa3d";
 762                 gpu = ac_get_llvm_processor_name(sscreen->info.family);
 763                 if (ret) {
 764                         sprintf(ret, "%s-%s", gpu, triple);
 765                 }
 766                 /* +2 for dash and terminating NIL byte */
 767                 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 768         }
 769         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 770                 if (ret) {
 771                         uint64_t *grid_dimension = ret;
 772                         grid_dimension[0] = 3;
 773                 }
 774                 return 1 * sizeof(uint64_t);
 775
 776         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 777                 if (ret) {
 778                         uint64_t *grid_size = ret;
 779                         grid_size[0] = 65535;
 780                         grid_size[1] = 65535;
 781                         grid_size[2] = 65535;
 782                 }
 783                 return 3 * sizeof(uint64_t) ;
 784
 785         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 786                 if (ret) {
 787                         uint64_t *block_size = ret;
 788                         unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 789                         block_size[0] = threads_per_block;
 790                         block_size[1] = threads_per_block;
 791                         block_size[2] = threads_per_block;
 792                 }
 793                 return 3 * sizeof(uint64_t);
 794
 795         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 796                 if (ret) {
 797                         uint64_t *max_threads_per_block = ret;
 798                         *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 799                 }
 800                 return sizeof(uint64_t);
 801         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 802                 if (ret) {
 803                         uint32_t *address_bits = ret;
 804                         address_bits[0] = 64;
 805                 }
 806                 return 1 * sizeof(uint32_t);
 807
 808         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 809                 if (ret) {
 810                         uint64_t *max_global_size = ret;
 811                         uint64_t max_mem_alloc_size;
 812
 813                         si_get_compute_param(screen, ir_type,
 814                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 815                                 &max_mem_alloc_size);
 816
 817                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 818                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 819                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 820                          * make sure we never report more than
 821                          * 4 * MAX_MEM_ALLOC_SIZE.
 822                          */
 823                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 824                                                 MAX2(sscreen->info.gart_size,
 825                                                      sscreen->info.vram_size));
 826                 }
 827                 return sizeof(uint64_t);
 828
 829         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 830                 if (ret) {
 831                         uint64_t *max_local_size = ret;
 832                         /* Value reported by the closed source driver. */
 833                         *max_local_size = 32768;
 834                 }
 835                 return sizeof(uint64_t);
 836
 837         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 838                 if (ret) {
 839                         uint64_t *max_input_size = ret;
 840                         /* Value reported by the closed source driver. */
 841                         *max_input_size = 1024;
 842                 }
 843                 return sizeof(uint64_t);
 844
 845         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 846                 if (ret) {
 847                         uint64_t *max_mem_alloc_size = ret;
 848
 849                         *max_mem_alloc_size = sscreen->info.max_alloc_size;
 850                 }
 851                 return sizeof(uint64_t);
 852
 853         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 854                 if (ret) {
 855                         uint32_t *max_clock_frequency = ret;
 856                         *max_clock_frequency = sscreen->info.max_shader_clock;
 857                 }
 858                 return sizeof(uint32_t);
 859
 860         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 861                 if (ret) {
 862                         uint32_t *max_compute_units = ret;
 863                         *max_compute_units = sscreen->info.num_good_compute_units;
 864                 }
 865                 return sizeof(uint32_t);
 866
 867         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 868                 if (ret) {
 869                         uint32_t *images_supported = ret;
 870                         *images_supported = 0;
 871                 }
 872                 return sizeof(uint32_t);
 873         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 874                 break; /* unused */
 875         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 876                 if (ret) {
 877                         uint32_t *subgroup_size = ret;
 878                         *subgroup_size = 64;
 879                 }
 880                 return sizeof(uint32_t);
 881         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 882                 if (ret) {
 883                         uint64_t *max_variable_threads_per_block = ret;
 884                         if (ir_type == PIPE_SHADER_IR_NATIVE)
 885                                 *max_variable_threads_per_block = 0;
 886                         else
 887                                 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
 888                 }
 889                 return sizeof(uint64_t);
 890         }
 891
 892         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 893         return 0;
 894 }
 895
 896 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 897 {
 898         struct si_screen *sscreen = (struct si_screen*)screen;
 899
 900         return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
 901                         sscreen->info.clock_crystal_freq;
 902 }
 903
 904 static void si_query_memory_info(struct pipe_screen *screen,
 905                                  struct pipe_memory_info *info)
 906 {
 907         struct si_screen *sscreen = (struct si_screen*)screen;
 908         struct radeon_winsys *ws = sscreen->ws;
 909         unsigned vram_usage, gtt_usage;
 910
 911         info->total_device_memory = sscreen->info.vram_size / 1024;
 912         info->total_staging_memory = sscreen->info.gart_size / 1024;
 913
 914         /* The real TTM memory usage is somewhat random, because:
 915          *
 916          * 1) TTM delays freeing memory, because it can only free it after
 917          *    fences expire.
 918          *
 919          * 2) The memory usage can be really low if big VRAM evictions are
 920          *    taking place, but the real usage is well above the size of VRAM.
 921          *
 922          * Instead, return statistics of this process.
 923          */
 924         vram_usage = ws->query_value(ws, RADEON_VRAM_USAGE) / 1024;
 925         gtt_usage =  ws->query_value(ws, RADEON_GTT_USAGE) / 1024;
 926
 927         info->avail_device_memory =
 928                 vram_usage <= info->total_device_memory ?
 929                                 info->total_device_memory - vram_usage : 0;
 930         info->avail_staging_memory =
 931                 gtt_usage <= info->total_staging_memory ?
 932                                 info->total_staging_memory - gtt_usage : 0;
 933
 934         info->device_memory_evicted =
 935                 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 936
 937         if (sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 4)
 938                 info->nr_device_memory_evictions =
 939                         ws->query_value(ws, RADEON_NUM_EVICTIONS);
 940         else
 941                 /* Just return the number of evicted 64KB pages. */
 942                 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 943 }
 944
 945 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 946 {
 947         struct si_screen *sscreen = (struct si_screen*)pscreen;
 948
 949         return sscreen->disk_shader_cache;
 950 }
 951
 952 static void si_init_renderer_string(struct si_screen *sscreen)
 953 {
 954         struct radeon_winsys *ws = sscreen->ws;
 955         char family_name[32] = {}, kernel_version[128] = {};
 956         struct utsname uname_data;
 957
 958         const char *chip_name = si_get_marketing_name(ws);
 959
 960         if (chip_name)
 961                 snprintf(family_name, sizeof(family_name), "%s, ",
 962                          si_get_family_name(sscreen) + 4);
 963         else
 964                 chip_name = si_get_family_name(sscreen);
 965
 966         if (uname(&uname_data) == 0)
 967                 snprintf(kernel_version, sizeof(kernel_version),
 968                          ", %s", uname_data.release);
 969
 970         snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
 971                  "%s (%sDRM %i.%i.%i%s, LLVM %i.%i.%i)",
 972                  chip_name, family_name, sscreen->info.drm_major,
 973                  sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
 974                  kernel_version,
 975                  (HAVE_LLVM >> 8) & 0xff,
 976                  HAVE_LLVM & 0xff,
 977                  MESA_LLVM_VERSION_PATCH);
 978 }
 979
 980 void si_init_screen_get_functions(struct si_screen *sscreen)
 981 {
 982         sscreen->b.get_name = si_get_name;
 983         sscreen->b.get_vendor = si_get_vendor;
 984         sscreen->b.get_device_vendor = si_get_device_vendor;
 985         sscreen->b.get_param = si_get_param;
 986         sscreen->b.get_paramf = si_get_paramf;
 987         sscreen->b.get_compute_param = si_get_compute_param;
 988         sscreen->b.get_timestamp = si_get_timestamp;
 989         sscreen->b.get_shader_param = si_get_shader_param;
 990         sscreen->b.get_compiler_options = si_get_compiler_options;
 991         sscreen->b.get_device_uuid = si_get_device_uuid;
 992         sscreen->b.get_driver_uuid = si_get_driver_uuid;
 993         sscreen->b.query_memory_info = si_query_memory_info;
 994         sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
 995
 996         if (sscreen->info.has_hw_decode) {
 997                 sscreen->b.get_video_param = si_get_video_param;
 998                 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
 999         } else {
1000                 sscreen->b.get_video_param = si_get_video_param_no_decode;
1001                 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1002         }
1003
1004         si_init_renderer_string(sscreen);
1005 }