src/gallium/drivers/radeonsi/si_get.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "si_pipe.h"
  26 #include "radeon/radeon_video.h"
  27 #include "radeon/radeon_vce.h"
  28 #include "radeon/radeon_uvd_enc.h"
  29 #include "ac_llvm_util.h"
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32 #include "util/u_screen.h"
  33 #include "util/u_video.h"
  34 #include "compiler/nir/nir.h"
  35
  36 #include <sys/utsname.h>
  37
  38 static const char *si_get_vendor(struct pipe_screen *pscreen)
  39 {
  40         /* Don't change this. Games such as Alien Isolation are broken if this
  41          * returns "Advanced Micro Devices, Inc."
  42          */
  43         return "X.Org";
  44 }
  45
  46 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
  47 {
  48         return "AMD";
  49 }
  50
  51 static const char *si_get_marketing_name(struct radeon_winsys *ws)
  52 {
  53         if (!ws->get_chip_name)
  54                 return NULL;
  55         return ws->get_chip_name(ws);
  56 }
  57
  58 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  59 {
  60         struct si_screen *sscreen = (struct si_screen *)pscreen;
  61
  62         switch (param) {
  63         /* Supported features (boolean caps). */
  64         case PIPE_CAP_ACCELERATED:
  65         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  66         case PIPE_CAP_ANISOTROPIC_FILTER:
  67         case PIPE_CAP_POINT_SPRITE:
  68         case PIPE_CAP_OCCLUSION_QUERY:
  69         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  70         case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
  71         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  72         case PIPE_CAP_TEXTURE_SWIZZLE:
  73         case PIPE_CAP_DEPTH_CLIP_DISABLE:
  74         case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
  75         case PIPE_CAP_SHADER_STENCIL_EXPORT:
  76         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
  77         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  78         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  79         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  80         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  81         case PIPE_CAP_SM3:
  82         case PIPE_CAP_SEAMLESS_CUBE_MAP:
  83         case PIPE_CAP_PRIMITIVE_RESTART:
  84         case PIPE_CAP_CONDITIONAL_RENDER:
  85         case PIPE_CAP_TEXTURE_BARRIER:
  86         case PIPE_CAP_INDEP_BLEND_ENABLE:
  87         case PIPE_CAP_INDEP_BLEND_FUNC:
  88         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  89         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
  90         case PIPE_CAP_START_INSTANCE:
  91         case PIPE_CAP_NPOT_TEXTURES:
  92         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  93         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
  94         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
  95         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
  96         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  97         case PIPE_CAP_TGSI_INSTANCEID:
  98         case PIPE_CAP_COMPUTE:
  99         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 100         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 101         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 102         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 103         case PIPE_CAP_CUBE_MAP_ARRAY:
 104         case PIPE_CAP_SAMPLE_SHADING:
 105         case PIPE_CAP_DRAW_INDIRECT:
 106         case PIPE_CAP_CLIP_HALFZ:
 107         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 108         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 109         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 110         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 111         case PIPE_CAP_TGSI_TEXCOORD:
 112         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 113         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 114         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 115         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 116         case PIPE_CAP_SHAREABLE_SHADERS:
 117         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 118         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 119         case PIPE_CAP_TEXTURE_QUERY_LOD:
 120         case PIPE_CAP_TEXTURE_GATHER_SM5:
 121         case PIPE_CAP_TGSI_TXQS:
 122         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 123         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 124         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 125         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 126         case PIPE_CAP_INVALIDATE_BUFFER:
 127         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 128         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 129         case PIPE_CAP_QUERY_MEMORY_INFO:
 130         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 131         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 132         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 133         case PIPE_CAP_GENERATE_MIPMAP:
 134         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 135         case PIPE_CAP_STRING_MARKER:
 136         case PIPE_CAP_CLEAR_TEXTURE:
 137         case PIPE_CAP_CULL_DISTANCE:
 138         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 139         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 140         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 141         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 142         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 143         case PIPE_CAP_DOUBLES:
 144         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 145         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 146         case PIPE_CAP_BINDLESS_TEXTURE:
 147         case PIPE_CAP_QUERY_TIMESTAMP:
 148         case PIPE_CAP_QUERY_TIME_ELAPSED:
 149         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 150         case PIPE_CAP_QUERY_SO_OVERFLOW:
 151         case PIPE_CAP_MEMOBJ:
 152         case PIPE_CAP_LOAD_CONSTBUF:
 153         case PIPE_CAP_INT64:
 154         case PIPE_CAP_INT64_DIVMOD:
 155         case PIPE_CAP_TGSI_CLOCK:
 156         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 157         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 158         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 159         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 160         case PIPE_CAP_TGSI_BALLOT:
 161         case PIPE_CAP_TGSI_VOTE:
 162         case PIPE_CAP_TGSI_FS_FBFETCH:
 163                 return 1;
 164
 165         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 166                 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 167
 168         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 169                 return sscreen->info.has_gpu_reset_status_query ||
 170                        sscreen->info.has_gpu_reset_counter_query;
 171
 172         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 173                 return sscreen->info.has_2d_tiling;
 174
 175         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 176                 return SI_MAP_BUFFER_ALIGNMENT;
 177
 178         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 179         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 180         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 181         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 182         case PIPE_CAP_MAX_VERTEX_STREAMS:
 183         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 184         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 185                 return 4;
 186
 187         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 188         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 189                 if (sscreen->info.has_indirect_compute_dispatch)
 190                                 return 450;
 191                 return 420;
 192
 193         case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 194                 /* Optimal number for good TexSubImage performance on Polaris10. */
 195                 return 64 * 1024 * 1024;
 196
 197         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 198         case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 199                 return MIN2(sscreen->info.max_alloc_size, INT_MAX);
 200
 201         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 202         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 203         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 204                 return !sscreen->info.has_unaligned_shader_loads;
 205
 206         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 207                 return sscreen->info.has_sparse_vm_mappings ?
 208                                 RADEON_SPARSE_PAGE_SIZE : 0;
 209
 210         case PIPE_CAP_PACKED_UNIFORMS:
 211                 if (sscreen->debug_flags & DBG(NIR))
 212                         return 1;
 213                 return 0;
 214
 215         /* Unsupported features. */
 216         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 217         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 218         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 219         case PIPE_CAP_USER_VERTEX_BUFFERS:
 220         case PIPE_CAP_FAKE_SW_MSAA:
 221         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 222         case PIPE_CAP_VERTEXID_NOBASE:
 223         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 224         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 225         case PIPE_CAP_UMA:
 226         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 227         case PIPE_CAP_POST_DEPTH_COVERAGE:
 228         case PIPE_CAP_TILE_RASTER_ORDER:
 229         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 230         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 231         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 232         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 233         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 234         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 235         case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 236         case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 237         case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 238                 return 0;
 239
 240         case PIPE_CAP_FENCE_SIGNAL:
 241                 return sscreen->info.has_syncobj;
 242
 243         case PIPE_CAP_CONSTBUF0_FLAGS:
 244                 return SI_RESOURCE_FLAG_32BIT;
 245
 246         case PIPE_CAP_NATIVE_FENCE_FD:
 247                 return sscreen->info.has_fence_to_handle;
 248
 249         case PIPE_CAP_DRAW_PARAMETERS:
 250         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 251         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 252                 return sscreen->has_draw_indirect_multi;
 253
 254         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 255                 return 30;
 256
 257         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 258                 return sscreen->info.chip_class <= VI ?
 259                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 260
 261         /* Stream output. */
 262         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 263         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 264                 return 32*4;
 265
 266         /* Geometry shader output. */
 267         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 268                 return 1024;
 269         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 270                 return 4095;
 271         case PIPE_CAP_MAX_GS_INVOCATIONS:
 272                 /* The closed driver exposes 127, but 125 is the greatest
 273                  * number that works. */
 274                 return 125;
 275
 276         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 277                 return 2048;
 278
 279         /* Texturing. */
 280         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 281         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 282                 return 15; /* 16384 */
 283         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 284                 /* textures support 8192, but layered rendering supports 2048 */
 285                 return 12;
 286         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 287                 /* textures support 8192, but layered rendering supports 2048 */
 288                 return 2048;
 289
 290         /* Viewports and render targets. */
 291         case PIPE_CAP_MAX_VIEWPORTS:
 292                 return SI_MAX_VIEWPORTS;
 293         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 294         case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 295         case PIPE_CAP_MAX_RENDER_TARGETS:
 296                 return 8;
 297         case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 298                 return sscreen->info.has_eqaa_surface_allocator ? 2 : 0;
 299
 300         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 301         case PIPE_CAP_MIN_TEXEL_OFFSET:
 302                 return -32;
 303
 304         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 305         case PIPE_CAP_MAX_TEXEL_OFFSET:
 306                 return 31;
 307
 308         case PIPE_CAP_ENDIANNESS:
 309                 return PIPE_ENDIAN_LITTLE;
 310
 311         case PIPE_CAP_VENDOR_ID:
 312                 return ATI_VENDOR_ID;
 313         case PIPE_CAP_DEVICE_ID:
 314                 return sscreen->info.pci_id;
 315         case PIPE_CAP_VIDEO_MEMORY:
 316                 return sscreen->info.vram_size >> 20;
 317         case PIPE_CAP_PCI_GROUP:
 318                 return sscreen->info.pci_domain;
 319         case PIPE_CAP_PCI_BUS:
 320                 return sscreen->info.pci_bus;
 321         case PIPE_CAP_PCI_DEVICE:
 322                 return sscreen->info.pci_dev;
 323         case PIPE_CAP_PCI_FUNCTION:
 324                 return sscreen->info.pci_func;
 325
 326         default:
 327                 return u_pipe_screen_get_param_defaults(pscreen, param);
 328         }
 329 }
 330
 331 static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
 332 {
 333         switch (param) {
 334         case PIPE_CAPF_MAX_LINE_WIDTH:
 335         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 336                 /* This depends on the quant mode, though the precise interactions
 337                  * are unknown. */
 338                 return 2048;
 339         case PIPE_CAPF_MAX_POINT_WIDTH:
 340         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 341                 return SI_MAX_POINT_SIZE;
 342         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 343                 return 16.0f;
 344         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 345                 return 16.0f;
 346         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 347         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 348         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 349                 return 0.0f;
 350         }
 351         return 0.0f;
 352 }
 353
 354 static int si_get_shader_param(struct pipe_screen* pscreen,
 355                                enum pipe_shader_type shader,
 356                                enum pipe_shader_cap param)
 357 {
 358         struct si_screen *sscreen = (struct si_screen *)pscreen;
 359
 360         switch(shader)
 361         {
 362         case PIPE_SHADER_FRAGMENT:
 363         case PIPE_SHADER_VERTEX:
 364         case PIPE_SHADER_GEOMETRY:
 365         case PIPE_SHADER_TESS_CTRL:
 366         case PIPE_SHADER_TESS_EVAL:
 367                 break;
 368         case PIPE_SHADER_COMPUTE:
 369                 switch (param) {
 370                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 371                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 372
 373                         if (sscreen->info.has_indirect_compute_dispatch)
 374                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 375
 376                         return ir;
 377                 }
 378
 379                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 380                         uint64_t max_const_buffer_size;
 381                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 382                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 383                                 &max_const_buffer_size);
 384                         return MIN2(max_const_buffer_size, INT_MAX);
 385                 }
 386                 default:
 387                         /* If compute shaders don't require a special value
 388                          * for this cap, we can return the same value we
 389                          * do for other shader types. */
 390                         break;
 391                 }
 392                 break;
 393         default:
 394                 return 0;
 395         }
 396
 397         switch (param) {
 398         /* Shader limits. */
 399         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 400         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 401         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 402         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 403         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 404                 return 16384;
 405         case PIPE_SHADER_CAP_MAX_INPUTS:
 406                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 407         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 408                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 409         case PIPE_SHADER_CAP_MAX_TEMPS:
 410                 return 256; /* Max native temporaries. */
 411         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 412                 return MIN2(sscreen->info.max_alloc_size, INT_MAX - 3); /* aligned to 4 */
 413         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 414                 return SI_NUM_CONST_BUFFERS;
 415         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 416         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 417                 return SI_NUM_SAMPLERS;
 418         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 419                 return SI_NUM_SHADER_BUFFERS;
 420         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 421                 return SI_NUM_IMAGES;
 422         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 423                 if (sscreen->debug_flags & DBG(NIR))
 424                         return 0;
 425                 return 32;
 426         case PIPE_SHADER_CAP_PREFERRED_IR:
 427                 if (sscreen->debug_flags & DBG(NIR))
 428                         return PIPE_SHADER_IR_NIR;
 429                 return PIPE_SHADER_IR_TGSI;
 430         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 431                 return 4;
 432
 433         /* Supported boolean features. */
 434         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 435         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 436         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 437         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 438         case PIPE_SHADER_CAP_INTEGERS:
 439         case PIPE_SHADER_CAP_INT64_ATOMICS:
 440         case PIPE_SHADER_CAP_FP16:
 441         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 442         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 443         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 444         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 445         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 446         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 447                 return 1;
 448
 449         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 450                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 451                 if (shader == PIPE_SHADER_GEOMETRY)
 452                         return 0;
 453
 454                 if (shader == PIPE_SHADER_VERTEX &&
 455                     !sscreen->llvm_has_working_vgpr_indexing)
 456                         return 0;
 457
 458                 /* Doing indirect indexing on GFX9 with LLVM 6.0 hangs.
 459                  * This means we don't support INTERP instructions with
 460                  * indirect indexing on inputs.
 461                  */
 462                 if (shader == PIPE_SHADER_FRAGMENT &&
 463                     !sscreen->llvm_has_working_vgpr_indexing &&
 464                     HAVE_LLVM < 0x0700)
 465                         return 0;
 466
 467                 /* TCS and TES load inputs directly from LDS or offchip
 468                  * memory, so indirect indexing is always supported.
 469                  * PS has to support indirect indexing, because we can't
 470                  * lower that to TEMPs for INTERP instructions.
 471                  */
 472                 return 1;
 473
 474         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 475                 return sscreen->llvm_has_working_vgpr_indexing ||
 476                        /* TCS stores outputs directly to memory. */
 477                        shader == PIPE_SHADER_TESS_CTRL;
 478
 479         /* Unsupported boolean features. */
 480         case PIPE_SHADER_CAP_SUBROUTINES:
 481         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 482         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 483         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 484                 return 0;
 485         case PIPE_SHADER_CAP_SCALAR_ISA:
 486                 return 1;
 487         }
 488         return 0;
 489 }
 490
 491 static const struct nir_shader_compiler_options nir_options = {
 492         .lower_scmp = true,
 493         .lower_flrp32 = true,
 494         .lower_flrp64 = true,
 495         .lower_fpow = true,
 496         .lower_fsat = true,
 497         .lower_fdiv = true,
 498         .lower_sub = true,
 499         .lower_ffma = true,
 500         .lower_pack_snorm_2x16 = true,
 501         .lower_pack_snorm_4x8 = true,
 502         .lower_pack_unorm_2x16 = true,
 503         .lower_pack_unorm_4x8 = true,
 504         .lower_unpack_snorm_2x16 = true,
 505         .lower_unpack_snorm_4x8 = true,
 506         .lower_unpack_unorm_2x16 = true,
 507         .lower_unpack_unorm_4x8 = true,
 508         .lower_extract_byte = true,
 509         .lower_extract_word = true,
 510         .max_unroll_iterations = 32,
 511         .native_integers = true,
 512 };
 513
 514 static const void *
 515 si_get_compiler_options(struct pipe_screen *screen,
 516                         enum pipe_shader_ir ir,
 517                         enum pipe_shader_type shader)
 518 {
 519         assert(ir == PIPE_SHADER_IR_NIR);
 520         return &nir_options;
 521 }
 522
 523 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 524 {
 525         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 526 }
 527
 528 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 529 {
 530         struct si_screen *sscreen = (struct si_screen *)pscreen;
 531
 532         ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
 533 }
 534
 535 static const char* si_get_name(struct pipe_screen *pscreen)
 536 {
 537         struct si_screen *sscreen = (struct si_screen*)pscreen;
 538
 539         return sscreen->renderer_string;
 540 }
 541
 542 static int si_get_video_param_no_decode(struct pipe_screen *screen,
 543                                         enum pipe_video_profile profile,
 544                                         enum pipe_video_entrypoint entrypoint,
 545                                         enum pipe_video_cap param)
 546 {
 547         switch (param) {
 548         case PIPE_VIDEO_CAP_SUPPORTED:
 549                 return vl_profile_supported(screen, profile, entrypoint);
 550         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 551                 return 1;
 552         case PIPE_VIDEO_CAP_MAX_WIDTH:
 553         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 554                 return vl_video_buffer_max_size(screen);
 555         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 556                 return PIPE_FORMAT_NV12;
 557         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 558                 return false;
 559         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 560                 return false;
 561         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 562                 return true;
 563         case PIPE_VIDEO_CAP_MAX_LEVEL:
 564                 return vl_level_supported(screen, profile);
 565         default:
 566                 return 0;
 567         }
 568 }
 569
 570 static int si_get_video_param(struct pipe_screen *screen,
 571                               enum pipe_video_profile profile,
 572                               enum pipe_video_entrypoint entrypoint,
 573                               enum pipe_video_cap param)
 574 {
 575         struct si_screen *sscreen = (struct si_screen *)screen;
 576         enum pipe_video_format codec = u_reduce_video_profile(profile);
 577
 578         if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 579                 switch (param) {
 580                 case PIPE_VIDEO_CAP_SUPPORTED:
 581                         return (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 582                                 (si_vce_is_fw_version_supported(sscreen) ||
 583                                  sscreen->info.family == CHIP_RAVEN ||
 584                                  sscreen->info.family == CHIP_RAVEN2)) ||
 585                                 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
 586                                 (sscreen->info.family == CHIP_RAVEN ||
 587                                  sscreen->info.family == CHIP_RAVEN2 ||
 588                                  si_radeon_uvd_enc_supported(sscreen)));
 589                 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 590                         return 1;
 591                 case PIPE_VIDEO_CAP_MAX_WIDTH:
 592                         return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 593                 case PIPE_VIDEO_CAP_MAX_HEIGHT:
 594                         return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
 595                 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 596                         return PIPE_FORMAT_NV12;
 597                 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 598                         return false;
 599                 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 600                         return false;
 601                 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 602                         return true;
 603                 case PIPE_VIDEO_CAP_STACKED_FRAMES:
 604                         return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
 605                 default:
 606                         return 0;
 607                 }
 608         }
 609
 610         switch (param) {
 611         case PIPE_VIDEO_CAP_SUPPORTED:
 612                 switch (codec) {
 613                 case PIPE_VIDEO_FORMAT_MPEG12:
 614                         return profile != PIPE_VIDEO_PROFILE_MPEG1;
 615                 case PIPE_VIDEO_FORMAT_MPEG4:
 616                         return 1;
 617                 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 618                         if ((sscreen->info.family == CHIP_POLARIS10 ||
 619                              sscreen->info.family == CHIP_POLARIS11) &&
 620                             sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
 621                                 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 622                                 return false;
 623                         }
 624                         return true;
 625                 case PIPE_VIDEO_FORMAT_VC1:
 626                         return true;
 627                 case PIPE_VIDEO_FORMAT_HEVC:
 628                         /* Carrizo only supports HEVC Main */
 629                         if (sscreen->info.family >= CHIP_STONEY)
 630                                 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 631                                         profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 632                         else if (sscreen->info.family >= CHIP_CARRIZO)
 633                                 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 634                         return false;
 635                 case PIPE_VIDEO_FORMAT_JPEG:
 636                         if (sscreen->info.family == CHIP_RAVEN ||
 637                             sscreen->info.family == CHIP_RAVEN2)
 638                                 return true;
 639                         if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
 640                                 return false;
 641                         if (!(sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 19)) {
 642                                 RVID_ERR("No MJPEG support for the kernel version\n");
 643                                 return false;
 644                         }
 645                         return true;
 646                 case PIPE_VIDEO_FORMAT_VP9:
 647                         if (sscreen->info.family < CHIP_RAVEN)
 648                                 return false;
 649                         return true;
 650                 default:
 651                         return false;
 652                 }
 653         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 654                 return 1;
 655         case PIPE_VIDEO_CAP_MAX_WIDTH:
 656                 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 657         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 658                 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
 659         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 660                 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 ||
 661                     profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 662                         return PIPE_FORMAT_P016;
 663                 else
 664                         return PIPE_FORMAT_NV12;
 665
 666         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 667         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 668                 enum pipe_video_format format = u_reduce_video_profile(profile);
 669
 670                 if (format == PIPE_VIDEO_FORMAT_HEVC)
 671                         return false; //The firmware doesn't support interlaced HEVC.
 672                 else if (format == PIPE_VIDEO_FORMAT_JPEG)
 673                         return false;
 674                 else if (format == PIPE_VIDEO_FORMAT_VP9)
 675                         return false;
 676                 return true;
 677         }
 678         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 679                 return true;
 680         case PIPE_VIDEO_CAP_MAX_LEVEL:
 681                 switch (profile) {
 682                 case PIPE_VIDEO_PROFILE_MPEG1:
 683                         return 0;
 684                 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 685                 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 686                         return 3;
 687                 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 688                         return 3;
 689                 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 690                         return 5;
 691                 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 692                         return 1;
 693                 case PIPE_VIDEO_PROFILE_VC1_MAIN:
 694                         return 2;
 695                 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 696                         return 4;
 697                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 698                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 699                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 700                         return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
 701                 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 702                 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 703                         return 186;
 704                 default:
 705                         return 0;
 706                 }
 707         default:
 708                 return 0;
 709         }
 710 }
 711
 712 static boolean si_vid_is_format_supported(struct pipe_screen *screen,
 713                                           enum pipe_format format,
 714                                           enum pipe_video_profile profile,
 715                                           enum pipe_video_entrypoint entrypoint)
 716 {
 717         /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
 718         if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 719                 return (format == PIPE_FORMAT_NV12) ||
 720                         (format == PIPE_FORMAT_P016);
 721
 722         /* we can only handle this one with UVD */
 723         if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 724                 return format == PIPE_FORMAT_NV12;
 725
 726         return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 727 }
 728
 729 static unsigned get_max_threads_per_block(struct si_screen *screen,
 730                                           enum pipe_shader_ir ir_type)
 731 {
 732         if (ir_type == PIPE_SHADER_IR_NATIVE)
 733                 return 256;
 734
 735         /* Only 16 waves per thread-group on gfx9. */
 736         if (screen->info.chip_class >= GFX9)
 737                 return 1024;
 738
 739         /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
 740          * round number.
 741          */
 742         return 2048;
 743 }
 744
 745 static int si_get_compute_param(struct pipe_screen *screen,
 746                                 enum pipe_shader_ir ir_type,
 747                                 enum pipe_compute_cap param,
 748                                 void *ret)
 749 {
 750         struct si_screen *sscreen = (struct si_screen *)screen;
 751
 752         //TODO: select these params by asic
 753         switch (param) {
 754         case PIPE_COMPUTE_CAP_IR_TARGET: {
 755                 const char *gpu, *triple;
 756
 757                 triple = "amdgcn-mesa-mesa3d";
 758                 gpu = ac_get_llvm_processor_name(sscreen->info.family);
 759                 if (ret) {
 760                         sprintf(ret, "%s-%s", gpu, triple);
 761                 }
 762                 /* +2 for dash and terminating NIL byte */
 763                 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 764         }
 765         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 766                 if (ret) {
 767                         uint64_t *grid_dimension = ret;
 768                         grid_dimension[0] = 3;
 769                 }
 770                 return 1 * sizeof(uint64_t);
 771
 772         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 773                 if (ret) {
 774                         uint64_t *grid_size = ret;
 775                         grid_size[0] = 65535;
 776                         grid_size[1] = 65535;
 777                         grid_size[2] = 65535;
 778                 }
 779                 return 3 * sizeof(uint64_t) ;
 780
 781         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 782                 if (ret) {
 783                         uint64_t *block_size = ret;
 784                         unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 785                         block_size[0] = threads_per_block;
 786                         block_size[1] = threads_per_block;
 787                         block_size[2] = threads_per_block;
 788                 }
 789                 return 3 * sizeof(uint64_t);
 790
 791         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 792                 if (ret) {
 793                         uint64_t *max_threads_per_block = ret;
 794                         *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 795                 }
 796                 return sizeof(uint64_t);
 797         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 798                 if (ret) {
 799                         uint32_t *address_bits = ret;
 800                         address_bits[0] = 64;
 801                 }
 802                 return 1 * sizeof(uint32_t);
 803
 804         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 805                 if (ret) {
 806                         uint64_t *max_global_size = ret;
 807                         uint64_t max_mem_alloc_size;
 808
 809                         si_get_compute_param(screen, ir_type,
 810                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 811                                 &max_mem_alloc_size);
 812
 813                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 814                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 815                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 816                          * make sure we never report more than
 817                          * 4 * MAX_MEM_ALLOC_SIZE.
 818                          */
 819                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 820                                                 MAX2(sscreen->info.gart_size,
 821                                                      sscreen->info.vram_size));
 822                 }
 823                 return sizeof(uint64_t);
 824
 825         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 826                 if (ret) {
 827                         uint64_t *max_local_size = ret;
 828                         /* Value reported by the closed source driver. */
 829                         *max_local_size = 32768;
 830                 }
 831                 return sizeof(uint64_t);
 832
 833         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 834                 if (ret) {
 835                         uint64_t *max_input_size = ret;
 836                         /* Value reported by the closed source driver. */
 837                         *max_input_size = 1024;
 838                 }
 839                 return sizeof(uint64_t);
 840
 841         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 842                 if (ret) {
 843                         uint64_t *max_mem_alloc_size = ret;
 844
 845                         *max_mem_alloc_size = sscreen->info.max_alloc_size;
 846                 }
 847                 return sizeof(uint64_t);
 848
 849         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 850                 if (ret) {
 851                         uint32_t *max_clock_frequency = ret;
 852                         *max_clock_frequency = sscreen->info.max_shader_clock;
 853                 }
 854                 return sizeof(uint32_t);
 855
 856         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 857                 if (ret) {
 858                         uint32_t *max_compute_units = ret;
 859                         *max_compute_units = sscreen->info.num_good_compute_units;
 860                 }
 861                 return sizeof(uint32_t);
 862
 863         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 864                 if (ret) {
 865                         uint32_t *images_supported = ret;
 866                         *images_supported = 0;
 867                 }
 868                 return sizeof(uint32_t);
 869         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 870                 break; /* unused */
 871         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 872                 if (ret) {
 873                         uint32_t *subgroup_size = ret;
 874                         *subgroup_size = 64;
 875                 }
 876                 return sizeof(uint32_t);
 877         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 878                 if (ret) {
 879                         uint64_t *max_variable_threads_per_block = ret;
 880                         if (ir_type == PIPE_SHADER_IR_NATIVE)
 881                                 *max_variable_threads_per_block = 0;
 882                         else
 883                                 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
 884                 }
 885                 return sizeof(uint64_t);
 886         }
 887
 888         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 889         return 0;
 890 }
 891
 892 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 893 {
 894         struct si_screen *sscreen = (struct si_screen*)screen;
 895
 896         return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
 897                         sscreen->info.clock_crystal_freq;
 898 }
 899
 900 static void si_query_memory_info(struct pipe_screen *screen,
 901                                  struct pipe_memory_info *info)
 902 {
 903         struct si_screen *sscreen = (struct si_screen*)screen;
 904         struct radeon_winsys *ws = sscreen->ws;
 905         unsigned vram_usage, gtt_usage;
 906
 907         info->total_device_memory = sscreen->info.vram_size / 1024;
 908         info->total_staging_memory = sscreen->info.gart_size / 1024;
 909
 910         /* The real TTM memory usage is somewhat random, because:
 911          *
 912          * 1) TTM delays freeing memory, because it can only free it after
 913          *    fences expire.
 914          *
 915          * 2) The memory usage can be really low if big VRAM evictions are
 916          *    taking place, but the real usage is well above the size of VRAM.
 917          *
 918          * Instead, return statistics of this process.
 919          */
 920         vram_usage = ws->query_value(ws, RADEON_VRAM_USAGE) / 1024;
 921         gtt_usage =  ws->query_value(ws, RADEON_GTT_USAGE) / 1024;
 922
 923         info->avail_device_memory =
 924                 vram_usage <= info->total_device_memory ?
 925                                 info->total_device_memory - vram_usage : 0;
 926         info->avail_staging_memory =
 927                 gtt_usage <= info->total_staging_memory ?
 928                                 info->total_staging_memory - gtt_usage : 0;
 929
 930         info->device_memory_evicted =
 931                 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 932
 933         if (sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 4)
 934                 info->nr_device_memory_evictions =
 935                         ws->query_value(ws, RADEON_NUM_EVICTIONS);
 936         else
 937                 /* Just return the number of evicted 64KB pages. */
 938                 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 939 }
 940
 941 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 942 {
 943         struct si_screen *sscreen = (struct si_screen*)pscreen;
 944
 945         return sscreen->disk_shader_cache;
 946 }
 947
 948 static void si_init_renderer_string(struct si_screen *sscreen)
 949 {
 950         struct radeon_winsys *ws = sscreen->ws;
 951         char first_name[256], second_name[32] = {}, kernel_version[128] = {};
 952         struct utsname uname_data;
 953
 954         const char *marketing_name = si_get_marketing_name(ws);
 955
 956         if (marketing_name) {
 957                 snprintf(first_name, sizeof(first_name), "%s", marketing_name);
 958                 snprintf(second_name, sizeof(second_name), "%s, ",
 959                          sscreen->info.name);
 960         } else {
 961                 snprintf(first_name, sizeof(first_name), "AMD %s",
 962                          sscreen->info.name);
 963         }
 964
 965         if (uname(&uname_data) == 0)
 966                 snprintf(kernel_version, sizeof(kernel_version),
 967                          ", %s", uname_data.release);
 968
 969         snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
 970                  "%s (%sDRM %i.%i.%i%s, LLVM %i.%i.%i)",
 971                  first_name, second_name, sscreen->info.drm_major,
 972                  sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
 973                  kernel_version,
 974                  (HAVE_LLVM >> 8) & 0xff,
 975                  HAVE_LLVM & 0xff,
 976                  MESA_LLVM_VERSION_PATCH);
 977 }
 978
 979 void si_init_screen_get_functions(struct si_screen *sscreen)
 980 {
 981         sscreen->b.get_name = si_get_name;
 982         sscreen->b.get_vendor = si_get_vendor;
 983         sscreen->b.get_device_vendor = si_get_device_vendor;
 984         sscreen->b.get_param = si_get_param;
 985         sscreen->b.get_paramf = si_get_paramf;
 986         sscreen->b.get_compute_param = si_get_compute_param;
 987         sscreen->b.get_timestamp = si_get_timestamp;
 988         sscreen->b.get_shader_param = si_get_shader_param;
 989         sscreen->b.get_compiler_options = si_get_compiler_options;
 990         sscreen->b.get_device_uuid = si_get_device_uuid;
 991         sscreen->b.get_driver_uuid = si_get_driver_uuid;
 992         sscreen->b.query_memory_info = si_query_memory_info;
 993         sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
 994
 995         if (sscreen->info.has_hw_decode) {
 996                 sscreen->b.get_video_param = si_get_video_param;
 997                 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
 998         } else {
 999                 sscreen->b.get_video_param = si_get_video_param_no_decode;
1000                 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1001         }
1002
1003         si_init_renderer_string(sscreen);
1004 }