src/gallium/drivers/radeonsi/si_get.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "radeon/radeon_video.h"
  26 #include "radeon/radeon_vce.h"
  27 #include "radeon/radeon_uvd_enc.h"
  28 #include "ac_llvm_util.h"
  29 #include "vl/vl_decoder.h"
  30 #include "vl/vl_video_buffer.h"
  31 #include "util/u_video.h"
  32 #include "compiler/nir/nir.h"
  33
  34 #include <sys/utsname.h>
  35
  36 static const char *si_get_vendor(struct pipe_screen *pscreen)
  37 {
  38         /* Don't change this. Games such as Alien Isolation are broken if this
  39          * returns "Advanced Micro Devices, Inc."
  40          */
  41         return "X.Org";
  42 }
  43
  44 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
  45 {
  46         return "AMD";
  47 }
  48
  49 static const char *si_get_marketing_name(struct radeon_winsys *ws)
  50 {
  51         if (!ws->get_chip_name)
  52                 return NULL;
  53         return ws->get_chip_name(ws);
  54 }
  55
  56 const char *si_get_family_name(const struct si_screen *sscreen)
  57 {
  58         switch (sscreen->info.family) {
  59         case CHIP_TAHITI: return "AMD TAHITI";
  60         case CHIP_PITCAIRN: return "AMD PITCAIRN";
  61         case CHIP_VERDE: return "AMD CAPE VERDE";
  62         case CHIP_OLAND: return "AMD OLAND";
  63         case CHIP_HAINAN: return "AMD HAINAN";
  64         case CHIP_BONAIRE: return "AMD BONAIRE";
  65         case CHIP_KAVERI: return "AMD KAVERI";
  66         case CHIP_KABINI: return "AMD KABINI";
  67         case CHIP_HAWAII: return "AMD HAWAII";
  68         case CHIP_MULLINS: return "AMD MULLINS";
  69         case CHIP_TONGA: return "AMD TONGA";
  70         case CHIP_ICELAND: return "AMD ICELAND";
  71         case CHIP_CARRIZO: return "AMD CARRIZO";
  72         case CHIP_FIJI: return "AMD FIJI";
  73         case CHIP_POLARIS10: return "AMD POLARIS10";
  74         case CHIP_POLARIS11: return "AMD POLARIS11";
  75         case CHIP_POLARIS12: return "AMD POLARIS12";
  76         case CHIP_STONEY: return "AMD STONEY";
  77         case CHIP_VEGA10: return "AMD VEGA10";
  78         case CHIP_RAVEN: return "AMD RAVEN";
  79         default: return "AMD unknown";
  80         }
  81 }
  82
  83 static bool si_have_tgsi_compute(struct si_screen *sscreen)
  84 {
  85         /* Old kernels disallowed some register writes for SI
  86          * that are used for indirect dispatches. */
  87         return (sscreen->info.chip_class >= CIK ||
  88                 sscreen->info.drm_major == 3 ||
  89                 (sscreen->info.drm_major == 2 &&
  90                  sscreen->info.drm_minor >= 45));
  91 }
  92
  93 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  94 {
  95         struct si_screen *sscreen = (struct si_screen *)pscreen;
  96
  97         switch (param) {
  98         /* Supported features (boolean caps). */
  99         case PIPE_CAP_ACCELERATED:
 100         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 101         case PIPE_CAP_ANISOTROPIC_FILTER:
 102         case PIPE_CAP_POINT_SPRITE:
 103         case PIPE_CAP_OCCLUSION_QUERY:
 104         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 105         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 106         case PIPE_CAP_TEXTURE_SWIZZLE:
 107         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 108         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 109         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 110         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 111         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 112         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 113         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 114         case PIPE_CAP_SM3:
 115         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 116         case PIPE_CAP_PRIMITIVE_RESTART:
 117         case PIPE_CAP_CONDITIONAL_RENDER:
 118         case PIPE_CAP_TEXTURE_BARRIER:
 119         case PIPE_CAP_INDEP_BLEND_ENABLE:
 120         case PIPE_CAP_INDEP_BLEND_FUNC:
 121         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 122         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 123         case PIPE_CAP_START_INSTANCE:
 124         case PIPE_CAP_NPOT_TEXTURES:
 125         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 126         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 127         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 128         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 129         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 130         case PIPE_CAP_TGSI_INSTANCEID:
 131         case PIPE_CAP_COMPUTE:
 132         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 133         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 134         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 135         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 136         case PIPE_CAP_CUBE_MAP_ARRAY:
 137         case PIPE_CAP_SAMPLE_SHADING:
 138         case PIPE_CAP_DRAW_INDIRECT:
 139         case PIPE_CAP_CLIP_HALFZ:
 140         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 141         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 142         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 143         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 144         case PIPE_CAP_TGSI_TEXCOORD:
 145         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 146         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 147         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 148         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 149         case PIPE_CAP_SHAREABLE_SHADERS:
 150         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 151         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 152         case PIPE_CAP_TEXTURE_QUERY_LOD:
 153         case PIPE_CAP_TEXTURE_GATHER_SM5:
 154         case PIPE_CAP_TGSI_TXQS:
 155         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 156         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 157         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 158         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 159         case PIPE_CAP_INVALIDATE_BUFFER:
 160         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 161         case PIPE_CAP_QUERY_MEMORY_INFO:
 162         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 163         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 164         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 165         case PIPE_CAP_GENERATE_MIPMAP:
 166         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 167         case PIPE_CAP_STRING_MARKER:
 168         case PIPE_CAP_CLEAR_TEXTURE:
 169         case PIPE_CAP_CULL_DISTANCE:
 170         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 171         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 172         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 173         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 174         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 175         case PIPE_CAP_DOUBLES:
 176         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 177         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 178         case PIPE_CAP_BINDLESS_TEXTURE:
 179         case PIPE_CAP_QUERY_TIMESTAMP:
 180         case PIPE_CAP_QUERY_TIME_ELAPSED:
 181         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 182         case PIPE_CAP_QUERY_SO_OVERFLOW:
 183         case PIPE_CAP_MEMOBJ:
 184         case PIPE_CAP_LOAD_CONSTBUF:
 185         case PIPE_CAP_INT64:
 186         case PIPE_CAP_INT64_DIVMOD:
 187         case PIPE_CAP_TGSI_CLOCK:
 188         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 189         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 190         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 191         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 192         case PIPE_CAP_TGSI_VOTE:
 193                 return 1;
 194
 195         case PIPE_CAP_TGSI_BALLOT:
 196                 return HAVE_LLVM >= 0x0500;
 197
 198         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 199                 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 200
 201         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 202                 return (sscreen->info.drm_major == 2 &&
 203                         sscreen->info.drm_minor >= 43) ||
 204                        sscreen->info.drm_major == 3;
 205
 206         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 207                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 208                 return sscreen->info.chip_class < CIK ||
 209                        (sscreen->info.drm_major == 2 &&
 210                         sscreen->info.drm_minor >= 35) ||
 211                        sscreen->info.drm_major == 3;
 212
 213         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 214                 return R600_MAP_BUFFER_ALIGNMENT;
 215
 216         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 217         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 218         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 219         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 220         case PIPE_CAP_MAX_VERTEX_STREAMS:
 221         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 222                 return 4;
 223
 224         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 225                 if (si_have_tgsi_compute(sscreen))
 226                         return 450;
 227                 return 420;
 228
 229         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 230                 return MIN2(sscreen->info.max_alloc_size, INT_MAX);
 231
 232         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 233         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 234         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 235                 /* SI doesn't support unaligned loads.
 236                  * CIK needs DRM 2.50.0 on radeon. */
 237                 return sscreen->info.chip_class == SI ||
 238                        (sscreen->info.drm_major == 2 &&
 239                         sscreen->info.drm_minor < 50);
 240
 241         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 242                 /* TODO: GFX9 hangs. */
 243                 if (sscreen->info.chip_class >= GFX9)
 244                         return 0;
 245                 /* Disable on SI due to VM faults in CP DMA. Enable once these
 246                  * faults are mitigated in software.
 247                  */
 248                 if (sscreen->info.chip_class >= CIK &&
 249                     sscreen->info.drm_major == 3 &&
 250                     sscreen->info.drm_minor >= 13)
 251                         return RADEON_SPARSE_PAGE_SIZE;
 252                 return 0;
 253
 254         /* Unsupported features. */
 255         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 256         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 257         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 258         case PIPE_CAP_USER_VERTEX_BUFFERS:
 259         case PIPE_CAP_FAKE_SW_MSAA:
 260         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 261         case PIPE_CAP_VERTEXID_NOBASE:
 262         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 263         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 264         case PIPE_CAP_TGSI_FS_FBFETCH:
 265         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 266         case PIPE_CAP_UMA:
 267         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 268         case PIPE_CAP_POST_DEPTH_COVERAGE:
 269         case PIPE_CAP_TILE_RASTER_ORDER:
 270         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 271         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 272         case PIPE_CAP_PACKED_UNIFORMS:
 273                 return 0;
 274
 275         case PIPE_CAP_FENCE_SIGNAL:
 276                 return sscreen->info.has_syncobj;
 277
 278         case PIPE_CAP_CONSTBUF0_FLAGS:
 279                 return R600_RESOURCE_FLAG_32BIT;
 280
 281         case PIPE_CAP_NATIVE_FENCE_FD:
 282                 return sscreen->info.has_fence_to_handle;
 283
 284         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 285                 return si_have_tgsi_compute(sscreen);
 286
 287         case PIPE_CAP_DRAW_PARAMETERS:
 288         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 289         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 290                 return sscreen->has_draw_indirect_multi;
 291
 292         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 293                 return 30;
 294
 295         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 296                 return sscreen->info.chip_class <= VI ?
 297                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 298
 299         /* Stream output. */
 300         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 301         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 302                 return 32*4;
 303
 304         /* Geometry shader output. */
 305         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 306                 return 1024;
 307         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 308                 return 4095;
 309
 310         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 311                 return 2048;
 312
 313         /* Texturing. */
 314         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 315         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 316                 return 15; /* 16384 */
 317         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 318                 /* textures support 8192, but layered rendering supports 2048 */
 319                 return 12;
 320         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 321                 /* textures support 8192, but layered rendering supports 2048 */
 322                 return 2048;
 323
 324         /* Viewports and render targets. */
 325         case PIPE_CAP_MAX_VIEWPORTS:
 326                 return SI_MAX_VIEWPORTS;
 327         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 328         case PIPE_CAP_MAX_RENDER_TARGETS:
 329                 return 8;
 330
 331         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 332         case PIPE_CAP_MIN_TEXEL_OFFSET:
 333                 return -32;
 334
 335         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 336         case PIPE_CAP_MAX_TEXEL_OFFSET:
 337                 return 31;
 338
 339         case PIPE_CAP_ENDIANNESS:
 340                 return PIPE_ENDIAN_LITTLE;
 341
 342         case PIPE_CAP_VENDOR_ID:
 343                 return ATI_VENDOR_ID;
 344         case PIPE_CAP_DEVICE_ID:
 345                 return sscreen->info.pci_id;
 346         case PIPE_CAP_VIDEO_MEMORY:
 347                 return sscreen->info.vram_size >> 20;
 348         case PIPE_CAP_PCI_GROUP:
 349                 return sscreen->info.pci_domain;
 350         case PIPE_CAP_PCI_BUS:
 351                 return sscreen->info.pci_bus;
 352         case PIPE_CAP_PCI_DEVICE:
 353                 return sscreen->info.pci_dev;
 354         case PIPE_CAP_PCI_FUNCTION:
 355                 return sscreen->info.pci_func;
 356         }
 357         return 0;
 358 }
 359
 360 static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
 361 {
 362         switch (param) {
 363         case PIPE_CAPF_MAX_LINE_WIDTH:
 364         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 365         case PIPE_CAPF_MAX_POINT_WIDTH:
 366         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 367                 return 8192.0f;
 368         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 369                 return 16.0f;
 370         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 371                 return 16.0f;
 372         }
 373         return 0.0f;
 374 }
 375
 376 static int si_get_shader_param(struct pipe_screen* pscreen,
 377                                enum pipe_shader_type shader,
 378                                enum pipe_shader_cap param)
 379 {
 380         struct si_screen *sscreen = (struct si_screen *)pscreen;
 381
 382         switch(shader)
 383         {
 384         case PIPE_SHADER_FRAGMENT:
 385         case PIPE_SHADER_VERTEX:
 386         case PIPE_SHADER_GEOMETRY:
 387         case PIPE_SHADER_TESS_CTRL:
 388         case PIPE_SHADER_TESS_EVAL:
 389                 break;
 390         case PIPE_SHADER_COMPUTE:
 391                 switch (param) {
 392                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 393                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 394
 395                         if (si_have_tgsi_compute(sscreen))
 396                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 397
 398                         return ir;
 399                 }
 400
 401                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 402                         uint64_t max_const_buffer_size;
 403                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 404                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 405                                 &max_const_buffer_size);
 406                         return MIN2(max_const_buffer_size, INT_MAX);
 407                 }
 408                 default:
 409                         /* If compute shaders don't require a special value
 410                          * for this cap, we can return the same value we
 411                          * do for other shader types. */
 412                         break;
 413                 }
 414                 break;
 415         default:
 416                 return 0;
 417         }
 418
 419         switch (param) {
 420         /* Shader limits. */
 421         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 422         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 423         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 424         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 425         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 426                 return 16384;
 427         case PIPE_SHADER_CAP_MAX_INPUTS:
 428                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 429         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 430                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 431         case PIPE_SHADER_CAP_MAX_TEMPS:
 432                 return 256; /* Max native temporaries. */
 433         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 434                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 435         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 436                 return SI_NUM_CONST_BUFFERS;
 437         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 438         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 439                 return SI_NUM_SAMPLERS;
 440         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 441                 return SI_NUM_SHADER_BUFFERS;
 442         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 443                 return SI_NUM_IMAGES;
 444         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 445                 if (sscreen->debug_flags & DBG(NIR))
 446                         return 0;
 447                 return 32;
 448         case PIPE_SHADER_CAP_PREFERRED_IR:
 449                 if (sscreen->debug_flags & DBG(NIR))
 450                         return PIPE_SHADER_IR_NIR;
 451                 return PIPE_SHADER_IR_TGSI;
 452         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 453                 return 4;
 454
 455         /* Supported boolean features. */
 456         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 457         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 458         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 459         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 460         case PIPE_SHADER_CAP_INTEGERS:
 461         case PIPE_SHADER_CAP_INT64_ATOMICS:
 462         case PIPE_SHADER_CAP_FP16:
 463         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 464         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 465         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 466         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 467         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 468         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 469                 return 1;
 470
 471         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 472                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 473                 return shader != PIPE_SHADER_GEOMETRY &&
 474                        (sscreen->llvm_has_working_vgpr_indexing ||
 475                         /* TCS and TES load inputs directly from LDS or
 476                          * offchip memory, so indirect indexing is trivial. */
 477                         shader == PIPE_SHADER_TESS_CTRL ||
 478                         shader == PIPE_SHADER_TESS_EVAL);
 479
 480         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 481                 return sscreen->llvm_has_working_vgpr_indexing ||
 482                        /* TCS stores outputs directly to memory. */
 483                        shader == PIPE_SHADER_TESS_CTRL;
 484
 485         /* Unsupported boolean features. */
 486         case PIPE_SHADER_CAP_SUBROUTINES:
 487         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 488         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 489         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 490                 return 0;
 491         }
 492         return 0;
 493 }
 494
 495 static const struct nir_shader_compiler_options nir_options = {
 496         .lower_scmp = true,
 497         .lower_flrp32 = true,
 498         .lower_flrp64 = true,
 499         .lower_fpow = true,
 500         .lower_fsat = true,
 501         .lower_fdiv = true,
 502         .lower_sub = true,
 503         .lower_ffma = true,
 504         .lower_pack_snorm_2x16 = true,
 505         .lower_pack_snorm_4x8 = true,
 506         .lower_pack_unorm_2x16 = true,
 507         .lower_pack_unorm_4x8 = true,
 508         .lower_unpack_snorm_2x16 = true,
 509         .lower_unpack_snorm_4x8 = true,
 510         .lower_unpack_unorm_2x16 = true,
 511         .lower_unpack_unorm_4x8 = true,
 512         .lower_extract_byte = true,
 513         .lower_extract_word = true,
 514         .max_unroll_iterations = 32,
 515         .native_integers = true,
 516 };
 517
 518 static const void *
 519 si_get_compiler_options(struct pipe_screen *screen,
 520                         enum pipe_shader_ir ir,
 521                         enum pipe_shader_type shader)
 522 {
 523         assert(ir == PIPE_SHADER_IR_NIR);
 524         return &nir_options;
 525 }
 526
 527 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 528 {
 529         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 530 }
 531
 532 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 533 {
 534         struct si_screen *sscreen = (struct si_screen *)pscreen;
 535
 536         ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
 537 }
 538
 539 static const char* si_get_name(struct pipe_screen *pscreen)
 540 {
 541         struct si_screen *sscreen = (struct si_screen*)pscreen;
 542
 543         return sscreen->renderer_string;
 544 }
 545
 546 static int si_get_video_param_no_decode(struct pipe_screen *screen,
 547                                         enum pipe_video_profile profile,
 548                                         enum pipe_video_entrypoint entrypoint,
 549                                         enum pipe_video_cap param)
 550 {
 551         switch (param) {
 552         case PIPE_VIDEO_CAP_SUPPORTED:
 553                 return vl_profile_supported(screen, profile, entrypoint);
 554         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 555                 return 1;
 556         case PIPE_VIDEO_CAP_MAX_WIDTH:
 557         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 558                 return vl_video_buffer_max_size(screen);
 559         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 560                 return PIPE_FORMAT_NV12;
 561         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 562                 return false;
 563         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 564                 return false;
 565         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 566                 return true;
 567         case PIPE_VIDEO_CAP_MAX_LEVEL:
 568                 return vl_level_supported(screen, profile);
 569         default:
 570                 return 0;
 571         }
 572 }
 573
 574 static int si_get_video_param(struct pipe_screen *screen,
 575                               enum pipe_video_profile profile,
 576                               enum pipe_video_entrypoint entrypoint,
 577                               enum pipe_video_cap param)
 578 {
 579         struct si_screen *sscreen = (struct si_screen *)screen;
 580         enum pipe_video_format codec = u_reduce_video_profile(profile);
 581
 582         if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 583                 switch (param) {
 584                 case PIPE_VIDEO_CAP_SUPPORTED:
 585                         return (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 586                                 (si_vce_is_fw_version_supported(sscreen) ||
 587                                 sscreen->info.family == CHIP_RAVEN)) ||
 588                                 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
 589                                 (sscreen->info.family == CHIP_RAVEN ||
 590                                 si_radeon_uvd_enc_supported(sscreen)));
 591                 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 592                         return 1;
 593                 case PIPE_VIDEO_CAP_MAX_WIDTH:
 594                         return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 595                 case PIPE_VIDEO_CAP_MAX_HEIGHT:
 596                         return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
 597                 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 598                         return PIPE_FORMAT_NV12;
 599                 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 600                         return false;
 601                 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 602                         return false;
 603                 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 604                         return true;
 605                 case PIPE_VIDEO_CAP_STACKED_FRAMES:
 606                         return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
 607                 default:
 608                         return 0;
 609                 }
 610         }
 611
 612         switch (param) {
 613         case PIPE_VIDEO_CAP_SUPPORTED:
 614                 switch (codec) {
 615                 case PIPE_VIDEO_FORMAT_MPEG12:
 616                         return profile != PIPE_VIDEO_PROFILE_MPEG1;
 617                 case PIPE_VIDEO_FORMAT_MPEG4:
 618                         return 1;
 619                 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 620                         if ((sscreen->info.family == CHIP_POLARIS10 ||
 621                              sscreen->info.family == CHIP_POLARIS11) &&
 622                             sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
 623                                 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 624                                 return false;
 625                         }
 626                         return true;
 627                 case PIPE_VIDEO_FORMAT_VC1:
 628                         return true;
 629                 case PIPE_VIDEO_FORMAT_HEVC:
 630                         /* Carrizo only supports HEVC Main */
 631                         if (sscreen->info.family >= CHIP_STONEY)
 632                                 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 633                                         profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 634                         else if (sscreen->info.family >= CHIP_CARRIZO)
 635                                 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 636                         return false;
 637                 case PIPE_VIDEO_FORMAT_JPEG:
 638                         if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
 639                                 return false;
 640                         if (!(sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 19)) {
 641                                 RVID_ERR("No MJPEG support for the kernel version\n");
 642                                 return false;
 643                         }
 644                         return true;
 645                 default:
 646                         return false;
 647                 }
 648         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 649                 return 1;
 650         case PIPE_VIDEO_CAP_MAX_WIDTH:
 651                 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 652         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 653                 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
 654         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 655                 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 656                         return PIPE_FORMAT_P016;
 657                 else
 658                         return PIPE_FORMAT_NV12;
 659
 660         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 661         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 662                 enum pipe_video_format format = u_reduce_video_profile(profile);
 663
 664                 if (format == PIPE_VIDEO_FORMAT_HEVC)
 665                         return false; //The firmware doesn't support interlaced HEVC.
 666                 else if (format == PIPE_VIDEO_FORMAT_JPEG)
 667                         return false;
 668                 return true;
 669         }
 670         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 671                 return true;
 672         case PIPE_VIDEO_CAP_MAX_LEVEL:
 673                 switch (profile) {
 674                 case PIPE_VIDEO_PROFILE_MPEG1:
 675                         return 0;
 676                 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 677                 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 678                         return 3;
 679                 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 680                         return 3;
 681                 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 682                         return 5;
 683                 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 684                         return 1;
 685                 case PIPE_VIDEO_PROFILE_VC1_MAIN:
 686                         return 2;
 687                 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 688                         return 4;
 689                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 690                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 691                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 692                         return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
 693                 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 694                 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 695                         return 186;
 696                 default:
 697                         return 0;
 698                 }
 699         default:
 700                 return 0;
 701         }
 702 }
 703
 704 static boolean si_vid_is_format_supported(struct pipe_screen *screen,
 705                                           enum pipe_format format,
 706                                           enum pipe_video_profile profile,
 707                                           enum pipe_video_entrypoint entrypoint)
 708 {
 709         /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
 710         if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 711                 return (format == PIPE_FORMAT_NV12) ||
 712                         (format == PIPE_FORMAT_P016);
 713
 714         /* we can only handle this one with UVD */
 715         if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 716                 return format == PIPE_FORMAT_NV12;
 717
 718         return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 719 }
 720
 721 static unsigned get_max_threads_per_block(struct si_screen *screen,
 722                                           enum pipe_shader_ir ir_type)
 723 {
 724         if (ir_type == PIPE_SHADER_IR_NATIVE)
 725                 return 256;
 726
 727         /* Only 16 waves per thread-group on gfx9. */
 728         if (screen->info.chip_class >= GFX9)
 729                 return 1024;
 730
 731         /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
 732          * round number.
 733          */
 734         return 2048;
 735 }
 736
 737 static int si_get_compute_param(struct pipe_screen *screen,
 738                                 enum pipe_shader_ir ir_type,
 739                                 enum pipe_compute_cap param,
 740                                 void *ret)
 741 {
 742         struct si_screen *sscreen = (struct si_screen *)screen;
 743
 744         //TODO: select these params by asic
 745         switch (param) {
 746         case PIPE_COMPUTE_CAP_IR_TARGET: {
 747                 const char *gpu, *triple;
 748
 749                 triple = "amdgcn-mesa-mesa3d";
 750                 gpu = ac_get_llvm_processor_name(sscreen->info.family);
 751                 if (ret) {
 752                         sprintf(ret, "%s-%s", gpu, triple);
 753                 }
 754                 /* +2 for dash and terminating NIL byte */
 755                 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 756         }
 757         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 758                 if (ret) {
 759                         uint64_t *grid_dimension = ret;
 760                         grid_dimension[0] = 3;
 761                 }
 762                 return 1 * sizeof(uint64_t);
 763
 764         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 765                 if (ret) {
 766                         uint64_t *grid_size = ret;
 767                         grid_size[0] = 65535;
 768                         grid_size[1] = 65535;
 769                         grid_size[2] = 65535;
 770                 }
 771                 return 3 * sizeof(uint64_t) ;
 772
 773         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 774                 if (ret) {
 775                         uint64_t *block_size = ret;
 776                         unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 777                         block_size[0] = threads_per_block;
 778                         block_size[1] = threads_per_block;
 779                         block_size[2] = threads_per_block;
 780                 }
 781                 return 3 * sizeof(uint64_t);
 782
 783         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 784                 if (ret) {
 785                         uint64_t *max_threads_per_block = ret;
 786                         *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 787                 }
 788                 return sizeof(uint64_t);
 789         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 790                 if (ret) {
 791                         uint32_t *address_bits = ret;
 792                         address_bits[0] = 64;
 793                 }
 794                 return 1 * sizeof(uint32_t);
 795
 796         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 797                 if (ret) {
 798                         uint64_t *max_global_size = ret;
 799                         uint64_t max_mem_alloc_size;
 800
 801                         si_get_compute_param(screen, ir_type,
 802                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 803                                 &max_mem_alloc_size);
 804
 805                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 806                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 807                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 808                          * make sure we never report more than
 809                          * 4 * MAX_MEM_ALLOC_SIZE.
 810                          */
 811                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 812                                                 MAX2(sscreen->info.gart_size,
 813                                                      sscreen->info.vram_size));
 814                 }
 815                 return sizeof(uint64_t);
 816
 817         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 818                 if (ret) {
 819                         uint64_t *max_local_size = ret;
 820                         /* Value reported by the closed source driver. */
 821                         *max_local_size = 32768;
 822                 }
 823                 return sizeof(uint64_t);
 824
 825         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 826                 if (ret) {
 827                         uint64_t *max_input_size = ret;
 828                         /* Value reported by the closed source driver. */
 829                         *max_input_size = 1024;
 830                 }
 831                 return sizeof(uint64_t);
 832
 833         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 834                 if (ret) {
 835                         uint64_t *max_mem_alloc_size = ret;
 836
 837                         *max_mem_alloc_size = sscreen->info.max_alloc_size;
 838                 }
 839                 return sizeof(uint64_t);
 840
 841         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 842                 if (ret) {
 843                         uint32_t *max_clock_frequency = ret;
 844                         *max_clock_frequency = sscreen->info.max_shader_clock;
 845                 }
 846                 return sizeof(uint32_t);
 847
 848         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 849                 if (ret) {
 850                         uint32_t *max_compute_units = ret;
 851                         *max_compute_units = sscreen->info.num_good_compute_units;
 852                 }
 853                 return sizeof(uint32_t);
 854
 855         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 856                 if (ret) {
 857                         uint32_t *images_supported = ret;
 858                         *images_supported = 0;
 859                 }
 860                 return sizeof(uint32_t);
 861         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 862                 break; /* unused */
 863         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 864                 if (ret) {
 865                         uint32_t *subgroup_size = ret;
 866                         *subgroup_size = 64;
 867                 }
 868                 return sizeof(uint32_t);
 869         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 870                 if (ret) {
 871                         uint64_t *max_variable_threads_per_block = ret;
 872                         if (ir_type == PIPE_SHADER_IR_NATIVE)
 873                                 *max_variable_threads_per_block = 0;
 874                         else
 875                                 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
 876                 }
 877                 return sizeof(uint64_t);
 878         }
 879
 880         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 881         return 0;
 882 }
 883
 884 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 885 {
 886         struct si_screen *sscreen = (struct si_screen*)screen;
 887
 888         return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
 889                         sscreen->info.clock_crystal_freq;
 890 }
 891
 892 static void si_query_memory_info(struct pipe_screen *screen,
 893                                  struct pipe_memory_info *info)
 894 {
 895         struct si_screen *sscreen = (struct si_screen*)screen;
 896         struct radeon_winsys *ws = sscreen->ws;
 897         unsigned vram_usage, gtt_usage;
 898
 899         info->total_device_memory = sscreen->info.vram_size / 1024;
 900         info->total_staging_memory = sscreen->info.gart_size / 1024;
 901
 902         /* The real TTM memory usage is somewhat random, because:
 903          *
 904          * 1) TTM delays freeing memory, because it can only free it after
 905          *    fences expire.
 906          *
 907          * 2) The memory usage can be really low if big VRAM evictions are
 908          *    taking place, but the real usage is well above the size of VRAM.
 909          *
 910          * Instead, return statistics of this process.
 911          */
 912         vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
 913         gtt_usage =  ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
 914
 915         info->avail_device_memory =
 916                 vram_usage <= info->total_device_memory ?
 917                                 info->total_device_memory - vram_usage : 0;
 918         info->avail_staging_memory =
 919                 gtt_usage <= info->total_staging_memory ?
 920                                 info->total_staging_memory - gtt_usage : 0;
 921
 922         info->device_memory_evicted =
 923                 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 924
 925         if (sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 4)
 926                 info->nr_device_memory_evictions =
 927                         ws->query_value(ws, RADEON_NUM_EVICTIONS);
 928         else
 929                 /* Just return the number of evicted 64KB pages. */
 930                 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 931 }
 932
 933 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 934 {
 935         struct si_screen *sscreen = (struct si_screen*)pscreen;
 936
 937         return sscreen->disk_shader_cache;
 938 }
 939
 940 static void si_init_renderer_string(struct si_screen *sscreen)
 941 {
 942         struct radeon_winsys *ws = sscreen->ws;
 943         char family_name[32] = {}, llvm_string[32] = {}, kernel_version[128] = {};
 944         struct utsname uname_data;
 945
 946         const char *chip_name = si_get_marketing_name(ws);
 947
 948         if (chip_name)
 949                 snprintf(family_name, sizeof(family_name), "%s / ",
 950                          si_get_family_name(sscreen) + 4);
 951         else
 952                 chip_name = si_get_family_name(sscreen);
 953
 954         if (uname(&uname_data) == 0)
 955                 snprintf(kernel_version, sizeof(kernel_version),
 956                          " / %s", uname_data.release);
 957
 958         if (HAVE_LLVM > 0) {
 959                 snprintf(llvm_string, sizeof(llvm_string),
 960                          ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
 961                          HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
 962         }
 963
 964         snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
 965                  "%s (%sDRM %i.%i.%i%s%s)",
 966                  chip_name, family_name, sscreen->info.drm_major,
 967                  sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
 968                  kernel_version, llvm_string);
 969 }
 970
 971 void si_init_screen_get_functions(struct si_screen *sscreen)
 972 {
 973         sscreen->b.get_name = si_get_name;
 974         sscreen->b.get_vendor = si_get_vendor;
 975         sscreen->b.get_device_vendor = si_get_device_vendor;
 976         sscreen->b.get_param = si_get_param;
 977         sscreen->b.get_paramf = si_get_paramf;
 978         sscreen->b.get_compute_param = si_get_compute_param;
 979         sscreen->b.get_timestamp = si_get_timestamp;
 980         sscreen->b.get_shader_param = si_get_shader_param;
 981         sscreen->b.get_compiler_options = si_get_compiler_options;
 982         sscreen->b.get_device_uuid = si_get_device_uuid;
 983         sscreen->b.get_driver_uuid = si_get_driver_uuid;
 984         sscreen->b.query_memory_info = si_query_memory_info;
 985         sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
 986
 987         if (sscreen->info.has_hw_decode) {
 988                 sscreen->b.get_video_param = si_get_video_param;
 989                 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
 990         } else {
 991                 sscreen->b.get_video_param = si_get_video_param_no_decode;
 992                 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
 993         }
 994
 995         si_init_renderer_string(sscreen);
 996 }