src/gallium/drivers/radeonsi/si_get.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "radeon/radeon_video.h"
  26 #include "radeon/radeon_vce.h"
  27 #include "ac_llvm_util.h"
  28 #include "vl/vl_decoder.h"
  29 #include "vl/vl_video_buffer.h"
  30 #include "util/u_video.h"
  31 #include "compiler/nir/nir.h"
  32
  33 #include <sys/utsname.h>
  34
  35 static const char *si_get_vendor(struct pipe_screen *pscreen)
  36 {
  37         /* Don't change this. Games such as Alien Isolation are broken if this
  38          * returns "Advanced Micro Devices, Inc."
  39          */
  40         return "X.Org";
  41 }
  42
  43 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
  44 {
  45         return "AMD";
  46 }
  47
  48 static const char *si_get_marketing_name(struct radeon_winsys *ws)
  49 {
  50         if (!ws->get_chip_name)
  51                 return NULL;
  52         return ws->get_chip_name(ws);
  53 }
  54
  55 const char *si_get_family_name(const struct si_screen *sscreen)
  56 {
  57         switch (sscreen->info.family) {
  58         case CHIP_TAHITI: return "AMD TAHITI";
  59         case CHIP_PITCAIRN: return "AMD PITCAIRN";
  60         case CHIP_VERDE: return "AMD CAPE VERDE";
  61         case CHIP_OLAND: return "AMD OLAND";
  62         case CHIP_HAINAN: return "AMD HAINAN";
  63         case CHIP_BONAIRE: return "AMD BONAIRE";
  64         case CHIP_KAVERI: return "AMD KAVERI";
  65         case CHIP_KABINI: return "AMD KABINI";
  66         case CHIP_HAWAII: return "AMD HAWAII";
  67         case CHIP_MULLINS: return "AMD MULLINS";
  68         case CHIP_TONGA: return "AMD TONGA";
  69         case CHIP_ICELAND: return "AMD ICELAND";
  70         case CHIP_CARRIZO: return "AMD CARRIZO";
  71         case CHIP_FIJI: return "AMD FIJI";
  72         case CHIP_POLARIS10: return "AMD POLARIS10";
  73         case CHIP_POLARIS11: return "AMD POLARIS11";
  74         case CHIP_POLARIS12: return "AMD POLARIS12";
  75         case CHIP_STONEY: return "AMD STONEY";
  76         case CHIP_VEGA10: return "AMD VEGA10";
  77         case CHIP_RAVEN: return "AMD RAVEN";
  78         default: return "AMD unknown";
  79         }
  80 }
  81
  82 static bool si_have_tgsi_compute(struct si_screen *sscreen)
  83 {
  84         /* Old kernels disallowed some register writes for SI
  85          * that are used for indirect dispatches. */
  86         return (sscreen->info.chip_class >= CIK ||
  87                 sscreen->info.drm_major == 3 ||
  88                 (sscreen->info.drm_major == 2 &&
  89                  sscreen->info.drm_minor >= 45));
  90 }
  91
  92 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  93 {
  94         struct si_screen *sscreen = (struct si_screen *)pscreen;
  95
  96         switch (param) {
  97         /* Supported features (boolean caps). */
  98         case PIPE_CAP_ACCELERATED:
  99         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 100         case PIPE_CAP_ANISOTROPIC_FILTER:
 101         case PIPE_CAP_POINT_SPRITE:
 102         case PIPE_CAP_OCCLUSION_QUERY:
 103         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 104         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 105         case PIPE_CAP_TEXTURE_SWIZZLE:
 106         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 107         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 108         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 109         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 110         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 111         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 112         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 113         case PIPE_CAP_SM3:
 114         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 115         case PIPE_CAP_PRIMITIVE_RESTART:
 116         case PIPE_CAP_CONDITIONAL_RENDER:
 117         case PIPE_CAP_TEXTURE_BARRIER:
 118         case PIPE_CAP_INDEP_BLEND_ENABLE:
 119         case PIPE_CAP_INDEP_BLEND_FUNC:
 120         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 121         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 122         case PIPE_CAP_START_INSTANCE:
 123         case PIPE_CAP_NPOT_TEXTURES:
 124         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 125         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 126         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 127         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 128         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 129         case PIPE_CAP_TGSI_INSTANCEID:
 130         case PIPE_CAP_COMPUTE:
 131         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 132         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 133         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 134         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 135         case PIPE_CAP_CUBE_MAP_ARRAY:
 136         case PIPE_CAP_SAMPLE_SHADING:
 137         case PIPE_CAP_DRAW_INDIRECT:
 138         case PIPE_CAP_CLIP_HALFZ:
 139         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 140         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 141         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 142         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 143         case PIPE_CAP_TGSI_TEXCOORD:
 144         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 145         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 146         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 147         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 148         case PIPE_CAP_SHAREABLE_SHADERS:
 149         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 150         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 151         case PIPE_CAP_TEXTURE_QUERY_LOD:
 152         case PIPE_CAP_TEXTURE_GATHER_SM5:
 153         case PIPE_CAP_TGSI_TXQS:
 154         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 155         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 156         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 157         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 158         case PIPE_CAP_INVALIDATE_BUFFER:
 159         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 160         case PIPE_CAP_QUERY_MEMORY_INFO:
 161         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 162         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 163         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 164         case PIPE_CAP_GENERATE_MIPMAP:
 165         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 166         case PIPE_CAP_STRING_MARKER:
 167         case PIPE_CAP_CLEAR_TEXTURE:
 168         case PIPE_CAP_CULL_DISTANCE:
 169         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 170         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 171         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 172         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 173         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 174         case PIPE_CAP_DOUBLES:
 175         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 176         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 177         case PIPE_CAP_BINDLESS_TEXTURE:
 178         case PIPE_CAP_QUERY_TIMESTAMP:
 179         case PIPE_CAP_QUERY_TIME_ELAPSED:
 180         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 181         case PIPE_CAP_QUERY_SO_OVERFLOW:
 182         case PIPE_CAP_MEMOBJ:
 183         case PIPE_CAP_LOAD_CONSTBUF:
 184         case PIPE_CAP_INT64:
 185         case PIPE_CAP_INT64_DIVMOD:
 186         case PIPE_CAP_TGSI_CLOCK:
 187         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 188         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 189         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 190         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 191         case PIPE_CAP_TGSI_VOTE:
 192                 return 1;
 193
 194         case PIPE_CAP_TGSI_BALLOT:
 195                 return HAVE_LLVM >= 0x0500;
 196
 197         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 198                 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 199
 200         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 201                 return (sscreen->info.drm_major == 2 &&
 202                         sscreen->info.drm_minor >= 43) ||
 203                        sscreen->info.drm_major == 3;
 204
 205         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 206                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 207                 return sscreen->info.chip_class < CIK ||
 208                        (sscreen->info.drm_major == 2 &&
 209                         sscreen->info.drm_minor >= 35) ||
 210                        sscreen->info.drm_major == 3;
 211
 212         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 213                 return R600_MAP_BUFFER_ALIGNMENT;
 214
 215         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 216         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 217         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 218         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 219         case PIPE_CAP_MAX_VERTEX_STREAMS:
 220         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 221                 return 4;
 222
 223         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 224                 if (si_have_tgsi_compute(sscreen))
 225                         return 450;
 226                 return 420;
 227
 228         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 229                 return MIN2(sscreen->info.max_alloc_size, INT_MAX);
 230
 231         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 232         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 233         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 234                 /* SI doesn't support unaligned loads.
 235                  * CIK needs DRM 2.50.0 on radeon. */
 236                 return sscreen->info.chip_class == SI ||
 237                        (sscreen->info.drm_major == 2 &&
 238                         sscreen->info.drm_minor < 50);
 239
 240         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 241                 /* TODO: GFX9 hangs. */
 242                 if (sscreen->info.chip_class >= GFX9)
 243                         return 0;
 244                 /* Disable on SI due to VM faults in CP DMA. Enable once these
 245                  * faults are mitigated in software.
 246                  */
 247                 if (sscreen->info.chip_class >= CIK &&
 248                     sscreen->info.drm_major == 3 &&
 249                     sscreen->info.drm_minor >= 13)
 250                         return RADEON_SPARSE_PAGE_SIZE;
 251                 return 0;
 252
 253         /* Unsupported features. */
 254         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 255         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 256         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 257         case PIPE_CAP_USER_VERTEX_BUFFERS:
 258         case PIPE_CAP_FAKE_SW_MSAA:
 259         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 260         case PIPE_CAP_VERTEXID_NOBASE:
 261         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 262         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 263         case PIPE_CAP_TGSI_FS_FBFETCH:
 264         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 265         case PIPE_CAP_UMA:
 266         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 267         case PIPE_CAP_POST_DEPTH_COVERAGE:
 268         case PIPE_CAP_TILE_RASTER_ORDER:
 269         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 270         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 271                 return 0;
 272
 273         case PIPE_CAP_FENCE_SIGNAL:
 274                 return sscreen->info.has_syncobj;
 275
 276         case PIPE_CAP_NATIVE_FENCE_FD:
 277                 return sscreen->info.has_fence_to_handle;
 278
 279         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 280                 return si_have_tgsi_compute(sscreen);
 281
 282         case PIPE_CAP_DRAW_PARAMETERS:
 283         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 284         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 285                 return sscreen->has_draw_indirect_multi;
 286
 287         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 288                 return 30;
 289
 290         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 291                 return sscreen->info.chip_class <= VI ?
 292                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 293
 294         /* Stream output. */
 295         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 296         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 297                 return 32*4;
 298
 299         /* Geometry shader output. */
 300         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 301                 return 1024;
 302         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 303                 return 4095;
 304
 305         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 306                 return 2048;
 307
 308         /* Texturing. */
 309         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 310         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 311                 return 15; /* 16384 */
 312         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 313                 /* textures support 8192, but layered rendering supports 2048 */
 314                 return 12;
 315         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 316                 /* textures support 8192, but layered rendering supports 2048 */
 317                 return 2048;
 318
 319         /* Viewports and render targets. */
 320         case PIPE_CAP_MAX_VIEWPORTS:
 321                 return SI_MAX_VIEWPORTS;
 322         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 323         case PIPE_CAP_MAX_RENDER_TARGETS:
 324                 return 8;
 325
 326         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 327         case PIPE_CAP_MIN_TEXEL_OFFSET:
 328                 return -32;
 329
 330         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 331         case PIPE_CAP_MAX_TEXEL_OFFSET:
 332                 return 31;
 333
 334         case PIPE_CAP_ENDIANNESS:
 335                 return PIPE_ENDIAN_LITTLE;
 336
 337         case PIPE_CAP_VENDOR_ID:
 338                 return ATI_VENDOR_ID;
 339         case PIPE_CAP_DEVICE_ID:
 340                 return sscreen->info.pci_id;
 341         case PIPE_CAP_VIDEO_MEMORY:
 342                 return sscreen->info.vram_size >> 20;
 343         case PIPE_CAP_PCI_GROUP:
 344                 return sscreen->info.pci_domain;
 345         case PIPE_CAP_PCI_BUS:
 346                 return sscreen->info.pci_bus;
 347         case PIPE_CAP_PCI_DEVICE:
 348                 return sscreen->info.pci_dev;
 349         case PIPE_CAP_PCI_FUNCTION:
 350                 return sscreen->info.pci_func;
 351         }
 352         return 0;
 353 }
 354
 355 static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
 356 {
 357         switch (param) {
 358         case PIPE_CAPF_MAX_LINE_WIDTH:
 359         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 360         case PIPE_CAPF_MAX_POINT_WIDTH:
 361         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 362                 return 8192.0f;
 363         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 364                 return 16.0f;
 365         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 366                 return 16.0f;
 367         }
 368         return 0.0f;
 369 }
 370
 371 static int si_get_shader_param(struct pipe_screen* pscreen,
 372                                enum pipe_shader_type shader,
 373                                enum pipe_shader_cap param)
 374 {
 375         struct si_screen *sscreen = (struct si_screen *)pscreen;
 376
 377         switch(shader)
 378         {
 379         case PIPE_SHADER_FRAGMENT:
 380         case PIPE_SHADER_VERTEX:
 381         case PIPE_SHADER_GEOMETRY:
 382         case PIPE_SHADER_TESS_CTRL:
 383         case PIPE_SHADER_TESS_EVAL:
 384                 break;
 385         case PIPE_SHADER_COMPUTE:
 386                 switch (param) {
 387                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 388                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 389
 390                         if (si_have_tgsi_compute(sscreen))
 391                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 392
 393                         return ir;
 394                 }
 395
 396                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 397                         uint64_t max_const_buffer_size;
 398                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 399                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 400                                 &max_const_buffer_size);
 401                         return MIN2(max_const_buffer_size, INT_MAX);
 402                 }
 403                 default:
 404                         /* If compute shaders don't require a special value
 405                          * for this cap, we can return the same value we
 406                          * do for other shader types. */
 407                         break;
 408                 }
 409                 break;
 410         default:
 411                 return 0;
 412         }
 413
 414         switch (param) {
 415         /* Shader limits. */
 416         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 417         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 418         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 419         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 420         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 421                 return 16384;
 422         case PIPE_SHADER_CAP_MAX_INPUTS:
 423                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 424         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 425                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 426         case PIPE_SHADER_CAP_MAX_TEMPS:
 427                 return 256; /* Max native temporaries. */
 428         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 429                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 430         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 431                 return SI_NUM_CONST_BUFFERS;
 432         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 433         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 434                 return SI_NUM_SAMPLERS;
 435         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 436                 return SI_NUM_SHADER_BUFFERS;
 437         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 438                 return SI_NUM_IMAGES;
 439         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 440                 return 32;
 441         case PIPE_SHADER_CAP_PREFERRED_IR:
 442                 if (sscreen->debug_flags & DBG(NIR))
 443                         return PIPE_SHADER_IR_NIR;
 444                 return PIPE_SHADER_IR_TGSI;
 445         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 446                 return 4;
 447
 448         /* Supported boolean features. */
 449         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 450         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 451         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 452         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 453         case PIPE_SHADER_CAP_INTEGERS:
 454         case PIPE_SHADER_CAP_INT64_ATOMICS:
 455         case PIPE_SHADER_CAP_FP16:
 456         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 457         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 458         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 459         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 460         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 461         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 462                 return 1;
 463
 464         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 465                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 466                 return shader != PIPE_SHADER_GEOMETRY &&
 467                        (sscreen->llvm_has_working_vgpr_indexing ||
 468                         /* TCS and TES load inputs directly from LDS or
 469                          * offchip memory, so indirect indexing is trivial. */
 470                         shader == PIPE_SHADER_TESS_CTRL ||
 471                         shader == PIPE_SHADER_TESS_EVAL);
 472
 473         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 474                 return sscreen->llvm_has_working_vgpr_indexing ||
 475                        /* TCS stores outputs directly to memory. */
 476                        shader == PIPE_SHADER_TESS_CTRL;
 477
 478         /* Unsupported boolean features. */
 479         case PIPE_SHADER_CAP_SUBROUTINES:
 480         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 481         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 482         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 483                 return 0;
 484         }
 485         return 0;
 486 }
 487
 488 static const struct nir_shader_compiler_options nir_options = {
 489         .vertex_id_zero_based = true,
 490         .lower_scmp = true,
 491         .lower_flrp32 = true,
 492         .lower_flrp64 = true,
 493         .lower_fsat = true,
 494         .lower_fdiv = true,
 495         .lower_sub = true,
 496         .lower_ffma = true,
 497         .lower_pack_snorm_2x16 = true,
 498         .lower_pack_snorm_4x8 = true,
 499         .lower_pack_unorm_2x16 = true,
 500         .lower_pack_unorm_4x8 = true,
 501         .lower_unpack_snorm_2x16 = true,
 502         .lower_unpack_snorm_4x8 = true,
 503         .lower_unpack_unorm_2x16 = true,
 504         .lower_unpack_unorm_4x8 = true,
 505         .lower_extract_byte = true,
 506         .lower_extract_word = true,
 507         .max_unroll_iterations = 32,
 508         .native_integers = true,
 509 };
 510
 511 static const void *
 512 si_get_compiler_options(struct pipe_screen *screen,
 513                         enum pipe_shader_ir ir,
 514                         enum pipe_shader_type shader)
 515 {
 516         assert(ir == PIPE_SHADER_IR_NIR);
 517         return &nir_options;
 518 }
 519
 520 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 521 {
 522         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 523 }
 524
 525 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 526 {
 527         struct si_screen *sscreen = (struct si_screen *)pscreen;
 528
 529         ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
 530 }
 531
 532 static const char* si_get_name(struct pipe_screen *pscreen)
 533 {
 534         struct si_screen *sscreen = (struct si_screen*)pscreen;
 535
 536         return sscreen->renderer_string;
 537 }
 538
 539 static int si_get_video_param_no_decode(struct pipe_screen *screen,
 540                                         enum pipe_video_profile profile,
 541                                         enum pipe_video_entrypoint entrypoint,
 542                                         enum pipe_video_cap param)
 543 {
 544         switch (param) {
 545         case PIPE_VIDEO_CAP_SUPPORTED:
 546                 return vl_profile_supported(screen, profile, entrypoint);
 547         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 548                 return 1;
 549         case PIPE_VIDEO_CAP_MAX_WIDTH:
 550         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 551                 return vl_video_buffer_max_size(screen);
 552         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 553                 return PIPE_FORMAT_NV12;
 554         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 555                 return false;
 556         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 557                 return false;
 558         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 559                 return true;
 560         case PIPE_VIDEO_CAP_MAX_LEVEL:
 561                 return vl_level_supported(screen, profile);
 562         default:
 563                 return 0;
 564         }
 565 }
 566
 567 static int si_get_video_param(struct pipe_screen *screen,
 568                               enum pipe_video_profile profile,
 569                               enum pipe_video_entrypoint entrypoint,
 570                               enum pipe_video_cap param)
 571 {
 572         struct si_screen *sscreen = (struct si_screen *)screen;
 573         enum pipe_video_format codec = u_reduce_video_profile(profile);
 574
 575         if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 576                 switch (param) {
 577                 case PIPE_VIDEO_CAP_SUPPORTED:
 578                         return (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 579                                 (si_vce_is_fw_version_supported(sscreen) ||
 580                                 sscreen->info.family == CHIP_RAVEN)) ||
 581                                 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
 582                                 sscreen->info.family == CHIP_RAVEN);
 583                 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 584                         return 1;
 585                 case PIPE_VIDEO_CAP_MAX_WIDTH:
 586                         return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 587                 case PIPE_VIDEO_CAP_MAX_HEIGHT:
 588                         return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
 589                 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 590                         return PIPE_FORMAT_NV12;
 591                 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 592                         return false;
 593                 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 594                         return false;
 595                 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 596                         return true;
 597                 case PIPE_VIDEO_CAP_STACKED_FRAMES:
 598                         return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
 599                 default:
 600                         return 0;
 601                 }
 602         }
 603
 604         switch (param) {
 605         case PIPE_VIDEO_CAP_SUPPORTED:
 606                 switch (codec) {
 607                 case PIPE_VIDEO_FORMAT_MPEG12:
 608                         return profile != PIPE_VIDEO_PROFILE_MPEG1;
 609                 case PIPE_VIDEO_FORMAT_MPEG4:
 610                         return 1;
 611                 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 612                         if ((sscreen->info.family == CHIP_POLARIS10 ||
 613                              sscreen->info.family == CHIP_POLARIS11) &&
 614                             sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
 615                                 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 616                                 return false;
 617                         }
 618                         return true;
 619                 case PIPE_VIDEO_FORMAT_VC1:
 620                         return true;
 621                 case PIPE_VIDEO_FORMAT_HEVC:
 622                         /* Carrizo only supports HEVC Main */
 623                         if (sscreen->info.family >= CHIP_STONEY)
 624                                 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 625                                         profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 626                         else if (sscreen->info.family >= CHIP_CARRIZO)
 627                                 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 628                         return false;
 629                 case PIPE_VIDEO_FORMAT_JPEG:
 630                         if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
 631                                 return false;
 632                         if (!(sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 19)) {
 633                                 RVID_ERR("No MJPEG support for the kernel version\n");
 634                                 return false;
 635                         }
 636                         return true;
 637                 default:
 638                         return false;
 639                 }
 640         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 641                 return 1;
 642         case PIPE_VIDEO_CAP_MAX_WIDTH:
 643                 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 644         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 645                 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
 646         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 647                 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 648                         return PIPE_FORMAT_P016;
 649                 else
 650                         return PIPE_FORMAT_NV12;
 651
 652         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 653         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 654                 enum pipe_video_format format = u_reduce_video_profile(profile);
 655
 656                 if (format == PIPE_VIDEO_FORMAT_HEVC)
 657                         return false; //The firmware doesn't support interlaced HEVC.
 658                 else if (format == PIPE_VIDEO_FORMAT_JPEG)
 659                         return false;
 660                 return true;
 661         }
 662         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 663                 return true;
 664         case PIPE_VIDEO_CAP_MAX_LEVEL:
 665                 switch (profile) {
 666                 case PIPE_VIDEO_PROFILE_MPEG1:
 667                         return 0;
 668                 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 669                 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 670                         return 3;
 671                 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 672                         return 3;
 673                 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 674                         return 5;
 675                 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 676                         return 1;
 677                 case PIPE_VIDEO_PROFILE_VC1_MAIN:
 678                         return 2;
 679                 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 680                         return 4;
 681                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 682                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 683                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 684                         return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
 685                 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 686                 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 687                         return 186;
 688                 default:
 689                         return 0;
 690                 }
 691         default:
 692                 return 0;
 693         }
 694 }
 695
 696 static boolean si_vid_is_format_supported(struct pipe_screen *screen,
 697                                           enum pipe_format format,
 698                                           enum pipe_video_profile profile,
 699                                           enum pipe_video_entrypoint entrypoint)
 700 {
 701         /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
 702         if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 703                 return (format == PIPE_FORMAT_NV12) ||
 704                         (format == PIPE_FORMAT_P016);
 705
 706         /* we can only handle this one with UVD */
 707         if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 708                 return format == PIPE_FORMAT_NV12;
 709
 710         return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 711 }
 712
 713 static unsigned get_max_threads_per_block(struct si_screen *screen,
 714                                           enum pipe_shader_ir ir_type)
 715 {
 716         if (ir_type == PIPE_SHADER_IR_NATIVE)
 717                 return 256;
 718
 719         /* Only 16 waves per thread-group on gfx9. */
 720         if (screen->info.chip_class >= GFX9)
 721                 return 1024;
 722
 723         /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
 724          * round number.
 725          */
 726         return 2048;
 727 }
 728
 729 static int si_get_compute_param(struct pipe_screen *screen,
 730                                 enum pipe_shader_ir ir_type,
 731                                 enum pipe_compute_cap param,
 732                                 void *ret)
 733 {
 734         struct si_screen *sscreen = (struct si_screen *)screen;
 735
 736         //TODO: select these params by asic
 737         switch (param) {
 738         case PIPE_COMPUTE_CAP_IR_TARGET: {
 739                 const char *gpu, *triple;
 740
 741                 triple = "amdgcn-mesa-mesa3d";
 742                 gpu = ac_get_llvm_processor_name(sscreen->info.family);
 743                 if (ret) {
 744                         sprintf(ret, "%s-%s", gpu, triple);
 745                 }
 746                 /* +2 for dash and terminating NIL byte */
 747                 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 748         }
 749         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 750                 if (ret) {
 751                         uint64_t *grid_dimension = ret;
 752                         grid_dimension[0] = 3;
 753                 }
 754                 return 1 * sizeof(uint64_t);
 755
 756         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 757                 if (ret) {
 758                         uint64_t *grid_size = ret;
 759                         grid_size[0] = 65535;
 760                         grid_size[1] = 65535;
 761                         grid_size[2] = 65535;
 762                 }
 763                 return 3 * sizeof(uint64_t) ;
 764
 765         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 766                 if (ret) {
 767                         uint64_t *block_size = ret;
 768                         unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 769                         block_size[0] = threads_per_block;
 770                         block_size[1] = threads_per_block;
 771                         block_size[2] = threads_per_block;
 772                 }
 773                 return 3 * sizeof(uint64_t);
 774
 775         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 776                 if (ret) {
 777                         uint64_t *max_threads_per_block = ret;
 778                         *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 779                 }
 780                 return sizeof(uint64_t);
 781         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 782                 if (ret) {
 783                         uint32_t *address_bits = ret;
 784                         address_bits[0] = 64;
 785                 }
 786                 return 1 * sizeof(uint32_t);
 787
 788         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 789                 if (ret) {
 790                         uint64_t *max_global_size = ret;
 791                         uint64_t max_mem_alloc_size;
 792
 793                         si_get_compute_param(screen, ir_type,
 794                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 795                                 &max_mem_alloc_size);
 796
 797                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 798                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 799                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 800                          * make sure we never report more than
 801                          * 4 * MAX_MEM_ALLOC_SIZE.
 802                          */
 803                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 804                                                 MAX2(sscreen->info.gart_size,
 805                                                      sscreen->info.vram_size));
 806                 }
 807                 return sizeof(uint64_t);
 808
 809         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 810                 if (ret) {
 811                         uint64_t *max_local_size = ret;
 812                         /* Value reported by the closed source driver. */
 813                         *max_local_size = 32768;
 814                 }
 815                 return sizeof(uint64_t);
 816
 817         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 818                 if (ret) {
 819                         uint64_t *max_input_size = ret;
 820                         /* Value reported by the closed source driver. */
 821                         *max_input_size = 1024;
 822                 }
 823                 return sizeof(uint64_t);
 824
 825         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 826                 if (ret) {
 827                         uint64_t *max_mem_alloc_size = ret;
 828
 829                         *max_mem_alloc_size = sscreen->info.max_alloc_size;
 830                 }
 831                 return sizeof(uint64_t);
 832
 833         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 834                 if (ret) {
 835                         uint32_t *max_clock_frequency = ret;
 836                         *max_clock_frequency = sscreen->info.max_shader_clock;
 837                 }
 838                 return sizeof(uint32_t);
 839
 840         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 841                 if (ret) {
 842                         uint32_t *max_compute_units = ret;
 843                         *max_compute_units = sscreen->info.num_good_compute_units;
 844                 }
 845                 return sizeof(uint32_t);
 846
 847         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 848                 if (ret) {
 849                         uint32_t *images_supported = ret;
 850                         *images_supported = 0;
 851                 }
 852                 return sizeof(uint32_t);
 853         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 854                 break; /* unused */
 855         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 856                 if (ret) {
 857                         uint32_t *subgroup_size = ret;
 858                         *subgroup_size = 64;
 859                 }
 860                 return sizeof(uint32_t);
 861         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 862                 if (ret) {
 863                         uint64_t *max_variable_threads_per_block = ret;
 864                         if (ir_type == PIPE_SHADER_IR_NATIVE)
 865                                 *max_variable_threads_per_block = 0;
 866                         else
 867                                 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
 868                 }
 869                 return sizeof(uint64_t);
 870         }
 871
 872         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 873         return 0;
 874 }
 875
 876 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 877 {
 878         struct si_screen *sscreen = (struct si_screen*)screen;
 879
 880         return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
 881                         sscreen->info.clock_crystal_freq;
 882 }
 883
 884 static void si_query_memory_info(struct pipe_screen *screen,
 885                                  struct pipe_memory_info *info)
 886 {
 887         struct si_screen *sscreen = (struct si_screen*)screen;
 888         struct radeon_winsys *ws = sscreen->ws;
 889         unsigned vram_usage, gtt_usage;
 890
 891         info->total_device_memory = sscreen->info.vram_size / 1024;
 892         info->total_staging_memory = sscreen->info.gart_size / 1024;
 893
 894         /* The real TTM memory usage is somewhat random, because:
 895          *
 896          * 1) TTM delays freeing memory, because it can only free it after
 897          *    fences expire.
 898          *
 899          * 2) The memory usage can be really low if big VRAM evictions are
 900          *    taking place, but the real usage is well above the size of VRAM.
 901          *
 902          * Instead, return statistics of this process.
 903          */
 904         vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
 905         gtt_usage =  ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
 906
 907         info->avail_device_memory =
 908                 vram_usage <= info->total_device_memory ?
 909                                 info->total_device_memory - vram_usage : 0;
 910         info->avail_staging_memory =
 911                 gtt_usage <= info->total_staging_memory ?
 912                                 info->total_staging_memory - gtt_usage : 0;
 913
 914         info->device_memory_evicted =
 915                 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 916
 917         if (sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 4)
 918                 info->nr_device_memory_evictions =
 919                         ws->query_value(ws, RADEON_NUM_EVICTIONS);
 920         else
 921                 /* Just return the number of evicted 64KB pages. */
 922                 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 923 }
 924
 925 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 926 {
 927         struct si_screen *sscreen = (struct si_screen*)pscreen;
 928
 929         return sscreen->disk_shader_cache;
 930 }
 931
 932 static void si_init_renderer_string(struct si_screen *sscreen)
 933 {
 934         struct radeon_winsys *ws = sscreen->ws;
 935         char family_name[32] = {}, llvm_string[32] = {}, kernel_version[128] = {};
 936         struct utsname uname_data;
 937
 938         const char *chip_name = si_get_marketing_name(ws);
 939
 940         if (chip_name)
 941                 snprintf(family_name, sizeof(family_name), "%s / ",
 942                          si_get_family_name(sscreen) + 4);
 943         else
 944                 chip_name = si_get_family_name(sscreen);
 945
 946         if (uname(&uname_data) == 0)
 947                 snprintf(kernel_version, sizeof(kernel_version),
 948                          " / %s", uname_data.release);
 949
 950         if (HAVE_LLVM > 0) {
 951                 snprintf(llvm_string, sizeof(llvm_string),
 952                          ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
 953                          HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
 954         }
 955
 956         snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
 957                  "%s (%sDRM %i.%i.%i%s%s)",
 958                  chip_name, family_name, sscreen->info.drm_major,
 959                  sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
 960                  kernel_version, llvm_string);
 961 }
 962
 963 void si_init_screen_get_functions(struct si_screen *sscreen)
 964 {
 965         sscreen->b.get_name = si_get_name;
 966         sscreen->b.get_vendor = si_get_vendor;
 967         sscreen->b.get_device_vendor = si_get_device_vendor;
 968         sscreen->b.get_param = si_get_param;
 969         sscreen->b.get_paramf = si_get_paramf;
 970         sscreen->b.get_compute_param = si_get_compute_param;
 971         sscreen->b.get_timestamp = si_get_timestamp;
 972         sscreen->b.get_shader_param = si_get_shader_param;
 973         sscreen->b.get_compiler_options = si_get_compiler_options;
 974         sscreen->b.get_device_uuid = si_get_device_uuid;
 975         sscreen->b.get_driver_uuid = si_get_driver_uuid;
 976         sscreen->b.query_memory_info = si_query_memory_info;
 977         sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
 978
 979         if (sscreen->info.has_hw_decode) {
 980                 sscreen->b.get_video_param = si_get_video_param;
 981                 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
 982         } else {
 983                 sscreen->b.get_video_param = si_get_video_param_no_decode;
 984                 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
 985         }
 986
 987         si_init_renderer_string(sscreen);
 988 }