src/gallium/drivers/radeonsi/si_get.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "si_pipe.h"
  26 #include "radeon/radeon_video.h"
  27 #include "radeon/radeon_vce.h"
  28 #include "radeon/radeon_uvd_enc.h"
  29 #include "ac_llvm_util.h"
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32 #include "util/u_video.h"
  33 #include "compiler/nir/nir.h"
  34
  35 #include <sys/utsname.h>
  36
  37 static const char *si_get_vendor(struct pipe_screen *pscreen)
  38 {
  39         /* Don't change this. Games such as Alien Isolation are broken if this
  40          * returns "Advanced Micro Devices, Inc."
  41          */
  42         return "X.Org";
  43 }
  44
  45 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
  46 {
  47         return "AMD";
  48 }
  49
  50 static const char *si_get_marketing_name(struct radeon_winsys *ws)
  51 {
  52         if (!ws->get_chip_name)
  53                 return NULL;
  54         return ws->get_chip_name(ws);
  55 }
  56
  57 const char *si_get_family_name(const struct si_screen *sscreen)
  58 {
  59         switch (sscreen->info.family) {
  60         case CHIP_TAHITI: return "AMD TAHITI";
  61         case CHIP_PITCAIRN: return "AMD PITCAIRN";
  62         case CHIP_VERDE: return "AMD CAPE VERDE";
  63         case CHIP_OLAND: return "AMD OLAND";
  64         case CHIP_HAINAN: return "AMD HAINAN";
  65         case CHIP_BONAIRE: return "AMD BONAIRE";
  66         case CHIP_KAVERI: return "AMD KAVERI";
  67         case CHIP_KABINI: return "AMD KABINI";
  68         case CHIP_HAWAII: return "AMD HAWAII";
  69         case CHIP_MULLINS: return "AMD MULLINS";
  70         case CHIP_TONGA: return "AMD TONGA";
  71         case CHIP_ICELAND: return "AMD ICELAND";
  72         case CHIP_CARRIZO: return "AMD CARRIZO";
  73         case CHIP_FIJI: return "AMD FIJI";
  74         case CHIP_STONEY: return "AMD STONEY";
  75         case CHIP_POLARIS10: return "AMD POLARIS10";
  76         case CHIP_POLARIS11: return "AMD POLARIS11";
  77         case CHIP_POLARIS12: return "AMD POLARIS12";
  78         case CHIP_VEGAM: return "AMD VEGAM";
  79         case CHIP_VEGA10: return "AMD VEGA10";
  80         case CHIP_VEGA12: return "AMD VEGA12";
  81         case CHIP_RAVEN: return "AMD RAVEN";
  82         default: return "AMD unknown";
  83         }
  84 }
  85
  86 static bool si_have_tgsi_compute(struct si_screen *sscreen)
  87 {
  88         /* Old kernels disallowed some register writes for SI
  89          * that are used for indirect dispatches. */
  90         return (sscreen->info.chip_class >= CIK ||
  91                 sscreen->info.drm_major == 3 ||
  92                 (sscreen->info.drm_major == 2 &&
  93                  sscreen->info.drm_minor >= 45));
  94 }
  95
  96 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  97 {
  98         struct si_screen *sscreen = (struct si_screen *)pscreen;
  99
 100         switch (param) {
 101         /* Supported features (boolean caps). */
 102         case PIPE_CAP_ACCELERATED:
 103         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 104         case PIPE_CAP_ANISOTROPIC_FILTER:
 105         case PIPE_CAP_POINT_SPRITE:
 106         case PIPE_CAP_OCCLUSION_QUERY:
 107         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 108         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 109         case PIPE_CAP_TEXTURE_SWIZZLE:
 110         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 111         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 112         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 113         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 114         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 115         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 116         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 117         case PIPE_CAP_SM3:
 118         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 119         case PIPE_CAP_PRIMITIVE_RESTART:
 120         case PIPE_CAP_CONDITIONAL_RENDER:
 121         case PIPE_CAP_TEXTURE_BARRIER:
 122         case PIPE_CAP_INDEP_BLEND_ENABLE:
 123         case PIPE_CAP_INDEP_BLEND_FUNC:
 124         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 125         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 126         case PIPE_CAP_START_INSTANCE:
 127         case PIPE_CAP_NPOT_TEXTURES:
 128         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 129         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 130         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 131         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 132         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 133         case PIPE_CAP_TGSI_INSTANCEID:
 134         case PIPE_CAP_COMPUTE:
 135         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 136         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 137         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 138         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 139         case PIPE_CAP_CUBE_MAP_ARRAY:
 140         case PIPE_CAP_SAMPLE_SHADING:
 141         case PIPE_CAP_DRAW_INDIRECT:
 142         case PIPE_CAP_CLIP_HALFZ:
 143         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 144         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 145         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 146         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 147         case PIPE_CAP_TGSI_TEXCOORD:
 148         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 149         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 150         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 151         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 152         case PIPE_CAP_SHAREABLE_SHADERS:
 153         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 154         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 155         case PIPE_CAP_TEXTURE_QUERY_LOD:
 156         case PIPE_CAP_TEXTURE_GATHER_SM5:
 157         case PIPE_CAP_TGSI_TXQS:
 158         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 159         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 160         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 161         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 162         case PIPE_CAP_INVALIDATE_BUFFER:
 163         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 164         case PIPE_CAP_QUERY_MEMORY_INFO:
 165         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 166         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 167         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 168         case PIPE_CAP_GENERATE_MIPMAP:
 169         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 170         case PIPE_CAP_STRING_MARKER:
 171         case PIPE_CAP_CLEAR_TEXTURE:
 172         case PIPE_CAP_CULL_DISTANCE:
 173         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 174         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 175         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 176         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 177         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 178         case PIPE_CAP_DOUBLES:
 179         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 180         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 181         case PIPE_CAP_BINDLESS_TEXTURE:
 182         case PIPE_CAP_QUERY_TIMESTAMP:
 183         case PIPE_CAP_QUERY_TIME_ELAPSED:
 184         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 185         case PIPE_CAP_QUERY_SO_OVERFLOW:
 186         case PIPE_CAP_MEMOBJ:
 187         case PIPE_CAP_LOAD_CONSTBUF:
 188         case PIPE_CAP_INT64:
 189         case PIPE_CAP_INT64_DIVMOD:
 190         case PIPE_CAP_TGSI_CLOCK:
 191         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 192         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 193         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 194         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 195         case PIPE_CAP_TGSI_VOTE:
 196         case PIPE_CAP_TGSI_FS_FBFETCH:
 197                 return 1;
 198
 199         case PIPE_CAP_TGSI_BALLOT:
 200                 return HAVE_LLVM >= 0x0500;
 201
 202         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 203                 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 204
 205         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 206                 return (sscreen->info.drm_major == 2 &&
 207                         sscreen->info.drm_minor >= 43) ||
 208                        sscreen->info.drm_major == 3;
 209
 210         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 211                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 212                 return sscreen->info.chip_class < CIK ||
 213                        (sscreen->info.drm_major == 2 &&
 214                         sscreen->info.drm_minor >= 35) ||
 215                        sscreen->info.drm_major == 3;
 216
 217         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 218                 return SI_MAP_BUFFER_ALIGNMENT;
 219
 220         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 221         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 222         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 223         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 224         case PIPE_CAP_MAX_VERTEX_STREAMS:
 225         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 226                 return 4;
 227
 228         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 229                 if (si_have_tgsi_compute(sscreen))
 230                         return 450;
 231                 return 420;
 232
 233         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 234                 return MIN2(sscreen->info.max_alloc_size, INT_MAX);
 235
 236         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 237         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 238         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 239                 /* SI doesn't support unaligned loads.
 240                  * CIK needs DRM 2.50.0 on radeon. */
 241                 return sscreen->info.chip_class == SI ||
 242                        (sscreen->info.drm_major == 2 &&
 243                         sscreen->info.drm_minor < 50);
 244
 245         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 246                 /* TODO: GFX9 hangs. */
 247                 if (sscreen->info.chip_class >= GFX9)
 248                         return 0;
 249                 /* Disable on SI due to VM faults in CP DMA. Enable once these
 250                  * faults are mitigated in software.
 251                  */
 252                 if (sscreen->info.chip_class >= CIK &&
 253                     sscreen->info.drm_major == 3 &&
 254                     sscreen->info.drm_minor >= 13)
 255                         return RADEON_SPARSE_PAGE_SIZE;
 256                 return 0;
 257
 258         case PIPE_CAP_PACKED_UNIFORMS:
 259                 if (sscreen->debug_flags & DBG(NIR))
 260                         return 1;
 261                 return 0;
 262
 263         /* Unsupported features. */
 264         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 265         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 266         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 267         case PIPE_CAP_USER_VERTEX_BUFFERS:
 268         case PIPE_CAP_FAKE_SW_MSAA:
 269         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 270         case PIPE_CAP_VERTEXID_NOBASE:
 271         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 272         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 273         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 274         case PIPE_CAP_UMA:
 275         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 276         case PIPE_CAP_POST_DEPTH_COVERAGE:
 277         case PIPE_CAP_TILE_RASTER_ORDER:
 278         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 279         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 280                 return 0;
 281
 282         case PIPE_CAP_FENCE_SIGNAL:
 283                 return sscreen->info.has_syncobj;
 284
 285         case PIPE_CAP_CONSTBUF0_FLAGS:
 286                 return SI_RESOURCE_FLAG_32BIT;
 287
 288         case PIPE_CAP_NATIVE_FENCE_FD:
 289                 return sscreen->info.has_fence_to_handle;
 290
 291         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 292                 return si_have_tgsi_compute(sscreen);
 293
 294         case PIPE_CAP_DRAW_PARAMETERS:
 295         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 296         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 297                 return sscreen->has_draw_indirect_multi;
 298
 299         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 300                 return 30;
 301
 302         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 303                 return sscreen->info.chip_class <= VI ?
 304                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 305
 306         /* Stream output. */
 307         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 308         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 309                 return 32*4;
 310
 311         /* Geometry shader output. */
 312         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 313                 return 1024;
 314         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 315                 return 4095;
 316
 317         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 318                 return 2048;
 319
 320         /* Texturing. */
 321         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 322         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 323                 return 15; /* 16384 */
 324         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 325                 /* textures support 8192, but layered rendering supports 2048 */
 326                 return 12;
 327         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 328                 /* textures support 8192, but layered rendering supports 2048 */
 329                 return 2048;
 330
 331         /* Viewports and render targets. */
 332         case PIPE_CAP_MAX_VIEWPORTS:
 333                 return SI_MAX_VIEWPORTS;
 334         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 335         case PIPE_CAP_MAX_RENDER_TARGETS:
 336                 return 8;
 337
 338         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 339         case PIPE_CAP_MIN_TEXEL_OFFSET:
 340                 return -32;
 341
 342         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 343         case PIPE_CAP_MAX_TEXEL_OFFSET:
 344                 return 31;
 345
 346         case PIPE_CAP_ENDIANNESS:
 347                 return PIPE_ENDIAN_LITTLE;
 348
 349         case PIPE_CAP_VENDOR_ID:
 350                 return ATI_VENDOR_ID;
 351         case PIPE_CAP_DEVICE_ID:
 352                 return sscreen->info.pci_id;
 353         case PIPE_CAP_VIDEO_MEMORY:
 354                 return sscreen->info.vram_size >> 20;
 355         case PIPE_CAP_PCI_GROUP:
 356                 return sscreen->info.pci_domain;
 357         case PIPE_CAP_PCI_BUS:
 358                 return sscreen->info.pci_bus;
 359         case PIPE_CAP_PCI_DEVICE:
 360                 return sscreen->info.pci_dev;
 361         case PIPE_CAP_PCI_FUNCTION:
 362                 return sscreen->info.pci_func;
 363         }
 364         return 0;
 365 }
 366
 367 static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
 368 {
 369         switch (param) {
 370         case PIPE_CAPF_MAX_LINE_WIDTH:
 371         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 372         case PIPE_CAPF_MAX_POINT_WIDTH:
 373         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 374                 return 8192.0f;
 375         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 376                 return 16.0f;
 377         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 378                 return 16.0f;
 379         }
 380         return 0.0f;
 381 }
 382
 383 static int si_get_shader_param(struct pipe_screen* pscreen,
 384                                enum pipe_shader_type shader,
 385                                enum pipe_shader_cap param)
 386 {
 387         struct si_screen *sscreen = (struct si_screen *)pscreen;
 388
 389         switch(shader)
 390         {
 391         case PIPE_SHADER_FRAGMENT:
 392         case PIPE_SHADER_VERTEX:
 393         case PIPE_SHADER_GEOMETRY:
 394         case PIPE_SHADER_TESS_CTRL:
 395         case PIPE_SHADER_TESS_EVAL:
 396                 break;
 397         case PIPE_SHADER_COMPUTE:
 398                 switch (param) {
 399                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 400                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 401
 402                         if (si_have_tgsi_compute(sscreen))
 403                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 404
 405                         return ir;
 406                 }
 407
 408                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 409                         uint64_t max_const_buffer_size;
 410                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 411                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 412                                 &max_const_buffer_size);
 413                         return MIN2(max_const_buffer_size, INT_MAX);
 414                 }
 415                 default:
 416                         /* If compute shaders don't require a special value
 417                          * for this cap, we can return the same value we
 418                          * do for other shader types. */
 419                         break;
 420                 }
 421                 break;
 422         default:
 423                 return 0;
 424         }
 425
 426         switch (param) {
 427         /* Shader limits. */
 428         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 429         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 430         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 431         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 432         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 433                 return 16384;
 434         case PIPE_SHADER_CAP_MAX_INPUTS:
 435                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 436         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 437                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 438         case PIPE_SHADER_CAP_MAX_TEMPS:
 439                 return 256; /* Max native temporaries. */
 440         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 441                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 442         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 443                 return SI_NUM_CONST_BUFFERS;
 444         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 445         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 446                 return SI_NUM_SAMPLERS;
 447         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 448                 return SI_NUM_SHADER_BUFFERS;
 449         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 450                 return SI_NUM_IMAGES;
 451         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 452                 if (sscreen->debug_flags & DBG(NIR))
 453                         return 0;
 454                 return 32;
 455         case PIPE_SHADER_CAP_PREFERRED_IR:
 456                 if (sscreen->debug_flags & DBG(NIR))
 457                         return PIPE_SHADER_IR_NIR;
 458                 return PIPE_SHADER_IR_TGSI;
 459         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 460                 return 4;
 461
 462         /* Supported boolean features. */
 463         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 464         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 465         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 466         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 467         case PIPE_SHADER_CAP_INTEGERS:
 468         case PIPE_SHADER_CAP_INT64_ATOMICS:
 469         case PIPE_SHADER_CAP_FP16:
 470         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 471         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 472         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 473         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 474         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 475         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 476                 return 1;
 477
 478         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 479                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 480                 return shader != PIPE_SHADER_GEOMETRY &&
 481                        (sscreen->llvm_has_working_vgpr_indexing ||
 482                         /* TCS and TES load inputs directly from LDS or
 483                          * offchip memory, so indirect indexing is trivial. */
 484                         shader == PIPE_SHADER_TESS_CTRL ||
 485                         shader == PIPE_SHADER_TESS_EVAL);
 486
 487         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 488                 return sscreen->llvm_has_working_vgpr_indexing ||
 489                        /* TCS stores outputs directly to memory. */
 490                        shader == PIPE_SHADER_TESS_CTRL;
 491
 492         /* Unsupported boolean features. */
 493         case PIPE_SHADER_CAP_SUBROUTINES:
 494         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 495         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 496         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 497                 return 0;
 498         }
 499         return 0;
 500 }
 501
 502 static const struct nir_shader_compiler_options nir_options = {
 503         .lower_scmp = true,
 504         .lower_flrp32 = true,
 505         .lower_flrp64 = true,
 506         .lower_fpow = true,
 507         .lower_fsat = true,
 508         .lower_fdiv = true,
 509         .lower_sub = true,
 510         .lower_ffma = true,
 511         .lower_pack_snorm_2x16 = true,
 512         .lower_pack_snorm_4x8 = true,
 513         .lower_pack_unorm_2x16 = true,
 514         .lower_pack_unorm_4x8 = true,
 515         .lower_unpack_snorm_2x16 = true,
 516         .lower_unpack_snorm_4x8 = true,
 517         .lower_unpack_unorm_2x16 = true,
 518         .lower_unpack_unorm_4x8 = true,
 519         .lower_extract_byte = true,
 520         .lower_extract_word = true,
 521         .max_unroll_iterations = 32,
 522         .native_integers = true,
 523 };
 524
 525 static const void *
 526 si_get_compiler_options(struct pipe_screen *screen,
 527                         enum pipe_shader_ir ir,
 528                         enum pipe_shader_type shader)
 529 {
 530         assert(ir == PIPE_SHADER_IR_NIR);
 531         return &nir_options;
 532 }
 533
 534 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 535 {
 536         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 537 }
 538
 539 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 540 {
 541         struct si_screen *sscreen = (struct si_screen *)pscreen;
 542
 543         ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
 544 }
 545
 546 static const char* si_get_name(struct pipe_screen *pscreen)
 547 {
 548         struct si_screen *sscreen = (struct si_screen*)pscreen;
 549
 550         return sscreen->renderer_string;
 551 }
 552
 553 static int si_get_video_param_no_decode(struct pipe_screen *screen,
 554                                         enum pipe_video_profile profile,
 555                                         enum pipe_video_entrypoint entrypoint,
 556                                         enum pipe_video_cap param)
 557 {
 558         switch (param) {
 559         case PIPE_VIDEO_CAP_SUPPORTED:
 560                 return vl_profile_supported(screen, profile, entrypoint);
 561         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 562                 return 1;
 563         case PIPE_VIDEO_CAP_MAX_WIDTH:
 564         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 565                 return vl_video_buffer_max_size(screen);
 566         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 567                 return PIPE_FORMAT_NV12;
 568         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 569                 return false;
 570         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 571                 return false;
 572         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 573                 return true;
 574         case PIPE_VIDEO_CAP_MAX_LEVEL:
 575                 return vl_level_supported(screen, profile);
 576         default:
 577                 return 0;
 578         }
 579 }
 580
 581 static int si_get_video_param(struct pipe_screen *screen,
 582                               enum pipe_video_profile profile,
 583                               enum pipe_video_entrypoint entrypoint,
 584                               enum pipe_video_cap param)
 585 {
 586         struct si_screen *sscreen = (struct si_screen *)screen;
 587         enum pipe_video_format codec = u_reduce_video_profile(profile);
 588
 589         if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 590                 switch (param) {
 591                 case PIPE_VIDEO_CAP_SUPPORTED:
 592                         return (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 593                                 (si_vce_is_fw_version_supported(sscreen) ||
 594                                 sscreen->info.family == CHIP_RAVEN)) ||
 595                                 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
 596                                 (sscreen->info.family == CHIP_RAVEN ||
 597                                 si_radeon_uvd_enc_supported(sscreen)));
 598                 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 599                         return 1;
 600                 case PIPE_VIDEO_CAP_MAX_WIDTH:
 601                         return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 602                 case PIPE_VIDEO_CAP_MAX_HEIGHT:
 603                         return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
 604                 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 605                         return PIPE_FORMAT_NV12;
 606                 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 607                         return false;
 608                 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 609                         return false;
 610                 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 611                         return true;
 612                 case PIPE_VIDEO_CAP_STACKED_FRAMES:
 613                         return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
 614                 default:
 615                         return 0;
 616                 }
 617         }
 618
 619         switch (param) {
 620         case PIPE_VIDEO_CAP_SUPPORTED:
 621                 switch (codec) {
 622                 case PIPE_VIDEO_FORMAT_MPEG12:
 623                         return profile != PIPE_VIDEO_PROFILE_MPEG1;
 624                 case PIPE_VIDEO_FORMAT_MPEG4:
 625                         return 1;
 626                 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 627                         if ((sscreen->info.family == CHIP_POLARIS10 ||
 628                              sscreen->info.family == CHIP_POLARIS11) &&
 629                             sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
 630                                 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 631                                 return false;
 632                         }
 633                         return true;
 634                 case PIPE_VIDEO_FORMAT_VC1:
 635                         return true;
 636                 case PIPE_VIDEO_FORMAT_HEVC:
 637                         /* Carrizo only supports HEVC Main */
 638                         if (sscreen->info.family >= CHIP_STONEY)
 639                                 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 640                                         profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 641                         else if (sscreen->info.family >= CHIP_CARRIZO)
 642                                 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 643                         return false;
 644                 case PIPE_VIDEO_FORMAT_JPEG:
 645                         if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
 646                                 return false;
 647                         if (!(sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 19)) {
 648                                 RVID_ERR("No MJPEG support for the kernel version\n");
 649                                 return false;
 650                         }
 651                         return true;
 652                 case PIPE_VIDEO_FORMAT_VP9:
 653                         if (sscreen->info.family < CHIP_RAVEN)
 654                                 return false;
 655                         return true;
 656                 default:
 657                         return false;
 658                 }
 659         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 660                 return 1;
 661         case PIPE_VIDEO_CAP_MAX_WIDTH:
 662                 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 663         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 664                 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
 665         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 666                 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 ||
 667                     profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 668                         return PIPE_FORMAT_P016;
 669                 else
 670                         return PIPE_FORMAT_NV12;
 671
 672         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 673         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 674                 enum pipe_video_format format = u_reduce_video_profile(profile);
 675
 676                 if (format == PIPE_VIDEO_FORMAT_HEVC)
 677                         return false; //The firmware doesn't support interlaced HEVC.
 678                 else if (format == PIPE_VIDEO_FORMAT_JPEG)
 679                         return false;
 680                 else if (format == PIPE_VIDEO_FORMAT_VP9)
 681                         return false;
 682                 return true;
 683         }
 684         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 685                 return true;
 686         case PIPE_VIDEO_CAP_MAX_LEVEL:
 687                 switch (profile) {
 688                 case PIPE_VIDEO_PROFILE_MPEG1:
 689                         return 0;
 690                 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 691                 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 692                         return 3;
 693                 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 694                         return 3;
 695                 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 696                         return 5;
 697                 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 698                         return 1;
 699                 case PIPE_VIDEO_PROFILE_VC1_MAIN:
 700                         return 2;
 701                 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 702                         return 4;
 703                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 704                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 705                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 706                         return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
 707                 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 708                 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 709                         return 186;
 710                 default:
 711                         return 0;
 712                 }
 713         default:
 714                 return 0;
 715         }
 716 }
 717
 718 static boolean si_vid_is_format_supported(struct pipe_screen *screen,
 719                                           enum pipe_format format,
 720                                           enum pipe_video_profile profile,
 721                                           enum pipe_video_entrypoint entrypoint)
 722 {
 723         /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
 724         if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 725                 return (format == PIPE_FORMAT_NV12) ||
 726                         (format == PIPE_FORMAT_P016);
 727
 728         /* we can only handle this one with UVD */
 729         if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 730                 return format == PIPE_FORMAT_NV12;
 731
 732         return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 733 }
 734
 735 static unsigned get_max_threads_per_block(struct si_screen *screen,
 736                                           enum pipe_shader_ir ir_type)
 737 {
 738         if (ir_type == PIPE_SHADER_IR_NATIVE)
 739                 return 256;
 740
 741         /* Only 16 waves per thread-group on gfx9. */
 742         if (screen->info.chip_class >= GFX9)
 743                 return 1024;
 744
 745         /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
 746          * round number.
 747          */
 748         return 2048;
 749 }
 750
 751 static int si_get_compute_param(struct pipe_screen *screen,
 752                                 enum pipe_shader_ir ir_type,
 753                                 enum pipe_compute_cap param,
 754                                 void *ret)
 755 {
 756         struct si_screen *sscreen = (struct si_screen *)screen;
 757
 758         //TODO: select these params by asic
 759         switch (param) {
 760         case PIPE_COMPUTE_CAP_IR_TARGET: {
 761                 const char *gpu, *triple;
 762
 763                 triple = "amdgcn-mesa-mesa3d";
 764                 gpu = ac_get_llvm_processor_name(sscreen->info.family);
 765                 if (ret) {
 766                         sprintf(ret, "%s-%s", gpu, triple);
 767                 }
 768                 /* +2 for dash and terminating NIL byte */
 769                 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 770         }
 771         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 772                 if (ret) {
 773                         uint64_t *grid_dimension = ret;
 774                         grid_dimension[0] = 3;
 775                 }
 776                 return 1 * sizeof(uint64_t);
 777
 778         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 779                 if (ret) {
 780                         uint64_t *grid_size = ret;
 781                         grid_size[0] = 65535;
 782                         grid_size[1] = 65535;
 783                         grid_size[2] = 65535;
 784                 }
 785                 return 3 * sizeof(uint64_t) ;
 786
 787         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 788                 if (ret) {
 789                         uint64_t *block_size = ret;
 790                         unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 791                         block_size[0] = threads_per_block;
 792                         block_size[1] = threads_per_block;
 793                         block_size[2] = threads_per_block;
 794                 }
 795                 return 3 * sizeof(uint64_t);
 796
 797         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 798                 if (ret) {
 799                         uint64_t *max_threads_per_block = ret;
 800                         *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 801                 }
 802                 return sizeof(uint64_t);
 803         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 804                 if (ret) {
 805                         uint32_t *address_bits = ret;
 806                         address_bits[0] = 64;
 807                 }
 808                 return 1 * sizeof(uint32_t);
 809
 810         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 811                 if (ret) {
 812                         uint64_t *max_global_size = ret;
 813                         uint64_t max_mem_alloc_size;
 814
 815                         si_get_compute_param(screen, ir_type,
 816                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 817                                 &max_mem_alloc_size);
 818
 819                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 820                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 821                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 822                          * make sure we never report more than
 823                          * 4 * MAX_MEM_ALLOC_SIZE.
 824                          */
 825                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 826                                                 MAX2(sscreen->info.gart_size,
 827                                                      sscreen->info.vram_size));
 828                 }
 829                 return sizeof(uint64_t);
 830
 831         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 832                 if (ret) {
 833                         uint64_t *max_local_size = ret;
 834                         /* Value reported by the closed source driver. */
 835                         *max_local_size = 32768;
 836                 }
 837                 return sizeof(uint64_t);
 838
 839         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 840                 if (ret) {
 841                         uint64_t *max_input_size = ret;
 842                         /* Value reported by the closed source driver. */
 843                         *max_input_size = 1024;
 844                 }
 845                 return sizeof(uint64_t);
 846
 847         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 848                 if (ret) {
 849                         uint64_t *max_mem_alloc_size = ret;
 850
 851                         *max_mem_alloc_size = sscreen->info.max_alloc_size;
 852                 }
 853                 return sizeof(uint64_t);
 854
 855         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 856                 if (ret) {
 857                         uint32_t *max_clock_frequency = ret;
 858                         *max_clock_frequency = sscreen->info.max_shader_clock;
 859                 }
 860                 return sizeof(uint32_t);
 861
 862         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 863                 if (ret) {
 864                         uint32_t *max_compute_units = ret;
 865                         *max_compute_units = sscreen->info.num_good_compute_units;
 866                 }
 867                 return sizeof(uint32_t);
 868
 869         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 870                 if (ret) {
 871                         uint32_t *images_supported = ret;
 872                         *images_supported = 0;
 873                 }
 874                 return sizeof(uint32_t);
 875         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 876                 break; /* unused */
 877         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 878                 if (ret) {
 879                         uint32_t *subgroup_size = ret;
 880                         *subgroup_size = 64;
 881                 }
 882                 return sizeof(uint32_t);
 883         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 884                 if (ret) {
 885                         uint64_t *max_variable_threads_per_block = ret;
 886                         if (ir_type == PIPE_SHADER_IR_NATIVE)
 887                                 *max_variable_threads_per_block = 0;
 888                         else
 889                                 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
 890                 }
 891                 return sizeof(uint64_t);
 892         }
 893
 894         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 895         return 0;
 896 }
 897
 898 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 899 {
 900         struct si_screen *sscreen = (struct si_screen*)screen;
 901
 902         return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
 903                         sscreen->info.clock_crystal_freq;
 904 }
 905
 906 static void si_query_memory_info(struct pipe_screen *screen,
 907                                  struct pipe_memory_info *info)
 908 {
 909         struct si_screen *sscreen = (struct si_screen*)screen;
 910         struct radeon_winsys *ws = sscreen->ws;
 911         unsigned vram_usage, gtt_usage;
 912
 913         info->total_device_memory = sscreen->info.vram_size / 1024;
 914         info->total_staging_memory = sscreen->info.gart_size / 1024;
 915
 916         /* The real TTM memory usage is somewhat random, because:
 917          *
 918          * 1) TTM delays freeing memory, because it can only free it after
 919          *    fences expire.
 920          *
 921          * 2) The memory usage can be really low if big VRAM evictions are
 922          *    taking place, but the real usage is well above the size of VRAM.
 923          *
 924          * Instead, return statistics of this process.
 925          */
 926         vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
 927         gtt_usage =  ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
 928
 929         info->avail_device_memory =
 930                 vram_usage <= info->total_device_memory ?
 931                                 info->total_device_memory - vram_usage : 0;
 932         info->avail_staging_memory =
 933                 gtt_usage <= info->total_staging_memory ?
 934                                 info->total_staging_memory - gtt_usage : 0;
 935
 936         info->device_memory_evicted =
 937                 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 938
 939         if (sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 4)
 940                 info->nr_device_memory_evictions =
 941                         ws->query_value(ws, RADEON_NUM_EVICTIONS);
 942         else
 943                 /* Just return the number of evicted 64KB pages. */
 944                 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 945 }
 946
 947 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 948 {
 949         struct si_screen *sscreen = (struct si_screen*)pscreen;
 950
 951         return sscreen->disk_shader_cache;
 952 }
 953
 954 static void si_init_renderer_string(struct si_screen *sscreen)
 955 {
 956         struct radeon_winsys *ws = sscreen->ws;
 957         char family_name[32] = {}, kernel_version[128] = {};
 958         struct utsname uname_data;
 959
 960         const char *chip_name = si_get_marketing_name(ws);
 961
 962         if (chip_name)
 963                 snprintf(family_name, sizeof(family_name), "%s, ",
 964                          si_get_family_name(sscreen) + 4);
 965         else
 966                 chip_name = si_get_family_name(sscreen);
 967
 968         if (uname(&uname_data) == 0)
 969                 snprintf(kernel_version, sizeof(kernel_version),
 970                          ", %s", uname_data.release);
 971
 972         snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
 973                  "%s (%sDRM %i.%i.%i%s, LLVM %i.%i.%i)",
 974                  chip_name, family_name, sscreen->info.drm_major,
 975                  sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
 976                  kernel_version,
 977                  (HAVE_LLVM >> 8) & 0xff,
 978                  HAVE_LLVM & 0xff,
 979                  MESA_LLVM_VERSION_PATCH);
 980 }
 981
 982 void si_init_screen_get_functions(struct si_screen *sscreen)
 983 {
 984         sscreen->b.get_name = si_get_name;
 985         sscreen->b.get_vendor = si_get_vendor;
 986         sscreen->b.get_device_vendor = si_get_device_vendor;
 987         sscreen->b.get_param = si_get_param;
 988         sscreen->b.get_paramf = si_get_paramf;
 989         sscreen->b.get_compute_param = si_get_compute_param;
 990         sscreen->b.get_timestamp = si_get_timestamp;
 991         sscreen->b.get_shader_param = si_get_shader_param;
 992         sscreen->b.get_compiler_options = si_get_compiler_options;
 993         sscreen->b.get_device_uuid = si_get_device_uuid;
 994         sscreen->b.get_driver_uuid = si_get_driver_uuid;
 995         sscreen->b.query_memory_info = si_query_memory_info;
 996         sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
 997
 998         if (sscreen->info.has_hw_decode) {
 999                 sscreen->b.get_video_param = si_get_video_param;
1000                 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
1001         } else {
1002                 sscreen->b.get_video_param = si_get_video_param_no_decode;
1003                 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1004         }
1005
1006         si_init_renderer_string(sscreen);
1007 }