src/gallium/drivers/radeonsi/si_get.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "radeon/radeon_video.h"
  26 #include "radeon/radeon_vce.h"
  27 #include "ac_llvm_util.h"
  28 #include "vl/vl_decoder.h"
  29 #include "vl/vl_video_buffer.h"
  30 #include "util/u_video.h"
  31 #include "compiler/nir/nir.h"
  32
  33 #include <sys/utsname.h>
  34
  35 static const char *si_get_vendor(struct pipe_screen *pscreen)
  36 {
  37         /* Don't change this. Games such as Alien Isolation are broken if this
  38          * returns "Advanced Micro Devices, Inc."
  39          */
  40         return "X.Org";
  41 }
  42
  43 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
  44 {
  45         return "AMD";
  46 }
  47
  48 static const char *si_get_marketing_name(struct radeon_winsys *ws)
  49 {
  50         if (!ws->get_chip_name)
  51                 return NULL;
  52         return ws->get_chip_name(ws);
  53 }
  54
  55 const char *si_get_family_name(const struct si_screen *sscreen)
  56 {
  57         switch (sscreen->info.family) {
  58         case CHIP_TAHITI: return "AMD TAHITI";
  59         case CHIP_PITCAIRN: return "AMD PITCAIRN";
  60         case CHIP_VERDE: return "AMD CAPE VERDE";
  61         case CHIP_OLAND: return "AMD OLAND";
  62         case CHIP_HAINAN: return "AMD HAINAN";
  63         case CHIP_BONAIRE: return "AMD BONAIRE";
  64         case CHIP_KAVERI: return "AMD KAVERI";
  65         case CHIP_KABINI: return "AMD KABINI";
  66         case CHIP_HAWAII: return "AMD HAWAII";
  67         case CHIP_MULLINS: return "AMD MULLINS";
  68         case CHIP_TONGA: return "AMD TONGA";
  69         case CHIP_ICELAND: return "AMD ICELAND";
  70         case CHIP_CARRIZO: return "AMD CARRIZO";
  71         case CHIP_FIJI: return "AMD FIJI";
  72         case CHIP_POLARIS10: return "AMD POLARIS10";
  73         case CHIP_POLARIS11: return "AMD POLARIS11";
  74         case CHIP_POLARIS12: return "AMD POLARIS12";
  75         case CHIP_STONEY: return "AMD STONEY";
  76         case CHIP_VEGA10: return "AMD VEGA10";
  77         case CHIP_RAVEN: return "AMD RAVEN";
  78         default: return "AMD unknown";
  79         }
  80 }
  81
  82 static bool si_have_tgsi_compute(struct si_screen *sscreen)
  83 {
  84         /* Old kernels disallowed some register writes for SI
  85          * that are used for indirect dispatches. */
  86         return (sscreen->info.chip_class >= CIK ||
  87                 sscreen->info.drm_major == 3 ||
  88                 (sscreen->info.drm_major == 2 &&
  89                  sscreen->info.drm_minor >= 45));
  90 }
  91
  92 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  93 {
  94         struct si_screen *sscreen = (struct si_screen *)pscreen;
  95
  96         switch (param) {
  97         /* Supported features (boolean caps). */
  98         case PIPE_CAP_ACCELERATED:
  99         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 100         case PIPE_CAP_ANISOTROPIC_FILTER:
 101         case PIPE_CAP_POINT_SPRITE:
 102         case PIPE_CAP_OCCLUSION_QUERY:
 103         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 104         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 105         case PIPE_CAP_TEXTURE_SWIZZLE:
 106         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 107         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 108         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 109         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 110         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 111         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 112         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 113         case PIPE_CAP_SM3:
 114         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 115         case PIPE_CAP_PRIMITIVE_RESTART:
 116         case PIPE_CAP_CONDITIONAL_RENDER:
 117         case PIPE_CAP_TEXTURE_BARRIER:
 118         case PIPE_CAP_INDEP_BLEND_ENABLE:
 119         case PIPE_CAP_INDEP_BLEND_FUNC:
 120         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 121         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 122         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 123         case PIPE_CAP_START_INSTANCE:
 124         case PIPE_CAP_NPOT_TEXTURES:
 125         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 126         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 127         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 128         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 129         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 130         case PIPE_CAP_TGSI_INSTANCEID:
 131         case PIPE_CAP_COMPUTE:
 132         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 133         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 134         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 135         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 136         case PIPE_CAP_CUBE_MAP_ARRAY:
 137         case PIPE_CAP_SAMPLE_SHADING:
 138         case PIPE_CAP_DRAW_INDIRECT:
 139         case PIPE_CAP_CLIP_HALFZ:
 140         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 141         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 142         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 143         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 144         case PIPE_CAP_TGSI_TEXCOORD:
 145         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 146         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 147         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 148         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 149         case PIPE_CAP_SHAREABLE_SHADERS:
 150         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 151         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 152         case PIPE_CAP_TEXTURE_QUERY_LOD:
 153         case PIPE_CAP_TEXTURE_GATHER_SM5:
 154         case PIPE_CAP_TGSI_TXQS:
 155         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 156         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 157         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 158         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 159         case PIPE_CAP_INVALIDATE_BUFFER:
 160         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 161         case PIPE_CAP_QUERY_MEMORY_INFO:
 162         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 163         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 164         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 165         case PIPE_CAP_GENERATE_MIPMAP:
 166         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 167         case PIPE_CAP_STRING_MARKER:
 168         case PIPE_CAP_CLEAR_TEXTURE:
 169         case PIPE_CAP_CULL_DISTANCE:
 170         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 171         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 172         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 173         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 174         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 175         case PIPE_CAP_DOUBLES:
 176         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 177         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 178         case PIPE_CAP_BINDLESS_TEXTURE:
 179         case PIPE_CAP_QUERY_TIMESTAMP:
 180         case PIPE_CAP_QUERY_TIME_ELAPSED:
 181         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 182         case PIPE_CAP_QUERY_SO_OVERFLOW:
 183         case PIPE_CAP_MEMOBJ:
 184         case PIPE_CAP_LOAD_CONSTBUF:
 185         case PIPE_CAP_INT64:
 186         case PIPE_CAP_INT64_DIVMOD:
 187         case PIPE_CAP_TGSI_CLOCK:
 188         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 189         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 190         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 191         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 192                 return 1;
 193
 194         case PIPE_CAP_TGSI_VOTE:
 195                 return HAVE_LLVM >= 0x0400;
 196
 197         case PIPE_CAP_TGSI_BALLOT:
 198                 return HAVE_LLVM >= 0x0500;
 199
 200         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 201                 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 202
 203         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 204                 return (sscreen->info.drm_major == 2 &&
 205                         sscreen->info.drm_minor >= 43) ||
 206                        sscreen->info.drm_major == 3;
 207
 208         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 209                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 210                 return sscreen->info.chip_class < CIK ||
 211                        (sscreen->info.drm_major == 2 &&
 212                         sscreen->info.drm_minor >= 35) ||
 213                        sscreen->info.drm_major == 3;
 214
 215         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 216                 return R600_MAP_BUFFER_ALIGNMENT;
 217
 218         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 219         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 220         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 221         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 222         case PIPE_CAP_MAX_VERTEX_STREAMS:
 223         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 224                 return 4;
 225
 226         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 227                 if (si_have_tgsi_compute(sscreen))
 228                         return 450;
 229                 return 420;
 230
 231         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 232                 return MIN2(sscreen->info.max_alloc_size, INT_MAX);
 233
 234         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 235         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 236         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 237                 /* SI doesn't support unaligned loads.
 238                  * CIK needs DRM 2.50.0 on radeon. */
 239                 return sscreen->info.chip_class == SI ||
 240                        (sscreen->info.drm_major == 2 &&
 241                         sscreen->info.drm_minor < 50);
 242
 243         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 244                 /* TODO: GFX9 hangs. */
 245                 if (sscreen->info.chip_class >= GFX9)
 246                         return 0;
 247                 /* Disable on SI due to VM faults in CP DMA. Enable once these
 248                  * faults are mitigated in software.
 249                  */
 250                 if (sscreen->info.chip_class >= CIK &&
 251                     sscreen->info.drm_major == 3 &&
 252                     sscreen->info.drm_minor >= 13)
 253                         return RADEON_SPARSE_PAGE_SIZE;
 254                 return 0;
 255
 256         /* Unsupported features. */
 257         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 258         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 259         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 260         case PIPE_CAP_USER_VERTEX_BUFFERS:
 261         case PIPE_CAP_FAKE_SW_MSAA:
 262         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 263         case PIPE_CAP_VERTEXID_NOBASE:
 264         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 265         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 266         case PIPE_CAP_TGSI_FS_FBFETCH:
 267         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 268         case PIPE_CAP_UMA:
 269         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 270         case PIPE_CAP_POST_DEPTH_COVERAGE:
 271         case PIPE_CAP_TILE_RASTER_ORDER:
 272         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 273         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 274                 return 0;
 275
 276         case PIPE_CAP_NATIVE_FENCE_FD:
 277                 return sscreen->info.has_fence_to_handle;
 278
 279         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 280                 return si_have_tgsi_compute(sscreen);
 281
 282         case PIPE_CAP_DRAW_PARAMETERS:
 283         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 284         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 285                 return sscreen->has_draw_indirect_multi;
 286
 287         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 288                 return 30;
 289
 290         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 291                 return sscreen->info.chip_class <= VI ?
 292                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 293
 294         /* Stream output. */
 295         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 296         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 297                 return 32*4;
 298
 299         /* Geometry shader output. */
 300         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 301                 return 1024;
 302         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 303                 return 4095;
 304
 305         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 306                 return 2048;
 307
 308         /* Texturing. */
 309         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 310         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 311                 return 15; /* 16384 */
 312         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 313                 /* textures support 8192, but layered rendering supports 2048 */
 314                 return 12;
 315         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 316                 /* textures support 8192, but layered rendering supports 2048 */
 317                 return 2048;
 318
 319         /* Viewports and render targets. */
 320         case PIPE_CAP_MAX_VIEWPORTS:
 321                 return SI_MAX_VIEWPORTS;
 322         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 323         case PIPE_CAP_MAX_RENDER_TARGETS:
 324                 return 8;
 325
 326         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 327         case PIPE_CAP_MIN_TEXEL_OFFSET:
 328                 return -32;
 329
 330         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 331         case PIPE_CAP_MAX_TEXEL_OFFSET:
 332                 return 31;
 333
 334         case PIPE_CAP_ENDIANNESS:
 335                 return PIPE_ENDIAN_LITTLE;
 336
 337         case PIPE_CAP_VENDOR_ID:
 338                 return ATI_VENDOR_ID;
 339         case PIPE_CAP_DEVICE_ID:
 340                 return sscreen->info.pci_id;
 341         case PIPE_CAP_VIDEO_MEMORY:
 342                 return sscreen->info.vram_size >> 20;
 343         case PIPE_CAP_PCI_GROUP:
 344                 return sscreen->info.pci_domain;
 345         case PIPE_CAP_PCI_BUS:
 346                 return sscreen->info.pci_bus;
 347         case PIPE_CAP_PCI_DEVICE:
 348                 return sscreen->info.pci_dev;
 349         case PIPE_CAP_PCI_FUNCTION:
 350                 return sscreen->info.pci_func;
 351         }
 352         return 0;
 353 }
 354
 355 static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
 356 {
 357         switch (param) {
 358         case PIPE_CAPF_MAX_LINE_WIDTH:
 359         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 360         case PIPE_CAPF_MAX_POINT_WIDTH:
 361         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 362                 return 8192.0f;
 363         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 364                 return 16.0f;
 365         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 366                 return 16.0f;
 367         case PIPE_CAPF_GUARD_BAND_LEFT:
 368         case PIPE_CAPF_GUARD_BAND_TOP:
 369         case PIPE_CAPF_GUARD_BAND_RIGHT:
 370         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 371                 return 0.0f;
 372         }
 373         return 0.0f;
 374 }
 375
 376 static int si_get_shader_param(struct pipe_screen* pscreen,
 377                                enum pipe_shader_type shader,
 378                                enum pipe_shader_cap param)
 379 {
 380         struct si_screen *sscreen = (struct si_screen *)pscreen;
 381
 382         switch(shader)
 383         {
 384         case PIPE_SHADER_FRAGMENT:
 385         case PIPE_SHADER_VERTEX:
 386         case PIPE_SHADER_GEOMETRY:
 387         case PIPE_SHADER_TESS_CTRL:
 388         case PIPE_SHADER_TESS_EVAL:
 389                 break;
 390         case PIPE_SHADER_COMPUTE:
 391                 switch (param) {
 392                 case PIPE_SHADER_CAP_PREFERRED_IR:
 393                         return PIPE_SHADER_IR_NATIVE;
 394
 395                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 396                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 397
 398                         if (si_have_tgsi_compute(sscreen))
 399                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 400
 401                         return ir;
 402                 }
 403
 404                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 405                         uint64_t max_const_buffer_size;
 406                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 407                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 408                                 &max_const_buffer_size);
 409                         return MIN2(max_const_buffer_size, INT_MAX);
 410                 }
 411                 default:
 412                         /* If compute shaders don't require a special value
 413                          * for this cap, we can return the same value we
 414                          * do for other shader types. */
 415                         break;
 416                 }
 417                 break;
 418         default:
 419                 return 0;
 420         }
 421
 422         switch (param) {
 423         /* Shader limits. */
 424         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 425         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 426         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 427         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 428         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 429                 return 16384;
 430         case PIPE_SHADER_CAP_MAX_INPUTS:
 431                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 432         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 433                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 434         case PIPE_SHADER_CAP_MAX_TEMPS:
 435                 return 256; /* Max native temporaries. */
 436         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 437                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 438         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 439                 return SI_NUM_CONST_BUFFERS;
 440         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 441         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 442                 return SI_NUM_SAMPLERS;
 443         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 444                 return SI_NUM_SHADER_BUFFERS;
 445         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 446                 return SI_NUM_IMAGES;
 447         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 448                 return 32;
 449         case PIPE_SHADER_CAP_PREFERRED_IR:
 450                 if (sscreen->debug_flags & DBG(NIR))
 451                         return PIPE_SHADER_IR_NIR;
 452                 return PIPE_SHADER_IR_TGSI;
 453         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 454                 return 4;
 455
 456         /* Supported boolean features. */
 457         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 458         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 459         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 460         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 461         case PIPE_SHADER_CAP_INTEGERS:
 462         case PIPE_SHADER_CAP_INT64_ATOMICS:
 463         case PIPE_SHADER_CAP_FP16:
 464         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 465         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 466         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 467         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 468         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 469         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 470                 return 1;
 471
 472         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 473                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 474                 return shader != PIPE_SHADER_GEOMETRY &&
 475                        (sscreen->llvm_has_working_vgpr_indexing ||
 476                         /* TCS and TES load inputs directly from LDS or
 477                          * offchip memory, so indirect indexing is trivial. */
 478                         shader == PIPE_SHADER_TESS_CTRL ||
 479                         shader == PIPE_SHADER_TESS_EVAL);
 480
 481         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 482                 return sscreen->llvm_has_working_vgpr_indexing ||
 483                        /* TCS stores outputs directly to memory. */
 484                        shader == PIPE_SHADER_TESS_CTRL;
 485
 486         /* Unsupported boolean features. */
 487         case PIPE_SHADER_CAP_SUBROUTINES:
 488         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 489         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 490         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 491                 return 0;
 492         }
 493         return 0;
 494 }
 495
 496 static const struct nir_shader_compiler_options nir_options = {
 497         .vertex_id_zero_based = true,
 498         .lower_scmp = true,
 499         .lower_flrp32 = true,
 500         .lower_flrp64 = true,
 501         .lower_fsat = true,
 502         .lower_fdiv = true,
 503         .lower_sub = true,
 504         .lower_ffma = true,
 505         .lower_pack_snorm_2x16 = true,
 506         .lower_pack_snorm_4x8 = true,
 507         .lower_pack_unorm_2x16 = true,
 508         .lower_pack_unorm_4x8 = true,
 509         .lower_unpack_snorm_2x16 = true,
 510         .lower_unpack_snorm_4x8 = true,
 511         .lower_unpack_unorm_2x16 = true,
 512         .lower_unpack_unorm_4x8 = true,
 513         .lower_extract_byte = true,
 514         .lower_extract_word = true,
 515         .max_unroll_iterations = 32,
 516         .native_integers = true,
 517 };
 518
 519 static const void *
 520 si_get_compiler_options(struct pipe_screen *screen,
 521                         enum pipe_shader_ir ir,
 522                         enum pipe_shader_type shader)
 523 {
 524         assert(ir == PIPE_SHADER_IR_NIR);
 525         return &nir_options;
 526 }
 527
 528 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 529 {
 530         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 531 }
 532
 533 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 534 {
 535         struct si_screen *sscreen = (struct si_screen *)pscreen;
 536
 537         ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
 538 }
 539
 540 static const char* si_get_name(struct pipe_screen *pscreen)
 541 {
 542         struct si_screen *sscreen = (struct si_screen*)pscreen;
 543
 544         return sscreen->renderer_string;
 545 }
 546
 547 static int si_get_video_param_no_decode(struct pipe_screen *screen,
 548                                         enum pipe_video_profile profile,
 549                                         enum pipe_video_entrypoint entrypoint,
 550                                         enum pipe_video_cap param)
 551 {
 552         switch (param) {
 553         case PIPE_VIDEO_CAP_SUPPORTED:
 554                 return vl_profile_supported(screen, profile, entrypoint);
 555         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 556                 return 1;
 557         case PIPE_VIDEO_CAP_MAX_WIDTH:
 558         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 559                 return vl_video_buffer_max_size(screen);
 560         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 561                 return PIPE_FORMAT_NV12;
 562         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 563                 return false;
 564         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 565                 return false;
 566         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 567                 return true;
 568         case PIPE_VIDEO_CAP_MAX_LEVEL:
 569                 return vl_level_supported(screen, profile);
 570         default:
 571                 return 0;
 572         }
 573 }
 574
 575 static int si_get_video_param(struct pipe_screen *screen,
 576                               enum pipe_video_profile profile,
 577                               enum pipe_video_entrypoint entrypoint,
 578                               enum pipe_video_cap param)
 579 {
 580         struct si_screen *sscreen = (struct si_screen *)screen;
 581         enum pipe_video_format codec = u_reduce_video_profile(profile);
 582
 583         if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 584                 switch (param) {
 585                 case PIPE_VIDEO_CAP_SUPPORTED:
 586                         return codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 587                                 (si_vce_is_fw_version_supported(sscreen) ||
 588                                 sscreen->info.family == CHIP_RAVEN);
 589                 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 590                         return 1;
 591                 case PIPE_VIDEO_CAP_MAX_WIDTH:
 592                         return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 593                 case PIPE_VIDEO_CAP_MAX_HEIGHT:
 594                         return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
 595                 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 596                         return PIPE_FORMAT_NV12;
 597                 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 598                         return false;
 599                 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 600                         return false;
 601                 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 602                         return true;
 603                 case PIPE_VIDEO_CAP_STACKED_FRAMES:
 604                         return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
 605                 default:
 606                         return 0;
 607                 }
 608         }
 609
 610         switch (param) {
 611         case PIPE_VIDEO_CAP_SUPPORTED:
 612                 switch (codec) {
 613                 case PIPE_VIDEO_FORMAT_MPEG12:
 614                         return profile != PIPE_VIDEO_PROFILE_MPEG1;
 615                 case PIPE_VIDEO_FORMAT_MPEG4:
 616                         return 1;
 617                 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 618                         if ((sscreen->info.family == CHIP_POLARIS10 ||
 619                              sscreen->info.family == CHIP_POLARIS11) &&
 620                             sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
 621                                 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 622                                 return false;
 623                         }
 624                         return true;
 625                 case PIPE_VIDEO_FORMAT_VC1:
 626                         return true;
 627                 case PIPE_VIDEO_FORMAT_HEVC:
 628                         /* Carrizo only supports HEVC Main */
 629                         if (sscreen->info.family >= CHIP_STONEY)
 630                                 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 631                                         profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 632                         else if (sscreen->info.family >= CHIP_CARRIZO)
 633                                 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 634                         return false;
 635                 case PIPE_VIDEO_FORMAT_JPEG:
 636                         if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
 637                                 return false;
 638                         if (!(sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 19)) {
 639                                 RVID_ERR("No MJPEG support for the kernel version\n");
 640                                 return false;
 641                         }
 642                         return true;
 643                 default:
 644                         return false;
 645                 }
 646         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 647                 return 1;
 648         case PIPE_VIDEO_CAP_MAX_WIDTH:
 649                 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 650         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 651                 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
 652         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 653                 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 654                         return PIPE_FORMAT_P016;
 655                 else
 656                         return PIPE_FORMAT_NV12;
 657
 658         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 659         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 660                 enum pipe_video_format format = u_reduce_video_profile(profile);
 661
 662                 if (format == PIPE_VIDEO_FORMAT_HEVC)
 663                         return false; //The firmware doesn't support interlaced HEVC.
 664                 else if (format == PIPE_VIDEO_FORMAT_JPEG)
 665                         return false;
 666                 return true;
 667         }
 668         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 669                 return true;
 670         case PIPE_VIDEO_CAP_MAX_LEVEL:
 671                 switch (profile) {
 672                 case PIPE_VIDEO_PROFILE_MPEG1:
 673                         return 0;
 674                 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 675                 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 676                         return 3;
 677                 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 678                         return 3;
 679                 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 680                         return 5;
 681                 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 682                         return 1;
 683                 case PIPE_VIDEO_PROFILE_VC1_MAIN:
 684                         return 2;
 685                 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 686                         return 4;
 687                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 688                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 689                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 690                         return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
 691                 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 692                 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 693                         return 186;
 694                 default:
 695                         return 0;
 696                 }
 697         default:
 698                 return 0;
 699         }
 700 }
 701
 702 static boolean si_vid_is_format_supported(struct pipe_screen *screen,
 703                                           enum pipe_format format,
 704                                           enum pipe_video_profile profile,
 705                                           enum pipe_video_entrypoint entrypoint)
 706 {
 707         /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
 708         if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 709                 return (format == PIPE_FORMAT_NV12) ||
 710                         (format == PIPE_FORMAT_P016);
 711
 712         /* we can only handle this one with UVD */
 713         if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 714                 return format == PIPE_FORMAT_NV12;
 715
 716         return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 717 }
 718
 719 static unsigned get_max_threads_per_block(struct si_screen *screen,
 720                                           enum pipe_shader_ir ir_type)
 721 {
 722         if (ir_type != PIPE_SHADER_IR_TGSI)
 723                 return 256;
 724
 725         /* Only 16 waves per thread-group on gfx9. */
 726         if (screen->info.chip_class >= GFX9)
 727                 return 1024;
 728
 729         /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
 730          * round number.
 731          */
 732         return 2048;
 733 }
 734
 735 static int si_get_compute_param(struct pipe_screen *screen,
 736                                 enum pipe_shader_ir ir_type,
 737                                 enum pipe_compute_cap param,
 738                                 void *ret)
 739 {
 740         struct si_screen *sscreen = (struct si_screen *)screen;
 741
 742         //TODO: select these params by asic
 743         switch (param) {
 744         case PIPE_COMPUTE_CAP_IR_TARGET: {
 745                 const char *gpu;
 746                 const char *triple;
 747
 748                 if (HAVE_LLVM < 0x0400)
 749                         triple = "amdgcn--";
 750                 else
 751                         triple = "amdgcn-mesa-mesa3d";
 752
 753                 gpu = ac_get_llvm_processor_name(sscreen->info.family);
 754                 if (ret) {
 755                         sprintf(ret, "%s-%s", gpu, triple);
 756                 }
 757                 /* +2 for dash and terminating NIL byte */
 758                 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 759         }
 760         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 761                 if (ret) {
 762                         uint64_t *grid_dimension = ret;
 763                         grid_dimension[0] = 3;
 764                 }
 765                 return 1 * sizeof(uint64_t);
 766
 767         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 768                 if (ret) {
 769                         uint64_t *grid_size = ret;
 770                         grid_size[0] = 65535;
 771                         grid_size[1] = 65535;
 772                         grid_size[2] = 65535;
 773                 }
 774                 return 3 * sizeof(uint64_t) ;
 775
 776         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 777                 if (ret) {
 778                         uint64_t *block_size = ret;
 779                         unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 780                         block_size[0] = threads_per_block;
 781                         block_size[1] = threads_per_block;
 782                         block_size[2] = threads_per_block;
 783                 }
 784                 return 3 * sizeof(uint64_t);
 785
 786         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 787                 if (ret) {
 788                         uint64_t *max_threads_per_block = ret;
 789                         *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 790                 }
 791                 return sizeof(uint64_t);
 792         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 793                 if (ret) {
 794                         uint32_t *address_bits = ret;
 795                         address_bits[0] = 64;
 796                 }
 797                 return 1 * sizeof(uint32_t);
 798
 799         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 800                 if (ret) {
 801                         uint64_t *max_global_size = ret;
 802                         uint64_t max_mem_alloc_size;
 803
 804                         si_get_compute_param(screen, ir_type,
 805                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 806                                 &max_mem_alloc_size);
 807
 808                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 809                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 810                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 811                          * make sure we never report more than
 812                          * 4 * MAX_MEM_ALLOC_SIZE.
 813                          */
 814                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 815                                                 MAX2(sscreen->info.gart_size,
 816                                                      sscreen->info.vram_size));
 817                 }
 818                 return sizeof(uint64_t);
 819
 820         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 821                 if (ret) {
 822                         uint64_t *max_local_size = ret;
 823                         /* Value reported by the closed source driver. */
 824                         *max_local_size = 32768;
 825                 }
 826                 return sizeof(uint64_t);
 827
 828         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 829                 if (ret) {
 830                         uint64_t *max_input_size = ret;
 831                         /* Value reported by the closed source driver. */
 832                         *max_input_size = 1024;
 833                 }
 834                 return sizeof(uint64_t);
 835
 836         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 837                 if (ret) {
 838                         uint64_t *max_mem_alloc_size = ret;
 839
 840                         *max_mem_alloc_size = sscreen->info.max_alloc_size;
 841                 }
 842                 return sizeof(uint64_t);
 843
 844         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 845                 if (ret) {
 846                         uint32_t *max_clock_frequency = ret;
 847                         *max_clock_frequency = sscreen->info.max_shader_clock;
 848                 }
 849                 return sizeof(uint32_t);
 850
 851         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 852                 if (ret) {
 853                         uint32_t *max_compute_units = ret;
 854                         *max_compute_units = sscreen->info.num_good_compute_units;
 855                 }
 856                 return sizeof(uint32_t);
 857
 858         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 859                 if (ret) {
 860                         uint32_t *images_supported = ret;
 861                         *images_supported = 0;
 862                 }
 863                 return sizeof(uint32_t);
 864         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 865                 break; /* unused */
 866         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 867                 if (ret) {
 868                         uint32_t *subgroup_size = ret;
 869                         *subgroup_size = 64;
 870                 }
 871                 return sizeof(uint32_t);
 872         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 873                 if (ret) {
 874                         uint64_t *max_variable_threads_per_block = ret;
 875                         if (ir_type == PIPE_SHADER_IR_TGSI)
 876                                 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
 877                         else
 878                                 *max_variable_threads_per_block = 0;
 879                 }
 880                 return sizeof(uint64_t);
 881         }
 882
 883         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 884         return 0;
 885 }
 886
 887 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 888 {
 889         struct si_screen *sscreen = (struct si_screen*)screen;
 890
 891         return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
 892                         sscreen->info.clock_crystal_freq;
 893 }
 894
 895 static void si_query_memory_info(struct pipe_screen *screen,
 896                                  struct pipe_memory_info *info)
 897 {
 898         struct si_screen *sscreen = (struct si_screen*)screen;
 899         struct radeon_winsys *ws = sscreen->ws;
 900         unsigned vram_usage, gtt_usage;
 901
 902         info->total_device_memory = sscreen->info.vram_size / 1024;
 903         info->total_staging_memory = sscreen->info.gart_size / 1024;
 904
 905         /* The real TTM memory usage is somewhat random, because:
 906          *
 907          * 1) TTM delays freeing memory, because it can only free it after
 908          *    fences expire.
 909          *
 910          * 2) The memory usage can be really low if big VRAM evictions are
 911          *    taking place, but the real usage is well above the size of VRAM.
 912          *
 913          * Instead, return statistics of this process.
 914          */
 915         vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
 916         gtt_usage =  ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
 917
 918         info->avail_device_memory =
 919                 vram_usage <= info->total_device_memory ?
 920                                 info->total_device_memory - vram_usage : 0;
 921         info->avail_staging_memory =
 922                 gtt_usage <= info->total_staging_memory ?
 923                                 info->total_staging_memory - gtt_usage : 0;
 924
 925         info->device_memory_evicted =
 926                 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 927
 928         if (sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 4)
 929                 info->nr_device_memory_evictions =
 930                         ws->query_value(ws, RADEON_NUM_EVICTIONS);
 931         else
 932                 /* Just return the number of evicted 64KB pages. */
 933                 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 934 }
 935
 936 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 937 {
 938         struct si_screen *sscreen = (struct si_screen*)pscreen;
 939
 940         return sscreen->disk_shader_cache;
 941 }
 942
 943 static void si_init_renderer_string(struct si_screen *sscreen)
 944 {
 945         struct radeon_winsys *ws = sscreen->ws;
 946         char family_name[32] = {}, llvm_string[32] = {}, kernel_version[128] = {};
 947         struct utsname uname_data;
 948
 949         const char *chip_name = si_get_marketing_name(ws);
 950
 951         if (chip_name)
 952                 snprintf(family_name, sizeof(family_name), "%s / ",
 953                          si_get_family_name(sscreen) + 4);
 954         else
 955                 chip_name = si_get_family_name(sscreen);
 956
 957         if (uname(&uname_data) == 0)
 958                 snprintf(kernel_version, sizeof(kernel_version),
 959                          " / %s", uname_data.release);
 960
 961         if (HAVE_LLVM > 0) {
 962                 snprintf(llvm_string, sizeof(llvm_string),
 963                          ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
 964                          HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
 965         }
 966
 967         snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
 968                  "%s (%sDRM %i.%i.%i%s%s)",
 969                  chip_name, family_name, sscreen->info.drm_major,
 970                  sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
 971                  kernel_version, llvm_string);
 972 }
 973
 974 void si_init_screen_get_functions(struct si_screen *sscreen)
 975 {
 976         sscreen->b.get_name = si_get_name;
 977         sscreen->b.get_vendor = si_get_vendor;
 978         sscreen->b.get_device_vendor = si_get_device_vendor;
 979         sscreen->b.get_param = si_get_param;
 980         sscreen->b.get_paramf = si_get_paramf;
 981         sscreen->b.get_compute_param = si_get_compute_param;
 982         sscreen->b.get_timestamp = si_get_timestamp;
 983         sscreen->b.get_shader_param = si_get_shader_param;
 984         sscreen->b.get_compiler_options = si_get_compiler_options;
 985         sscreen->b.get_device_uuid = si_get_device_uuid;
 986         sscreen->b.get_driver_uuid = si_get_driver_uuid;
 987         sscreen->b.query_memory_info = si_query_memory_info;
 988         sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
 989
 990         if (sscreen->info.has_hw_decode) {
 991                 sscreen->b.get_video_param = si_get_video_param;
 992                 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
 993         } else {
 994                 sscreen->b.get_video_param = si_get_video_param_no_decode;
 995                 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
 996         }
 997
 998         si_init_renderer_string(sscreen);
 999 }