src/gallium/drivers/radeonsi/si_get.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "si_pipe.h"
  26 #include "radeon/radeon_video.h"
  27 #include "radeon/radeon_vce.h"
  28 #include "radeon/radeon_uvd_enc.h"
  29 #include "ac_llvm_util.h"
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32 #include "util/u_video.h"
  33 #include "compiler/nir/nir.h"
  34
  35 #include <sys/utsname.h>
  36
  37 static const char *si_get_vendor(struct pipe_screen *pscreen)
  38 {
  39         /* Don't change this. Games such as Alien Isolation are broken if this
  40          * returns "Advanced Micro Devices, Inc."
  41          */
  42         return "X.Org";
  43 }
  44
  45 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
  46 {
  47         return "AMD";
  48 }
  49
  50 static const char *si_get_marketing_name(struct radeon_winsys *ws)
  51 {
  52         if (!ws->get_chip_name)
  53                 return NULL;
  54         return ws->get_chip_name(ws);
  55 }
  56
  57 const char *si_get_family_name(const struct si_screen *sscreen)
  58 {
  59         switch (sscreen->info.family) {
  60         case CHIP_TAHITI: return "AMD TAHITI";
  61         case CHIP_PITCAIRN: return "AMD PITCAIRN";
  62         case CHIP_VERDE: return "AMD CAPE VERDE";
  63         case CHIP_OLAND: return "AMD OLAND";
  64         case CHIP_HAINAN: return "AMD HAINAN";
  65         case CHIP_BONAIRE: return "AMD BONAIRE";
  66         case CHIP_KAVERI: return "AMD KAVERI";
  67         case CHIP_KABINI: return "AMD KABINI";
  68         case CHIP_HAWAII: return "AMD HAWAII";
  69         case CHIP_MULLINS: return "AMD MULLINS";
  70         case CHIP_TONGA: return "AMD TONGA";
  71         case CHIP_ICELAND: return "AMD ICELAND";
  72         case CHIP_CARRIZO: return "AMD CARRIZO";
  73         case CHIP_FIJI: return "AMD FIJI";
  74         case CHIP_STONEY: return "AMD STONEY";
  75         case CHIP_POLARIS10: return "AMD POLARIS10";
  76         case CHIP_POLARIS11: return "AMD POLARIS11";
  77         case CHIP_POLARIS12: return "AMD POLARIS12";
  78         case CHIP_VEGAM: return "AMD VEGAM";
  79         case CHIP_VEGA10: return "AMD VEGA10";
  80         case CHIP_VEGA12: return "AMD VEGA12";
  81         case CHIP_RAVEN: return "AMD RAVEN";
  82         default: return "AMD unknown";
  83         }
  84 }
  85
  86 static bool si_have_tgsi_compute(struct si_screen *sscreen)
  87 {
  88         /* Old kernels disallowed some register writes for SI
  89          * that are used for indirect dispatches. */
  90         return (sscreen->info.chip_class >= CIK ||
  91                 sscreen->info.drm_major == 3 ||
  92                 (sscreen->info.drm_major == 2 &&
  93                  sscreen->info.drm_minor >= 45));
  94 }
  95
  96 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  97 {
  98         struct si_screen *sscreen = (struct si_screen *)pscreen;
  99
 100         switch (param) {
 101         /* Supported features (boolean caps). */
 102         case PIPE_CAP_ACCELERATED:
 103         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 104         case PIPE_CAP_ANISOTROPIC_FILTER:
 105         case PIPE_CAP_POINT_SPRITE:
 106         case PIPE_CAP_OCCLUSION_QUERY:
 107         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 108         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 109         case PIPE_CAP_TEXTURE_SWIZZLE:
 110         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 111         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 112         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 113         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 114         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 115         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 116         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 117         case PIPE_CAP_SM3:
 118         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 119         case PIPE_CAP_PRIMITIVE_RESTART:
 120         case PIPE_CAP_CONDITIONAL_RENDER:
 121         case PIPE_CAP_TEXTURE_BARRIER:
 122         case PIPE_CAP_INDEP_BLEND_ENABLE:
 123         case PIPE_CAP_INDEP_BLEND_FUNC:
 124         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 125         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 126         case PIPE_CAP_START_INSTANCE:
 127         case PIPE_CAP_NPOT_TEXTURES:
 128         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 129         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 130         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 131         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 132         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 133         case PIPE_CAP_TGSI_INSTANCEID:
 134         case PIPE_CAP_COMPUTE:
 135         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 136         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 137         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 138         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 139         case PIPE_CAP_CUBE_MAP_ARRAY:
 140         case PIPE_CAP_SAMPLE_SHADING:
 141         case PIPE_CAP_DRAW_INDIRECT:
 142         case PIPE_CAP_CLIP_HALFZ:
 143         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 144         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 145         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 146         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 147         case PIPE_CAP_TGSI_TEXCOORD:
 148         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 149         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 150         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 151         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 152         case PIPE_CAP_SHAREABLE_SHADERS:
 153         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 154         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 155         case PIPE_CAP_TEXTURE_QUERY_LOD:
 156         case PIPE_CAP_TEXTURE_GATHER_SM5:
 157         case PIPE_CAP_TGSI_TXQS:
 158         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 159         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 160         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 161         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 162         case PIPE_CAP_INVALIDATE_BUFFER:
 163         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 164         case PIPE_CAP_QUERY_MEMORY_INFO:
 165         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 166         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 167         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 168         case PIPE_CAP_GENERATE_MIPMAP:
 169         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 170         case PIPE_CAP_STRING_MARKER:
 171         case PIPE_CAP_CLEAR_TEXTURE:
 172         case PIPE_CAP_CULL_DISTANCE:
 173         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 174         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 175         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 176         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 177         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 178         case PIPE_CAP_DOUBLES:
 179         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 180         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 181         case PIPE_CAP_BINDLESS_TEXTURE:
 182         case PIPE_CAP_QUERY_TIMESTAMP:
 183         case PIPE_CAP_QUERY_TIME_ELAPSED:
 184         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 185         case PIPE_CAP_QUERY_SO_OVERFLOW:
 186         case PIPE_CAP_MEMOBJ:
 187         case PIPE_CAP_LOAD_CONSTBUF:
 188         case PIPE_CAP_INT64:
 189         case PIPE_CAP_INT64_DIVMOD:
 190         case PIPE_CAP_TGSI_CLOCK:
 191         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 192         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 193         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 194         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 195         case PIPE_CAP_TGSI_VOTE:
 196         case PIPE_CAP_TGSI_FS_FBFETCH:
 197                 return 1;
 198
 199         case PIPE_CAP_TGSI_BALLOT:
 200                 return HAVE_LLVM >= 0x0500;
 201
 202         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 203                 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 204
 205         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 206                 return (sscreen->info.drm_major == 2 &&
 207                         sscreen->info.drm_minor >= 43) ||
 208                        sscreen->info.drm_major == 3;
 209
 210         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 211                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 212                 return sscreen->info.chip_class < CIK ||
 213                        (sscreen->info.drm_major == 2 &&
 214                         sscreen->info.drm_minor >= 35) ||
 215                        sscreen->info.drm_major == 3;
 216
 217         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 218                 return SI_MAP_BUFFER_ALIGNMENT;
 219
 220         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 221         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 222         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 223         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 224         case PIPE_CAP_MAX_VERTEX_STREAMS:
 225         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 226                 return 4;
 227
 228         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 229                 if (si_have_tgsi_compute(sscreen))
 230                         return 450;
 231                 return 420;
 232
 233         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 234                 return MIN2(sscreen->info.max_alloc_size, INT_MAX);
 235
 236         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 237         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 238         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 239                 /* SI doesn't support unaligned loads.
 240                  * CIK needs DRM 2.50.0 on radeon. */
 241                 return sscreen->info.chip_class == SI ||
 242                        (sscreen->info.drm_major == 2 &&
 243                         sscreen->info.drm_minor < 50);
 244
 245         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 246                 /* TODO: GFX9 hangs. */
 247                 if (sscreen->info.chip_class >= GFX9)
 248                         return 0;
 249                 /* Disable on SI due to VM faults in CP DMA. Enable once these
 250                  * faults are mitigated in software.
 251                  */
 252                 if (sscreen->info.chip_class >= CIK &&
 253                     sscreen->info.drm_major == 3 &&
 254                     sscreen->info.drm_minor >= 13)
 255                         return RADEON_SPARSE_PAGE_SIZE;
 256                 return 0;
 257
 258         case PIPE_CAP_PACKED_UNIFORMS:
 259                 if (sscreen->debug_flags & DBG(NIR))
 260                         return 1;
 261                 return 0;
 262
 263         /* Unsupported features. */
 264         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 265         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 266         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 267         case PIPE_CAP_USER_VERTEX_BUFFERS:
 268         case PIPE_CAP_FAKE_SW_MSAA:
 269         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 270         case PIPE_CAP_VERTEXID_NOBASE:
 271         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 272         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 273         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 274         case PIPE_CAP_UMA:
 275         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 276         case PIPE_CAP_POST_DEPTH_COVERAGE:
 277         case PIPE_CAP_TILE_RASTER_ORDER:
 278         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 279         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 280         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 281         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 282         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 283         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 284         case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 285         case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 286                 return 0;
 287
 288         case PIPE_CAP_FENCE_SIGNAL:
 289                 return sscreen->info.has_syncobj;
 290
 291         case PIPE_CAP_CONSTBUF0_FLAGS:
 292                 return SI_RESOURCE_FLAG_32BIT;
 293
 294         case PIPE_CAP_NATIVE_FENCE_FD:
 295                 return sscreen->info.has_fence_to_handle;
 296
 297         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 298                 return si_have_tgsi_compute(sscreen);
 299
 300         case PIPE_CAP_DRAW_PARAMETERS:
 301         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 302         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 303                 return sscreen->has_draw_indirect_multi;
 304
 305         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 306                 return 30;
 307
 308         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 309                 return sscreen->info.chip_class <= VI ?
 310                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 311
 312         /* Stream output. */
 313         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 314         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 315                 return 32*4;
 316
 317         /* Geometry shader output. */
 318         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 319                 return 1024;
 320         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 321                 return 4095;
 322
 323         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 324                 return 2048;
 325
 326         /* Texturing. */
 327         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 328         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 329                 return 15; /* 16384 */
 330         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 331                 /* textures support 8192, but layered rendering supports 2048 */
 332                 return 12;
 333         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 334                 /* textures support 8192, but layered rendering supports 2048 */
 335                 return 2048;
 336
 337         /* Viewports and render targets. */
 338         case PIPE_CAP_MAX_VIEWPORTS:
 339                 return SI_MAX_VIEWPORTS;
 340         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 341         case PIPE_CAP_MAX_RENDER_TARGETS:
 342                 return 8;
 343
 344         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 345         case PIPE_CAP_MIN_TEXEL_OFFSET:
 346                 return -32;
 347
 348         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 349         case PIPE_CAP_MAX_TEXEL_OFFSET:
 350                 return 31;
 351
 352         case PIPE_CAP_ENDIANNESS:
 353                 return PIPE_ENDIAN_LITTLE;
 354
 355         case PIPE_CAP_VENDOR_ID:
 356                 return ATI_VENDOR_ID;
 357         case PIPE_CAP_DEVICE_ID:
 358                 return sscreen->info.pci_id;
 359         case PIPE_CAP_VIDEO_MEMORY:
 360                 return sscreen->info.vram_size >> 20;
 361         case PIPE_CAP_PCI_GROUP:
 362                 return sscreen->info.pci_domain;
 363         case PIPE_CAP_PCI_BUS:
 364                 return sscreen->info.pci_bus;
 365         case PIPE_CAP_PCI_DEVICE:
 366                 return sscreen->info.pci_dev;
 367         case PIPE_CAP_PCI_FUNCTION:
 368                 return sscreen->info.pci_func;
 369         }
 370         return 0;
 371 }
 372
 373 static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
 374 {
 375         switch (param) {
 376         case PIPE_CAPF_MAX_LINE_WIDTH:
 377         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 378         case PIPE_CAPF_MAX_POINT_WIDTH:
 379         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 380                 return 8192.0f;
 381         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 382                 return 16.0f;
 383         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 384                 return 16.0f;
 385         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 386         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 387         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 388                 return 0.0f;
 389         }
 390         return 0.0f;
 391 }
 392
 393 static int si_get_shader_param(struct pipe_screen* pscreen,
 394                                enum pipe_shader_type shader,
 395                                enum pipe_shader_cap param)
 396 {
 397         struct si_screen *sscreen = (struct si_screen *)pscreen;
 398
 399         switch(shader)
 400         {
 401         case PIPE_SHADER_FRAGMENT:
 402         case PIPE_SHADER_VERTEX:
 403         case PIPE_SHADER_GEOMETRY:
 404         case PIPE_SHADER_TESS_CTRL:
 405         case PIPE_SHADER_TESS_EVAL:
 406                 break;
 407         case PIPE_SHADER_COMPUTE:
 408                 switch (param) {
 409                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 410                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 411
 412                         if (si_have_tgsi_compute(sscreen))
 413                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 414
 415                         return ir;
 416                 }
 417
 418                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 419                         uint64_t max_const_buffer_size;
 420                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 421                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 422                                 &max_const_buffer_size);
 423                         return MIN2(max_const_buffer_size, INT_MAX);
 424                 }
 425                 default:
 426                         /* If compute shaders don't require a special value
 427                          * for this cap, we can return the same value we
 428                          * do for other shader types. */
 429                         break;
 430                 }
 431                 break;
 432         default:
 433                 return 0;
 434         }
 435
 436         switch (param) {
 437         /* Shader limits. */
 438         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 439         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 440         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 441         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 442         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 443                 return 16384;
 444         case PIPE_SHADER_CAP_MAX_INPUTS:
 445                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 446         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 447                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 448         case PIPE_SHADER_CAP_MAX_TEMPS:
 449                 return 256; /* Max native temporaries. */
 450         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 451                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 452         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 453                 return SI_NUM_CONST_BUFFERS;
 454         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 455         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 456                 return SI_NUM_SAMPLERS;
 457         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 458                 return SI_NUM_SHADER_BUFFERS;
 459         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 460                 return SI_NUM_IMAGES;
 461         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 462                 if (sscreen->debug_flags & DBG(NIR))
 463                         return 0;
 464                 return 32;
 465         case PIPE_SHADER_CAP_PREFERRED_IR:
 466                 if (sscreen->debug_flags & DBG(NIR))
 467                         return PIPE_SHADER_IR_NIR;
 468                 return PIPE_SHADER_IR_TGSI;
 469         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 470                 return 4;
 471
 472         /* Supported boolean features. */
 473         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 474         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 475         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 476         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 477         case PIPE_SHADER_CAP_INTEGERS:
 478         case PIPE_SHADER_CAP_INT64_ATOMICS:
 479         case PIPE_SHADER_CAP_FP16:
 480         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 481         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 482         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 483         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 484         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 485         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 486                 return 1;
 487
 488         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 489                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 490                 if (shader == PIPE_SHADER_GEOMETRY)
 491                         return 0;
 492
 493                 if (shader == PIPE_SHADER_VERTEX &&
 494                     !sscreen->llvm_has_working_vgpr_indexing)
 495                         return 0;
 496
 497                 /* TCS and TES load inputs directly from LDS or offchip
 498                  * memory, so indirect indexing is always supported.
 499                  * PS has to support indirect indexing, because we can't
 500                  * lower that to TEMPs for INTERP instructions.
 501                  */
 502                 return 1;
 503
 504         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 505                 return sscreen->llvm_has_working_vgpr_indexing ||
 506                        /* TCS stores outputs directly to memory. */
 507                        shader == PIPE_SHADER_TESS_CTRL;
 508
 509         /* Unsupported boolean features. */
 510         case PIPE_SHADER_CAP_SUBROUTINES:
 511         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 512         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 513         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 514                 return 0;
 515         }
 516         return 0;
 517 }
 518
 519 static const struct nir_shader_compiler_options nir_options = {
 520         .lower_scmp = true,
 521         .lower_flrp32 = true,
 522         .lower_flrp64 = true,
 523         .lower_fpow = true,
 524         .lower_fsat = true,
 525         .lower_fdiv = true,
 526         .lower_sub = true,
 527         .lower_ffma = true,
 528         .lower_pack_snorm_2x16 = true,
 529         .lower_pack_snorm_4x8 = true,
 530         .lower_pack_unorm_2x16 = true,
 531         .lower_pack_unorm_4x8 = true,
 532         .lower_unpack_snorm_2x16 = true,
 533         .lower_unpack_snorm_4x8 = true,
 534         .lower_unpack_unorm_2x16 = true,
 535         .lower_unpack_unorm_4x8 = true,
 536         .lower_extract_byte = true,
 537         .lower_extract_word = true,
 538         .max_unroll_iterations = 32,
 539         .native_integers = true,
 540 };
 541
 542 static const void *
 543 si_get_compiler_options(struct pipe_screen *screen,
 544                         enum pipe_shader_ir ir,
 545                         enum pipe_shader_type shader)
 546 {
 547         assert(ir == PIPE_SHADER_IR_NIR);
 548         return &nir_options;
 549 }
 550
 551 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 552 {
 553         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 554 }
 555
 556 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 557 {
 558         struct si_screen *sscreen = (struct si_screen *)pscreen;
 559
 560         ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
 561 }
 562
 563 static const char* si_get_name(struct pipe_screen *pscreen)
 564 {
 565         struct si_screen *sscreen = (struct si_screen*)pscreen;
 566
 567         return sscreen->renderer_string;
 568 }
 569
 570 static int si_get_video_param_no_decode(struct pipe_screen *screen,
 571                                         enum pipe_video_profile profile,
 572                                         enum pipe_video_entrypoint entrypoint,
 573                                         enum pipe_video_cap param)
 574 {
 575         switch (param) {
 576         case PIPE_VIDEO_CAP_SUPPORTED:
 577                 return vl_profile_supported(screen, profile, entrypoint);
 578         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 579                 return 1;
 580         case PIPE_VIDEO_CAP_MAX_WIDTH:
 581         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 582                 return vl_video_buffer_max_size(screen);
 583         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 584                 return PIPE_FORMAT_NV12;
 585         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 586                 return false;
 587         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 588                 return false;
 589         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 590                 return true;
 591         case PIPE_VIDEO_CAP_MAX_LEVEL:
 592                 return vl_level_supported(screen, profile);
 593         default:
 594                 return 0;
 595         }
 596 }
 597
 598 static int si_get_video_param(struct pipe_screen *screen,
 599                               enum pipe_video_profile profile,
 600                               enum pipe_video_entrypoint entrypoint,
 601                               enum pipe_video_cap param)
 602 {
 603         struct si_screen *sscreen = (struct si_screen *)screen;
 604         enum pipe_video_format codec = u_reduce_video_profile(profile);
 605
 606         if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 607                 switch (param) {
 608                 case PIPE_VIDEO_CAP_SUPPORTED:
 609                         return (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 610                                 (si_vce_is_fw_version_supported(sscreen) ||
 611                                 sscreen->info.family == CHIP_RAVEN)) ||
 612                                 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
 613                                 (sscreen->info.family == CHIP_RAVEN ||
 614                                 si_radeon_uvd_enc_supported(sscreen)));
 615                 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 616                         return 1;
 617                 case PIPE_VIDEO_CAP_MAX_WIDTH:
 618                         return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 619                 case PIPE_VIDEO_CAP_MAX_HEIGHT:
 620                         return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
 621                 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 622                         return PIPE_FORMAT_NV12;
 623                 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 624                         return false;
 625                 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 626                         return false;
 627                 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 628                         return true;
 629                 case PIPE_VIDEO_CAP_STACKED_FRAMES:
 630                         return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
 631                 default:
 632                         return 0;
 633                 }
 634         }
 635
 636         switch (param) {
 637         case PIPE_VIDEO_CAP_SUPPORTED:
 638                 switch (codec) {
 639                 case PIPE_VIDEO_FORMAT_MPEG12:
 640                         return profile != PIPE_VIDEO_PROFILE_MPEG1;
 641                 case PIPE_VIDEO_FORMAT_MPEG4:
 642                         return 1;
 643                 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 644                         if ((sscreen->info.family == CHIP_POLARIS10 ||
 645                              sscreen->info.family == CHIP_POLARIS11) &&
 646                             sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
 647                                 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 648                                 return false;
 649                         }
 650                         return true;
 651                 case PIPE_VIDEO_FORMAT_VC1:
 652                         return true;
 653                 case PIPE_VIDEO_FORMAT_HEVC:
 654                         /* Carrizo only supports HEVC Main */
 655                         if (sscreen->info.family >= CHIP_STONEY)
 656                                 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 657                                         profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 658                         else if (sscreen->info.family >= CHIP_CARRIZO)
 659                                 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 660                         return false;
 661                 case PIPE_VIDEO_FORMAT_JPEG:
 662                         if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
 663                                 return false;
 664                         if (!(sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 19)) {
 665                                 RVID_ERR("No MJPEG support for the kernel version\n");
 666                                 return false;
 667                         }
 668                         return true;
 669                 case PIPE_VIDEO_FORMAT_VP9:
 670                         if (sscreen->info.family < CHIP_RAVEN)
 671                                 return false;
 672                         return true;
 673                 default:
 674                         return false;
 675                 }
 676         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 677                 return 1;
 678         case PIPE_VIDEO_CAP_MAX_WIDTH:
 679                 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 680         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 681                 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
 682         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 683                 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 ||
 684                     profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 685                         return PIPE_FORMAT_P016;
 686                 else
 687                         return PIPE_FORMAT_NV12;
 688
 689         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 690         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 691                 enum pipe_video_format format = u_reduce_video_profile(profile);
 692
 693                 if (format == PIPE_VIDEO_FORMAT_HEVC)
 694                         return false; //The firmware doesn't support interlaced HEVC.
 695                 else if (format == PIPE_VIDEO_FORMAT_JPEG)
 696                         return false;
 697                 else if (format == PIPE_VIDEO_FORMAT_VP9)
 698                         return false;
 699                 return true;
 700         }
 701         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 702                 return true;
 703         case PIPE_VIDEO_CAP_MAX_LEVEL:
 704                 switch (profile) {
 705                 case PIPE_VIDEO_PROFILE_MPEG1:
 706                         return 0;
 707                 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 708                 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 709                         return 3;
 710                 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 711                         return 3;
 712                 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 713                         return 5;
 714                 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 715                         return 1;
 716                 case PIPE_VIDEO_PROFILE_VC1_MAIN:
 717                         return 2;
 718                 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 719                         return 4;
 720                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 721                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 722                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 723                         return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
 724                 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 725                 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 726                         return 186;
 727                 default:
 728                         return 0;
 729                 }
 730         default:
 731                 return 0;
 732         }
 733 }
 734
 735 static boolean si_vid_is_format_supported(struct pipe_screen *screen,
 736                                           enum pipe_format format,
 737                                           enum pipe_video_profile profile,
 738                                           enum pipe_video_entrypoint entrypoint)
 739 {
 740         /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
 741         if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 742                 return (format == PIPE_FORMAT_NV12) ||
 743                         (format == PIPE_FORMAT_P016);
 744
 745         /* we can only handle this one with UVD */
 746         if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 747                 return format == PIPE_FORMAT_NV12;
 748
 749         return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 750 }
 751
 752 static unsigned get_max_threads_per_block(struct si_screen *screen,
 753                                           enum pipe_shader_ir ir_type)
 754 {
 755         if (ir_type == PIPE_SHADER_IR_NATIVE)
 756                 return 256;
 757
 758         /* Only 16 waves per thread-group on gfx9. */
 759         if (screen->info.chip_class >= GFX9)
 760                 return 1024;
 761
 762         /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
 763          * round number.
 764          */
 765         return 2048;
 766 }
 767
 768 static int si_get_compute_param(struct pipe_screen *screen,
 769                                 enum pipe_shader_ir ir_type,
 770                                 enum pipe_compute_cap param,
 771                                 void *ret)
 772 {
 773         struct si_screen *sscreen = (struct si_screen *)screen;
 774
 775         //TODO: select these params by asic
 776         switch (param) {
 777         case PIPE_COMPUTE_CAP_IR_TARGET: {
 778                 const char *gpu, *triple;
 779
 780                 triple = "amdgcn-mesa-mesa3d";
 781                 gpu = ac_get_llvm_processor_name(sscreen->info.family);
 782                 if (ret) {
 783                         sprintf(ret, "%s-%s", gpu, triple);
 784                 }
 785                 /* +2 for dash and terminating NIL byte */
 786                 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 787         }
 788         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 789                 if (ret) {
 790                         uint64_t *grid_dimension = ret;
 791                         grid_dimension[0] = 3;
 792                 }
 793                 return 1 * sizeof(uint64_t);
 794
 795         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 796                 if (ret) {
 797                         uint64_t *grid_size = ret;
 798                         grid_size[0] = 65535;
 799                         grid_size[1] = 65535;
 800                         grid_size[2] = 65535;
 801                 }
 802                 return 3 * sizeof(uint64_t) ;
 803
 804         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 805                 if (ret) {
 806                         uint64_t *block_size = ret;
 807                         unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 808                         block_size[0] = threads_per_block;
 809                         block_size[1] = threads_per_block;
 810                         block_size[2] = threads_per_block;
 811                 }
 812                 return 3 * sizeof(uint64_t);
 813
 814         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 815                 if (ret) {
 816                         uint64_t *max_threads_per_block = ret;
 817                         *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 818                 }
 819                 return sizeof(uint64_t);
 820         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 821                 if (ret) {
 822                         uint32_t *address_bits = ret;
 823                         address_bits[0] = 64;
 824                 }
 825                 return 1 * sizeof(uint32_t);
 826
 827         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 828                 if (ret) {
 829                         uint64_t *max_global_size = ret;
 830                         uint64_t max_mem_alloc_size;
 831
 832                         si_get_compute_param(screen, ir_type,
 833                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 834                                 &max_mem_alloc_size);
 835
 836                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 837                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 838                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 839                          * make sure we never report more than
 840                          * 4 * MAX_MEM_ALLOC_SIZE.
 841                          */
 842                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 843                                                 MAX2(sscreen->info.gart_size,
 844                                                      sscreen->info.vram_size));
 845                 }
 846                 return sizeof(uint64_t);
 847
 848         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 849                 if (ret) {
 850                         uint64_t *max_local_size = ret;
 851                         /* Value reported by the closed source driver. */
 852                         *max_local_size = 32768;
 853                 }
 854                 return sizeof(uint64_t);
 855
 856         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 857                 if (ret) {
 858                         uint64_t *max_input_size = ret;
 859                         /* Value reported by the closed source driver. */
 860                         *max_input_size = 1024;
 861                 }
 862                 return sizeof(uint64_t);
 863
 864         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 865                 if (ret) {
 866                         uint64_t *max_mem_alloc_size = ret;
 867
 868                         *max_mem_alloc_size = sscreen->info.max_alloc_size;
 869                 }
 870                 return sizeof(uint64_t);
 871
 872         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 873                 if (ret) {
 874                         uint32_t *max_clock_frequency = ret;
 875                         *max_clock_frequency = sscreen->info.max_shader_clock;
 876                 }
 877                 return sizeof(uint32_t);
 878
 879         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 880                 if (ret) {
 881                         uint32_t *max_compute_units = ret;
 882                         *max_compute_units = sscreen->info.num_good_compute_units;
 883                 }
 884                 return sizeof(uint32_t);
 885
 886         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 887                 if (ret) {
 888                         uint32_t *images_supported = ret;
 889                         *images_supported = 0;
 890                 }
 891                 return sizeof(uint32_t);
 892         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 893                 break; /* unused */
 894         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 895                 if (ret) {
 896                         uint32_t *subgroup_size = ret;
 897                         *subgroup_size = 64;
 898                 }
 899                 return sizeof(uint32_t);
 900         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 901                 if (ret) {
 902                         uint64_t *max_variable_threads_per_block = ret;
 903                         if (ir_type == PIPE_SHADER_IR_NATIVE)
 904                                 *max_variable_threads_per_block = 0;
 905                         else
 906                                 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
 907                 }
 908                 return sizeof(uint64_t);
 909         }
 910
 911         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 912         return 0;
 913 }
 914
 915 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 916 {
 917         struct si_screen *sscreen = (struct si_screen*)screen;
 918
 919         return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
 920                         sscreen->info.clock_crystal_freq;
 921 }
 922
 923 static void si_query_memory_info(struct pipe_screen *screen,
 924                                  struct pipe_memory_info *info)
 925 {
 926         struct si_screen *sscreen = (struct si_screen*)screen;
 927         struct radeon_winsys *ws = sscreen->ws;
 928         unsigned vram_usage, gtt_usage;
 929
 930         info->total_device_memory = sscreen->info.vram_size / 1024;
 931         info->total_staging_memory = sscreen->info.gart_size / 1024;
 932
 933         /* The real TTM memory usage is somewhat random, because:
 934          *
 935          * 1) TTM delays freeing memory, because it can only free it after
 936          *    fences expire.
 937          *
 938          * 2) The memory usage can be really low if big VRAM evictions are
 939          *    taking place, but the real usage is well above the size of VRAM.
 940          *
 941          * Instead, return statistics of this process.
 942          */
 943         vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
 944         gtt_usage =  ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
 945
 946         info->avail_device_memory =
 947                 vram_usage <= info->total_device_memory ?
 948                                 info->total_device_memory - vram_usage : 0;
 949         info->avail_staging_memory =
 950                 gtt_usage <= info->total_staging_memory ?
 951                                 info->total_staging_memory - gtt_usage : 0;
 952
 953         info->device_memory_evicted =
 954                 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 955
 956         if (sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 4)
 957                 info->nr_device_memory_evictions =
 958                         ws->query_value(ws, RADEON_NUM_EVICTIONS);
 959         else
 960                 /* Just return the number of evicted 64KB pages. */
 961                 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 962 }
 963
 964 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 965 {
 966         struct si_screen *sscreen = (struct si_screen*)pscreen;
 967
 968         return sscreen->disk_shader_cache;
 969 }
 970
 971 static void si_init_renderer_string(struct si_screen *sscreen)
 972 {
 973         struct radeon_winsys *ws = sscreen->ws;
 974         char family_name[32] = {}, kernel_version[128] = {};
 975         struct utsname uname_data;
 976
 977         const char *chip_name = si_get_marketing_name(ws);
 978
 979         if (chip_name)
 980                 snprintf(family_name, sizeof(family_name), "%s, ",
 981                          si_get_family_name(sscreen) + 4);
 982         else
 983                 chip_name = si_get_family_name(sscreen);
 984
 985         if (uname(&uname_data) == 0)
 986                 snprintf(kernel_version, sizeof(kernel_version),
 987                          ", %s", uname_data.release);
 988
 989         snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
 990                  "%s (%sDRM %i.%i.%i%s, LLVM %i.%i.%i)",
 991                  chip_name, family_name, sscreen->info.drm_major,
 992                  sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
 993                  kernel_version,
 994                  (HAVE_LLVM >> 8) & 0xff,
 995                  HAVE_LLVM & 0xff,
 996                  MESA_LLVM_VERSION_PATCH);
 997 }
 998
 999 void si_init_screen_get_functions(struct si_screen *sscreen)
1000 {
1001         sscreen->b.get_name = si_get_name;
1002         sscreen->b.get_vendor = si_get_vendor;
1003         sscreen->b.get_device_vendor = si_get_device_vendor;
1004         sscreen->b.get_param = si_get_param;
1005         sscreen->b.get_paramf = si_get_paramf;
1006         sscreen->b.get_compute_param = si_get_compute_param;
1007         sscreen->b.get_timestamp = si_get_timestamp;
1008         sscreen->b.get_shader_param = si_get_shader_param;
1009         sscreen->b.get_compiler_options = si_get_compiler_options;
1010         sscreen->b.get_device_uuid = si_get_device_uuid;
1011         sscreen->b.get_driver_uuid = si_get_driver_uuid;
1012         sscreen->b.query_memory_info = si_query_memory_info;
1013         sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
1014
1015         if (sscreen->info.has_hw_decode) {
1016                 sscreen->b.get_video_param = si_get_video_param;
1017                 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
1018         } else {
1019                 sscreen->b.get_video_param = si_get_video_param_no_decode;
1020                 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1021         }
1022
1023         si_init_renderer_string(sscreen);
1024 }