src/gallium/drivers/radeonsi/si_gfx_cs.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  * Copyright 2018 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * on the rights to use, copy, modify, merge, publish, distribute, sub
  10  * license, and/or sell copies of the Software, and to permit persons to whom
  11  * the Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  21  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  22  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include "si_pipe.h"
  27 #include "radeon/r600_cs.h"
  28
  29 #include "util/os_time.h"
  30
  31 /* initialize */
  32 void si_need_gfx_cs_space(struct si_context *ctx)
  33 {
  34         struct radeon_winsys_cs *cs = ctx->b.gfx_cs;
  35
  36         /* There is no need to flush the DMA IB here, because
  37          * r600_need_dma_space always flushes the GFX IB if there is
  38          * a conflict, which means any unflushed DMA commands automatically
  39          * precede the GFX IB (= they had no dependency on the GFX IB when
  40          * they were submitted).
  41          */
  42
  43         /* There are two memory usage counters in the winsys for all buffers
  44          * that have been added (cs_add_buffer) and two counters in the pipe
  45          * driver for those that haven't been added yet.
  46          */
  47         if (unlikely(!radeon_cs_memory_below_limit(ctx->b.screen, ctx->b.gfx_cs,
  48                                                    ctx->b.vram, ctx->b.gtt))) {
  49                 ctx->b.gtt = 0;
  50                 ctx->b.vram = 0;
  51                 si_flush_gfx_cs(ctx, PIPE_FLUSH_ASYNC, NULL);
  52                 return;
  53         }
  54         ctx->b.gtt = 0;
  55         ctx->b.vram = 0;
  56
  57         /* If the IB is sufficiently large, don't count the space needed
  58          * and just flush if there is not enough space left.
  59          *
  60          * Also reserve space for stopping queries at the end of IB, because
  61          * the number of active queries is mostly unlimited.
  62          */
  63         unsigned need_dwords = 2048 + ctx->b.num_cs_dw_queries_suspend;
  64         if (!ctx->b.ws->cs_check_space(cs, need_dwords))
  65                 si_flush_gfx_cs(ctx, PIPE_FLUSH_ASYNC, NULL);
  66 }
  67
  68 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
  69                      struct pipe_fence_handle **fence)
  70 {
  71         struct radeon_winsys_cs *cs = ctx->b.gfx_cs;
  72         struct radeon_winsys *ws = ctx->b.ws;
  73
  74         if (ctx->gfx_flush_in_progress)
  75                 return;
  76
  77         if (!radeon_emitted(cs, ctx->b.initial_gfx_cs_size))
  78                 return;
  79
  80         if (si_check_device_reset(ctx))
  81                 return;
  82
  83         if (ctx->screen->debug_flags & DBG(CHECK_VM))
  84                 flags &= ~PIPE_FLUSH_ASYNC;
  85
  86         /* If the state tracker is flushing the GFX IB, si_flush_from_st is
  87          * responsible for flushing the DMA IB and merging the fences from both.
  88          * This code is only needed when the driver flushes the GFX IB
  89          * internally, and it never asks for a fence handle.
  90          */
  91         if (radeon_emitted(ctx->b.dma_cs, 0)) {
  92                 assert(fence == NULL); /* internal flushes only */
  93                 si_flush_dma_cs(ctx, flags, NULL);
  94         }
  95
  96         ctx->gfx_flush_in_progress = true;
  97
  98         if (!LIST_IS_EMPTY(&ctx->b.active_queries))
  99                 si_suspend_queries(ctx);
 100
 101         ctx->streamout.suspended = false;
 102         if (ctx->streamout.begin_emitted) {
 103                 si_emit_streamout_end(ctx);
 104                 ctx->streamout.suspended = true;
 105         }
 106
 107         ctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
 108                         SI_CONTEXT_PS_PARTIAL_FLUSH;
 109
 110         /* DRM 3.1.0 doesn't flush TC for VI correctly. */
 111         if (ctx->b.chip_class == VI && ctx->b.screen->info.drm_minor <= 1)
 112                 ctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2 |
 113                                 SI_CONTEXT_INV_VMEM_L1;
 114
 115         si_emit_cache_flush(ctx);
 116
 117         if (ctx->current_saved_cs) {
 118                 si_trace_emit(ctx);
 119                 si_log_hw_flush(ctx);
 120
 121                 /* Save the IB for debug contexts. */
 122                 si_save_cs(ws, cs, &ctx->current_saved_cs->gfx, true);
 123                 ctx->current_saved_cs->flushed = true;
 124                 ctx->current_saved_cs->time_flush = os_time_get_nano();
 125         }
 126
 127         /* Flush the CS. */
 128         ws->cs_flush(cs, flags, &ctx->b.last_gfx_fence);
 129         if (fence)
 130                 ws->fence_reference(fence, ctx->b.last_gfx_fence);
 131
 132         /* This must be after cs_flush returns, since the context's API
 133          * thread can concurrently read this value in si_fence_finish. */
 134         ctx->b.num_gfx_cs_flushes++;
 135
 136         /* Check VM faults if needed. */
 137         if (ctx->screen->debug_flags & DBG(CHECK_VM)) {
 138                 /* Use conservative timeout 800ms, after which we won't wait any
 139                  * longer and assume the GPU is hung.
 140                  */
 141                 ctx->b.ws->fence_wait(ctx->b.ws, ctx->b.last_gfx_fence, 800*1000*1000);
 142
 143                 si_check_vm_faults(ctx, &ctx->current_saved_cs->gfx, RING_GFX);
 144         }
 145
 146         if (ctx->current_saved_cs)
 147                 si_saved_cs_reference(&ctx->current_saved_cs, NULL);
 148
 149         si_begin_new_gfx_cs(ctx);
 150         ctx->gfx_flush_in_progress = false;
 151 }
 152
 153 static void si_begin_gfx_cs_debug(struct si_context *ctx)
 154 {
 155         static const uint32_t zeros[1];
 156         assert(!ctx->current_saved_cs);
 157
 158         ctx->current_saved_cs = calloc(1, sizeof(*ctx->current_saved_cs));
 159         if (!ctx->current_saved_cs)
 160                 return;
 161
 162         pipe_reference_init(&ctx->current_saved_cs->reference, 1);
 163
 164         ctx->current_saved_cs->trace_buf = (struct r600_resource*)
 165                                  pipe_buffer_create(ctx->b.b.screen, 0,
 166                                                     PIPE_USAGE_STAGING, 8);
 167         if (!ctx->current_saved_cs->trace_buf) {
 168                 free(ctx->current_saved_cs);
 169                 ctx->current_saved_cs = NULL;
 170                 return;
 171         }
 172
 173         pipe_buffer_write_nooverlap(&ctx->b.b, &ctx->current_saved_cs->trace_buf->b.b,
 174                                     0, sizeof(zeros), zeros);
 175         ctx->current_saved_cs->trace_id = 0;
 176
 177         si_trace_emit(ctx);
 178
 179         radeon_add_to_buffer_list(ctx, ctx->b.gfx_cs, ctx->current_saved_cs->trace_buf,
 180                               RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
 181 }
 182
 183 void si_begin_new_gfx_cs(struct si_context *ctx)
 184 {
 185         if (ctx->is_debug)
 186                 si_begin_gfx_cs_debug(ctx);
 187
 188         /* Flush read caches at the beginning of CS not flushed by the kernel. */
 189         if (ctx->b.chip_class >= CIK)
 190                 ctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
 191                                 SI_CONTEXT_INV_ICACHE;
 192
 193         ctx->b.flags |= SI_CONTEXT_START_PIPELINE_STATS;
 194
 195         /* set all valid group as dirty so they get reemited on
 196          * next draw command
 197          */
 198         si_pm4_reset_emitted(ctx);
 199
 200         /* The CS initialization should be emitted before everything else. */
 201         si_pm4_emit(ctx, ctx->init_config);
 202         if (ctx->init_config_gs_rings)
 203                 si_pm4_emit(ctx, ctx->init_config_gs_rings);
 204
 205         if (ctx->queued.named.ls)
 206                 ctx->prefetch_L2_mask |= SI_PREFETCH_LS;
 207         if (ctx->queued.named.hs)
 208                 ctx->prefetch_L2_mask |= SI_PREFETCH_HS;
 209         if (ctx->queued.named.es)
 210                 ctx->prefetch_L2_mask |= SI_PREFETCH_ES;
 211         if (ctx->queued.named.gs)
 212                 ctx->prefetch_L2_mask |= SI_PREFETCH_GS;
 213         if (ctx->queued.named.vs)
 214                 ctx->prefetch_L2_mask |= SI_PREFETCH_VS;
 215         if (ctx->queued.named.ps)
 216                 ctx->prefetch_L2_mask |= SI_PREFETCH_PS;
 217         if (ctx->vb_descriptors_buffer && ctx->vertex_elements)
 218                 ctx->prefetch_L2_mask |= SI_PREFETCH_VBO_DESCRIPTORS;
 219
 220         /* CLEAR_STATE disables all colorbuffers, so only enable bound ones. */
 221         bool has_clear_state = ctx->screen->has_clear_state;
 222         if (has_clear_state) {
 223                 ctx->framebuffer.dirty_cbufs =
 224                          u_bit_consecutive(0, ctx->framebuffer.state.nr_cbufs);
 225                 /* CLEAR_STATE disables the zbuffer, so only enable it if it's bound. */
 226                 ctx->framebuffer.dirty_zsbuf = ctx->framebuffer.state.zsbuf != NULL;
 227         } else {
 228                 ctx->framebuffer.dirty_cbufs = u_bit_consecutive(0, 8);
 229                 ctx->framebuffer.dirty_zsbuf = true;
 230         }
 231         /* This should always be marked as dirty to set the framebuffer scissor
 232          * at least. */
 233         si_mark_atom_dirty(ctx, &ctx->framebuffer.atom);
 234
 235         si_mark_atom_dirty(ctx, &ctx->clip_regs);
 236         /* CLEAR_STATE sets zeros. */
 237         if (!has_clear_state || ctx->clip_state.any_nonzeros)
 238                 si_mark_atom_dirty(ctx, &ctx->clip_state.atom);
 239         ctx->msaa_sample_locs.nr_samples = 0;
 240         si_mark_atom_dirty(ctx, &ctx->msaa_sample_locs.atom);
 241         si_mark_atom_dirty(ctx, &ctx->msaa_config);
 242         /* CLEAR_STATE sets 0xffff. */
 243         if (!has_clear_state || ctx->sample_mask.sample_mask != 0xffff)
 244                 si_mark_atom_dirty(ctx, &ctx->sample_mask.atom);
 245         si_mark_atom_dirty(ctx, &ctx->cb_render_state);
 246         /* CLEAR_STATE sets zeros. */
 247         if (!has_clear_state || ctx->blend_color.any_nonzeros)
 248                 si_mark_atom_dirty(ctx, &ctx->blend_color.atom);
 249         si_mark_atom_dirty(ctx, &ctx->db_render_state);
 250         if (ctx->b.chip_class >= GFX9)
 251                 si_mark_atom_dirty(ctx, &ctx->dpbb_state);
 252         si_mark_atom_dirty(ctx, &ctx->stencil_ref.atom);
 253         si_mark_atom_dirty(ctx, &ctx->spi_map);
 254         si_mark_atom_dirty(ctx, &ctx->streamout.enable_atom);
 255         si_mark_atom_dirty(ctx, &ctx->b.render_cond_atom);
 256         si_all_descriptors_begin_new_cs(ctx);
 257         si_all_resident_buffers_begin_new_cs(ctx);
 258
 259         ctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 260         ctx->viewports.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 261         ctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 262         si_mark_atom_dirty(ctx, &ctx->scissors.atom);
 263         si_mark_atom_dirty(ctx, &ctx->viewports.atom);
 264
 265         si_mark_atom_dirty(ctx, &ctx->scratch_state);
 266         if (ctx->scratch_buffer) {
 267                 si_context_add_resource_size(ctx, &ctx->scratch_buffer->b.b);
 268         }
 269
 270         if (ctx->streamout.suspended) {
 271                 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
 272                 si_streamout_buffers_dirty(ctx);
 273         }
 274
 275         if (!LIST_IS_EMPTY(&ctx->b.active_queries))
 276                 si_resume_queries(ctx);
 277
 278         assert(!ctx->b.gfx_cs->prev_dw);
 279         ctx->b.initial_gfx_cs_size = ctx->b.gfx_cs->current.cdw;
 280
 281         /* Invalidate various draw states so that they are emitted before
 282          * the first draw call. */
 283         si_invalidate_draw_sh_constants(ctx);
 284         ctx->last_index_size = -1;
 285         ctx->last_primitive_restart_en = -1;
 286         ctx->last_restart_index = SI_RESTART_INDEX_UNKNOWN;
 287         ctx->last_gs_out_prim = -1;
 288         ctx->last_prim = -1;
 289         ctx->last_multi_vgt_param = -1;
 290         ctx->last_rast_prim = -1;
 291         ctx->last_sc_line_stipple = ~0;
 292         ctx->last_vs_state = ~0;
 293         ctx->last_ls = NULL;
 294         ctx->last_tcs = NULL;
 295         ctx->last_tes_sh_base = -1;
 296         ctx->last_num_tcs_input_cp = -1;
 297
 298         ctx->cs_shader_state.initialized = false;
 299 }