src/gallium/drivers/radeonsi/si_gfx_cs.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  * Copyright 2018 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * on the rights to use, copy, modify, merge, publish, distribute, sub
  10  * license, and/or sell copies of the Software, and to permit persons to whom
  11  * the Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  21  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  22  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include "si_pipe.h"
  27 #include "si_build_pm4.h"
  28 #include "sid.h"
  29
  30 #include "util/os_time.h"
  31 #include "util/u_upload_mgr.h"
  32
  33 /* initialize */
  34 void si_need_gfx_cs_space(struct si_context *ctx)
  35 {
  36         struct radeon_cmdbuf *cs = ctx->gfx_cs;
  37
  38         /* There is no need to flush the DMA IB here, because
  39          * si_need_dma_space always flushes the GFX IB if there is
  40          * a conflict, which means any unflushed DMA commands automatically
  41          * precede the GFX IB (= they had no dependency on the GFX IB when
  42          * they were submitted).
  43          */
  44
  45         /* There are two memory usage counters in the winsys for all buffers
  46          * that have been added (cs_add_buffer) and two counters in the pipe
  47          * driver for those that haven't been added yet.
  48          */
  49         if (unlikely(!radeon_cs_memory_below_limit(ctx->screen, ctx->gfx_cs,
  50                                                    ctx->vram, ctx->gtt))) {
  51                 ctx->gtt = 0;
  52                 ctx->vram = 0;
  53                 si_flush_gfx_cs(ctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
  54                 return;
  55         }
  56         ctx->gtt = 0;
  57         ctx->vram = 0;
  58
  59         unsigned need_dwords = si_get_minimum_num_gfx_cs_dwords(ctx);
  60         if (!ctx->ws->cs_check_space(cs, need_dwords, false))
  61                 si_flush_gfx_cs(ctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
  62 }
  63
  64 void si_unref_sdma_uploads(struct si_context *sctx)
  65 {
  66         for (unsigned i = 0; i < sctx->num_sdma_uploads; i++) {
  67                 si_resource_reference(&sctx->sdma_uploads[i].dst, NULL);
  68                 si_resource_reference(&sctx->sdma_uploads[i].src, NULL);
  69         }
  70         sctx->num_sdma_uploads = 0;
  71 }
  72
  73 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
  74                      struct pipe_fence_handle **fence)
  75 {
  76         struct radeon_cmdbuf *cs = ctx->gfx_cs;
  77         struct radeon_winsys *ws = ctx->ws;
  78         unsigned wait_flags = 0;
  79
  80         if (ctx->gfx_flush_in_progress)
  81                 return;
  82
  83         if (!ctx->screen->info.kernel_flushes_tc_l2_after_ib) {
  84                 wait_flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
  85                               SI_CONTEXT_CS_PARTIAL_FLUSH |
  86                               SI_CONTEXT_INV_L2;
  87         } else if (ctx->chip_class == GFX6) {
  88                 /* The kernel flushes L2 before shaders are finished. */
  89                 wait_flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
  90                               SI_CONTEXT_CS_PARTIAL_FLUSH;
  91         } else if (!(flags & RADEON_FLUSH_START_NEXT_GFX_IB_NOW)) {
  92                 wait_flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
  93                               SI_CONTEXT_CS_PARTIAL_FLUSH;
  94         }
  95
  96         /* Drop this flush if it's a no-op. */
  97         if (!radeon_emitted(cs, ctx->initial_gfx_cs_size) &&
  98             (!wait_flags || !ctx->gfx_last_ib_is_busy))
  99                 return;
 100
 101         if (si_check_device_reset(ctx))
 102                 return;
 103
 104         if (ctx->screen->debug_flags & DBG(CHECK_VM))
 105                 flags &= ~PIPE_FLUSH_ASYNC;
 106
 107         ctx->gfx_flush_in_progress = true;
 108
 109         /* If the state tracker is flushing the GFX IB, si_flush_from_st is
 110          * responsible for flushing the DMA IB and merging the fences from both.
 111          * If the driver flushes the GFX IB internally, and it should never ask
 112          * for a fence handle.
 113          */
 114         assert(!radeon_emitted(ctx->dma_cs, 0) || fence == NULL);
 115
 116         /* Update the sdma_uploads list by flushing the uploader. */
 117         u_upload_unmap(ctx->b.const_uploader);
 118
 119         /* Execute SDMA uploads. */
 120         ctx->sdma_uploads_in_progress = true;
 121         for (unsigned i = 0; i < ctx->num_sdma_uploads; i++) {
 122                 struct si_sdma_upload *up = &ctx->sdma_uploads[i];
 123                 struct pipe_box box;
 124
 125                 assert(up->src_offset % 4 == 0 && up->dst_offset % 4 == 0 &&
 126                        up->size % 4 == 0);
 127
 128                 u_box_1d(up->src_offset, up->size, &box);
 129                 ctx->dma_copy(&ctx->b, &up->dst->b.b, 0, up->dst_offset, 0, 0,
 130                               &up->src->b.b, 0, &box);
 131         }
 132         ctx->sdma_uploads_in_progress = false;
 133         si_unref_sdma_uploads(ctx);
 134
 135         /* Flush SDMA (preamble IB). */
 136         if (radeon_emitted(ctx->dma_cs, 0))
 137                 si_flush_dma_cs(ctx, flags, NULL);
 138
 139         if (radeon_emitted(ctx->prim_discard_compute_cs, 0)) {
 140                 struct radeon_cmdbuf *compute_cs = ctx->prim_discard_compute_cs;
 141                 si_compute_signal_gfx(ctx);
 142
 143                 /* Make sure compute shaders are idle before leaving the IB, so that
 144                  * the next IB doesn't overwrite GDS that might be in use. */
 145                 radeon_emit(compute_cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 146                 radeon_emit(compute_cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) |
 147                                         EVENT_INDEX(4));
 148
 149                 /* Save the GDS prim restart counter if needed. */
 150                 if (ctx->preserve_prim_restart_gds_at_flush) {
 151                         si_cp_copy_data(ctx, compute_cs,
 152                                         COPY_DATA_DST_MEM, ctx->wait_mem_scratch, 4,
 153                                         COPY_DATA_GDS, NULL, 4);
 154                 }
 155         }
 156
 157         if (ctx->has_graphics) {
 158                 if (!LIST_IS_EMPTY(&ctx->active_queries))
 159                         si_suspend_queries(ctx);
 160
 161                 ctx->streamout.suspended = false;
 162                 if (ctx->streamout.begin_emitted) {
 163                         si_emit_streamout_end(ctx);
 164                         ctx->streamout.suspended = true;
 165                 }
 166         }
 167
 168         /* Make sure CP DMA is idle at the end of IBs after L2 prefetches
 169          * because the kernel doesn't wait for it. */
 170         if (ctx->chip_class >= GFX7)
 171                 si_cp_dma_wait_for_idle(ctx);
 172
 173         /* Wait for draw calls to finish if needed. */
 174         if (wait_flags) {
 175                 ctx->flags |= wait_flags;
 176                 si_emit_cache_flush(ctx);
 177         }
 178         ctx->gfx_last_ib_is_busy = wait_flags == 0;
 179
 180         if (ctx->current_saved_cs) {
 181                 si_trace_emit(ctx);
 182
 183                 /* Save the IB for debug contexts. */
 184                 si_save_cs(ws, cs, &ctx->current_saved_cs->gfx, true);
 185                 ctx->current_saved_cs->flushed = true;
 186                 ctx->current_saved_cs->time_flush = os_time_get_nano();
 187
 188                 si_log_hw_flush(ctx);
 189         }
 190
 191         if (si_compute_prim_discard_enabled(ctx)) {
 192                 /* The compute IB can start after the previous gfx IB starts. */
 193                 if (radeon_emitted(ctx->prim_discard_compute_cs, 0) &&
 194                     ctx->last_gfx_fence) {
 195                         ctx->ws->cs_add_fence_dependency(ctx->gfx_cs,
 196                                                          ctx->last_gfx_fence,
 197                                                          RADEON_DEPENDENCY_PARALLEL_COMPUTE_ONLY |
 198                                                          RADEON_DEPENDENCY_START_FENCE);
 199                 }
 200
 201                 /* Remember the last execution barrier. It's in the IB.
 202                  * It will signal the start of the next compute IB.
 203                  */
 204                 if (flags & RADEON_FLUSH_START_NEXT_GFX_IB_NOW &&
 205                     ctx->last_pkt3_write_data) {
 206                         *ctx->last_pkt3_write_data = PKT3(PKT3_WRITE_DATA, 3, 0);
 207                         ctx->last_pkt3_write_data = NULL;
 208
 209                         si_resource_reference(&ctx->last_ib_barrier_buf, ctx->barrier_buf);
 210                         ctx->last_ib_barrier_buf_offset = ctx->barrier_buf_offset;
 211                         si_resource_reference(&ctx->barrier_buf, NULL);
 212
 213                         ws->fence_reference(&ctx->last_ib_barrier_fence, NULL);
 214                 }
 215         }
 216
 217         /* Flush the CS. */
 218         ws->cs_flush(cs, flags, &ctx->last_gfx_fence);
 219         if (fence)
 220                 ws->fence_reference(fence, ctx->last_gfx_fence);
 221
 222         ctx->num_gfx_cs_flushes++;
 223
 224         if (si_compute_prim_discard_enabled(ctx)) {
 225                 /* Remember the last execution barrier, which is the last fence
 226                  * in this case.
 227                  */
 228                 if (!(flags & RADEON_FLUSH_START_NEXT_GFX_IB_NOW)) {
 229                         ctx->last_pkt3_write_data = NULL;
 230                         si_resource_reference(&ctx->last_ib_barrier_buf, NULL);
 231                         ws->fence_reference(&ctx->last_ib_barrier_fence, ctx->last_gfx_fence);
 232                 }
 233         }
 234
 235         /* Check VM faults if needed. */
 236         if (ctx->screen->debug_flags & DBG(CHECK_VM)) {
 237                 /* Use conservative timeout 800ms, after which we won't wait any
 238                  * longer and assume the GPU is hung.
 239                  */
 240                 ctx->ws->fence_wait(ctx->ws, ctx->last_gfx_fence, 800*1000*1000);
 241
 242                 si_check_vm_faults(ctx, &ctx->current_saved_cs->gfx, RING_GFX);
 243         }
 244
 245         if (ctx->current_saved_cs)
 246                 si_saved_cs_reference(&ctx->current_saved_cs, NULL);
 247
 248         si_begin_new_gfx_cs(ctx);
 249         ctx->gfx_flush_in_progress = false;
 250 }
 251
 252 static void si_begin_gfx_cs_debug(struct si_context *ctx)
 253 {
 254         static const uint32_t zeros[1];
 255         assert(!ctx->current_saved_cs);
 256
 257         ctx->current_saved_cs = calloc(1, sizeof(*ctx->current_saved_cs));
 258         if (!ctx->current_saved_cs)
 259                 return;
 260
 261         pipe_reference_init(&ctx->current_saved_cs->reference, 1);
 262
 263         ctx->current_saved_cs->trace_buf = si_resource(
 264                 pipe_buffer_create(ctx->b.screen, 0, PIPE_USAGE_STAGING, 8));
 265         if (!ctx->current_saved_cs->trace_buf) {
 266                 free(ctx->current_saved_cs);
 267                 ctx->current_saved_cs = NULL;
 268                 return;
 269         }
 270
 271         pipe_buffer_write_nooverlap(&ctx->b, &ctx->current_saved_cs->trace_buf->b.b,
 272                                     0, sizeof(zeros), zeros);
 273         ctx->current_saved_cs->trace_id = 0;
 274
 275         si_trace_emit(ctx);
 276
 277         radeon_add_to_buffer_list(ctx, ctx->gfx_cs, ctx->current_saved_cs->trace_buf,
 278                               RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
 279 }
 280
 281 void si_begin_new_gfx_cs(struct si_context *ctx)
 282 {
 283         if (ctx->is_debug)
 284                 si_begin_gfx_cs_debug(ctx);
 285
 286         if (ctx->gds) {
 287                 ctx->ws->cs_add_buffer(ctx->gfx_cs, ctx->gds,
 288                                        RADEON_USAGE_READWRITE, 0, 0);
 289                 if (ctx->gds_oa) {
 290                         ctx->ws->cs_add_buffer(ctx->gfx_cs, ctx->gds_oa,
 291                                                RADEON_USAGE_READWRITE, 0, 0);
 292                 }
 293         }
 294
 295
 296         /* Always invalidate caches at the beginning of IBs, because external
 297          * users (e.g. BO evictions and SDMA/UVD/VCE IBs) can modify our
 298          * buffers.
 299          *
 300          * Note that the cache flush done by the kernel at the end of GFX IBs
 301          * isn't useful here, because that flush can finish after the following
 302          * IB starts drawing.
 303          *
 304          * TODO: Do we also need to invalidate CB & DB caches?
 305          */
 306         ctx->flags |= SI_CONTEXT_INV_ICACHE |
 307                       SI_CONTEXT_INV_SCACHE |
 308                       SI_CONTEXT_INV_VCACHE |
 309                       SI_CONTEXT_INV_L2 |
 310                       SI_CONTEXT_START_PIPELINE_STATS;
 311
 312         ctx->cs_shader_state.initialized = false;
 313         si_all_descriptors_begin_new_cs(ctx);
 314
 315         if (!ctx->has_graphics) {
 316                 ctx->initial_gfx_cs_size = ctx->gfx_cs->current.cdw;
 317                 return;
 318         }
 319
 320         /* set all valid group as dirty so they get reemited on
 321          * next draw command
 322          */
 323         si_pm4_reset_emitted(ctx);
 324
 325         /* The CS initialization should be emitted before everything else. */
 326         si_pm4_emit(ctx, ctx->init_config);
 327         if (ctx->init_config_gs_rings)
 328                 si_pm4_emit(ctx, ctx->init_config_gs_rings);
 329
 330         if (ctx->queued.named.ls)
 331                 ctx->prefetch_L2_mask |= SI_PREFETCH_LS;
 332         if (ctx->queued.named.hs)
 333                 ctx->prefetch_L2_mask |= SI_PREFETCH_HS;
 334         if (ctx->queued.named.es)
 335                 ctx->prefetch_L2_mask |= SI_PREFETCH_ES;
 336         if (ctx->queued.named.gs)
 337                 ctx->prefetch_L2_mask |= SI_PREFETCH_GS;
 338         if (ctx->queued.named.vs)
 339                 ctx->prefetch_L2_mask |= SI_PREFETCH_VS;
 340         if (ctx->queued.named.ps)
 341                 ctx->prefetch_L2_mask |= SI_PREFETCH_PS;
 342         if (ctx->vb_descriptors_buffer && ctx->vertex_elements)
 343                 ctx->prefetch_L2_mask |= SI_PREFETCH_VBO_DESCRIPTORS;
 344
 345         /* CLEAR_STATE disables all colorbuffers, so only enable bound ones. */
 346         bool has_clear_state = ctx->screen->has_clear_state;
 347         if (has_clear_state) {
 348                 ctx->framebuffer.dirty_cbufs =
 349                          u_bit_consecutive(0, ctx->framebuffer.state.nr_cbufs);
 350                 /* CLEAR_STATE disables the zbuffer, so only enable it if it's bound. */
 351                 ctx->framebuffer.dirty_zsbuf = ctx->framebuffer.state.zsbuf != NULL;
 352         } else {
 353                 ctx->framebuffer.dirty_cbufs = u_bit_consecutive(0, 8);
 354                 ctx->framebuffer.dirty_zsbuf = true;
 355         }
 356         /* This should always be marked as dirty to set the framebuffer scissor
 357          * at least. */
 358         si_mark_atom_dirty(ctx, &ctx->atoms.s.framebuffer);
 359
 360         si_mark_atom_dirty(ctx, &ctx->atoms.s.clip_regs);
 361         /* CLEAR_STATE sets zeros. */
 362         if (!has_clear_state || ctx->clip_state.any_nonzeros)
 363                 si_mark_atom_dirty(ctx, &ctx->atoms.s.clip_state);
 364         ctx->sample_locs_num_samples = 0;
 365         si_mark_atom_dirty(ctx, &ctx->atoms.s.msaa_sample_locs);
 366         si_mark_atom_dirty(ctx, &ctx->atoms.s.msaa_config);
 367         /* CLEAR_STATE sets 0xffff. */
 368         if (!has_clear_state || ctx->sample_mask != 0xffff)
 369                 si_mark_atom_dirty(ctx, &ctx->atoms.s.sample_mask);
 370         si_mark_atom_dirty(ctx, &ctx->atoms.s.cb_render_state);
 371         /* CLEAR_STATE sets zeros. */
 372         if (!has_clear_state || ctx->blend_color.any_nonzeros)
 373                 si_mark_atom_dirty(ctx, &ctx->atoms.s.blend_color);
 374         si_mark_atom_dirty(ctx, &ctx->atoms.s.db_render_state);
 375         if (ctx->chip_class >= GFX9)
 376                 si_mark_atom_dirty(ctx, &ctx->atoms.s.dpbb_state);
 377         si_mark_atom_dirty(ctx, &ctx->atoms.s.stencil_ref);
 378         si_mark_atom_dirty(ctx, &ctx->atoms.s.spi_map);
 379         si_mark_atom_dirty(ctx, &ctx->atoms.s.streamout_enable);
 380         si_mark_atom_dirty(ctx, &ctx->atoms.s.render_cond);
 381         /* CLEAR_STATE disables all window rectangles. */
 382         if (!has_clear_state || ctx->num_window_rectangles > 0)
 383                 si_mark_atom_dirty(ctx, &ctx->atoms.s.window_rectangles);
 384
 385         si_mark_atom_dirty(ctx, &ctx->atoms.s.guardband);
 386         si_mark_atom_dirty(ctx, &ctx->atoms.s.scissors);
 387         si_mark_atom_dirty(ctx, &ctx->atoms.s.viewports);
 388
 389         si_mark_atom_dirty(ctx, &ctx->atoms.s.scratch_state);
 390         if (ctx->scratch_buffer) {
 391                 si_context_add_resource_size(ctx, &ctx->scratch_buffer->b.b);
 392         }
 393
 394         if (ctx->streamout.suspended) {
 395                 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
 396                 si_streamout_buffers_dirty(ctx);
 397         }
 398
 399         if (!LIST_IS_EMPTY(&ctx->active_queries))
 400                 si_resume_queries(ctx);
 401
 402         assert(!ctx->gfx_cs->prev_dw);
 403         ctx->initial_gfx_cs_size = ctx->gfx_cs->current.cdw;
 404
 405         /* Invalidate various draw states so that they are emitted before
 406          * the first draw call. */
 407         si_invalidate_draw_sh_constants(ctx);
 408         ctx->last_index_size = -1;
 409         ctx->last_primitive_restart_en = -1;
 410         ctx->last_restart_index = SI_RESTART_INDEX_UNKNOWN;
 411         ctx->last_prim = -1;
 412         ctx->last_multi_vgt_param = -1;
 413         ctx->last_rast_prim = -1;
 414         ctx->last_sc_line_stipple = ~0;
 415         ctx->last_vs_state = ~0;
 416         ctx->last_ls = NULL;
 417         ctx->last_tcs = NULL;
 418         ctx->last_tes_sh_base = -1;
 419         ctx->last_num_tcs_input_cp = -1;
 420         ctx->last_ls_hs_config = -1; /* impossible value */
 421
 422         ctx->prim_discard_compute_ib_initialized = false;
 423
 424         /* Compute-based primitive discard:
 425          *   The index ring is divided into 2 halves. Switch between the halves
 426          *   in the same fashion as doublebuffering.
 427          */
 428         if (ctx->index_ring_base)
 429                 ctx->index_ring_base = 0;
 430         else
 431                 ctx->index_ring_base = ctx->index_ring_size_per_ib;
 432
 433         ctx->index_ring_offset = 0;
 434
 435         if (has_clear_state) {
 436                 ctx->tracked_regs.reg_value[SI_TRACKED_DB_RENDER_CONTROL] = 0x00000000;
 437                 ctx->tracked_regs.reg_value[SI_TRACKED_DB_COUNT_CONTROL] = 0x00000000;
 438                 ctx->tracked_regs.reg_value[SI_TRACKED_DB_RENDER_OVERRIDE2] = 0x00000000;
 439                 ctx->tracked_regs.reg_value[SI_TRACKED_DB_SHADER_CONTROL] = 0x00000000;
 440                 ctx->tracked_regs.reg_value[SI_TRACKED_CB_TARGET_MASK] = 0xffffffff;
 441                 ctx->tracked_regs.reg_value[SI_TRACKED_CB_DCC_CONTROL] = 0x00000000;
 442                 ctx->tracked_regs.reg_value[SI_TRACKED_SX_PS_DOWNCONVERT] = 0x00000000;
 443                 ctx->tracked_regs.reg_value[SI_TRACKED_SX_BLEND_OPT_EPSILON] = 0x00000000;
 444                 ctx->tracked_regs.reg_value[SI_TRACKED_SX_BLEND_OPT_CONTROL] = 0x00000000;
 445                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_LINE_CNTL] = 0x00001000;
 446                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_AA_CONFIG] = 0x00000000;
 447                 ctx->tracked_regs.reg_value[SI_TRACKED_DB_EQAA] = 0x00000000;
 448                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_MODE_CNTL_1] = 0x00000000;
 449                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_PRIM_FILTER_CNTL] = 0;
 450                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL] = 0x00000000;
 451                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_VS_OUT_CNTL] = 0x00000000;
 452                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_CLIP_CNTL] = 0x00090000;
 453                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_BINNER_CNTL_0] = 0x00000003;
 454                 ctx->tracked_regs.reg_value[SI_TRACKED_DB_DFSM_CONTROL] = 0x00000000;
 455                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ]  = 0x3f800000;
 456                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_VERT_DISC_ADJ]  = 0x3f800000;
 457                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_HORZ_CLIP_ADJ]  = 0x3f800000;
 458                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_HORZ_DISC_ADJ]  = 0x3f800000;
 459                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET] = 0;
 460                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_VTX_CNTL] = 0x00000005;
 461                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_CLIPRECT_RULE]     = 0xffff;
 462                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_ESGS_RING_ITEMSIZE]  = 0x00000000;
 463                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_1]  = 0x00000000;
 464                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_2]  = 0x00000000;
 465                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_3]  = 0x00000000;
 466                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_OUT_PRIM_TYPE]    = 0x00000000;
 467                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_ITEMSIZE]  = 0x00000000;
 468                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_MAX_VERT_OUT]  = 0x00000000;
 469                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE]  = 0x00000000;
 470                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE_1]  = 0x00000000;
 471                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE_2]  = 0x00000000;
 472                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE_3]  = 0x00000000;
 473                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_INSTANCE_CNT]  = 0x00000000;
 474                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_ONCHIP_CNTL]  = 0x00000000;
 475                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP]  = 0x00000000;
 476                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_MODE]  = 0x00000000;
 477                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_PRIMITIVEID_EN]  = 0x00000000;
 478                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_REUSE_OFF]  = 0x00000000;
 479                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_VS_OUT_CONFIG]  = 0x00000000;
 480                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_POS_FORMAT]  = 0x00000000;
 481                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_VTE_CNTL]  = 0x00000000;
 482                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_PS_INPUT_ENA]  = 0x00000000;
 483                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_PS_INPUT_ADDR]  = 0x00000000;
 484                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_BARYC_CNTL]  = 0x00000000;
 485                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_PS_IN_CONTROL]  = 0x00000002;
 486                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_Z_FORMAT]  = 0x00000000;
 487                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_COL_FORMAT]  = 0x00000000;
 488                 ctx->tracked_regs.reg_value[SI_TRACKED_CB_SHADER_MASK]  = 0xffffffff;
 489                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_TF_PARAM]  = 0x00000000;
 490                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL]  = 0x0000001e; /* From GFX8 */
 491
 492                 /* Set all saved registers state to saved. */
 493                 ctx->tracked_regs.reg_saved = 0xffffffffffffffff;
 494         } else {
 495                 /* Set all saved registers state to unknown. */
 496                 ctx->tracked_regs.reg_saved = 0;
 497         }
 498
 499         /* 0xffffffff is a impossible value to register SPI_PS_INPUT_CNTL_n */
 500         memset(ctx->tracked_regs.spi_ps_input_cntl, 0xff, sizeof(uint32_t) * 32);
 501 }