src/gallium/drivers/radeonsi/si_gfx_cs.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "radeon/r600_cs.h"
  26
  27 #include "util/os_time.h"
  28
  29 /* initialize */
  30 void si_need_gfx_cs_space(struct si_context *ctx)
  31 {
  32         struct radeon_winsys_cs *cs = ctx->b.gfx_cs;
  33
  34         /* There is no need to flush the DMA IB here, because
  35          * r600_need_dma_space always flushes the GFX IB if there is
  36          * a conflict, which means any unflushed DMA commands automatically
  37          * precede the GFX IB (= they had no dependency on the GFX IB when
  38          * they were submitted).
  39          */
  40
  41         /* There are two memory usage counters in the winsys for all buffers
  42          * that have been added (cs_add_buffer) and two counters in the pipe
  43          * driver for those that haven't been added yet.
  44          */
  45         if (unlikely(!radeon_cs_memory_below_limit(ctx->b.screen, ctx->b.gfx_cs,
  46                                                    ctx->b.vram, ctx->b.gtt))) {
  47                 ctx->b.gtt = 0;
  48                 ctx->b.vram = 0;
  49                 si_flush_gfx_cs(ctx, PIPE_FLUSH_ASYNC, NULL);
  50                 return;
  51         }
  52         ctx->b.gtt = 0;
  53         ctx->b.vram = 0;
  54
  55         /* If the IB is sufficiently large, don't count the space needed
  56          * and just flush if there is not enough space left.
  57          *
  58          * Also reserve space for stopping queries at the end of IB, because
  59          * the number of active queries is mostly unlimited.
  60          */
  61         unsigned need_dwords = 2048 + ctx->b.num_cs_dw_queries_suspend;
  62         if (!ctx->b.ws->cs_check_space(cs, need_dwords))
  63                 si_flush_gfx_cs(ctx, PIPE_FLUSH_ASYNC, NULL);
  64 }
  65
  66 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
  67                      struct pipe_fence_handle **fence)
  68 {
  69         struct radeon_winsys_cs *cs = ctx->b.gfx_cs;
  70         struct radeon_winsys *ws = ctx->b.ws;
  71
  72         if (ctx->gfx_flush_in_progress)
  73                 return;
  74
  75         if (!radeon_emitted(cs, ctx->b.initial_gfx_cs_size))
  76                 return;
  77
  78         if (si_check_device_reset(&ctx->b))
  79                 return;
  80
  81         if (ctx->screen->debug_flags & DBG(CHECK_VM))
  82                 flags &= ~PIPE_FLUSH_ASYNC;
  83
  84         /* If the state tracker is flushing the GFX IB, r600_flush_from_st is
  85          * responsible for flushing the DMA IB and merging the fences from both.
  86          * This code is only needed when the driver flushes the GFX IB
  87          * internally, and it never asks for a fence handle.
  88          */
  89         if (radeon_emitted(ctx->b.dma_cs, 0)) {
  90                 assert(fence == NULL); /* internal flushes only */
  91                 si_flush_dma_cs(ctx, flags, NULL);
  92         }
  93
  94         ctx->gfx_flush_in_progress = true;
  95
  96         if (!LIST_IS_EMPTY(&ctx->b.active_queries))
  97                 si_suspend_queries(ctx);
  98
  99         ctx->streamout.suspended = false;
 100         if (ctx->streamout.begin_emitted) {
 101                 si_emit_streamout_end(ctx);
 102                 ctx->streamout.suspended = true;
 103         }
 104
 105         ctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
 106                         SI_CONTEXT_PS_PARTIAL_FLUSH;
 107
 108         /* DRM 3.1.0 doesn't flush TC for VI correctly. */
 109         if (ctx->b.chip_class == VI && ctx->b.screen->info.drm_minor <= 1)
 110                 ctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2 |
 111                                 SI_CONTEXT_INV_VMEM_L1;
 112
 113         si_emit_cache_flush(ctx);
 114
 115         if (ctx->current_saved_cs) {
 116                 si_trace_emit(ctx);
 117                 si_log_hw_flush(ctx);
 118
 119                 /* Save the IB for debug contexts. */
 120                 si_save_cs(ws, cs, &ctx->current_saved_cs->gfx, true);
 121                 ctx->current_saved_cs->flushed = true;
 122                 ctx->current_saved_cs->time_flush = os_time_get_nano();
 123         }
 124
 125         /* Flush the CS. */
 126         ws->cs_flush(cs, flags, &ctx->b.last_gfx_fence);
 127         if (fence)
 128                 ws->fence_reference(fence, ctx->b.last_gfx_fence);
 129
 130         /* This must be after cs_flush returns, since the context's API
 131          * thread can concurrently read this value in si_fence_finish. */
 132         ctx->b.num_gfx_cs_flushes++;
 133
 134         /* Check VM faults if needed. */
 135         if (ctx->screen->debug_flags & DBG(CHECK_VM)) {
 136                 /* Use conservative timeout 800ms, after which we won't wait any
 137                  * longer and assume the GPU is hung.
 138                  */
 139                 ctx->b.ws->fence_wait(ctx->b.ws, ctx->b.last_gfx_fence, 800*1000*1000);
 140
 141                 si_check_vm_faults(ctx, &ctx->current_saved_cs->gfx, RING_GFX);
 142         }
 143
 144         if (ctx->current_saved_cs)
 145                 si_saved_cs_reference(&ctx->current_saved_cs, NULL);
 146
 147         si_begin_new_gfx_cs(ctx);
 148         ctx->gfx_flush_in_progress = false;
 149 }
 150
 151 static void si_begin_gfx_cs_debug(struct si_context *ctx)
 152 {
 153         static const uint32_t zeros[1];
 154         assert(!ctx->current_saved_cs);
 155
 156         ctx->current_saved_cs = calloc(1, sizeof(*ctx->current_saved_cs));
 157         if (!ctx->current_saved_cs)
 158                 return;
 159
 160         pipe_reference_init(&ctx->current_saved_cs->reference, 1);
 161
 162         ctx->current_saved_cs->trace_buf = (struct r600_resource*)
 163                                  pipe_buffer_create(ctx->b.b.screen, 0,
 164                                                     PIPE_USAGE_STAGING, 8);
 165         if (!ctx->current_saved_cs->trace_buf) {
 166                 free(ctx->current_saved_cs);
 167                 ctx->current_saved_cs = NULL;
 168                 return;
 169         }
 170
 171         pipe_buffer_write_nooverlap(&ctx->b.b, &ctx->current_saved_cs->trace_buf->b.b,
 172                                     0, sizeof(zeros), zeros);
 173         ctx->current_saved_cs->trace_id = 0;
 174
 175         si_trace_emit(ctx);
 176
 177         radeon_add_to_buffer_list(ctx, ctx->b.gfx_cs, ctx->current_saved_cs->trace_buf,
 178                               RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
 179 }
 180
 181 void si_begin_new_gfx_cs(struct si_context *ctx)
 182 {
 183         if (ctx->is_debug)
 184                 si_begin_gfx_cs_debug(ctx);
 185
 186         /* Flush read caches at the beginning of CS not flushed by the kernel. */
 187         if (ctx->b.chip_class >= CIK)
 188                 ctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
 189                                 SI_CONTEXT_INV_ICACHE;
 190
 191         ctx->b.flags |= SI_CONTEXT_START_PIPELINE_STATS;
 192
 193         /* set all valid group as dirty so they get reemited on
 194          * next draw command
 195          */
 196         si_pm4_reset_emitted(ctx);
 197
 198         /* The CS initialization should be emitted before everything else. */
 199         si_pm4_emit(ctx, ctx->init_config);
 200         if (ctx->init_config_gs_rings)
 201                 si_pm4_emit(ctx, ctx->init_config_gs_rings);
 202
 203         if (ctx->queued.named.ls)
 204                 ctx->prefetch_L2_mask |= SI_PREFETCH_LS;
 205         if (ctx->queued.named.hs)
 206                 ctx->prefetch_L2_mask |= SI_PREFETCH_HS;
 207         if (ctx->queued.named.es)
 208                 ctx->prefetch_L2_mask |= SI_PREFETCH_ES;
 209         if (ctx->queued.named.gs)
 210                 ctx->prefetch_L2_mask |= SI_PREFETCH_GS;
 211         if (ctx->queued.named.vs)
 212                 ctx->prefetch_L2_mask |= SI_PREFETCH_VS;
 213         if (ctx->queued.named.ps)
 214                 ctx->prefetch_L2_mask |= SI_PREFETCH_PS;
 215         if (ctx->vb_descriptors_buffer && ctx->vertex_elements)
 216                 ctx->prefetch_L2_mask |= SI_PREFETCH_VBO_DESCRIPTORS;
 217
 218         /* CLEAR_STATE disables all colorbuffers, so only enable bound ones. */
 219         bool has_clear_state = ctx->screen->has_clear_state;
 220         if (has_clear_state) {
 221                 ctx->framebuffer.dirty_cbufs =
 222                          u_bit_consecutive(0, ctx->framebuffer.state.nr_cbufs);
 223                 /* CLEAR_STATE disables the zbuffer, so only enable it if it's bound. */
 224                 ctx->framebuffer.dirty_zsbuf = ctx->framebuffer.state.zsbuf != NULL;
 225         } else {
 226                 ctx->framebuffer.dirty_cbufs = u_bit_consecutive(0, 8);
 227                 ctx->framebuffer.dirty_zsbuf = true;
 228         }
 229         /* This should always be marked as dirty to set the framebuffer scissor
 230          * at least. */
 231         si_mark_atom_dirty(ctx, &ctx->framebuffer.atom);
 232
 233         si_mark_atom_dirty(ctx, &ctx->clip_regs);
 234         /* CLEAR_STATE sets zeros. */
 235         if (!has_clear_state || ctx->clip_state.any_nonzeros)
 236                 si_mark_atom_dirty(ctx, &ctx->clip_state.atom);
 237         ctx->msaa_sample_locs.nr_samples = 0;
 238         si_mark_atom_dirty(ctx, &ctx->msaa_sample_locs.atom);
 239         si_mark_atom_dirty(ctx, &ctx->msaa_config);
 240         /* CLEAR_STATE sets 0xffff. */
 241         if (!has_clear_state || ctx->sample_mask.sample_mask != 0xffff)
 242                 si_mark_atom_dirty(ctx, &ctx->sample_mask.atom);
 243         si_mark_atom_dirty(ctx, &ctx->cb_render_state);
 244         /* CLEAR_STATE sets zeros. */
 245         if (!has_clear_state || ctx->blend_color.any_nonzeros)
 246                 si_mark_atom_dirty(ctx, &ctx->blend_color.atom);
 247         si_mark_atom_dirty(ctx, &ctx->db_render_state);
 248         if (ctx->b.chip_class >= GFX9)
 249                 si_mark_atom_dirty(ctx, &ctx->dpbb_state);
 250         si_mark_atom_dirty(ctx, &ctx->stencil_ref.atom);
 251         si_mark_atom_dirty(ctx, &ctx->spi_map);
 252         si_mark_atom_dirty(ctx, &ctx->streamout.enable_atom);
 253         si_mark_atom_dirty(ctx, &ctx->b.render_cond_atom);
 254         si_all_descriptors_begin_new_cs(ctx);
 255         si_all_resident_buffers_begin_new_cs(ctx);
 256
 257         ctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 258         ctx->viewports.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 259         ctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 260         si_mark_atom_dirty(ctx, &ctx->scissors.atom);
 261         si_mark_atom_dirty(ctx, &ctx->viewports.atom);
 262
 263         si_mark_atom_dirty(ctx, &ctx->scratch_state);
 264         if (ctx->scratch_buffer) {
 265                 si_context_add_resource_size(&ctx->b.b,
 266                                              &ctx->scratch_buffer->b.b);
 267         }
 268
 269         if (ctx->streamout.suspended) {
 270                 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
 271                 si_streamout_buffers_dirty(ctx);
 272         }
 273
 274         if (!LIST_IS_EMPTY(&ctx->b.active_queries))
 275                 si_resume_queries(ctx);
 276
 277         assert(!ctx->b.gfx_cs->prev_dw);
 278         ctx->b.initial_gfx_cs_size = ctx->b.gfx_cs->current.cdw;
 279
 280         /* Invalidate various draw states so that they are emitted before
 281          * the first draw call. */
 282         si_invalidate_draw_sh_constants(ctx);
 283         ctx->last_index_size = -1;
 284         ctx->last_primitive_restart_en = -1;
 285         ctx->last_restart_index = SI_RESTART_INDEX_UNKNOWN;
 286         ctx->last_gs_out_prim = -1;
 287         ctx->last_prim = -1;
 288         ctx->last_multi_vgt_param = -1;
 289         ctx->last_rast_prim = -1;
 290         ctx->last_sc_line_stipple = ~0;
 291         ctx->last_vs_state = ~0;
 292         ctx->last_ls = NULL;
 293         ctx->last_tcs = NULL;
 294         ctx->last_tes_sh_base = -1;
 295         ctx->last_num_tcs_input_cp = -1;
 296
 297         ctx->cs_shader_state.initialized = false;
 298 }