src/gallium/drivers/radeonsi/si_gfx_cs.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  * Copyright 2018 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * on the rights to use, copy, modify, merge, publish, distribute, sub
  10  * license, and/or sell copies of the Software, and to permit persons to whom
  11  * the Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  21  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  22  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include "si_pipe.h"
  27
  28 #include "util/os_time.h"
  29
  30 /* initialize */
  31 void si_need_gfx_cs_space(struct si_context *ctx)
  32 {
  33         struct radeon_cmdbuf *cs = ctx->gfx_cs;
  34
  35         /* There is no need to flush the DMA IB here, because
  36          * r600_need_dma_space always flushes the GFX IB if there is
  37          * a conflict, which means any unflushed DMA commands automatically
  38          * precede the GFX IB (= they had no dependency on the GFX IB when
  39          * they were submitted).
  40          */
  41
  42         /* There are two memory usage counters in the winsys for all buffers
  43          * that have been added (cs_add_buffer) and two counters in the pipe
  44          * driver for those that haven't been added yet.
  45          */
  46         if (unlikely(!radeon_cs_memory_below_limit(ctx->screen, ctx->gfx_cs,
  47                                                    ctx->vram, ctx->gtt))) {
  48                 ctx->gtt = 0;
  49                 ctx->vram = 0;
  50                 si_flush_gfx_cs(ctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
  51                 return;
  52         }
  53         ctx->gtt = 0;
  54         ctx->vram = 0;
  55
  56         /* If the IB is sufficiently large, don't count the space needed
  57          * and just flush if there is not enough space left.
  58          *
  59          * Also reserve space for stopping queries at the end of IB, because
  60          * the number of active queries is mostly unlimited.
  61          */
  62         unsigned need_dwords = 2048 + ctx->num_cs_dw_queries_suspend;
  63         if (!ctx->ws->cs_check_space(cs, need_dwords))
  64                 si_flush_gfx_cs(ctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
  65 }
  66
  67 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
  68                      struct pipe_fence_handle **fence)
  69 {
  70         struct radeon_cmdbuf *cs = ctx->gfx_cs;
  71         struct radeon_winsys *ws = ctx->ws;
  72         unsigned wait_flags = 0;
  73
  74         if (ctx->gfx_flush_in_progress)
  75                 return;
  76
  77         if (!ctx->screen->info.kernel_flushes_tc_l2_after_ib) {
  78                 wait_flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
  79                               SI_CONTEXT_CS_PARTIAL_FLUSH |
  80                               SI_CONTEXT_INV_GLOBAL_L2;
  81         } else if (ctx->chip_class == SI) {
  82                 /* The kernel flushes L2 before shaders are finished. */
  83                 wait_flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
  84                               SI_CONTEXT_CS_PARTIAL_FLUSH;
  85         } else if (!(flags & RADEON_FLUSH_START_NEXT_GFX_IB_NOW)) {
  86                 wait_flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
  87                               SI_CONTEXT_CS_PARTIAL_FLUSH;
  88         }
  89
  90         /* Drop this flush if it's a no-op. */
  91         if (!radeon_emitted(cs, ctx->initial_gfx_cs_size) &&
  92             (!wait_flags || !ctx->gfx_last_ib_is_busy))
  93                 return;
  94
  95         if (si_check_device_reset(ctx))
  96                 return;
  97
  98         if (ctx->screen->debug_flags & DBG(CHECK_VM))
  99                 flags &= ~PIPE_FLUSH_ASYNC;
 100
 101         /* If the state tracker is flushing the GFX IB, si_flush_from_st is
 102          * responsible for flushing the DMA IB and merging the fences from both.
 103          * This code is only needed when the driver flushes the GFX IB
 104          * internally, and it never asks for a fence handle.
 105          */
 106         if (radeon_emitted(ctx->dma_cs, 0)) {
 107                 assert(fence == NULL); /* internal flushes only */
 108                 si_flush_dma_cs(ctx, flags, NULL);
 109         }
 110
 111         ctx->gfx_flush_in_progress = true;
 112
 113         if (!LIST_IS_EMPTY(&ctx->active_queries))
 114                 si_suspend_queries(ctx);
 115
 116         ctx->streamout.suspended = false;
 117         if (ctx->streamout.begin_emitted) {
 118                 si_emit_streamout_end(ctx);
 119                 ctx->streamout.suspended = true;
 120         }
 121
 122         /* Make sure CP DMA is idle at the end of IBs after L2 prefetches
 123          * because the kernel doesn't wait for it. */
 124         if (ctx->chip_class >= CIK)
 125                 si_cp_dma_wait_for_idle(ctx);
 126
 127         /* Wait for draw calls to finish if needed. */
 128         if (wait_flags) {
 129                 ctx->flags |= wait_flags;
 130                 si_emit_cache_flush(ctx);
 131         }
 132         ctx->gfx_last_ib_is_busy = wait_flags == 0;
 133
 134         if (ctx->current_saved_cs) {
 135                 si_trace_emit(ctx);
 136
 137                 /* Save the IB for debug contexts. */
 138                 si_save_cs(ws, cs, &ctx->current_saved_cs->gfx, true);
 139                 ctx->current_saved_cs->flushed = true;
 140                 ctx->current_saved_cs->time_flush = os_time_get_nano();
 141
 142                 si_log_hw_flush(ctx);
 143         }
 144
 145         /* Flush the CS. */
 146         ws->cs_flush(cs, flags, &ctx->last_gfx_fence);
 147         if (fence)
 148                 ws->fence_reference(fence, ctx->last_gfx_fence);
 149
 150         ctx->num_gfx_cs_flushes++;
 151
 152         /* Check VM faults if needed. */
 153         if (ctx->screen->debug_flags & DBG(CHECK_VM)) {
 154                 /* Use conservative timeout 800ms, after which we won't wait any
 155                  * longer and assume the GPU is hung.
 156                  */
 157                 ctx->ws->fence_wait(ctx->ws, ctx->last_gfx_fence, 800*1000*1000);
 158
 159                 si_check_vm_faults(ctx, &ctx->current_saved_cs->gfx, RING_GFX);
 160         }
 161
 162         if (ctx->current_saved_cs)
 163                 si_saved_cs_reference(&ctx->current_saved_cs, NULL);
 164
 165         si_begin_new_gfx_cs(ctx);
 166         ctx->gfx_flush_in_progress = false;
 167 }
 168
 169 static void si_begin_gfx_cs_debug(struct si_context *ctx)
 170 {
 171         static const uint32_t zeros[1];
 172         assert(!ctx->current_saved_cs);
 173
 174         ctx->current_saved_cs = calloc(1, sizeof(*ctx->current_saved_cs));
 175         if (!ctx->current_saved_cs)
 176                 return;
 177
 178         pipe_reference_init(&ctx->current_saved_cs->reference, 1);
 179
 180         ctx->current_saved_cs->trace_buf = r600_resource(
 181                 pipe_buffer_create(ctx->b.screen, 0, PIPE_USAGE_STAGING, 8));
 182         if (!ctx->current_saved_cs->trace_buf) {
 183                 free(ctx->current_saved_cs);
 184                 ctx->current_saved_cs = NULL;
 185                 return;
 186         }
 187
 188         pipe_buffer_write_nooverlap(&ctx->b, &ctx->current_saved_cs->trace_buf->b.b,
 189                                     0, sizeof(zeros), zeros);
 190         ctx->current_saved_cs->trace_id = 0;
 191
 192         si_trace_emit(ctx);
 193
 194         radeon_add_to_buffer_list(ctx, ctx->gfx_cs, ctx->current_saved_cs->trace_buf,
 195                               RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
 196 }
 197
 198 void si_begin_new_gfx_cs(struct si_context *ctx)
 199 {
 200         if (ctx->is_debug)
 201                 si_begin_gfx_cs_debug(ctx);
 202
 203         /* Always invalidate caches at the beginning of IBs, because external
 204          * users (e.g. BO evictions and SDMA/UVD/VCE IBs) can modify our
 205          * buffers.
 206          *
 207          * Note that the cache flush done by the kernel at the end of GFX IBs
 208          * isn't useful here, because that flush can finish after the following
 209          * IB starts drawing.
 210          *
 211          * TODO: Do we also need to invalidate CB & DB caches?
 212          */
 213         ctx->flags |= SI_CONTEXT_INV_ICACHE |
 214                       SI_CONTEXT_INV_SMEM_L1 |
 215                       SI_CONTEXT_INV_VMEM_L1 |
 216                       SI_CONTEXT_INV_GLOBAL_L2 |
 217                       SI_CONTEXT_START_PIPELINE_STATS;
 218
 219         /* set all valid group as dirty so they get reemited on
 220          * next draw command
 221          */
 222         si_pm4_reset_emitted(ctx);
 223
 224         /* The CS initialization should be emitted before everything else. */
 225         si_pm4_emit(ctx, ctx->init_config);
 226         if (ctx->init_config_gs_rings)
 227                 si_pm4_emit(ctx, ctx->init_config_gs_rings);
 228
 229         if (ctx->queued.named.ls)
 230                 ctx->prefetch_L2_mask |= SI_PREFETCH_LS;
 231         if (ctx->queued.named.hs)
 232                 ctx->prefetch_L2_mask |= SI_PREFETCH_HS;
 233         if (ctx->queued.named.es)
 234                 ctx->prefetch_L2_mask |= SI_PREFETCH_ES;
 235         if (ctx->queued.named.gs)
 236                 ctx->prefetch_L2_mask |= SI_PREFETCH_GS;
 237         if (ctx->queued.named.vs)
 238                 ctx->prefetch_L2_mask |= SI_PREFETCH_VS;
 239         if (ctx->queued.named.ps)
 240                 ctx->prefetch_L2_mask |= SI_PREFETCH_PS;
 241         if (ctx->vb_descriptors_buffer && ctx->vertex_elements)
 242                 ctx->prefetch_L2_mask |= SI_PREFETCH_VBO_DESCRIPTORS;
 243
 244         /* CLEAR_STATE disables all colorbuffers, so only enable bound ones. */
 245         bool has_clear_state = ctx->screen->has_clear_state;
 246         if (has_clear_state) {
 247                 ctx->framebuffer.dirty_cbufs =
 248                          u_bit_consecutive(0, ctx->framebuffer.state.nr_cbufs);
 249                 /* CLEAR_STATE disables the zbuffer, so only enable it if it's bound. */
 250                 ctx->framebuffer.dirty_zsbuf = ctx->framebuffer.state.zsbuf != NULL;
 251         } else {
 252                 ctx->framebuffer.dirty_cbufs = u_bit_consecutive(0, 8);
 253                 ctx->framebuffer.dirty_zsbuf = true;
 254         }
 255         /* This should always be marked as dirty to set the framebuffer scissor
 256          * at least. */
 257         si_mark_atom_dirty(ctx, &ctx->atoms.s.framebuffer);
 258
 259         si_mark_atom_dirty(ctx, &ctx->atoms.s.clip_regs);
 260         /* CLEAR_STATE sets zeros. */
 261         if (!has_clear_state || ctx->clip_state.any_nonzeros)
 262                 si_mark_atom_dirty(ctx, &ctx->atoms.s.clip_state);
 263         ctx->sample_locs_num_samples = 0;
 264         si_mark_atom_dirty(ctx, &ctx->atoms.s.msaa_sample_locs);
 265         si_mark_atom_dirty(ctx, &ctx->atoms.s.msaa_config);
 266         /* CLEAR_STATE sets 0xffff. */
 267         if (!has_clear_state || ctx->sample_mask != 0xffff)
 268                 si_mark_atom_dirty(ctx, &ctx->atoms.s.sample_mask);
 269         si_mark_atom_dirty(ctx, &ctx->atoms.s.cb_render_state);
 270         /* CLEAR_STATE sets zeros. */
 271         if (!has_clear_state || ctx->blend_color.any_nonzeros)
 272                 si_mark_atom_dirty(ctx, &ctx->atoms.s.blend_color);
 273         si_mark_atom_dirty(ctx, &ctx->atoms.s.db_render_state);
 274         if (ctx->chip_class >= GFX9)
 275                 si_mark_atom_dirty(ctx, &ctx->atoms.s.dpbb_state);
 276         si_mark_atom_dirty(ctx, &ctx->atoms.s.stencil_ref);
 277         si_mark_atom_dirty(ctx, &ctx->atoms.s.spi_map);
 278         si_mark_atom_dirty(ctx, &ctx->atoms.s.streamout_enable);
 279         si_mark_atom_dirty(ctx, &ctx->atoms.s.render_cond);
 280         /* CLEAR_STATE disables all window rectangles. */
 281         if (!has_clear_state || ctx->num_window_rectangles > 0)
 282                 si_mark_atom_dirty(ctx, &ctx->atoms.s.window_rectangles);
 283         si_all_descriptors_begin_new_cs(ctx);
 284         si_all_resident_buffers_begin_new_cs(ctx);
 285
 286         ctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 287         ctx->viewports.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 288         ctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 289         si_mark_atom_dirty(ctx, &ctx->atoms.s.guardband);
 290         si_mark_atom_dirty(ctx, &ctx->atoms.s.scissors);
 291         si_mark_atom_dirty(ctx, &ctx->atoms.s.viewports);
 292
 293         si_mark_atom_dirty(ctx, &ctx->atoms.s.scratch_state);
 294         if (ctx->scratch_buffer) {
 295                 si_context_add_resource_size(ctx, &ctx->scratch_buffer->b.b);
 296         }
 297
 298         if (ctx->streamout.suspended) {
 299                 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
 300                 si_streamout_buffers_dirty(ctx);
 301         }
 302
 303         if (!LIST_IS_EMPTY(&ctx->active_queries))
 304                 si_resume_queries(ctx);
 305
 306         assert(!ctx->gfx_cs->prev_dw);
 307         ctx->initial_gfx_cs_size = ctx->gfx_cs->current.cdw;
 308
 309         /* Invalidate various draw states so that they are emitted before
 310          * the first draw call. */
 311         si_invalidate_draw_sh_constants(ctx);
 312         ctx->last_index_size = -1;
 313         ctx->last_primitive_restart_en = -1;
 314         ctx->last_restart_index = SI_RESTART_INDEX_UNKNOWN;
 315         ctx->last_prim = -1;
 316         ctx->last_multi_vgt_param = -1;
 317         ctx->last_rast_prim = -1;
 318         ctx->last_sc_line_stipple = ~0;
 319         ctx->last_vs_state = ~0;
 320         ctx->last_ls = NULL;
 321         ctx->last_tcs = NULL;
 322         ctx->last_tes_sh_base = -1;
 323         ctx->last_num_tcs_input_cp = -1;
 324         ctx->last_ls_hs_config = -1; /* impossible value */
 325
 326         ctx->cs_shader_state.initialized = false;
 327
 328         if (has_clear_state) {
 329                 ctx->tracked_regs.reg_value[SI_TRACKED_DB_RENDER_CONTROL] = 0x00000000;
 330                 ctx->tracked_regs.reg_value[SI_TRACKED_DB_COUNT_CONTROL] = 0x00000000;
 331                 ctx->tracked_regs.reg_value[SI_TRACKED_DB_RENDER_OVERRIDE2] = 0x00000000;
 332                 ctx->tracked_regs.reg_value[SI_TRACKED_DB_SHADER_CONTROL] = 0x00000000;
 333                 ctx->tracked_regs.reg_value[SI_TRACKED_CB_TARGET_MASK] = 0xffffffff;
 334                 ctx->tracked_regs.reg_value[SI_TRACKED_CB_DCC_CONTROL] = 0x00000000;
 335                 ctx->tracked_regs.reg_value[SI_TRACKED_SX_PS_DOWNCONVERT] = 0x00000000;
 336                 ctx->tracked_regs.reg_value[SI_TRACKED_SX_BLEND_OPT_EPSILON] = 0x00000000;
 337                 ctx->tracked_regs.reg_value[SI_TRACKED_SX_BLEND_OPT_CONTROL] = 0x00000000;
 338                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_LINE_CNTL] = 0x00001000;
 339                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_AA_CONFIG] = 0x00000000;
 340                 ctx->tracked_regs.reg_value[SI_TRACKED_DB_EQAA] = 0x00000000;
 341                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_MODE_CNTL_1] = 0x00000000;
 342                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_PRIM_FILTER_CNTL] = 0;
 343                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL] = 0x00000000;
 344                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_VS_OUT_CNTL] = 0x00000000;
 345                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_CLIP_CNTL] = 0x00090000;
 346                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_BINNER_CNTL_0] = 0x00000003;
 347                 ctx->tracked_regs.reg_value[SI_TRACKED_DB_DFSM_CONTROL] = 0x00000000;
 348                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ]  = 0x3f800000;
 349                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_VERT_DISC_ADJ]  = 0x3f800000;
 350                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_HORZ_CLIP_ADJ]  = 0x3f800000;
 351                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_HORZ_DISC_ADJ]  = 0x3f800000;
 352                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET] = 0;
 353                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_CLIPRECT_RULE]     = 0xffff;
 354                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_ESGS_RING_ITEMSIZE]  = 0x00000000;
 355                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_1]  = 0x00000000;
 356                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_2]  = 0x00000000;
 357                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_3]  = 0x00000000;
 358                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_OUT_PRIM_TYPE]    = 0x00000000;
 359                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_ITEMSIZE]  = 0x00000000;
 360                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_MAX_VERT_OUT]  = 0x00000000;
 361                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE]  = 0x00000000;
 362                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE_1]  = 0x00000000;
 363                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE_2]  = 0x00000000;
 364                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE_3]  = 0x00000000;
 365                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_INSTANCE_CNT]  = 0x00000000;
 366                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_ONCHIP_CNTL]  = 0x00000000;
 367                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP]  = 0x00000000;
 368                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_MODE]  = 0x00000000;
 369                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_PRIMITIVEID_EN]  = 0x00000000;
 370                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_REUSE_OFF]  = 0x00000000;
 371                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_VS_OUT_CONFIG]  = 0x00000000;
 372                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_POS_FORMAT]  = 0x00000000;
 373                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_VTE_CNTL]  = 0x00000000;
 374                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_PS_INPUT_ENA]  = 0x00000000;
 375                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_PS_INPUT_ADDR]  = 0x00000000;
 376                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_BARYC_CNTL]  = 0x00000000;
 377                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_PS_IN_CONTROL]  = 0x00000002;
 378                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_Z_FORMAT]  = 0x00000000;
 379                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_COL_FORMAT]  = 0x00000000;
 380                 ctx->tracked_regs.reg_value[SI_TRACKED_CB_SHADER_MASK]  = 0xffffffff;
 381                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_TF_PARAM]  = 0x00000000;
 382                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL]  = 0x0000001e; /* From VI */
 383
 384                 /* Set all saved registers state to saved. */
 385                 ctx->tracked_regs.reg_saved = 0xffffffffffffffff;
 386         } else {
 387                 /* Set all saved registers state to unknown. */
 388                 ctx->tracked_regs.reg_saved = 0;
 389         }
 390
 391         /* 0xffffffff is a impossible value to register SPI_PS_INPUT_CNTL_n */
 392         memset(ctx->tracked_regs.spi_ps_input_cntl, 0xff, sizeof(uint32_t) * 32);
 393 }