src/gallium/drivers/radeonsi/si_gfx_cs.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  * Copyright 2018 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * on the rights to use, copy, modify, merge, publish, distribute, sub
  10  * license, and/or sell copies of the Software, and to permit persons to whom
  11  * the Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  21  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  22  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include "si_pipe.h"
  27 #include "si_build_pm4.h"
  28 #include "sid.h"
  29
  30 #include "util/os_time.h"
  31 #include "util/u_upload_mgr.h"
  32
  33 /* initialize */
  34 void si_need_gfx_cs_space(struct si_context *ctx)
  35 {
  36         struct radeon_cmdbuf *cs = ctx->gfx_cs;
  37
  38         /* There is no need to flush the DMA IB here, because
  39          * si_need_dma_space always flushes the GFX IB if there is
  40          * a conflict, which means any unflushed DMA commands automatically
  41          * precede the GFX IB (= they had no dependency on the GFX IB when
  42          * they were submitted).
  43          */
  44
  45         /* There are two memory usage counters in the winsys for all buffers
  46          * that have been added (cs_add_buffer) and two counters in the pipe
  47          * driver for those that haven't been added yet.
  48          */
  49         if (unlikely(!radeon_cs_memory_below_limit(ctx->screen, ctx->gfx_cs,
  50                                                    ctx->vram, ctx->gtt))) {
  51                 ctx->gtt = 0;
  52                 ctx->vram = 0;
  53                 si_flush_gfx_cs(ctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
  54                 return;
  55         }
  56         ctx->gtt = 0;
  57         ctx->vram = 0;
  58
  59         unsigned need_dwords = si_get_minimum_num_gfx_cs_dwords(ctx);
  60         if (!ctx->ws->cs_check_space(cs, need_dwords, false))
  61                 si_flush_gfx_cs(ctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
  62 }
  63
  64 void si_unref_sdma_uploads(struct si_context *sctx)
  65 {
  66         for (unsigned i = 0; i < sctx->num_sdma_uploads; i++) {
  67                 si_resource_reference(&sctx->sdma_uploads[i].dst, NULL);
  68                 si_resource_reference(&sctx->sdma_uploads[i].src, NULL);
  69         }
  70         sctx->num_sdma_uploads = 0;
  71 }
  72
  73 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
  74                      struct pipe_fence_handle **fence)
  75 {
  76         struct radeon_cmdbuf *cs = ctx->gfx_cs;
  77         struct radeon_winsys *ws = ctx->ws;
  78         const unsigned wait_ps_cs = SI_CONTEXT_PS_PARTIAL_FLUSH |
  79                                     SI_CONTEXT_CS_PARTIAL_FLUSH;
  80         unsigned wait_flags = 0;
  81
  82         if (ctx->gfx_flush_in_progress)
  83                 return;
  84
  85         if (!ctx->screen->info.kernel_flushes_tc_l2_after_ib) {
  86                 wait_flags |= wait_ps_cs |
  87                               SI_CONTEXT_INV_L2;
  88         } else if (ctx->chip_class == GFX6) {
  89                 /* The kernel flushes L2 before shaders are finished. */
  90                 wait_flags |= wait_ps_cs;
  91         } else if (!(flags & RADEON_FLUSH_START_NEXT_GFX_IB_NOW)) {
  92                 wait_flags |= wait_ps_cs;
  93         }
  94
  95         /* Drop this flush if it's a no-op. */
  96         if (!radeon_emitted(cs, ctx->initial_gfx_cs_size) &&
  97             (!wait_flags || !ctx->gfx_last_ib_is_busy))
  98                 return;
  99
 100         if (ctx->b.get_device_reset_status(&ctx->b) != PIPE_NO_RESET)
 101                 return;
 102
 103         if (ctx->screen->debug_flags & DBG(CHECK_VM))
 104                 flags &= ~PIPE_FLUSH_ASYNC;
 105
 106         ctx->gfx_flush_in_progress = true;
 107
 108         /* If the state tracker is flushing the GFX IB, si_flush_from_st is
 109          * responsible for flushing the DMA IB and merging the fences from both.
 110          * If the driver flushes the GFX IB internally, and it should never ask
 111          * for a fence handle.
 112          */
 113         assert(!radeon_emitted(ctx->sdma_cs, 0) || fence == NULL);
 114
 115         /* Update the sdma_uploads list by flushing the uploader. */
 116         u_upload_unmap(ctx->b.const_uploader);
 117
 118         /* Execute SDMA uploads. */
 119         ctx->sdma_uploads_in_progress = true;
 120         for (unsigned i = 0; i < ctx->num_sdma_uploads; i++) {
 121                 struct si_sdma_upload *up = &ctx->sdma_uploads[i];
 122
 123                 assert(up->src_offset % 4 == 0 && up->dst_offset % 4 == 0 &&
 124                        up->size % 4 == 0);
 125
 126                 si_sdma_copy_buffer(ctx, &up->dst->b.b, &up->src->b.b,
 127                                     up->dst_offset, up->src_offset, up->size);
 128         }
 129         ctx->sdma_uploads_in_progress = false;
 130         si_unref_sdma_uploads(ctx);
 131
 132         /* Flush SDMA (preamble IB). */
 133         if (radeon_emitted(ctx->sdma_cs, 0))
 134                 si_flush_dma_cs(ctx, flags, NULL);
 135
 136         if (radeon_emitted(ctx->prim_discard_compute_cs, 0)) {
 137                 struct radeon_cmdbuf *compute_cs = ctx->prim_discard_compute_cs;
 138                 si_compute_signal_gfx(ctx);
 139
 140                 /* Make sure compute shaders are idle before leaving the IB, so that
 141                  * the next IB doesn't overwrite GDS that might be in use. */
 142                 radeon_emit(compute_cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 143                 radeon_emit(compute_cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) |
 144                                         EVENT_INDEX(4));
 145
 146                 /* Save the GDS prim restart counter if needed. */
 147                 if (ctx->preserve_prim_restart_gds_at_flush) {
 148                         si_cp_copy_data(ctx, compute_cs,
 149                                         COPY_DATA_DST_MEM, ctx->wait_mem_scratch, 4,
 150                                         COPY_DATA_GDS, NULL, 4);
 151                 }
 152         }
 153
 154         if (ctx->has_graphics) {
 155                 if (!list_is_empty(&ctx->active_queries))
 156                         si_suspend_queries(ctx);
 157
 158                 ctx->streamout.suspended = false;
 159                 if (ctx->streamout.begin_emitted) {
 160                         si_emit_streamout_end(ctx);
 161                         ctx->streamout.suspended = true;
 162
 163                         /* Since NGG streamout uses GDS, we need to make GDS
 164                          * idle when we leave the IB, otherwise another process
 165                          * might overwrite it while our shaders are busy.
 166                          */
 167                         if (ctx->screen->use_ngg_streamout)
 168                                 wait_flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
 169                 }
 170         }
 171
 172         /* Make sure CP DMA is idle at the end of IBs after L2 prefetches
 173          * because the kernel doesn't wait for it. */
 174         if (ctx->chip_class >= GFX7)
 175                 si_cp_dma_wait_for_idle(ctx);
 176
 177         /* Wait for draw calls to finish if needed. */
 178         if (wait_flags) {
 179                 ctx->flags |= wait_flags;
 180                 ctx->emit_cache_flush(ctx);
 181         }
 182         ctx->gfx_last_ib_is_busy = (wait_flags & wait_ps_cs) != wait_ps_cs;
 183
 184         if (ctx->current_saved_cs) {
 185                 si_trace_emit(ctx);
 186
 187                 /* Save the IB for debug contexts. */
 188                 si_save_cs(ws, cs, &ctx->current_saved_cs->gfx, true);
 189                 ctx->current_saved_cs->flushed = true;
 190                 ctx->current_saved_cs->time_flush = os_time_get_nano();
 191
 192                 si_log_hw_flush(ctx);
 193         }
 194
 195         if (si_compute_prim_discard_enabled(ctx)) {
 196                 /* The compute IB can start after the previous gfx IB starts. */
 197                 if (radeon_emitted(ctx->prim_discard_compute_cs, 0) &&
 198                     ctx->last_gfx_fence) {
 199                         ctx->ws->cs_add_fence_dependency(ctx->gfx_cs,
 200                                                          ctx->last_gfx_fence,
 201                                                          RADEON_DEPENDENCY_PARALLEL_COMPUTE_ONLY |
 202                                                          RADEON_DEPENDENCY_START_FENCE);
 203                 }
 204
 205                 /* Remember the last execution barrier. It's in the IB.
 206                  * It will signal the start of the next compute IB.
 207                  */
 208                 if (flags & RADEON_FLUSH_START_NEXT_GFX_IB_NOW &&
 209                     ctx->last_pkt3_write_data) {
 210                         *ctx->last_pkt3_write_data = PKT3(PKT3_WRITE_DATA, 3, 0);
 211                         ctx->last_pkt3_write_data = NULL;
 212
 213                         si_resource_reference(&ctx->last_ib_barrier_buf, ctx->barrier_buf);
 214                         ctx->last_ib_barrier_buf_offset = ctx->barrier_buf_offset;
 215                         si_resource_reference(&ctx->barrier_buf, NULL);
 216
 217                         ws->fence_reference(&ctx->last_ib_barrier_fence, NULL);
 218                 }
 219         }
 220
 221         /* Flush the CS. */
 222         ws->cs_flush(cs, flags, &ctx->last_gfx_fence);
 223         if (fence)
 224                 ws->fence_reference(fence, ctx->last_gfx_fence);
 225
 226         ctx->num_gfx_cs_flushes++;
 227
 228         if (si_compute_prim_discard_enabled(ctx)) {
 229                 /* Remember the last execution barrier, which is the last fence
 230                  * in this case.
 231                  */
 232                 if (!(flags & RADEON_FLUSH_START_NEXT_GFX_IB_NOW)) {
 233                         ctx->last_pkt3_write_data = NULL;
 234                         si_resource_reference(&ctx->last_ib_barrier_buf, NULL);
 235                         ws->fence_reference(&ctx->last_ib_barrier_fence, ctx->last_gfx_fence);
 236                 }
 237         }
 238
 239         /* Check VM faults if needed. */
 240         if (ctx->screen->debug_flags & DBG(CHECK_VM)) {
 241                 /* Use conservative timeout 800ms, after which we won't wait any
 242                  * longer and assume the GPU is hung.
 243                  */
 244                 ctx->ws->fence_wait(ctx->ws, ctx->last_gfx_fence, 800*1000*1000);
 245
 246                 si_check_vm_faults(ctx, &ctx->current_saved_cs->gfx, RING_GFX);
 247         }
 248
 249         if (ctx->current_saved_cs)
 250                 si_saved_cs_reference(&ctx->current_saved_cs, NULL);
 251
 252         si_begin_new_gfx_cs(ctx);
 253         ctx->gfx_flush_in_progress = false;
 254 }
 255
 256 static void si_begin_gfx_cs_debug(struct si_context *ctx)
 257 {
 258         static const uint32_t zeros[1];
 259         assert(!ctx->current_saved_cs);
 260
 261         ctx->current_saved_cs = calloc(1, sizeof(*ctx->current_saved_cs));
 262         if (!ctx->current_saved_cs)
 263                 return;
 264
 265         pipe_reference_init(&ctx->current_saved_cs->reference, 1);
 266
 267         ctx->current_saved_cs->trace_buf = si_resource(
 268                 pipe_buffer_create(ctx->b.screen, 0, PIPE_USAGE_STAGING, 8));
 269         if (!ctx->current_saved_cs->trace_buf) {
 270                 free(ctx->current_saved_cs);
 271                 ctx->current_saved_cs = NULL;
 272                 return;
 273         }
 274
 275         pipe_buffer_write_nooverlap(&ctx->b, &ctx->current_saved_cs->trace_buf->b.b,
 276                                     0, sizeof(zeros), zeros);
 277         ctx->current_saved_cs->trace_id = 0;
 278
 279         si_trace_emit(ctx);
 280
 281         radeon_add_to_buffer_list(ctx, ctx->gfx_cs, ctx->current_saved_cs->trace_buf,
 282                               RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
 283 }
 284
 285 static void si_add_gds_to_buffer_list(struct si_context *sctx)
 286 {
 287         if (sctx->gds) {
 288                 sctx->ws->cs_add_buffer(sctx->gfx_cs, sctx->gds,
 289                                        RADEON_USAGE_READWRITE, 0, 0);
 290                 if (sctx->gds_oa) {
 291                         sctx->ws->cs_add_buffer(sctx->gfx_cs, sctx->gds_oa,
 292                                                RADEON_USAGE_READWRITE, 0, 0);
 293                 }
 294         }
 295 }
 296
 297 void si_allocate_gds(struct si_context *sctx)
 298 {
 299         struct radeon_winsys *ws = sctx->ws;
 300
 301         if (sctx->gds)
 302                 return;
 303
 304         assert(sctx->screen->use_ngg_streamout);
 305
 306         /* 4 streamout GDS counters.
 307          * We need 256B (64 dw) of GDS, otherwise streamout hangs.
 308          */
 309         sctx->gds = ws->buffer_create(ws, 256, 4, RADEON_DOMAIN_GDS, 0);
 310         sctx->gds_oa = ws->buffer_create(ws, 4, 1, RADEON_DOMAIN_OA, 0);
 311
 312         assert(sctx->gds && sctx->gds_oa);
 313         si_add_gds_to_buffer_list(sctx);
 314 }
 315
 316 void si_begin_new_gfx_cs(struct si_context *ctx)
 317 {
 318         if (ctx->is_debug)
 319                 si_begin_gfx_cs_debug(ctx);
 320
 321         si_add_gds_to_buffer_list(ctx);
 322
 323         /* Always invalidate caches at the beginning of IBs, because external
 324          * users (e.g. BO evictions and SDMA/UVD/VCE IBs) can modify our
 325          * buffers.
 326          *
 327          * Note that the cache flush done by the kernel at the end of GFX IBs
 328          * isn't useful here, because that flush can finish after the following
 329          * IB starts drawing.
 330          *
 331          * TODO: Do we also need to invalidate CB & DB caches?
 332          */
 333         ctx->flags |= SI_CONTEXT_INV_ICACHE |
 334                       SI_CONTEXT_INV_SCACHE |
 335                       SI_CONTEXT_INV_VCACHE |
 336                       SI_CONTEXT_INV_L2 |
 337                       SI_CONTEXT_START_PIPELINE_STATS;
 338
 339         ctx->cs_shader_state.initialized = false;
 340         si_all_descriptors_begin_new_cs(ctx);
 341
 342         if (!ctx->has_graphics) {
 343                 ctx->initial_gfx_cs_size = ctx->gfx_cs->current.cdw;
 344                 return;
 345         }
 346
 347         /* set all valid group as dirty so they get reemited on
 348          * next draw command
 349          */
 350         si_pm4_reset_emitted(ctx);
 351
 352         /* The CS initialization should be emitted before everything else. */
 353         si_pm4_emit(ctx, ctx->init_config);
 354         if (ctx->init_config_gs_rings)
 355                 si_pm4_emit(ctx, ctx->init_config_gs_rings);
 356
 357         if (ctx->queued.named.ls)
 358                 ctx->prefetch_L2_mask |= SI_PREFETCH_LS;
 359         if (ctx->queued.named.hs)
 360                 ctx->prefetch_L2_mask |= SI_PREFETCH_HS;
 361         if (ctx->queued.named.es)
 362                 ctx->prefetch_L2_mask |= SI_PREFETCH_ES;
 363         if (ctx->queued.named.gs)
 364                 ctx->prefetch_L2_mask |= SI_PREFETCH_GS;
 365         if (ctx->queued.named.vs)
 366                 ctx->prefetch_L2_mask |= SI_PREFETCH_VS;
 367         if (ctx->queued.named.ps)
 368                 ctx->prefetch_L2_mask |= SI_PREFETCH_PS;
 369         if (ctx->vb_descriptors_buffer && ctx->vertex_elements)
 370                 ctx->prefetch_L2_mask |= SI_PREFETCH_VBO_DESCRIPTORS;
 371
 372         /* CLEAR_STATE disables all colorbuffers, so only enable bound ones. */
 373         bool has_clear_state = ctx->screen->info.has_clear_state;
 374         if (has_clear_state) {
 375                 ctx->framebuffer.dirty_cbufs =
 376                          u_bit_consecutive(0, ctx->framebuffer.state.nr_cbufs);
 377                 /* CLEAR_STATE disables the zbuffer, so only enable it if it's bound. */
 378                 ctx->framebuffer.dirty_zsbuf = ctx->framebuffer.state.zsbuf != NULL;
 379         } else {
 380                 ctx->framebuffer.dirty_cbufs = u_bit_consecutive(0, 8);
 381                 ctx->framebuffer.dirty_zsbuf = true;
 382         }
 383         /* This should always be marked as dirty to set the framebuffer scissor
 384          * at least. */
 385         si_mark_atom_dirty(ctx, &ctx->atoms.s.framebuffer);
 386
 387         si_mark_atom_dirty(ctx, &ctx->atoms.s.clip_regs);
 388         /* CLEAR_STATE sets zeros. */
 389         if (!has_clear_state || ctx->clip_state.any_nonzeros)
 390                 si_mark_atom_dirty(ctx, &ctx->atoms.s.clip_state);
 391         ctx->sample_locs_num_samples = 0;
 392         si_mark_atom_dirty(ctx, &ctx->atoms.s.msaa_sample_locs);
 393         si_mark_atom_dirty(ctx, &ctx->atoms.s.msaa_config);
 394         /* CLEAR_STATE sets 0xffff. */
 395         if (!has_clear_state || ctx->sample_mask != 0xffff)
 396                 si_mark_atom_dirty(ctx, &ctx->atoms.s.sample_mask);
 397         si_mark_atom_dirty(ctx, &ctx->atoms.s.cb_render_state);
 398         /* CLEAR_STATE sets zeros. */
 399         if (!has_clear_state || ctx->blend_color.any_nonzeros)
 400                 si_mark_atom_dirty(ctx, &ctx->atoms.s.blend_color);
 401         si_mark_atom_dirty(ctx, &ctx->atoms.s.db_render_state);
 402         if (ctx->chip_class >= GFX9)
 403                 si_mark_atom_dirty(ctx, &ctx->atoms.s.dpbb_state);
 404         si_mark_atom_dirty(ctx, &ctx->atoms.s.stencil_ref);
 405         si_mark_atom_dirty(ctx, &ctx->atoms.s.spi_map);
 406         if (!ctx->screen->use_ngg_streamout)
 407                 si_mark_atom_dirty(ctx, &ctx->atoms.s.streamout_enable);
 408         si_mark_atom_dirty(ctx, &ctx->atoms.s.render_cond);
 409         /* CLEAR_STATE disables all window rectangles. */
 410         if (!has_clear_state || ctx->num_window_rectangles > 0)
 411                 si_mark_atom_dirty(ctx, &ctx->atoms.s.window_rectangles);
 412
 413         si_mark_atom_dirty(ctx, &ctx->atoms.s.guardband);
 414         si_mark_atom_dirty(ctx, &ctx->atoms.s.scissors);
 415         si_mark_atom_dirty(ctx, &ctx->atoms.s.viewports);
 416
 417         si_mark_atom_dirty(ctx, &ctx->atoms.s.scratch_state);
 418         if (ctx->scratch_buffer) {
 419                 si_context_add_resource_size(ctx, &ctx->scratch_buffer->b.b);
 420         }
 421
 422         if (ctx->streamout.suspended) {
 423                 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
 424                 si_streamout_buffers_dirty(ctx);
 425         }
 426
 427         if (!list_is_empty(&ctx->active_queries))
 428                 si_resume_queries(ctx);
 429
 430         assert(!ctx->gfx_cs->prev_dw);
 431         ctx->initial_gfx_cs_size = ctx->gfx_cs->current.cdw;
 432
 433         /* Invalidate various draw states so that they are emitted before
 434          * the first draw call. */
 435         si_invalidate_draw_sh_constants(ctx);
 436         ctx->last_index_size = -1;
 437         ctx->last_primitive_restart_en = -1;
 438         ctx->last_restart_index = SI_RESTART_INDEX_UNKNOWN;
 439         ctx->last_prim = -1;
 440         ctx->last_multi_vgt_param = -1;
 441         ctx->last_vs_state = ~0;
 442         ctx->last_ls = NULL;
 443         ctx->last_tcs = NULL;
 444         ctx->last_tes_sh_base = -1;
 445         ctx->last_num_tcs_input_cp = -1;
 446         ctx->last_ls_hs_config = -1; /* impossible value */
 447         ctx->last_binning_enabled = -1;
 448
 449         ctx->prim_discard_compute_ib_initialized = false;
 450
 451         /* Compute-based primitive discard:
 452          *   The index ring is divided into 2 halves. Switch between the halves
 453          *   in the same fashion as doublebuffering.
 454          */
 455         if (ctx->index_ring_base)
 456                 ctx->index_ring_base = 0;
 457         else
 458                 ctx->index_ring_base = ctx->index_ring_size_per_ib;
 459
 460         ctx->index_ring_offset = 0;
 461
 462         STATIC_ASSERT(SI_NUM_TRACKED_REGS <= sizeof(ctx->tracked_regs.reg_saved) * 8);
 463
 464         if (has_clear_state) {
 465                 ctx->tracked_regs.reg_value[SI_TRACKED_DB_RENDER_CONTROL] = 0x00000000;
 466                 ctx->tracked_regs.reg_value[SI_TRACKED_DB_COUNT_CONTROL] = 0x00000000;
 467                 ctx->tracked_regs.reg_value[SI_TRACKED_DB_RENDER_OVERRIDE2] = 0x00000000;
 468                 ctx->tracked_regs.reg_value[SI_TRACKED_DB_SHADER_CONTROL] = 0x00000000;
 469                 ctx->tracked_regs.reg_value[SI_TRACKED_CB_TARGET_MASK] = 0xffffffff;
 470                 ctx->tracked_regs.reg_value[SI_TRACKED_CB_DCC_CONTROL] = 0x00000000;
 471                 ctx->tracked_regs.reg_value[SI_TRACKED_SX_PS_DOWNCONVERT] = 0x00000000;
 472                 ctx->tracked_regs.reg_value[SI_TRACKED_SX_BLEND_OPT_EPSILON] = 0x00000000;
 473                 ctx->tracked_regs.reg_value[SI_TRACKED_SX_BLEND_OPT_CONTROL] = 0x00000000;
 474                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_LINE_CNTL] = 0x00001000;
 475                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_AA_CONFIG] = 0x00000000;
 476                 ctx->tracked_regs.reg_value[SI_TRACKED_DB_EQAA] = 0x00000000;
 477                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_MODE_CNTL_1] = 0x00000000;
 478                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_PRIM_FILTER_CNTL] = 0;
 479                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL] = 0x00000000;
 480                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_VS_OUT_CNTL__VS] = 0x00000000;
 481                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_VS_OUT_CNTL__CL] = 0x00000000;
 482                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_CLIP_CNTL] = 0x00090000;
 483                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_BINNER_CNTL_0] = 0x00000003;
 484                 ctx->tracked_regs.reg_value[SI_TRACKED_DB_DFSM_CONTROL] = 0x00000000;
 485                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ]  = 0x3f800000;
 486                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_VERT_DISC_ADJ]  = 0x3f800000;
 487                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_HORZ_CLIP_ADJ]  = 0x3f800000;
 488                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_HORZ_DISC_ADJ]  = 0x3f800000;
 489                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET] = 0;
 490                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_VTX_CNTL] = 0x00000005;
 491                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_CLIPRECT_RULE]     = 0xffff;
 492                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_LINE_STIPPLE]      = 0;
 493                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_ESGS_RING_ITEMSIZE]  = 0x00000000;
 494                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_1]  = 0x00000000;
 495                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_2]  = 0x00000000;
 496                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_3]  = 0x00000000;
 497                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_ITEMSIZE]  = 0x00000000;
 498                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_MAX_VERT_OUT]  = 0x00000000;
 499                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE]  = 0x00000000;
 500                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE_1]  = 0x00000000;
 501                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE_2]  = 0x00000000;
 502                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE_3]  = 0x00000000;
 503                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_INSTANCE_CNT]  = 0x00000000;
 504                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_ONCHIP_CNTL]  = 0x00000000;
 505                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP]  = 0x00000000;
 506                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_MODE]  = 0x00000000;
 507                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_PRIMITIVEID_EN]  = 0x00000000;
 508                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_REUSE_OFF]  = 0x00000000;
 509                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_VS_OUT_CONFIG]  = 0x00000000;
 510                 ctx->tracked_regs.reg_value[SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP]  = 0x00000000;
 511                 ctx->tracked_regs.reg_value[SI_TRACKED_GE_NGG_SUBGRP_CNTL]  = 0x00000000;
 512                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_IDX_FORMAT]  = 0x00000000;
 513                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_POS_FORMAT]  = 0x00000000;
 514                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_VTE_CNTL]  = 0x00000000;
 515                 ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_NGG_CNTL]  = 0x00000000;
 516                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_PS_INPUT_ENA]  = 0x00000000;
 517                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_PS_INPUT_ADDR]  = 0x00000000;
 518                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_BARYC_CNTL]  = 0x00000000;
 519                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_PS_IN_CONTROL]  = 0x00000002;
 520                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_Z_FORMAT]  = 0x00000000;
 521                 ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_COL_FORMAT]  = 0x00000000;
 522                 ctx->tracked_regs.reg_value[SI_TRACKED_CB_SHADER_MASK]  = 0xffffffff;
 523                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_TF_PARAM]  = 0x00000000;
 524                 ctx->tracked_regs.reg_value[SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL]  = 0x0000001e; /* From GFX8 */
 525
 526                 /* Set all cleared context registers to saved. */
 527                 ctx->tracked_regs.reg_saved = 0xffffffffffffffff;
 528                 ctx->last_gs_out_prim = 0; /* cleared by CLEAR_STATE */
 529         } else {
 530                 /* Set all saved registers state to unknown. */
 531                 ctx->tracked_regs.reg_saved = 0;
 532                 ctx->last_gs_out_prim = -1; /* unknown */
 533         }
 534
 535         /* 0xffffffff is a impossible value to register SPI_PS_INPUT_CNTL_n */
 536         memset(ctx->tracked_regs.spi_ps_input_cntl, 0xff, sizeof(uint32_t) * 32);
 537 }