0e1cde2e25e0b5cc65cee734f6aa629fc9df91a6
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "si_pipe.h"
27
28 #include "driver_ddebug/dd_util.h"
29 #include "gallium/winsys/amdgpu/drm/amdgpu_public.h"
30 #include "gallium/winsys/radeon/drm/radeon_drm_public.h"
31 #include "radeon/radeon_uvd.h"
32 #include "si_compute.h"
33 #include "si_public.h"
34 #include "si_shader_internal.h"
35 #include "sid.h"
36 #include "util/disk_cache.h"
37 #include "util/u_log.h"
38 #include "util/u_memory.h"
39 #include "util/u_suballoc.h"
40 #include "util/u_tests.h"
41 #include "util/u_upload_mgr.h"
42 #include "util/xmlconfig.h"
43 #include "vl/vl_decoder.h"
44
45 #include <xf86drm.h>
46
47 static struct pipe_context *si_create_context(struct pipe_screen *screen, unsigned flags);
48
49 static const struct debug_named_value debug_options[] = {
50 /* Shader logging options: */
51 {"vs", DBG(VS), "Print vertex shaders"},
52 {"ps", DBG(PS), "Print pixel shaders"},
53 {"gs", DBG(GS), "Print geometry shaders"},
54 {"tcs", DBG(TCS), "Print tessellation control shaders"},
55 {"tes", DBG(TES), "Print tessellation evaluation shaders"},
56 {"cs", DBG(CS), "Print compute shaders"},
57 {"noir", DBG(NO_IR), "Don't print the LLVM IR"},
58 {"nonir", DBG(NO_NIR), "Don't print NIR when printing shaders"},
59 {"noasm", DBG(NO_ASM), "Don't print disassembled shaders"},
60 {"preoptir", DBG(PREOPT_IR), "Print the LLVM IR before initial optimizations"},
61
62 /* Shader compiler options the shader cache should be aware of: */
63 {"gisel", DBG(GISEL), "Enable LLVM global instruction selector."},
64 {"w32ge", DBG(W32_GE), "Use Wave32 for vertex, tessellation, and geometry shaders."},
65 {"w32ps", DBG(W32_PS), "Use Wave32 for pixel shaders."},
66 {"w32cs", DBG(W32_CS), "Use Wave32 for computes shaders."},
67 {"w64ge", DBG(W64_GE), "Use Wave64 for vertex, tessellation, and geometry shaders."},
68 {"w64ps", DBG(W64_PS), "Use Wave64 for pixel shaders."},
69 {"w64cs", DBG(W64_CS), "Use Wave64 for computes shaders."},
70 {"noinfinterp", DBG(KILL_PS_INF_INTERP), "Kill PS with infinite interp coeff"},
71
72 /* Shader compiler options (with no effect on the shader cache): */
73 {"checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR"},
74 {"mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand"},
75 {"nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants."},
76
77 /* Information logging options: */
78 {"info", DBG(INFO), "Print driver information"},
79 {"tex", DBG(TEX), "Print texture info"},
80 {"compute", DBG(COMPUTE), "Print compute info"},
81 {"vm", DBG(VM), "Print virtual addresses when creating resources"},
82 {"cache_stats", DBG(CACHE_STATS), "Print shader cache statistics."},
83
84 /* Driver options: */
85 {"forcedma", DBG(FORCE_SDMA), "Use SDMA for all operations when possible."},
86 {"nodma", DBG(NO_SDMA), "Disable SDMA"},
87 {"nodmaclear", DBG(NO_SDMA_CLEARS), "Disable SDMA clears"},
88 {"nodmacopyimage", DBG(NO_SDMA_COPY_IMAGE), "Disable SDMA image copies"},
89 {"nowc", DBG(NO_WC), "Disable GTT write combining"},
90 {"check_vm", DBG(CHECK_VM), "Check VM faults and dump debug info."},
91 {"reserve_vmid", DBG(RESERVE_VMID), "Force VMID reservation per context."},
92 {"zerovram", DBG(ZERO_VRAM), "Clear VRAM allocations."},
93 {"shadowregs", DBG(SHADOW_REGS), "Enable CP register shadowing."},
94
95 /* 3D engine options: */
96 {"nogfx", DBG(NO_GFX), "Disable graphics. Only multimedia compute paths can be used."},
97 {"nongg", DBG(NO_NGG), "Disable NGG and use the legacy pipeline."},
98 {"nggc", DBG(ALWAYS_NGG_CULLING_ALL), "Always use NGG culling even when it can hurt."},
99 {"nggctess", DBG(ALWAYS_NGG_CULLING_TESS), "Always use NGG culling for tessellation."},
100 {"nonggc", DBG(NO_NGG_CULLING), "Disable NGG culling."},
101 {"alwayspd", DBG(ALWAYS_PD), "Always enable the primitive discard compute shader."},
102 {"pd", DBG(PD), "Enable the primitive discard compute shader for large draw calls."},
103 {"nopd", DBG(NO_PD), "Disable the primitive discard compute shader."},
104 {"switch_on_eop", DBG(SWITCH_ON_EOP), "Program WD/IA to switch on end-of-packet."},
105 {"nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order rasterization"},
106 {"nodpbb", DBG(NO_DPBB), "Disable DPBB."},
107 {"nodfsm", DBG(NO_DFSM), "Disable DFSM."},
108 {"dpbb", DBG(DPBB), "Enable DPBB."},
109 {"dfsm", DBG(DFSM), "Enable DFSM."},
110 {"nohyperz", DBG(NO_HYPERZ), "Disable Hyper-Z"},
111 {"norbplus", DBG(NO_RB_PLUS), "Disable RB+."},
112 {"no2d", DBG(NO_2D_TILING), "Disable 2D tiling"},
113 {"notiling", DBG(NO_TILING), "Disable tiling"},
114 {"nodcc", DBG(NO_DCC), "Disable DCC."},
115 {"nodccclear", DBG(NO_DCC_CLEAR), "Disable DCC fast clear."},
116 {"nodccfb", DBG(NO_DCC_FB), "Disable separate DCC on the main framebuffer"},
117 {"nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA"},
118 {"nofmask", DBG(NO_FMASK), "Disable MSAA compression"},
119
120 DEBUG_NAMED_VALUE_END /* must be last */
121 };
122
123 static const struct debug_named_value test_options[] = {
124 /* Tests: */
125 {"testdma", DBG(TEST_DMA), "Invoke SDMA tests and exit."},
126 {"testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and exit."},
127 {"testvmfaultsdma", DBG(TEST_VMFAULT_SDMA), "Invoke a SDMA VM fault test and exit."},
128 {"testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM fault test and exit."},
129 {"testdmaperf", DBG(TEST_DMA_PERF), "Test DMA performance"},
130 {"testgds", DBG(TEST_GDS), "Test GDS."},
131 {"testgdsmm", DBG(TEST_GDS_MM), "Test GDS memory management."},
132 {"testgdsoamm", DBG(TEST_GDS_OA_MM), "Test GDS OA memory management."},
133
134 DEBUG_NAMED_VALUE_END /* must be last */
135 };
136
137 void si_init_compiler(struct si_screen *sscreen, struct ac_llvm_compiler *compiler)
138 {
139 /* Only create the less-optimizing version of the compiler on APUs
140 * predating Ryzen (Raven). */
141 bool create_low_opt_compiler =
142 !sscreen->info.has_dedicated_vram && sscreen->info.chip_class <= GFX8;
143
144 enum ac_target_machine_options tm_options =
145 (sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL : 0) |
146 (sscreen->info.chip_class <= GFX8 ? AC_TM_FORCE_DISABLE_XNACK :
147 sscreen->info.chip_class <= GFX10 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
148 (!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0) |
149 (sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0) |
150 (create_low_opt_compiler ? AC_TM_CREATE_LOW_OPT : 0);
151
152 ac_init_llvm_once();
153 ac_init_llvm_compiler(compiler, sscreen->info.family, tm_options);
154 compiler->passes = ac_create_llvm_passes(compiler->tm);
155
156 if (compiler->tm_wave32)
157 compiler->passes_wave32 = ac_create_llvm_passes(compiler->tm_wave32);
158 if (compiler->low_opt_tm)
159 compiler->low_opt_passes = ac_create_llvm_passes(compiler->low_opt_tm);
160 }
161
162 static void si_destroy_compiler(struct ac_llvm_compiler *compiler)
163 {
164 ac_destroy_llvm_compiler(compiler);
165 }
166
167 /*
168 * pipe_context
169 */
170 static void si_destroy_context(struct pipe_context *context)
171 {
172 struct si_context *sctx = (struct si_context *)context;
173 int i;
174
175 /* Unreference the framebuffer normally to disable related logic
176 * properly.
177 */
178 struct pipe_framebuffer_state fb = {};
179 if (context->set_framebuffer_state)
180 context->set_framebuffer_state(context, &fb);
181
182 si_release_all_descriptors(sctx);
183
184 if (sctx->chip_class >= GFX10 && sctx->has_graphics)
185 gfx10_destroy_query(sctx);
186
187 pipe_resource_reference(&sctx->esgs_ring, NULL);
188 pipe_resource_reference(&sctx->gsvs_ring, NULL);
189 pipe_resource_reference(&sctx->tess_rings, NULL);
190 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
191 pipe_resource_reference(&sctx->sample_pos_buffer, NULL);
192 si_resource_reference(&sctx->border_color_buffer, NULL);
193 free(sctx->border_color_table);
194 si_resource_reference(&sctx->scratch_buffer, NULL);
195 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
196 si_resource_reference(&sctx->wait_mem_scratch, NULL);
197 si_resource_reference(&sctx->small_prim_cull_info_buf, NULL);
198
199 if (sctx->cs_preamble_state)
200 si_pm4_free_state(sctx, sctx->cs_preamble_state, ~0);
201 if (sctx->cs_preamble_gs_rings)
202 si_pm4_free_state(sctx, sctx->cs_preamble_gs_rings, ~0);
203 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
204 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
205
206 if (sctx->fixed_func_tcs_shader.cso)
207 sctx->b.delete_tcs_state(&sctx->b, sctx->fixed_func_tcs_shader.cso);
208 if (sctx->custom_dsa_flush)
209 sctx->b.delete_depth_stencil_alpha_state(&sctx->b, sctx->custom_dsa_flush);
210 if (sctx->custom_blend_resolve)
211 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_resolve);
212 if (sctx->custom_blend_fmask_decompress)
213 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_fmask_decompress);
214 if (sctx->custom_blend_eliminate_fastclear)
215 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_eliminate_fastclear);
216 if (sctx->custom_blend_dcc_decompress)
217 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_dcc_decompress);
218 if (sctx->vs_blit_pos)
219 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos);
220 if (sctx->vs_blit_pos_layered)
221 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos_layered);
222 if (sctx->vs_blit_color)
223 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color);
224 if (sctx->vs_blit_color_layered)
225 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color_layered);
226 if (sctx->vs_blit_texcoord)
227 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_texcoord);
228 if (sctx->cs_clear_buffer)
229 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_buffer);
230 if (sctx->cs_copy_buffer)
231 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_buffer);
232 if (sctx->cs_copy_image)
233 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image);
234 if (sctx->cs_copy_image_1d_array)
235 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image_1d_array);
236 if (sctx->cs_clear_render_target)
237 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target);
238 if (sctx->cs_clear_render_target_1d_array)
239 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target_1d_array);
240 if (sctx->cs_clear_12bytes_buffer)
241 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_12bytes_buffer);
242 if (sctx->cs_dcc_decompress)
243 sctx->b.delete_compute_state(&sctx->b, sctx->cs_dcc_decompress);
244 if (sctx->cs_dcc_retile)
245 sctx->b.delete_compute_state(&sctx->b, sctx->cs_dcc_retile);
246
247 for (unsigned i = 0; i < ARRAY_SIZE(sctx->cs_fmask_expand); i++) {
248 for (unsigned j = 0; j < ARRAY_SIZE(sctx->cs_fmask_expand[i]); j++) {
249 if (sctx->cs_fmask_expand[i][j]) {
250 sctx->b.delete_compute_state(&sctx->b, sctx->cs_fmask_expand[i][j]);
251 }
252 }
253 }
254
255 if (sctx->blitter)
256 util_blitter_destroy(sctx->blitter);
257
258 /* Release DCC stats. */
259 for (int i = 0; i < ARRAY_SIZE(sctx->dcc_stats); i++) {
260 assert(!sctx->dcc_stats[i].query_active);
261
262 for (int j = 0; j < ARRAY_SIZE(sctx->dcc_stats[i].ps_stats); j++)
263 if (sctx->dcc_stats[i].ps_stats[j])
264 sctx->b.destroy_query(&sctx->b, sctx->dcc_stats[i].ps_stats[j]);
265
266 si_texture_reference(&sctx->dcc_stats[i].tex, NULL);
267 }
268
269 if (sctx->query_result_shader)
270 sctx->b.delete_compute_state(&sctx->b, sctx->query_result_shader);
271 if (sctx->sh_query_result_shader)
272 sctx->b.delete_compute_state(&sctx->b, sctx->sh_query_result_shader);
273
274 if (sctx->gfx_cs)
275 sctx->ws->cs_destroy(sctx->gfx_cs);
276 if (sctx->sdma_cs)
277 sctx->ws->cs_destroy(sctx->sdma_cs);
278 if (sctx->ctx)
279 sctx->ws->ctx_destroy(sctx->ctx);
280
281 if (sctx->b.stream_uploader)
282 u_upload_destroy(sctx->b.stream_uploader);
283 if (sctx->b.const_uploader)
284 u_upload_destroy(sctx->b.const_uploader);
285 if (sctx->cached_gtt_allocator)
286 u_upload_destroy(sctx->cached_gtt_allocator);
287
288 slab_destroy_child(&sctx->pool_transfers);
289 slab_destroy_child(&sctx->pool_transfers_unsync);
290
291 if (sctx->allocator_zeroed_memory)
292 u_suballocator_destroy(sctx->allocator_zeroed_memory);
293
294 sctx->ws->fence_reference(&sctx->last_gfx_fence, NULL);
295 sctx->ws->fence_reference(&sctx->last_sdma_fence, NULL);
296 sctx->ws->fence_reference(&sctx->last_ib_barrier_fence, NULL);
297 si_resource_reference(&sctx->eop_bug_scratch, NULL);
298 si_resource_reference(&sctx->index_ring, NULL);
299 si_resource_reference(&sctx->barrier_buf, NULL);
300 si_resource_reference(&sctx->last_ib_barrier_buf, NULL);
301 si_resource_reference(&sctx->shadowed_regs, NULL);
302 pb_reference(&sctx->gds, NULL);
303 pb_reference(&sctx->gds_oa, NULL);
304
305 si_destroy_compiler(&sctx->compiler);
306
307 si_saved_cs_reference(&sctx->current_saved_cs, NULL);
308
309 _mesa_hash_table_destroy(sctx->tex_handles, NULL);
310 _mesa_hash_table_destroy(sctx->img_handles, NULL);
311
312 util_dynarray_fini(&sctx->resident_tex_handles);
313 util_dynarray_fini(&sctx->resident_img_handles);
314 util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
315 util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
316 util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
317 si_unref_sdma_uploads(sctx);
318 free(sctx->sdma_uploads);
319 FREE(sctx);
320 }
321
322 static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx)
323 {
324 struct si_context *sctx = (struct si_context *)ctx;
325 struct si_screen *sscreen = sctx->screen;
326 enum pipe_reset_status status = sctx->ws->ctx_query_reset_status(sctx->ctx);
327
328 if (status != PIPE_NO_RESET) {
329 /* Call the gallium frontend to set a no-op API dispatch. */
330 if (sctx->device_reset_callback.reset) {
331 sctx->device_reset_callback.reset(sctx->device_reset_callback.data, status);
332 }
333
334 /* Re-create the auxiliary context, because it won't submit
335 * any new IBs due to a GPU reset.
336 */
337 simple_mtx_lock(&sscreen->aux_context_lock);
338
339 struct u_log_context *aux_log = ((struct si_context *)sscreen->aux_context)->log;
340 sscreen->aux_context->set_log_context(sscreen->aux_context, NULL);
341 sscreen->aux_context->destroy(sscreen->aux_context);
342
343 sscreen->aux_context = si_create_context(
344 &sscreen->b, (sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) |
345 (sscreen->info.has_graphics ? 0 : PIPE_CONTEXT_COMPUTE_ONLY));
346 sscreen->aux_context->set_log_context(sscreen->aux_context, aux_log);
347 simple_mtx_unlock(&sscreen->aux_context_lock);
348 }
349 return status;
350 }
351
352 static void si_set_device_reset_callback(struct pipe_context *ctx,
353 const struct pipe_device_reset_callback *cb)
354 {
355 struct si_context *sctx = (struct si_context *)ctx;
356
357 if (cb)
358 sctx->device_reset_callback = *cb;
359 else
360 memset(&sctx->device_reset_callback, 0, sizeof(sctx->device_reset_callback));
361 }
362
363 /* Apitrace profiling:
364 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
365 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
366 * and remember its number.
367 * 3) In Mesa, enable queries and performance counters around that draw
368 * call and print the results.
369 * 4) glretrace --benchmark --markers ..
370 */
371 static void si_emit_string_marker(struct pipe_context *ctx, const char *string, int len)
372 {
373 struct si_context *sctx = (struct si_context *)ctx;
374
375 dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
376
377 if (sctx->log)
378 u_log_printf(sctx->log, "\nString marker: %*s\n", len, string);
379 }
380
381 static void si_set_debug_callback(struct pipe_context *ctx, const struct pipe_debug_callback *cb)
382 {
383 struct si_context *sctx = (struct si_context *)ctx;
384 struct si_screen *screen = sctx->screen;
385
386 util_queue_finish(&screen->shader_compiler_queue);
387 util_queue_finish(&screen->shader_compiler_queue_low_priority);
388
389 if (cb)
390 sctx->debug = *cb;
391 else
392 memset(&sctx->debug, 0, sizeof(sctx->debug));
393 }
394
395 static void si_set_log_context(struct pipe_context *ctx, struct u_log_context *log)
396 {
397 struct si_context *sctx = (struct si_context *)ctx;
398 sctx->log = log;
399
400 if (log)
401 u_log_add_auto_logger(log, si_auto_log_cs, sctx);
402 }
403
404 static void si_set_context_param(struct pipe_context *ctx, enum pipe_context_param param,
405 unsigned value)
406 {
407 struct radeon_winsys *ws = ((struct si_context *)ctx)->ws;
408
409 switch (param) {
410 case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE:
411 ws->pin_threads_to_L3_cache(ws, value);
412 break;
413 default:;
414 }
415 }
416
417 static struct pipe_context *si_create_context(struct pipe_screen *screen, unsigned flags)
418 {
419 struct si_screen *sscreen = (struct si_screen *)screen;
420 STATIC_ASSERT(DBG_COUNT <= 64);
421
422 /* Don't create a context if it's not compute-only and hw is compute-only. */
423 if (!sscreen->info.has_graphics && !(flags & PIPE_CONTEXT_COMPUTE_ONLY))
424 return NULL;
425
426 struct si_context *sctx = CALLOC_STRUCT(si_context);
427 struct radeon_winsys *ws = sscreen->ws;
428 int shader, i;
429 bool stop_exec_on_failure = (flags & PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET) != 0;
430
431 if (!sctx)
432 return NULL;
433
434 sctx->has_graphics = sscreen->info.chip_class == GFX6 || !(flags & PIPE_CONTEXT_COMPUTE_ONLY);
435
436 if (flags & PIPE_CONTEXT_DEBUG)
437 sscreen->record_llvm_ir = true; /* racy but not critical */
438
439 sctx->b.screen = screen; /* this must be set first */
440 sctx->b.priv = NULL;
441 sctx->b.destroy = si_destroy_context;
442 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
443 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
444
445 slab_create_child(&sctx->pool_transfers, &sscreen->pool_transfers);
446 slab_create_child(&sctx->pool_transfers_unsync, &sscreen->pool_transfers);
447
448 sctx->ws = sscreen->ws;
449 sctx->family = sscreen->info.family;
450 sctx->chip_class = sscreen->info.chip_class;
451
452 if (sctx->chip_class == GFX7 || sctx->chip_class == GFX8 || sctx->chip_class == GFX9) {
453 sctx->eop_bug_scratch = si_resource(pipe_buffer_create(
454 &sscreen->b, 0, PIPE_USAGE_DEFAULT, 16 * sscreen->info.num_render_backends));
455 if (!sctx->eop_bug_scratch)
456 goto fail;
457 }
458
459 /* Initialize context allocators. */
460 sctx->allocator_zeroed_memory =
461 u_suballocator_create(&sctx->b, 128 * 1024, 0, PIPE_USAGE_DEFAULT,
462 SI_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_CLEAR, false);
463 if (!sctx->allocator_zeroed_memory)
464 goto fail;
465
466 sctx->b.stream_uploader =
467 u_upload_create(&sctx->b, 1024 * 1024, 0, PIPE_USAGE_STREAM, SI_RESOURCE_FLAG_READ_ONLY);
468 if (!sctx->b.stream_uploader)
469 goto fail;
470
471 sctx->cached_gtt_allocator = u_upload_create(&sctx->b, 16 * 1024, 0, PIPE_USAGE_STAGING, 0);
472 if (!sctx->cached_gtt_allocator)
473 goto fail;
474
475 sctx->ctx = sctx->ws->ctx_create(sctx->ws);
476 if (!sctx->ctx)
477 goto fail;
478
479 if (sscreen->info.num_rings[RING_DMA] && !(sscreen->debug_flags & DBG(NO_SDMA)) &&
480 /* SDMA causes corruption on RX 580:
481 * https://gitlab.freedesktop.org/mesa/mesa/-/issues/1399
482 * https://gitlab.freedesktop.org/mesa/mesa/-/issues/1889
483 */
484 (sctx->chip_class != GFX8 || sscreen->debug_flags & DBG(FORCE_SDMA)) &&
485 /* SDMA timeouts sometimes on gfx10 so disable it for now. See:
486 * https://bugs.freedesktop.org/show_bug.cgi?id=111481
487 * https://gitlab.freedesktop.org/mesa/mesa/-/issues/1907
488 */
489 (sctx->chip_class != GFX10 || sscreen->debug_flags & DBG(FORCE_SDMA))) {
490 sctx->sdma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA, (void *)si_flush_dma_cs, sctx,
491 stop_exec_on_failure);
492 }
493
494 bool use_sdma_upload = sscreen->info.has_dedicated_vram && sctx->sdma_cs;
495 sctx->b.const_uploader =
496 u_upload_create(&sctx->b, 256 * 1024, 0, PIPE_USAGE_DEFAULT,
497 SI_RESOURCE_FLAG_32BIT |
498 (use_sdma_upload ? SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA : 0));
499 if (!sctx->b.const_uploader)
500 goto fail;
501
502 if (use_sdma_upload)
503 u_upload_enable_flush_explicit(sctx->b.const_uploader);
504
505 sctx->gfx_cs = ws->cs_create(sctx->ctx, sctx->has_graphics ? RING_GFX : RING_COMPUTE,
506 (void *)si_flush_gfx_cs, sctx, stop_exec_on_failure);
507
508 /* Border colors. */
509 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS * sizeof(*sctx->border_color_table));
510 if (!sctx->border_color_table)
511 goto fail;
512
513 sctx->border_color_buffer = si_resource(pipe_buffer_create(
514 screen, 0, PIPE_USAGE_DEFAULT, SI_MAX_BORDER_COLORS * sizeof(*sctx->border_color_table)));
515 if (!sctx->border_color_buffer)
516 goto fail;
517
518 sctx->border_color_map =
519 ws->buffer_map(sctx->border_color_buffer->buf, NULL, PIPE_TRANSFER_WRITE);
520 if (!sctx->border_color_map)
521 goto fail;
522
523 sctx->ngg = sscreen->use_ngg;
524
525 /* Initialize context functions used by graphics and compute. */
526 if (sctx->chip_class >= GFX10)
527 sctx->emit_cache_flush = gfx10_emit_cache_flush;
528 else
529 sctx->emit_cache_flush = si_emit_cache_flush;
530
531 sctx->b.emit_string_marker = si_emit_string_marker;
532 sctx->b.set_debug_callback = si_set_debug_callback;
533 sctx->b.set_log_context = si_set_log_context;
534 sctx->b.set_context_param = si_set_context_param;
535 sctx->b.get_device_reset_status = si_get_reset_status;
536 sctx->b.set_device_reset_callback = si_set_device_reset_callback;
537
538 si_init_all_descriptors(sctx);
539 si_init_buffer_functions(sctx);
540 si_init_clear_functions(sctx);
541 si_init_blit_functions(sctx);
542 si_init_compute_functions(sctx);
543 si_init_compute_blit_functions(sctx);
544 si_init_debug_functions(sctx);
545 si_init_fence_functions(sctx);
546 si_init_query_functions(sctx);
547 si_init_state_compute_functions(sctx);
548 si_init_context_texture_functions(sctx);
549
550 /* Initialize graphics-only context functions. */
551 if (sctx->has_graphics) {
552 if (sctx->chip_class >= GFX10)
553 gfx10_init_query(sctx);
554 si_init_msaa_functions(sctx);
555 si_init_shader_functions(sctx);
556 si_init_state_functions(sctx);
557 si_init_streamout_functions(sctx);
558 si_init_viewport_functions(sctx);
559
560 sctx->blitter = util_blitter_create(&sctx->b);
561 if (sctx->blitter == NULL)
562 goto fail;
563 sctx->blitter->skip_viewport_restore = true;
564
565 /* Some states are expected to be always non-NULL. */
566 sctx->noop_blend = util_blitter_get_noop_blend_state(sctx->blitter);
567 sctx->queued.named.blend = sctx->noop_blend;
568
569 sctx->noop_dsa = util_blitter_get_noop_dsa_state(sctx->blitter);
570 sctx->queued.named.dsa = sctx->noop_dsa;
571
572 sctx->discard_rasterizer_state = util_blitter_get_discard_rasterizer_state(sctx->blitter);
573 sctx->queued.named.rasterizer = sctx->discard_rasterizer_state;
574
575 si_init_draw_functions(sctx);
576
577 /* If aux_context == NULL, we are initializing aux_context right now. */
578 bool is_aux_context = !sscreen->aux_context;
579 si_initialize_prim_discard_tunables(sscreen, is_aux_context,
580 &sctx->prim_discard_vertex_count_threshold,
581 &sctx->index_ring_size_per_ib);
582 }
583
584 /* Initialize SDMA functions. */
585 if (sctx->chip_class >= GFX7)
586 cik_init_sdma_functions(sctx);
587 else
588 sctx->dma_copy = si_resource_copy_region;
589
590 if (sscreen->debug_flags & DBG(FORCE_SDMA))
591 sctx->b.resource_copy_region = sctx->dma_copy;
592
593 sctx->sample_mask = 0xffff;
594
595 /* Initialize multimedia functions. */
596 if (sscreen->info.has_hw_decode) {
597 sctx->b.create_video_codec = si_uvd_create_decoder;
598 sctx->b.create_video_buffer = si_video_buffer_create;
599 } else {
600 sctx->b.create_video_codec = vl_create_decoder;
601 sctx->b.create_video_buffer = vl_video_buffer_create;
602 }
603
604 if (sctx->chip_class >= GFX9 || si_compute_prim_discard_enabled(sctx)) {
605 sctx->wait_mem_scratch =
606 si_aligned_buffer_create(screen, SI_RESOURCE_FLAG_UNMAPPABLE,
607 PIPE_USAGE_DEFAULT, 8,
608 sscreen->info.tcc_cache_line_size);
609 if (!sctx->wait_mem_scratch)
610 goto fail;
611 }
612
613 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
614 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
615 if (sctx->chip_class == GFX7) {
616 sctx->null_const_buf.buffer =
617 pipe_aligned_buffer_create(screen, SI_RESOURCE_FLAG_32BIT, PIPE_USAGE_DEFAULT, 16,
618 sctx->screen->info.tcc_cache_line_size);
619 if (!sctx->null_const_buf.buffer)
620 goto fail;
621 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
622
623 unsigned start_shader = sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE;
624 for (shader = start_shader; shader < SI_NUM_SHADERS; shader++) {
625 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
626 sctx->b.set_constant_buffer(&sctx->b, shader, i, &sctx->null_const_buf);
627 }
628 }
629
630 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &sctx->null_const_buf);
631 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &sctx->null_const_buf);
632 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &sctx->null_const_buf);
633 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE, &sctx->null_const_buf);
634 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &sctx->null_const_buf);
635 }
636
637 uint64_t max_threads_per_block;
638 screen->get_compute_param(screen, PIPE_SHADER_IR_NIR, PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
639 &max_threads_per_block);
640
641 /* The maximum number of scratch waves. Scratch space isn't divided
642 * evenly between CUs. The number is only a function of the number of CUs.
643 * We can decrease the constant to decrease the scratch buffer size.
644 *
645 * sctx->scratch_waves must be >= the maximum posible size of
646 * 1 threadgroup, so that the hw doesn't hang from being unable
647 * to start any.
648 *
649 * The recommended value is 4 per CU at most. Higher numbers don't
650 * bring much benefit, but they still occupy chip resources (think
651 * async compute). I've seen ~2% performance difference between 4 and 32.
652 */
653 sctx->scratch_waves =
654 MAX2(32 * sscreen->info.num_good_compute_units, max_threads_per_block / 64);
655
656 /* Bindless handles. */
657 sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer, _mesa_key_pointer_equal);
658 sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer, _mesa_key_pointer_equal);
659
660 util_dynarray_init(&sctx->resident_tex_handles, NULL);
661 util_dynarray_init(&sctx->resident_img_handles, NULL);
662 util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
663 util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
664 util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
665
666 sctx->sample_pos_buffer =
667 pipe_buffer_create(sctx->b.screen, 0, PIPE_USAGE_DEFAULT, sizeof(sctx->sample_positions));
668 pipe_buffer_write(&sctx->b, sctx->sample_pos_buffer, 0, sizeof(sctx->sample_positions),
669 &sctx->sample_positions);
670
671 /* The remainder of this function initializes the gfx CS and must be last. */
672 assert(sctx->gfx_cs->current.cdw == 0);
673
674 if (sctx->has_graphics) {
675 si_init_cp_reg_shadowing(sctx);
676 }
677
678 si_begin_new_gfx_cs(sctx);
679 assert(sctx->gfx_cs->current.cdw == sctx->initial_gfx_cs_size);
680
681 /* Initialize per-context buffers. */
682 if (sctx->wait_mem_scratch) {
683 si_cp_write_data(sctx, sctx->wait_mem_scratch, 0, 4, V_370_MEM, V_370_ME,
684 &sctx->wait_mem_number);
685 }
686
687 if (sctx->chip_class == GFX7) {
688 /* Clear the NULL constant buffer, because loads should return zeros.
689 * Note that this forces CP DMA to be used, because clover deadlocks
690 * for some reason when the compute codepath is used.
691 */
692 uint32_t clear_value = 0;
693 si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0, sctx->null_const_buf.buffer->width0,
694 &clear_value, 4, SI_COHERENCY_SHADER, true);
695 }
696
697 sctx->initial_gfx_cs_size = sctx->gfx_cs->current.cdw;
698 return &sctx->b;
699 fail:
700 fprintf(stderr, "radeonsi: Failed to create a context.\n");
701 si_destroy_context(&sctx->b);
702 return NULL;
703 }
704
705 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen, void *priv,
706 unsigned flags)
707 {
708 struct si_screen *sscreen = (struct si_screen *)screen;
709 struct pipe_context *ctx;
710 uint64_t total_ram;
711
712 if (sscreen->debug_flags & DBG(CHECK_VM))
713 flags |= PIPE_CONTEXT_DEBUG;
714
715 ctx = si_create_context(screen, flags);
716
717 if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
718 return ctx;
719
720 /* Clover (compute-only) is unsupported. */
721 if (flags & PIPE_CONTEXT_COMPUTE_ONLY)
722 return ctx;
723
724 /* When shaders are logged to stderr, asynchronous compilation is
725 * disabled too. */
726 if (sscreen->debug_flags & DBG_ALL_SHADERS)
727 return ctx;
728
729 /* Use asynchronous flushes only on amdgpu, since the radeon
730 * implementation for fence_server_sync is incomplete. */
731 struct pipe_context * tc = threaded_context_create(
732 ctx, &sscreen->pool_transfers, si_replace_buffer_storage,
733 sscreen->info.is_amdgpu ? si_create_fence : NULL,
734 &((struct si_context *)ctx)->tc);
735
736 if (tc && tc != ctx && os_get_total_physical_memory(&total_ram)) {
737 ((struct threaded_context *) tc)->bytes_mapped_limit = total_ram / 4;
738 }
739
740 return tc;
741 }
742
743 /*
744 * pipe_screen
745 */
746 static void si_destroy_screen(struct pipe_screen *pscreen)
747 {
748 struct si_screen *sscreen = (struct si_screen *)pscreen;
749 struct si_shader_part *parts[] = {sscreen->vs_prologs, sscreen->tcs_epilogs, sscreen->gs_prologs,
750 sscreen->ps_prologs, sscreen->ps_epilogs};
751 unsigned i;
752
753 if (!sscreen->ws->unref(sscreen->ws))
754 return;
755
756 if (sscreen->debug_flags & DBG(CACHE_STATS)) {
757 printf("live shader cache: hits = %u, misses = %u\n", sscreen->live_shader_cache.hits,
758 sscreen->live_shader_cache.misses);
759 printf("memory shader cache: hits = %u, misses = %u\n", sscreen->num_memory_shader_cache_hits,
760 sscreen->num_memory_shader_cache_misses);
761 printf("disk shader cache: hits = %u, misses = %u\n", sscreen->num_disk_shader_cache_hits,
762 sscreen->num_disk_shader_cache_misses);
763 }
764
765 simple_mtx_destroy(&sscreen->aux_context_lock);
766
767 struct u_log_context *aux_log = ((struct si_context *)sscreen->aux_context)->log;
768 if (aux_log) {
769 sscreen->aux_context->set_log_context(sscreen->aux_context, NULL);
770 u_log_context_destroy(aux_log);
771 FREE(aux_log);
772 }
773
774 sscreen->aux_context->destroy(sscreen->aux_context);
775
776 util_queue_destroy(&sscreen->shader_compiler_queue);
777 util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
778
779 /* Release the reference on glsl types of the compiler threads. */
780 glsl_type_singleton_decref();
781
782 for (i = 0; i < ARRAY_SIZE(sscreen->compiler); i++)
783 si_destroy_compiler(&sscreen->compiler[i]);
784
785 for (i = 0; i < ARRAY_SIZE(sscreen->compiler_lowp); i++)
786 si_destroy_compiler(&sscreen->compiler_lowp[i]);
787
788 /* Free shader parts. */
789 for (i = 0; i < ARRAY_SIZE(parts); i++) {
790 while (parts[i]) {
791 struct si_shader_part *part = parts[i];
792
793 parts[i] = part->next;
794 si_shader_binary_clean(&part->binary);
795 FREE(part);
796 }
797 }
798 simple_mtx_destroy(&sscreen->shader_parts_mutex);
799 si_destroy_shader_cache(sscreen);
800
801 si_destroy_perfcounters(sscreen);
802 si_gpu_load_kill_thread(sscreen);
803
804 simple_mtx_destroy(&sscreen->gpu_load_mutex);
805
806 slab_destroy_parent(&sscreen->pool_transfers);
807
808 disk_cache_destroy(sscreen->disk_shader_cache);
809 util_live_shader_cache_deinit(&sscreen->live_shader_cache);
810 sscreen->ws->destroy(sscreen->ws);
811 FREE(sscreen);
812 }
813
814 static void si_init_gs_info(struct si_screen *sscreen)
815 {
816 sscreen->gs_table_depth = ac_get_gs_table_depth(sscreen->info.chip_class, sscreen->info.family);
817 }
818
819 static void si_test_vmfault(struct si_screen *sscreen, uint64_t test_flags)
820 {
821 struct pipe_context *ctx = sscreen->aux_context;
822 struct si_context *sctx = (struct si_context *)ctx;
823 struct pipe_resource *buf = pipe_buffer_create_const0(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 64);
824
825 if (!buf) {
826 puts("Buffer allocation failed.");
827 exit(1);
828 }
829
830 si_resource(buf)->gpu_address = 0; /* cause a VM fault */
831
832 if (test_flags & DBG(TEST_VMFAULT_CP)) {
833 si_cp_dma_copy_buffer(sctx, buf, buf, 0, 4, 4, 0, SI_COHERENCY_NONE, L2_BYPASS);
834 ctx->flush(ctx, NULL, 0);
835 puts("VM fault test: CP - done.");
836 }
837 if (test_flags & DBG(TEST_VMFAULT_SDMA)) {
838 si_sdma_clear_buffer(sctx, buf, 0, 4, 0);
839 ctx->flush(ctx, NULL, 0);
840 puts("VM fault test: SDMA - done.");
841 }
842 if (test_flags & DBG(TEST_VMFAULT_SHADER)) {
843 util_test_constant_buffer(ctx, buf);
844 puts("VM fault test: Shader - done.");
845 }
846 exit(0);
847 }
848
849 static void si_test_gds_memory_management(struct si_context *sctx, unsigned alloc_size,
850 unsigned alignment, enum radeon_bo_domain domain)
851 {
852 struct radeon_winsys *ws = sctx->ws;
853 struct radeon_cmdbuf *cs[8];
854 struct pb_buffer *gds_bo[ARRAY_SIZE(cs)];
855
856 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
857 cs[i] = ws->cs_create(sctx->ctx, RING_COMPUTE, NULL, NULL, false);
858 gds_bo[i] = ws->buffer_create(ws, alloc_size, alignment, domain, 0);
859 assert(gds_bo[i]);
860 }
861
862 for (unsigned iterations = 0; iterations < 20000; iterations++) {
863 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
864 /* This clears GDS with CP DMA.
865 *
866 * We don't care if GDS is present. Just add some packet
867 * to make the GPU busy for a moment.
868 */
869 si_cp_dma_clear_buffer(
870 sctx, cs[i], NULL, 0, alloc_size, 0,
871 SI_CPDMA_SKIP_BO_LIST_UPDATE | SI_CPDMA_SKIP_CHECK_CS_SPACE | SI_CPDMA_SKIP_GFX_SYNC, 0,
872 0);
873
874 ws->cs_add_buffer(cs[i], gds_bo[i], RADEON_USAGE_READWRITE, domain, 0);
875 ws->cs_flush(cs[i], PIPE_FLUSH_ASYNC, NULL);
876 }
877 }
878 exit(0);
879 }
880
881 static void si_disk_cache_create(struct si_screen *sscreen)
882 {
883 /* Don't use the cache if shader dumping is enabled. */
884 if (sscreen->debug_flags & DBG_ALL_SHADERS)
885 return;
886
887 struct mesa_sha1 ctx;
888 unsigned char sha1[20];
889 char cache_id[20 * 2 + 1];
890
891 _mesa_sha1_init(&ctx);
892
893 if (!disk_cache_get_function_identifier(si_disk_cache_create, &ctx) ||
894 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
895 return;
896
897 _mesa_sha1_final(&ctx, sha1);
898 disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
899
900 /* These flags affect shader compilation. */
901 #define ALL_FLAGS (DBG(GISEL) | DBG(KILL_PS_INF_INTERP))
902 uint64_t shader_debug_flags = sscreen->debug_flags & ALL_FLAGS;
903
904 /* Add the high bits of 32-bit addresses, which affects
905 * how 32-bit addresses are expanded to 64 bits.
906 */
907 STATIC_ASSERT(ALL_FLAGS <= UINT_MAX);
908 assert((int16_t)sscreen->info.address32_hi == (int32_t)sscreen->info.address32_hi);
909 shader_debug_flags |= (uint64_t)(sscreen->info.address32_hi & 0xffff) << 32;
910
911 sscreen->disk_shader_cache = disk_cache_create(sscreen->info.name, cache_id, shader_debug_flags);
912 }
913
914 static void si_set_max_shader_compiler_threads(struct pipe_screen *screen, unsigned max_threads)
915 {
916 struct si_screen *sscreen = (struct si_screen *)screen;
917
918 /* This function doesn't allow a greater number of threads than
919 * the queue had at its creation. */
920 util_queue_adjust_num_threads(&sscreen->shader_compiler_queue, max_threads);
921 /* Don't change the number of threads on the low priority queue. */
922 }
923
924 static bool si_is_parallel_shader_compilation_finished(struct pipe_screen *screen, void *shader,
925 enum pipe_shader_type shader_type)
926 {
927 struct si_shader_selector *sel = (struct si_shader_selector *)shader;
928
929 return util_queue_fence_is_signalled(&sel->ready);
930 }
931
932 static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws,
933 const struct pipe_screen_config *config)
934 {
935 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
936 unsigned hw_threads, num_comp_hi_threads, num_comp_lo_threads;
937 uint64_t test_flags;
938
939 if (!sscreen) {
940 return NULL;
941 }
942
943 sscreen->ws = ws;
944 ws->query_info(ws, &sscreen->info);
945
946 if (sscreen->info.chip_class == GFX10_3 && LLVM_VERSION_MAJOR < 11) {
947 fprintf(stderr, "radeonsi: GFX 10.3 requires LLVM 11 or higher\n");
948 FREE(sscreen);
949 return NULL;
950 }
951
952 if (sscreen->info.chip_class == GFX10 && LLVM_VERSION_MAJOR < 9) {
953 fprintf(stderr, "radeonsi: Navi family support requires LLVM 9 or higher\n");
954 FREE(sscreen);
955 return NULL;
956 }
957
958 if (sscreen->info.chip_class >= GFX9) {
959 sscreen->se_tile_repeat = 32 * sscreen->info.max_se;
960 } else {
961 ac_get_raster_config(&sscreen->info, &sscreen->pa_sc_raster_config,
962 &sscreen->pa_sc_raster_config_1, &sscreen->se_tile_repeat);
963 }
964
965 sscreen->debug_flags = debug_get_flags_option("R600_DEBUG", debug_options, 0);
966 sscreen->debug_flags |= debug_get_flags_option("AMD_DEBUG", debug_options, 0);
967 test_flags = debug_get_flags_option("AMD_TEST", test_options, 0);
968
969 if (sscreen->debug_flags & DBG(NO_GFX))
970 sscreen->info.has_graphics = false;
971
972 /* Set functions first. */
973 sscreen->b.context_create = si_pipe_create_context;
974 sscreen->b.destroy = si_destroy_screen;
975 sscreen->b.set_max_shader_compiler_threads = si_set_max_shader_compiler_threads;
976 sscreen->b.is_parallel_shader_compilation_finished = si_is_parallel_shader_compilation_finished;
977 sscreen->b.finalize_nir = si_finalize_nir;
978
979 si_init_screen_get_functions(sscreen);
980 si_init_screen_buffer_functions(sscreen);
981 si_init_screen_fence_functions(sscreen);
982 si_init_screen_state_functions(sscreen);
983 si_init_screen_texture_functions(sscreen);
984 si_init_screen_query_functions(sscreen);
985 si_init_screen_live_shader_cache(sscreen);
986
987 /* Set these flags in debug_flags early, so that the shader cache takes
988 * them into account.
989 */
990 if (driQueryOptionb(config->options, "glsl_correct_derivatives_after_discard"))
991 sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
992
993 if (sscreen->debug_flags & DBG(INFO))
994 ac_print_gpu_info(&sscreen->info);
995
996 slab_create_parent(&sscreen->pool_transfers, sizeof(struct si_transfer), 64);
997
998 sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
999 if (sscreen->force_aniso == -1) {
1000 sscreen->force_aniso = MIN2(16, debug_get_num_option("AMD_TEX_ANISO", -1));
1001 }
1002
1003 if (sscreen->force_aniso >= 0) {
1004 printf("radeonsi: Forcing anisotropy filter to %ix\n",
1005 /* round down to a power of two */
1006 1 << util_logbase2(sscreen->force_aniso));
1007 }
1008
1009 (void)simple_mtx_init(&sscreen->aux_context_lock, mtx_plain);
1010 (void)simple_mtx_init(&sscreen->gpu_load_mutex, mtx_plain);
1011
1012 si_init_gs_info(sscreen);
1013 if (!si_init_shader_cache(sscreen)) {
1014 FREE(sscreen);
1015 return NULL;
1016 }
1017
1018 {
1019 #define OPT_BOOL(name, dflt, description) \
1020 sscreen->options.name = driQueryOptionb(config->options, "radeonsi_" #name);
1021 #include "si_debug_options.h"
1022 }
1023
1024 if (sscreen->options.no_infinite_interp) {
1025 sscreen->debug_flags |= DBG(KILL_PS_INF_INTERP);
1026 }
1027
1028 si_disk_cache_create(sscreen);
1029
1030 /* Determine the number of shader compiler threads. */
1031 hw_threads = sysconf(_SC_NPROCESSORS_ONLN);
1032
1033 if (hw_threads >= 12) {
1034 num_comp_hi_threads = hw_threads * 3 / 4;
1035 num_comp_lo_threads = hw_threads / 3;
1036 } else if (hw_threads >= 6) {
1037 num_comp_hi_threads = hw_threads - 2;
1038 num_comp_lo_threads = hw_threads / 2;
1039 } else if (hw_threads >= 2) {
1040 num_comp_hi_threads = hw_threads - 1;
1041 num_comp_lo_threads = hw_threads / 2;
1042 } else {
1043 num_comp_hi_threads = 1;
1044 num_comp_lo_threads = 1;
1045 }
1046
1047 num_comp_hi_threads = MIN2(num_comp_hi_threads, ARRAY_SIZE(sscreen->compiler));
1048 num_comp_lo_threads = MIN2(num_comp_lo_threads, ARRAY_SIZE(sscreen->compiler_lowp));
1049
1050 /* Take a reference on the glsl types for the compiler threads. */
1051 glsl_type_singleton_init_or_ref();
1052
1053 if (!util_queue_init(
1054 &sscreen->shader_compiler_queue, "sh", 64, num_comp_hi_threads,
1055 UTIL_QUEUE_INIT_RESIZE_IF_FULL | UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY)) {
1056 si_destroy_shader_cache(sscreen);
1057 FREE(sscreen);
1058 glsl_type_singleton_decref();
1059 return NULL;
1060 }
1061
1062 if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority, "shlo", 64,
1063 num_comp_lo_threads,
1064 UTIL_QUEUE_INIT_RESIZE_IF_FULL | UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY |
1065 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
1066 si_destroy_shader_cache(sscreen);
1067 FREE(sscreen);
1068 glsl_type_singleton_decref();
1069 return NULL;
1070 }
1071
1072 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1073 si_init_perfcounters(sscreen);
1074
1075 unsigned prim_discard_vertex_count_threshold, tmp;
1076 si_initialize_prim_discard_tunables(sscreen, false, &prim_discard_vertex_count_threshold, &tmp);
1077 /* Compute-shader-based culling doesn't support VBOs in user SGPRs. */
1078 if (prim_discard_vertex_count_threshold == UINT_MAX)
1079 sscreen->num_vbos_in_user_sgprs = sscreen->info.chip_class >= GFX9 ? 5 : 1;
1080
1081 /* Determine tessellation ring info. */
1082 bool double_offchip_buffers = sscreen->info.chip_class >= GFX7 &&
1083 sscreen->info.family != CHIP_CARRIZO &&
1084 sscreen->info.family != CHIP_STONEY;
1085 /* This must be one less than the maximum number due to a hw limitation.
1086 * Various hardware bugs need this.
1087 */
1088 unsigned max_offchip_buffers_per_se;
1089
1090 if (sscreen->info.chip_class >= GFX10)
1091 max_offchip_buffers_per_se = 128;
1092 /* Only certain chips can use the maximum value. */
1093 else if (sscreen->info.family == CHIP_VEGA12 || sscreen->info.family == CHIP_VEGA20)
1094 max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1095 else
1096 max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
1097
1098 unsigned max_offchip_buffers = max_offchip_buffers_per_se * sscreen->info.max_se;
1099 unsigned offchip_granularity;
1100
1101 /* Hawaii has a bug with offchip buffers > 256 that can be worked
1102 * around by setting 4K granularity.
1103 */
1104 if (sscreen->info.family == CHIP_HAWAII) {
1105 sscreen->tess_offchip_block_dw_size = 4096;
1106 offchip_granularity = V_03093C_X_4K_DWORDS;
1107 } else {
1108 sscreen->tess_offchip_block_dw_size = 8192;
1109 offchip_granularity = V_03093C_X_8K_DWORDS;
1110 }
1111
1112 sscreen->tess_factor_ring_size = 32768 * sscreen->info.max_se;
1113 sscreen->tess_offchip_ring_size = max_offchip_buffers * sscreen->tess_offchip_block_dw_size * 4;
1114
1115 if (sscreen->info.chip_class >= GFX10_3) {
1116 sscreen->vgt_hs_offchip_param =
1117 S_03093C_OFFCHIP_BUFFERING_GFX103(max_offchip_buffers - 1) |
1118 S_03093C_OFFCHIP_GRANULARITY_GFX103(offchip_granularity);
1119 } else if (sscreen->info.chip_class >= GFX7) {
1120 if (sscreen->info.chip_class >= GFX8)
1121 --max_offchip_buffers;
1122 sscreen->vgt_hs_offchip_param = S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1123 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1124 } else {
1125 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
1126 sscreen->vgt_hs_offchip_param = S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1127 }
1128
1129 sscreen->has_draw_indirect_multi =
1130 (sscreen->info.family >= CHIP_POLARIS10) ||
1131 (sscreen->info.chip_class == GFX8 && sscreen->info.pfp_fw_version >= 121 &&
1132 sscreen->info.me_fw_version >= 87) ||
1133 (sscreen->info.chip_class == GFX7 && sscreen->info.pfp_fw_version >= 211 &&
1134 sscreen->info.me_fw_version >= 173) ||
1135 (sscreen->info.chip_class == GFX6 && sscreen->info.pfp_fw_version >= 79 &&
1136 sscreen->info.me_fw_version >= 142);
1137
1138 sscreen->has_out_of_order_rast =
1139 sscreen->info.has_out_of_order_rast && !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER));
1140 sscreen->assume_no_z_fights = driQueryOptionb(config->options, "radeonsi_assume_no_z_fights") ||
1141 driQueryOptionb(config->options, "allow_draw_out_of_order");
1142 sscreen->commutative_blend_add =
1143 driQueryOptionb(config->options, "radeonsi_commutative_blend_add") ||
1144 driQueryOptionb(config->options, "allow_draw_out_of_order");
1145
1146 sscreen->use_ngg = sscreen->info.chip_class >= GFX10 && sscreen->info.family != CHIP_NAVI14 &&
1147 !(sscreen->debug_flags & DBG(NO_NGG));
1148 sscreen->use_ngg_culling = sscreen->use_ngg && !(sscreen->debug_flags & DBG(NO_NGG_CULLING));
1149 sscreen->always_use_ngg_culling_all =
1150 sscreen->use_ngg_culling && sscreen->debug_flags & DBG(ALWAYS_NGG_CULLING_ALL);
1151 sscreen->always_use_ngg_culling_tess =
1152 sscreen->use_ngg_culling && sscreen->debug_flags & DBG(ALWAYS_NGG_CULLING_TESS);
1153 sscreen->use_ngg_streamout = false;
1154
1155 /* Only enable primitive binning on APUs by default. */
1156 if (sscreen->info.chip_class >= GFX10) {
1157 sscreen->dpbb_allowed = true;
1158 /* DFSM is not supported on GFX 10.3 and not beneficial on Navi1x. */
1159 } else if (sscreen->info.chip_class == GFX9) {
1160 sscreen->dpbb_allowed = !sscreen->info.has_dedicated_vram;
1161 sscreen->dfsm_allowed = !sscreen->info.has_dedicated_vram;
1162 }
1163
1164 /* Process DPBB enable flags. */
1165 if (sscreen->debug_flags & DBG(DPBB)) {
1166 sscreen->dpbb_allowed = true;
1167 if (sscreen->debug_flags & DBG(DFSM))
1168 sscreen->dfsm_allowed = true;
1169 }
1170
1171 /* Process DPBB disable flags. */
1172 if (sscreen->debug_flags & DBG(NO_DPBB)) {
1173 sscreen->dpbb_allowed = false;
1174 sscreen->dfsm_allowed = false;
1175 } else if (sscreen->debug_flags & DBG(NO_DFSM)) {
1176 sscreen->dfsm_allowed = false;
1177 }
1178
1179 /* While it would be nice not to have this flag, we are constrained
1180 * by the reality that LLVM 9.0 has buggy VGPR indexing on GFX9.
1181 */
1182 sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class != GFX9;
1183
1184 sscreen->dcc_msaa_allowed = !(sscreen->debug_flags & DBG(NO_DCC_MSAA));
1185
1186 (void)simple_mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1187 sscreen->use_monolithic_shaders = (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
1188
1189 sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SCACHE | SI_CONTEXT_INV_VCACHE;
1190 if (sscreen->info.chip_class <= GFX8) {
1191 sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_L2;
1192 sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WB_L2;
1193 }
1194
1195 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1196 sscreen->debug_flags |= DBG_ALL_SHADERS;
1197
1198 /* Syntax:
1199 * EQAA=s,z,c
1200 * Example:
1201 * EQAA=8,4,2
1202
1203 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1204 * Constraints:
1205 * s >= z >= c (ignoring this only wastes memory)
1206 * s = [2..16]
1207 * z = [2..8]
1208 * c = [2..8]
1209 *
1210 * Only MSAA color and depth buffers are overriden.
1211 */
1212 if (sscreen->info.has_eqaa_surface_allocator) {
1213 const char *eqaa = debug_get_option("EQAA", NULL);
1214 unsigned s, z, f;
1215
1216 if (eqaa && sscanf(eqaa, "%u,%u,%u", &s, &z, &f) == 3 && s && z && f) {
1217 sscreen->eqaa_force_coverage_samples = s;
1218 sscreen->eqaa_force_z_samples = z;
1219 sscreen->eqaa_force_color_samples = f;
1220 }
1221 }
1222
1223 sscreen->ge_wave_size = 64;
1224 sscreen->ps_wave_size = 64;
1225 sscreen->compute_wave_size = 64;
1226
1227 if (sscreen->info.chip_class >= GFX10) {
1228 /* Pixel shaders: Wave64 is always fastest.
1229 * Vertex shaders: Wave64 is probably better, because:
1230 * - greater chance of L0 cache hits, because more threads are assigned
1231 * to the same CU
1232 * - scalar instructions are only executed once for 64 threads instead of twice
1233 * - VGPR allocation granularity is half of Wave32, so 1 Wave64 can
1234 * sometimes use fewer VGPRs than 2 Wave32
1235 * - TessMark X64 with NGG culling is faster with Wave64
1236 */
1237 if (sscreen->debug_flags & DBG(W32_GE))
1238 sscreen->ge_wave_size = 32;
1239 if (sscreen->debug_flags & DBG(W32_PS))
1240 sscreen->ps_wave_size = 32;
1241 if (sscreen->debug_flags & DBG(W32_CS))
1242 sscreen->compute_wave_size = 32;
1243
1244 if (sscreen->debug_flags & DBG(W64_GE))
1245 sscreen->ge_wave_size = 64;
1246 if (sscreen->debug_flags & DBG(W64_PS))
1247 sscreen->ps_wave_size = 64;
1248 if (sscreen->debug_flags & DBG(W64_CS))
1249 sscreen->compute_wave_size = 64;
1250 }
1251
1252 /* Create the auxiliary context. This must be done last. */
1253 sscreen->aux_context = si_create_context(
1254 &sscreen->b, (sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) |
1255 (sscreen->info.has_graphics ? 0 : PIPE_CONTEXT_COMPUTE_ONLY));
1256 if (sscreen->options.aux_debug) {
1257 struct u_log_context *log = CALLOC_STRUCT(u_log_context);
1258 u_log_context_init(log);
1259 sscreen->aux_context->set_log_context(sscreen->aux_context, log);
1260 }
1261
1262 if (test_flags & DBG(TEST_DMA))
1263 si_test_dma(sscreen);
1264
1265 if (test_flags & DBG(TEST_DMA_PERF)) {
1266 si_test_dma_perf(sscreen);
1267 }
1268
1269 if (test_flags & (DBG(TEST_VMFAULT_CP) | DBG(TEST_VMFAULT_SDMA) | DBG(TEST_VMFAULT_SHADER)))
1270 si_test_vmfault(sscreen, test_flags);
1271
1272 if (test_flags & DBG(TEST_GDS))
1273 si_test_gds((struct si_context *)sscreen->aux_context);
1274
1275 if (test_flags & DBG(TEST_GDS_MM)) {
1276 si_test_gds_memory_management((struct si_context *)sscreen->aux_context, 32 * 1024, 4,
1277 RADEON_DOMAIN_GDS);
1278 }
1279 if (test_flags & DBG(TEST_GDS_OA_MM)) {
1280 si_test_gds_memory_management((struct si_context *)sscreen->aux_context, 4, 1,
1281 RADEON_DOMAIN_OA);
1282 }
1283
1284 STATIC_ASSERT(sizeof(union si_vgt_stages_key) == 4);
1285 return &sscreen->b;
1286 }
1287
1288 struct pipe_screen *radeonsi_screen_create(int fd, const struct pipe_screen_config *config)
1289 {
1290 drmVersionPtr version = drmGetVersion(fd);
1291 struct radeon_winsys *rw = NULL;
1292
1293 switch (version->version_major) {
1294 case 2:
1295 rw = radeon_drm_winsys_create(fd, config, radeonsi_screen_create_impl);
1296 break;
1297 case 3:
1298 rw = amdgpu_winsys_create(fd, config, radeonsi_screen_create_impl);
1299 break;
1300 }
1301
1302 drmFreeVersion(version);
1303 return rw ? rw->screen : NULL;
1304 }