2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "si_public.h"
28 #include "si_shader_internal.h"
29 #include "si_compute.h"
32 #include "ac_llvm_util.h"
33 #include "radeon/radeon_uvd.h"
34 #include "util/disk_cache.h"
35 #include "util/u_log.h"
36 #include "util/u_memory.h"
37 #include "util/u_suballoc.h"
38 #include "util/u_tests.h"
39 #include "util/u_upload_mgr.h"
40 #include "util/xmlconfig.h"
41 #include "vl/vl_decoder.h"
42 #include "driver_ddebug/dd_util.h"
44 #include "gallium/winsys/radeon/drm/radeon_drm_public.h"
45 #include "gallium/winsys/amdgpu/drm/amdgpu_public.h"
48 #include <llvm/Config/llvm-config.h>
50 static struct pipe_context
*si_create_context(struct pipe_screen
*screen
,
53 static const struct debug_named_value debug_options
[] = {
54 /* Shader logging options: */
55 { "vs", DBG(VS
), "Print vertex shaders" },
56 { "ps", DBG(PS
), "Print pixel shaders" },
57 { "gs", DBG(GS
), "Print geometry shaders" },
58 { "tcs", DBG(TCS
), "Print tessellation control shaders" },
59 { "tes", DBG(TES
), "Print tessellation evaluation shaders" },
60 { "cs", DBG(CS
), "Print compute shaders" },
61 { "noir", DBG(NO_IR
), "Don't print the LLVM IR"},
62 { "notgsi", DBG(NO_TGSI
), "Don't print the TGSI"},
63 { "noasm", DBG(NO_ASM
), "Don't print disassembled shaders"},
64 { "preoptir", DBG(PREOPT_IR
), "Print the LLVM IR before initial optimizations" },
66 /* Shader compiler options the shader cache should be aware of: */
67 { "sisched", DBG(SI_SCHED
), "Enable LLVM SI Machine Instruction Scheduler." },
68 { "gisel", DBG(GISEL
), "Enable LLVM global instruction selector." },
69 { "w32ge", DBG(W32_GE
), "Use Wave32 for vertex, tessellation, and geometry shaders." },
70 { "w32ps", DBG(W32_PS
), "Use Wave32 for pixel shaders." },
71 { "w32cs", DBG(W32_CS
), "Use Wave32 for computes shaders." },
72 { "w64ge", DBG(W64_GE
), "Use Wave64 for vertex, tessellation, and geometry shaders." },
73 { "w64ps", DBG(W64_PS
), "Use Wave64 for pixel shaders." },
74 { "w64cs", DBG(W64_CS
), "Use Wave64 for computes shaders." },
76 /* Shader compiler options (with no effect on the shader cache): */
77 { "checkir", DBG(CHECK_IR
), "Enable additional sanity checks on shader IR" },
78 { "mono", DBG(MONOLITHIC_SHADERS
), "Use old-style monolithic shaders compiled on demand" },
79 { "nooptvariant", DBG(NO_OPT_VARIANT
), "Disable compiling optimized shader variants." },
81 /* Information logging options: */
82 { "info", DBG(INFO
), "Print driver information" },
83 { "tex", DBG(TEX
), "Print texture info" },
84 { "compute", DBG(COMPUTE
), "Print compute info" },
85 { "vm", DBG(VM
), "Print virtual addresses when creating resources" },
88 { "forcedma", DBG(FORCE_DMA
), "Use asynchronous DMA for all operations when possible." },
89 { "nodma", DBG(NO_ASYNC_DMA
), "Disable asynchronous DMA" },
90 { "nowc", DBG(NO_WC
), "Disable GTT write combining" },
91 { "check_vm", DBG(CHECK_VM
), "Check VM faults and dump debug info." },
92 { "reserve_vmid", DBG(RESERVE_VMID
), "Force VMID reservation per context." },
93 { "zerovram", DBG(ZERO_VRAM
), "Clear VRAM allocations." },
95 /* 3D engine options: */
96 { "nogfx", DBG(NO_GFX
), "Disable graphics. Only multimedia compute paths can be used." },
97 { "nongg", DBG(NO_NGG
), "Disable NGG and use the legacy pipeline." },
98 { "alwayspd", DBG(ALWAYS_PD
), "Always enable the primitive discard compute shader." },
99 { "pd", DBG(PD
), "Enable the primitive discard compute shader for large draw calls." },
100 { "nopd", DBG(NO_PD
), "Disable the primitive discard compute shader." },
101 { "switch_on_eop", DBG(SWITCH_ON_EOP
), "Program WD/IA to switch on end-of-packet." },
102 { "nooutoforder", DBG(NO_OUT_OF_ORDER
), "Disable out-of-order rasterization" },
103 { "nodpbb", DBG(NO_DPBB
), "Disable DPBB." },
104 { "nodfsm", DBG(NO_DFSM
), "Disable DFSM." },
105 { "dpbb", DBG(DPBB
), "Enable DPBB." },
106 { "dfsm", DBG(DFSM
), "Enable DFSM." },
107 { "nohyperz", DBG(NO_HYPERZ
), "Disable Hyper-Z" },
108 { "norbplus", DBG(NO_RB_PLUS
), "Disable RB+." },
109 { "no2d", DBG(NO_2D_TILING
), "Disable 2D tiling" },
110 { "notiling", DBG(NO_TILING
), "Disable tiling" },
111 { "nodcc", DBG(NO_DCC
), "Disable DCC." },
112 { "nodccclear", DBG(NO_DCC_CLEAR
), "Disable DCC fast clear." },
113 { "nodccfb", DBG(NO_DCC_FB
), "Disable separate DCC on the main framebuffer" },
114 { "nodccmsaa", DBG(NO_DCC_MSAA
), "Disable DCC for MSAA" },
115 { "nofmask", DBG(NO_FMASK
), "Disable MSAA compression" },
118 { "testdma", DBG(TEST_DMA
), "Invoke SDMA tests and exit." },
119 { "testvmfaultcp", DBG(TEST_VMFAULT_CP
), "Invoke a CP VM fault test and exit." },
120 { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA
), "Invoke a SDMA VM fault test and exit." },
121 { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER
), "Invoke a shader VM fault test and exit." },
122 { "testdmaperf", DBG(TEST_DMA_PERF
), "Test DMA performance" },
123 { "testgds", DBG(TEST_GDS
), "Test GDS." },
124 { "testgdsmm", DBG(TEST_GDS_MM
), "Test GDS memory management." },
125 { "testgdsoamm", DBG(TEST_GDS_OA_MM
), "Test GDS OA memory management." },
127 DEBUG_NAMED_VALUE_END
/* must be last */
130 static void si_init_compiler(struct si_screen
*sscreen
,
131 struct ac_llvm_compiler
*compiler
)
133 /* Only create the less-optimizing version of the compiler on APUs
134 * predating Ryzen (Raven). */
135 bool create_low_opt_compiler
= !sscreen
->info
.has_dedicated_vram
&&
136 sscreen
->info
.chip_class
<= GFX8
;
138 enum ac_target_machine_options tm_options
=
139 (sscreen
->debug_flags
& DBG(SI_SCHED
) ? AC_TM_SISCHED
: 0) |
140 (sscreen
->debug_flags
& DBG(GISEL
) ? AC_TM_ENABLE_GLOBAL_ISEL
: 0) |
141 (sscreen
->info
.chip_class
>= GFX9
? AC_TM_FORCE_ENABLE_XNACK
: 0) |
142 (sscreen
->info
.chip_class
< GFX9
? AC_TM_FORCE_DISABLE_XNACK
: 0) |
143 (!sscreen
->llvm_has_working_vgpr_indexing
? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH
: 0) |
144 (sscreen
->debug_flags
& DBG(CHECK_IR
) ? AC_TM_CHECK_IR
: 0) |
145 (create_low_opt_compiler
? AC_TM_CREATE_LOW_OPT
: 0);
148 ac_init_llvm_compiler(compiler
, sscreen
->info
.family
, tm_options
);
149 compiler
->passes
= ac_create_llvm_passes(compiler
->tm
);
151 if (compiler
->tm_wave32
)
152 compiler
->passes_wave32
= ac_create_llvm_passes(compiler
->tm_wave32
);
153 if (compiler
->low_opt_tm
)
154 compiler
->low_opt_passes
= ac_create_llvm_passes(compiler
->low_opt_tm
);
157 static void si_destroy_compiler(struct ac_llvm_compiler
*compiler
)
159 ac_destroy_llvm_compiler(compiler
);
165 static void si_destroy_context(struct pipe_context
*context
)
167 struct si_context
*sctx
= (struct si_context
*)context
;
170 util_queue_finish(&sctx
->screen
->shader_compiler_queue
);
171 util_queue_finish(&sctx
->screen
->shader_compiler_queue_low_priority
);
173 /* Unreference the framebuffer normally to disable related logic
176 struct pipe_framebuffer_state fb
= {};
177 if (context
->set_framebuffer_state
)
178 context
->set_framebuffer_state(context
, &fb
);
180 si_release_all_descriptors(sctx
);
182 if (sctx
->chip_class
>= GFX10
&& sctx
->has_graphics
)
183 gfx10_destroy_query(sctx
);
185 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
186 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
187 pipe_resource_reference(&sctx
->tess_rings
, NULL
);
188 pipe_resource_reference(&sctx
->null_const_buf
.buffer
, NULL
);
189 pipe_resource_reference(&sctx
->sample_pos_buffer
, NULL
);
190 si_resource_reference(&sctx
->border_color_buffer
, NULL
);
191 free(sctx
->border_color_table
);
192 si_resource_reference(&sctx
->scratch_buffer
, NULL
);
193 si_resource_reference(&sctx
->compute_scratch_buffer
, NULL
);
194 si_resource_reference(&sctx
->wait_mem_scratch
, NULL
);
196 si_pm4_free_state(sctx
, sctx
->init_config
, ~0);
197 if (sctx
->init_config_gs_rings
)
198 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
199 for (i
= 0; i
< ARRAY_SIZE(sctx
->vgt_shader_config
); i
++)
200 si_pm4_delete_state(sctx
, vgt_shader_config
, sctx
->vgt_shader_config
[i
]);
202 if (sctx
->fixed_func_tcs_shader
.cso
)
203 sctx
->b
.delete_tcs_state(&sctx
->b
, sctx
->fixed_func_tcs_shader
.cso
);
204 if (sctx
->custom_dsa_flush
)
205 sctx
->b
.delete_depth_stencil_alpha_state(&sctx
->b
, sctx
->custom_dsa_flush
);
206 if (sctx
->custom_blend_resolve
)
207 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_resolve
);
208 if (sctx
->custom_blend_fmask_decompress
)
209 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_fmask_decompress
);
210 if (sctx
->custom_blend_eliminate_fastclear
)
211 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_eliminate_fastclear
);
212 if (sctx
->custom_blend_dcc_decompress
)
213 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_dcc_decompress
);
214 if (sctx
->vs_blit_pos
)
215 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_pos
);
216 if (sctx
->vs_blit_pos_layered
)
217 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_pos_layered
);
218 if (sctx
->vs_blit_color
)
219 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_color
);
220 if (sctx
->vs_blit_color_layered
)
221 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_color_layered
);
222 if (sctx
->vs_blit_texcoord
)
223 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_texcoord
);
224 if (sctx
->cs_clear_buffer
)
225 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_clear_buffer
);
226 if (sctx
->cs_copy_buffer
)
227 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_copy_buffer
);
228 if (sctx
->cs_copy_image
)
229 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_copy_image
);
230 if (sctx
->cs_copy_image_1d_array
)
231 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_copy_image_1d_array
);
232 if (sctx
->cs_clear_render_target
)
233 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_clear_render_target
);
234 if (sctx
->cs_clear_render_target_1d_array
)
235 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_clear_render_target_1d_array
);
236 if (sctx
->cs_dcc_retile
)
237 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_dcc_retile
);
239 for (unsigned i
= 0; i
< ARRAY_SIZE(sctx
->cs_fmask_expand
); i
++) {
240 for (unsigned j
= 0; j
< ARRAY_SIZE(sctx
->cs_fmask_expand
[i
]); j
++) {
241 if (sctx
->cs_fmask_expand
[i
][j
]) {
242 sctx
->b
.delete_compute_state(&sctx
->b
,
243 sctx
->cs_fmask_expand
[i
][j
]);
249 util_blitter_destroy(sctx
->blitter
);
251 /* Release DCC stats. */
252 for (int i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++) {
253 assert(!sctx
->dcc_stats
[i
].query_active
);
255 for (int j
= 0; j
< ARRAY_SIZE(sctx
->dcc_stats
[i
].ps_stats
); j
++)
256 if (sctx
->dcc_stats
[i
].ps_stats
[j
])
257 sctx
->b
.destroy_query(&sctx
->b
,
258 sctx
->dcc_stats
[i
].ps_stats
[j
]);
260 si_texture_reference(&sctx
->dcc_stats
[i
].tex
, NULL
);
263 if (sctx
->query_result_shader
)
264 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->query_result_shader
);
265 if (sctx
->sh_query_result_shader
)
266 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->sh_query_result_shader
);
269 sctx
->ws
->cs_destroy(sctx
->gfx_cs
);
271 sctx
->ws
->cs_destroy(sctx
->dma_cs
);
273 sctx
->ws
->ctx_destroy(sctx
->ctx
);
275 if (sctx
->b
.stream_uploader
)
276 u_upload_destroy(sctx
->b
.stream_uploader
);
277 if (sctx
->b
.const_uploader
)
278 u_upload_destroy(sctx
->b
.const_uploader
);
279 if (sctx
->cached_gtt_allocator
)
280 u_upload_destroy(sctx
->cached_gtt_allocator
);
282 slab_destroy_child(&sctx
->pool_transfers
);
283 slab_destroy_child(&sctx
->pool_transfers_unsync
);
285 if (sctx
->allocator_zeroed_memory
)
286 u_suballocator_destroy(sctx
->allocator_zeroed_memory
);
288 sctx
->ws
->fence_reference(&sctx
->last_gfx_fence
, NULL
);
289 sctx
->ws
->fence_reference(&sctx
->last_sdma_fence
, NULL
);
290 sctx
->ws
->fence_reference(&sctx
->last_ib_barrier_fence
, NULL
);
291 si_resource_reference(&sctx
->eop_bug_scratch
, NULL
);
292 si_resource_reference(&sctx
->index_ring
, NULL
);
293 si_resource_reference(&sctx
->barrier_buf
, NULL
);
294 si_resource_reference(&sctx
->last_ib_barrier_buf
, NULL
);
295 pb_reference(&sctx
->gds
, NULL
);
296 pb_reference(&sctx
->gds_oa
, NULL
);
298 si_destroy_compiler(&sctx
->compiler
);
300 si_saved_cs_reference(&sctx
->current_saved_cs
, NULL
);
302 _mesa_hash_table_destroy(sctx
->tex_handles
, NULL
);
303 _mesa_hash_table_destroy(sctx
->img_handles
, NULL
);
305 util_dynarray_fini(&sctx
->resident_tex_handles
);
306 util_dynarray_fini(&sctx
->resident_img_handles
);
307 util_dynarray_fini(&sctx
->resident_tex_needs_color_decompress
);
308 util_dynarray_fini(&sctx
->resident_img_needs_color_decompress
);
309 util_dynarray_fini(&sctx
->resident_tex_needs_depth_decompress
);
310 si_unref_sdma_uploads(sctx
);
311 free(sctx
->sdma_uploads
);
315 static enum pipe_reset_status
si_get_reset_status(struct pipe_context
*ctx
)
317 struct si_context
*sctx
= (struct si_context
*)ctx
;
318 struct si_screen
*sscreen
= sctx
->screen
;
319 enum pipe_reset_status status
= sctx
->ws
->ctx_query_reset_status(sctx
->ctx
);
321 if (status
!= PIPE_NO_RESET
) {
322 /* Call the state tracker to set a no-op API dispatch. */
323 if (sctx
->device_reset_callback
.reset
) {
324 sctx
->device_reset_callback
.reset(sctx
->device_reset_callback
.data
,
328 /* Re-create the auxiliary context, because it won't submit
329 * any new IBs due to a GPU reset.
331 simple_mtx_lock(&sscreen
->aux_context_lock
);
333 struct u_log_context
*aux_log
= ((struct si_context
*)sscreen
->aux_context
)->log
;
334 sscreen
->aux_context
->set_log_context(sscreen
->aux_context
, NULL
);
335 sscreen
->aux_context
->destroy(sscreen
->aux_context
);
337 sscreen
->aux_context
= si_create_context(&sscreen
->b
,
338 (sscreen
->options
.aux_debug
? PIPE_CONTEXT_DEBUG
: 0) |
339 (sscreen
->info
.has_graphics
? 0 : PIPE_CONTEXT_COMPUTE_ONLY
));
340 sscreen
->aux_context
->set_log_context(sscreen
->aux_context
, aux_log
);
341 simple_mtx_unlock(&sscreen
->aux_context_lock
);
346 static void si_set_device_reset_callback(struct pipe_context
*ctx
,
347 const struct pipe_device_reset_callback
*cb
)
349 struct si_context
*sctx
= (struct si_context
*)ctx
;
352 sctx
->device_reset_callback
= *cb
;
354 memset(&sctx
->device_reset_callback
, 0,
355 sizeof(sctx
->device_reset_callback
));
358 /* Apitrace profiling:
359 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
360 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
361 * and remember its number.
362 * 3) In Mesa, enable queries and performance counters around that draw
363 * call and print the results.
364 * 4) glretrace --benchmark --markers ..
366 static void si_emit_string_marker(struct pipe_context
*ctx
,
367 const char *string
, int len
)
369 struct si_context
*sctx
= (struct si_context
*)ctx
;
371 dd_parse_apitrace_marker(string
, len
, &sctx
->apitrace_call_number
);
374 u_log_printf(sctx
->log
, "\nString marker: %*s\n", len
, string
);
377 static void si_set_debug_callback(struct pipe_context
*ctx
,
378 const struct pipe_debug_callback
*cb
)
380 struct si_context
*sctx
= (struct si_context
*)ctx
;
381 struct si_screen
*screen
= sctx
->screen
;
383 util_queue_finish(&screen
->shader_compiler_queue
);
384 util_queue_finish(&screen
->shader_compiler_queue_low_priority
);
389 memset(&sctx
->debug
, 0, sizeof(sctx
->debug
));
392 static void si_set_log_context(struct pipe_context
*ctx
,
393 struct u_log_context
*log
)
395 struct si_context
*sctx
= (struct si_context
*)ctx
;
399 u_log_add_auto_logger(log
, si_auto_log_cs
, sctx
);
402 static void si_set_context_param(struct pipe_context
*ctx
,
403 enum pipe_context_param param
,
406 struct radeon_winsys
*ws
= ((struct si_context
*)ctx
)->ws
;
409 case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE
:
410 ws
->pin_threads_to_L3_cache(ws
, value
);
416 static struct pipe_context
*si_create_context(struct pipe_screen
*screen
,
419 struct si_screen
* sscreen
= (struct si_screen
*)screen
;
421 /* Don't create a context if it's not compute-only and hw is compute-only. */
422 if (!sscreen
->info
.has_graphics
&&
423 !(flags
& PIPE_CONTEXT_COMPUTE_ONLY
))
426 struct si_context
*sctx
= CALLOC_STRUCT(si_context
);
427 struct radeon_winsys
*ws
= sscreen
->ws
;
429 bool stop_exec_on_failure
= (flags
& PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET
) != 0;
434 sctx
->has_graphics
= sscreen
->info
.chip_class
== GFX6
||
435 !(flags
& PIPE_CONTEXT_COMPUTE_ONLY
);
437 if (flags
& PIPE_CONTEXT_DEBUG
)
438 sscreen
->record_llvm_ir
= true; /* racy but not critical */
440 sctx
->b
.screen
= screen
; /* this must be set first */
442 sctx
->b
.destroy
= si_destroy_context
;
443 sctx
->screen
= sscreen
; /* Easy accessing of screen/winsys. */
444 sctx
->is_debug
= (flags
& PIPE_CONTEXT_DEBUG
) != 0;
446 slab_create_child(&sctx
->pool_transfers
, &sscreen
->pool_transfers
);
447 slab_create_child(&sctx
->pool_transfers_unsync
, &sscreen
->pool_transfers
);
449 sctx
->ws
= sscreen
->ws
;
450 sctx
->family
= sscreen
->info
.family
;
451 sctx
->chip_class
= sscreen
->info
.chip_class
;
453 if (sctx
->chip_class
== GFX7
||
454 sctx
->chip_class
== GFX8
||
455 sctx
->chip_class
== GFX9
) {
456 sctx
->eop_bug_scratch
= si_resource(
457 pipe_buffer_create(&sscreen
->b
, 0, PIPE_USAGE_DEFAULT
,
458 16 * sscreen
->info
.num_render_backends
));
459 if (!sctx
->eop_bug_scratch
)
463 /* Initialize context allocators. */
464 sctx
->allocator_zeroed_memory
=
465 u_suballocator_create(&sctx
->b
, 128 * 1024,
466 0, PIPE_USAGE_DEFAULT
,
467 SI_RESOURCE_FLAG_UNMAPPABLE
|
468 SI_RESOURCE_FLAG_CLEAR
, false);
469 if (!sctx
->allocator_zeroed_memory
)
472 sctx
->b
.stream_uploader
= u_upload_create(&sctx
->b
, 1024 * 1024,
473 0, PIPE_USAGE_STREAM
,
474 SI_RESOURCE_FLAG_READ_ONLY
);
475 if (!sctx
->b
.stream_uploader
)
478 sctx
->cached_gtt_allocator
= u_upload_create(&sctx
->b
, 16 * 1024,
479 0, PIPE_USAGE_STAGING
, 0);
480 if (!sctx
->cached_gtt_allocator
)
483 sctx
->ctx
= sctx
->ws
->ctx_create(sctx
->ws
);
487 if (sscreen
->info
.num_sdma_rings
&& !(sscreen
->debug_flags
& DBG(NO_ASYNC_DMA
))) {
488 sctx
->dma_cs
= sctx
->ws
->cs_create(sctx
->ctx
, RING_DMA
,
489 (void*)si_flush_dma_cs
,
490 sctx
, stop_exec_on_failure
);
493 bool use_sdma_upload
= sscreen
->info
.has_dedicated_vram
&& sctx
->dma_cs
;
494 sctx
->b
.const_uploader
= u_upload_create(&sctx
->b
, 256 * 1024,
495 0, PIPE_USAGE_DEFAULT
,
496 SI_RESOURCE_FLAG_32BIT
|
498 SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA
: 0));
499 if (!sctx
->b
.const_uploader
)
503 u_upload_enable_flush_explicit(sctx
->b
.const_uploader
);
505 sctx
->gfx_cs
= ws
->cs_create(sctx
->ctx
,
506 sctx
->has_graphics
? RING_GFX
: RING_COMPUTE
,
507 (void*)si_flush_gfx_cs
, sctx
, stop_exec_on_failure
);
510 sctx
->border_color_table
= malloc(SI_MAX_BORDER_COLORS
*
511 sizeof(*sctx
->border_color_table
));
512 if (!sctx
->border_color_table
)
515 sctx
->border_color_buffer
= si_resource(
516 pipe_buffer_create(screen
, 0, PIPE_USAGE_DEFAULT
,
517 SI_MAX_BORDER_COLORS
*
518 sizeof(*sctx
->border_color_table
)));
519 if (!sctx
->border_color_buffer
)
522 sctx
->border_color_map
=
523 ws
->buffer_map(sctx
->border_color_buffer
->buf
,
524 NULL
, PIPE_TRANSFER_WRITE
);
525 if (!sctx
->border_color_map
)
528 sctx
->ngg
= sscreen
->use_ngg
;
530 /* Initialize context functions used by graphics and compute. */
531 if (sctx
->chip_class
>= GFX10
)
532 sctx
->emit_cache_flush
= gfx10_emit_cache_flush
;
534 sctx
->emit_cache_flush
= si_emit_cache_flush
;
536 sctx
->b
.emit_string_marker
= si_emit_string_marker
;
537 sctx
->b
.set_debug_callback
= si_set_debug_callback
;
538 sctx
->b
.set_log_context
= si_set_log_context
;
539 sctx
->b
.set_context_param
= si_set_context_param
;
540 sctx
->b
.get_device_reset_status
= si_get_reset_status
;
541 sctx
->b
.set_device_reset_callback
= si_set_device_reset_callback
;
543 si_init_all_descriptors(sctx
);
544 si_init_buffer_functions(sctx
);
545 si_init_clear_functions(sctx
);
546 si_init_blit_functions(sctx
);
547 si_init_compute_functions(sctx
);
548 si_init_compute_blit_functions(sctx
);
549 si_init_debug_functions(sctx
);
550 si_init_fence_functions(sctx
);
551 si_init_query_functions(sctx
);
552 si_init_state_compute_functions(sctx
);
553 si_init_context_texture_functions(sctx
);
555 /* Initialize graphics-only context functions. */
556 if (sctx
->has_graphics
) {
557 if (sctx
->chip_class
>= GFX10
)
558 gfx10_init_query(sctx
);
559 si_init_msaa_functions(sctx
);
560 si_init_shader_functions(sctx
);
561 si_init_state_functions(sctx
);
562 si_init_streamout_functions(sctx
);
563 si_init_viewport_functions(sctx
);
565 sctx
->blitter
= util_blitter_create(&sctx
->b
);
566 if (sctx
->blitter
== NULL
)
568 sctx
->blitter
->skip_viewport_restore
= true;
570 /* Some states are expected to be always non-NULL. */
571 sctx
->noop_blend
= util_blitter_get_noop_blend_state(sctx
->blitter
);
572 sctx
->queued
.named
.blend
= sctx
->noop_blend
;
574 sctx
->noop_dsa
= util_blitter_get_noop_dsa_state(sctx
->blitter
);
575 sctx
->queued
.named
.dsa
= sctx
->noop_dsa
;
577 sctx
->discard_rasterizer_state
=
578 util_blitter_get_discard_rasterizer_state(sctx
->blitter
);
579 sctx
->queued
.named
.rasterizer
= sctx
->discard_rasterizer_state
;
581 si_init_draw_functions(sctx
);
582 si_initialize_prim_discard_tunables(sctx
);
585 /* Initialize SDMA functions. */
586 if (sctx
->chip_class
>= GFX7
)
587 cik_init_sdma_functions(sctx
);
589 si_init_dma_functions(sctx
);
591 if (sscreen
->debug_flags
& DBG(FORCE_DMA
))
592 sctx
->b
.resource_copy_region
= sctx
->dma_copy
;
594 sctx
->sample_mask
= 0xffff;
596 /* Initialize multimedia functions. */
597 if (sscreen
->info
.has_hw_decode
) {
598 sctx
->b
.create_video_codec
= si_uvd_create_decoder
;
599 sctx
->b
.create_video_buffer
= si_video_buffer_create
;
601 sctx
->b
.create_video_codec
= vl_create_decoder
;
602 sctx
->b
.create_video_buffer
= vl_video_buffer_create
;
605 if (sctx
->chip_class
>= GFX9
) {
606 sctx
->wait_mem_scratch
= si_resource(
607 pipe_buffer_create(screen
, 0, PIPE_USAGE_DEFAULT
, 8));
608 if (!sctx
->wait_mem_scratch
)
611 /* Initialize the memory. */
612 si_cp_write_data(sctx
, sctx
->wait_mem_scratch
, 0, 4,
613 V_370_MEM
, V_370_ME
, &sctx
->wait_mem_number
);
616 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
617 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
618 if (sctx
->chip_class
== GFX7
) {
619 sctx
->null_const_buf
.buffer
=
620 pipe_aligned_buffer_create(screen
,
621 SI_RESOURCE_FLAG_32BIT
,
622 PIPE_USAGE_DEFAULT
, 16,
623 sctx
->screen
->info
.tcc_cache_line_size
);
624 if (!sctx
->null_const_buf
.buffer
)
626 sctx
->null_const_buf
.buffer_size
= sctx
->null_const_buf
.buffer
->width0
;
628 unsigned start_shader
= sctx
->has_graphics
? 0 : PIPE_SHADER_COMPUTE
;
629 for (shader
= start_shader
; shader
< SI_NUM_SHADERS
; shader
++) {
630 for (i
= 0; i
< SI_NUM_CONST_BUFFERS
; i
++) {
631 sctx
->b
.set_constant_buffer(&sctx
->b
, shader
, i
,
632 &sctx
->null_const_buf
);
636 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
,
637 &sctx
->null_const_buf
);
638 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
,
639 &sctx
->null_const_buf
);
640 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
,
641 &sctx
->null_const_buf
);
642 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
,
643 &sctx
->null_const_buf
);
644 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
,
645 &sctx
->null_const_buf
);
648 uint64_t max_threads_per_block
;
649 screen
->get_compute_param(screen
, PIPE_SHADER_IR_TGSI
,
650 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
,
651 &max_threads_per_block
);
653 /* The maximum number of scratch waves. Scratch space isn't divided
654 * evenly between CUs. The number is only a function of the number of CUs.
655 * We can decrease the constant to decrease the scratch buffer size.
657 * sctx->scratch_waves must be >= the maximum posible size of
658 * 1 threadgroup, so that the hw doesn't hang from being unable
661 * The recommended value is 4 per CU at most. Higher numbers don't
662 * bring much benefit, but they still occupy chip resources (think
663 * async compute). I've seen ~2% performance difference between 4 and 32.
665 sctx
->scratch_waves
= MAX2(32 * sscreen
->info
.num_good_compute_units
,
666 max_threads_per_block
/ 64);
668 si_init_compiler(sscreen
, &sctx
->compiler
);
670 /* Bindless handles. */
671 sctx
->tex_handles
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
672 _mesa_key_pointer_equal
);
673 sctx
->img_handles
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
674 _mesa_key_pointer_equal
);
676 util_dynarray_init(&sctx
->resident_tex_handles
, NULL
);
677 util_dynarray_init(&sctx
->resident_img_handles
, NULL
);
678 util_dynarray_init(&sctx
->resident_tex_needs_color_decompress
, NULL
);
679 util_dynarray_init(&sctx
->resident_img_needs_color_decompress
, NULL
);
680 util_dynarray_init(&sctx
->resident_tex_needs_depth_decompress
, NULL
);
682 sctx
->sample_pos_buffer
=
683 pipe_buffer_create(sctx
->b
.screen
, 0, PIPE_USAGE_DEFAULT
,
684 sizeof(sctx
->sample_positions
));
685 pipe_buffer_write(&sctx
->b
, sctx
->sample_pos_buffer
, 0,
686 sizeof(sctx
->sample_positions
), &sctx
->sample_positions
);
688 /* this must be last */
689 si_begin_new_gfx_cs(sctx
);
691 if (sctx
->chip_class
== GFX7
) {
692 /* Clear the NULL constant buffer, because loads should return zeros.
693 * Note that this forces CP DMA to be used, because clover deadlocks
694 * for some reason when the compute codepath is used.
696 uint32_t clear_value
= 0;
697 si_clear_buffer(sctx
, sctx
->null_const_buf
.buffer
, 0,
698 sctx
->null_const_buf
.buffer
->width0
,
699 &clear_value
, 4, SI_COHERENCY_SHADER
, true);
703 fprintf(stderr
, "radeonsi: Failed to create a context.\n");
704 si_destroy_context(&sctx
->b
);
708 static struct pipe_context
*si_pipe_create_context(struct pipe_screen
*screen
,
709 void *priv
, unsigned flags
)
711 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
712 struct pipe_context
*ctx
;
714 if (sscreen
->debug_flags
& DBG(CHECK_VM
))
715 flags
|= PIPE_CONTEXT_DEBUG
;
717 ctx
= si_create_context(screen
, flags
);
719 if (!(flags
& PIPE_CONTEXT_PREFER_THREADED
))
722 /* Clover (compute-only) is unsupported. */
723 if (flags
& PIPE_CONTEXT_COMPUTE_ONLY
)
726 /* When shaders are logged to stderr, asynchronous compilation is
728 if (sscreen
->debug_flags
& DBG_ALL_SHADERS
)
731 /* Use asynchronous flushes only on amdgpu, since the radeon
732 * implementation for fence_server_sync is incomplete. */
733 return threaded_context_create(ctx
, &sscreen
->pool_transfers
,
734 si_replace_buffer_storage
,
735 sscreen
->info
.is_amdgpu
? si_create_fence
: NULL
,
736 &((struct si_context
*)ctx
)->tc
);
742 static void si_destroy_screen(struct pipe_screen
* pscreen
)
744 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
745 struct si_shader_part
*parts
[] = {
747 sscreen
->tcs_epilogs
,
754 if (!sscreen
->ws
->unref(sscreen
->ws
))
757 simple_mtx_destroy(&sscreen
->aux_context_lock
);
759 struct u_log_context
*aux_log
= ((struct si_context
*)sscreen
->aux_context
)->log
;
761 sscreen
->aux_context
->set_log_context(sscreen
->aux_context
, NULL
);
762 u_log_context_destroy(aux_log
);
766 sscreen
->aux_context
->destroy(sscreen
->aux_context
);
768 util_queue_destroy(&sscreen
->shader_compiler_queue
);
769 util_queue_destroy(&sscreen
->shader_compiler_queue_low_priority
);
771 /* Release the reference on glsl types of the compiler threads. */
772 glsl_type_singleton_decref();
774 for (i
= 0; i
< ARRAY_SIZE(sscreen
->compiler
); i
++)
775 si_destroy_compiler(&sscreen
->compiler
[i
]);
777 for (i
= 0; i
< ARRAY_SIZE(sscreen
->compiler_lowp
); i
++)
778 si_destroy_compiler(&sscreen
->compiler_lowp
[i
]);
780 /* Free shader parts. */
781 for (i
= 0; i
< ARRAY_SIZE(parts
); i
++) {
783 struct si_shader_part
*part
= parts
[i
];
785 parts
[i
] = part
->next
;
786 si_shader_binary_clean(&part
->binary
);
790 simple_mtx_destroy(&sscreen
->shader_parts_mutex
);
791 si_destroy_shader_cache(sscreen
);
793 si_destroy_perfcounters(sscreen
);
794 si_gpu_load_kill_thread(sscreen
);
796 simple_mtx_destroy(&sscreen
->gpu_load_mutex
);
798 slab_destroy_parent(&sscreen
->pool_transfers
);
800 disk_cache_destroy(sscreen
->disk_shader_cache
);
801 sscreen
->ws
->destroy(sscreen
->ws
);
805 static void si_init_gs_info(struct si_screen
*sscreen
)
807 sscreen
->gs_table_depth
= ac_get_gs_table_depth(sscreen
->info
.chip_class
,
808 sscreen
->info
.family
);
811 static void si_test_vmfault(struct si_screen
*sscreen
)
813 struct pipe_context
*ctx
= sscreen
->aux_context
;
814 struct si_context
*sctx
= (struct si_context
*)ctx
;
815 struct pipe_resource
*buf
=
816 pipe_buffer_create_const0(&sscreen
->b
, 0, PIPE_USAGE_DEFAULT
, 64);
819 puts("Buffer allocation failed.");
823 si_resource(buf
)->gpu_address
= 0; /* cause a VM fault */
825 if (sscreen
->debug_flags
& DBG(TEST_VMFAULT_CP
)) {
826 si_cp_dma_copy_buffer(sctx
, buf
, buf
, 0, 4, 4, 0,
827 SI_COHERENCY_NONE
, L2_BYPASS
);
828 ctx
->flush(ctx
, NULL
, 0);
829 puts("VM fault test: CP - done.");
831 if (sscreen
->debug_flags
& DBG(TEST_VMFAULT_SDMA
)) {
832 si_sdma_clear_buffer(sctx
, buf
, 0, 4, 0);
833 ctx
->flush(ctx
, NULL
, 0);
834 puts("VM fault test: SDMA - done.");
836 if (sscreen
->debug_flags
& DBG(TEST_VMFAULT_SHADER
)) {
837 util_test_constant_buffer(ctx
, buf
);
838 puts("VM fault test: Shader - done.");
843 static void si_test_gds_memory_management(struct si_context
*sctx
,
844 unsigned alloc_size
, unsigned alignment
,
845 enum radeon_bo_domain domain
)
847 struct radeon_winsys
*ws
= sctx
->ws
;
848 struct radeon_cmdbuf
*cs
[8];
849 struct pb_buffer
*gds_bo
[ARRAY_SIZE(cs
)];
851 for (unsigned i
= 0; i
< ARRAY_SIZE(cs
); i
++) {
852 cs
[i
] = ws
->cs_create(sctx
->ctx
, RING_COMPUTE
,
854 gds_bo
[i
] = ws
->buffer_create(ws
, alloc_size
, alignment
, domain
, 0);
858 for (unsigned iterations
= 0; iterations
< 20000; iterations
++) {
859 for (unsigned i
= 0; i
< ARRAY_SIZE(cs
); i
++) {
860 /* This clears GDS with CP DMA.
862 * We don't care if GDS is present. Just add some packet
863 * to make the GPU busy for a moment.
865 si_cp_dma_clear_buffer(sctx
, cs
[i
], NULL
, 0, alloc_size
, 0,
866 SI_CPDMA_SKIP_BO_LIST_UPDATE
|
867 SI_CPDMA_SKIP_CHECK_CS_SPACE
|
868 SI_CPDMA_SKIP_GFX_SYNC
, 0, 0);
870 ws
->cs_add_buffer(cs
[i
], gds_bo
[i
], domain
,
871 RADEON_USAGE_READWRITE
, 0);
872 ws
->cs_flush(cs
[i
], PIPE_FLUSH_ASYNC
, NULL
);
878 static void si_disk_cache_create(struct si_screen
*sscreen
)
880 /* Don't use the cache if shader dumping is enabled. */
881 if (sscreen
->debug_flags
& DBG_ALL_SHADERS
)
884 struct mesa_sha1 ctx
;
885 unsigned char sha1
[20];
886 char cache_id
[20 * 2 + 1];
888 _mesa_sha1_init(&ctx
);
890 if (!disk_cache_get_function_identifier(si_disk_cache_create
, &ctx
) ||
891 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo
,
895 _mesa_sha1_final(&ctx
, sha1
);
896 disk_cache_format_hex_id(cache_id
, sha1
, 20 * 2);
898 /* These flags affect shader compilation. */
899 #define ALL_FLAGS (DBG(SI_SCHED) | DBG(GISEL))
900 uint64_t shader_debug_flags
= sscreen
->debug_flags
& ALL_FLAGS
;
902 /* Add the high bits of 32-bit addresses, which affects
903 * how 32-bit addresses are expanded to 64 bits.
905 STATIC_ASSERT(ALL_FLAGS
<= UINT_MAX
);
906 assert((int16_t)sscreen
->info
.address32_hi
== (int32_t)sscreen
->info
.address32_hi
);
907 shader_debug_flags
|= (uint64_t)(sscreen
->info
.address32_hi
& 0xffff) << 32;
909 sscreen
->disk_shader_cache
=
910 disk_cache_create(sscreen
->info
.name
,
915 static void si_set_max_shader_compiler_threads(struct pipe_screen
*screen
,
916 unsigned max_threads
)
918 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
920 /* This function doesn't allow a greater number of threads than
921 * the queue had at its creation. */
922 util_queue_adjust_num_threads(&sscreen
->shader_compiler_queue
,
924 /* Don't change the number of threads on the low priority queue. */
927 static bool si_is_parallel_shader_compilation_finished(struct pipe_screen
*screen
,
929 enum pipe_shader_type shader_type
)
931 struct si_shader_selector
*sel
= (struct si_shader_selector
*)shader
;
933 return util_queue_fence_is_signalled(&sel
->ready
);
936 static struct pipe_screen
*
937 radeonsi_screen_create_impl(struct radeon_winsys
*ws
,
938 const struct pipe_screen_config
*config
)
940 struct si_screen
*sscreen
= CALLOC_STRUCT(si_screen
);
941 unsigned hw_threads
, num_comp_hi_threads
, num_comp_lo_threads
, i
;
948 ws
->query_info(ws
, &sscreen
->info
);
950 if (sscreen
->info
.chip_class
== GFX10
&& LLVM_VERSION_MAJOR
< 9) {
951 fprintf(stderr
, "radeonsi: Navi family support requires LLVM 9 or higher\n");
956 if (sscreen
->info
.chip_class
>= GFX9
) {
957 sscreen
->se_tile_repeat
= 32 * sscreen
->info
.max_se
;
959 ac_get_raster_config(&sscreen
->info
,
960 &sscreen
->pa_sc_raster_config
,
961 &sscreen
->pa_sc_raster_config_1
,
962 &sscreen
->se_tile_repeat
);
965 sscreen
->debug_flags
= debug_get_flags_option("R600_DEBUG",
967 sscreen
->debug_flags
|= debug_get_flags_option("AMD_DEBUG",
970 if (sscreen
->debug_flags
& DBG(NO_GFX
))
971 sscreen
->info
.has_graphics
= false;
973 /* Set functions first. */
974 sscreen
->b
.context_create
= si_pipe_create_context
;
975 sscreen
->b
.destroy
= si_destroy_screen
;
976 sscreen
->b
.set_max_shader_compiler_threads
=
977 si_set_max_shader_compiler_threads
;
978 sscreen
->b
.is_parallel_shader_compilation_finished
=
979 si_is_parallel_shader_compilation_finished
;
980 sscreen
->b
.finalize_nir
= si_finalize_nir
;
982 si_init_screen_get_functions(sscreen
);
983 si_init_screen_buffer_functions(sscreen
);
984 si_init_screen_fence_functions(sscreen
);
985 si_init_screen_state_functions(sscreen
);
986 si_init_screen_texture_functions(sscreen
);
987 si_init_screen_query_functions(sscreen
);
989 /* Set these flags in debug_flags early, so that the shader cache takes
992 if (driQueryOptionb(config
->options
,
993 "glsl_correct_derivatives_after_discard"))
994 sscreen
->debug_flags
|= DBG(FS_CORRECT_DERIVS_AFTER_KILL
);
995 if (driQueryOptionb(config
->options
, "radeonsi_enable_sisched"))
996 sscreen
->debug_flags
|= DBG(SI_SCHED
);
998 if (sscreen
->debug_flags
& DBG(INFO
))
999 ac_print_gpu_info(&sscreen
->info
);
1001 slab_create_parent(&sscreen
->pool_transfers
,
1002 sizeof(struct si_transfer
), 64);
1004 sscreen
->force_aniso
= MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1005 if (sscreen
->force_aniso
== -1) {
1006 sscreen
->force_aniso
= MIN2(16, debug_get_num_option("AMD_TEX_ANISO", -1));
1009 if (sscreen
->force_aniso
>= 0) {
1010 printf("radeonsi: Forcing anisotropy filter to %ix\n",
1011 /* round down to a power of two */
1012 1 << util_logbase2(sscreen
->force_aniso
));
1015 (void) simple_mtx_init(&sscreen
->aux_context_lock
, mtx_plain
);
1016 (void) simple_mtx_init(&sscreen
->gpu_load_mutex
, mtx_plain
);
1018 si_init_gs_info(sscreen
);
1019 if (!si_init_shader_cache(sscreen
)) {
1024 si_disk_cache_create(sscreen
);
1026 /* Determine the number of shader compiler threads. */
1027 hw_threads
= sysconf(_SC_NPROCESSORS_ONLN
);
1029 if (hw_threads
>= 12) {
1030 num_comp_hi_threads
= hw_threads
* 3 / 4;
1031 num_comp_lo_threads
= hw_threads
/ 3;
1032 } else if (hw_threads
>= 6) {
1033 num_comp_hi_threads
= hw_threads
- 2;
1034 num_comp_lo_threads
= hw_threads
/ 2;
1035 } else if (hw_threads
>= 2) {
1036 num_comp_hi_threads
= hw_threads
- 1;
1037 num_comp_lo_threads
= hw_threads
/ 2;
1039 num_comp_hi_threads
= 1;
1040 num_comp_lo_threads
= 1;
1043 num_comp_hi_threads
= MIN2(num_comp_hi_threads
,
1044 ARRAY_SIZE(sscreen
->compiler
));
1045 num_comp_lo_threads
= MIN2(num_comp_lo_threads
,
1046 ARRAY_SIZE(sscreen
->compiler_lowp
));
1048 /* Take a reference on the glsl types for the compiler threads. */
1049 glsl_type_singleton_init_or_ref();
1051 if (!util_queue_init(&sscreen
->shader_compiler_queue
, "sh",
1052 64, num_comp_hi_threads
,
1053 UTIL_QUEUE_INIT_RESIZE_IF_FULL
|
1054 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY
)) {
1055 si_destroy_shader_cache(sscreen
);
1057 glsl_type_singleton_decref();
1061 if (!util_queue_init(&sscreen
->shader_compiler_queue_low_priority
,
1063 64, num_comp_lo_threads
,
1064 UTIL_QUEUE_INIT_RESIZE_IF_FULL
|
1065 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY
|
1066 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY
)) {
1067 si_destroy_shader_cache(sscreen
);
1069 glsl_type_singleton_decref();
1073 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1074 si_init_perfcounters(sscreen
);
1076 /* Determine tessellation ring info. */
1077 bool double_offchip_buffers
= sscreen
->info
.chip_class
>= GFX7
&&
1078 sscreen
->info
.family
!= CHIP_CARRIZO
&&
1079 sscreen
->info
.family
!= CHIP_STONEY
;
1080 /* This must be one less than the maximum number due to a hw limitation.
1081 * Various hardware bugs need this.
1083 unsigned max_offchip_buffers_per_se
;
1085 if (sscreen
->info
.chip_class
>= GFX10
)
1086 max_offchip_buffers_per_se
= 256;
1087 /* Only certain chips can use the maximum value. */
1088 else if (sscreen
->info
.family
== CHIP_VEGA12
||
1089 sscreen
->info
.family
== CHIP_VEGA20
)
1090 max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
1092 max_offchip_buffers_per_se
= double_offchip_buffers
? 127 : 63;
1094 unsigned max_offchip_buffers
= max_offchip_buffers_per_se
*
1095 sscreen
->info
.max_se
;
1096 unsigned offchip_granularity
;
1098 /* Hawaii has a bug with offchip buffers > 256 that can be worked
1099 * around by setting 4K granularity.
1101 if (sscreen
->info
.family
== CHIP_HAWAII
) {
1102 sscreen
->tess_offchip_block_dw_size
= 4096;
1103 offchip_granularity
= V_03093C_X_4K_DWORDS
;
1105 sscreen
->tess_offchip_block_dw_size
= 8192;
1106 offchip_granularity
= V_03093C_X_8K_DWORDS
;
1109 sscreen
->tess_factor_ring_size
= 32768 * sscreen
->info
.max_se
;
1110 sscreen
->tess_offchip_ring_size
= max_offchip_buffers
*
1111 sscreen
->tess_offchip_block_dw_size
* 4;
1113 if (sscreen
->info
.chip_class
>= GFX7
) {
1114 if (sscreen
->info
.chip_class
>= GFX8
)
1115 --max_offchip_buffers
;
1116 sscreen
->vgt_hs_offchip_param
=
1117 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
1118 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
1120 assert(offchip_granularity
== V_03093C_X_8K_DWORDS
);
1121 sscreen
->vgt_hs_offchip_param
=
1122 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
1125 sscreen
->has_draw_indirect_multi
=
1126 (sscreen
->info
.family
>= CHIP_POLARIS10
) ||
1127 (sscreen
->info
.chip_class
== GFX8
&&
1128 sscreen
->info
.pfp_fw_version
>= 121 &&
1129 sscreen
->info
.me_fw_version
>= 87) ||
1130 (sscreen
->info
.chip_class
== GFX7
&&
1131 sscreen
->info
.pfp_fw_version
>= 211 &&
1132 sscreen
->info
.me_fw_version
>= 173) ||
1133 (sscreen
->info
.chip_class
== GFX6
&&
1134 sscreen
->info
.pfp_fw_version
>= 79 &&
1135 sscreen
->info
.me_fw_version
>= 142);
1137 sscreen
->has_out_of_order_rast
= sscreen
->info
.has_out_of_order_rast
&&
1138 !(sscreen
->debug_flags
& DBG(NO_OUT_OF_ORDER
));
1139 sscreen
->assume_no_z_fights
=
1140 driQueryOptionb(config
->options
, "radeonsi_assume_no_z_fights");
1141 sscreen
->commutative_blend_add
=
1142 driQueryOptionb(config
->options
, "radeonsi_commutative_blend_add");
1145 #define OPT_BOOL(name, dflt, description) \
1146 sscreen->options.name = \
1147 driQueryOptionb(config->options, "radeonsi_"#name);
1148 #include "si_debug_options.h"
1151 sscreen
->use_ngg
= sscreen
->info
.chip_class
>= GFX10
&&
1152 sscreen
->info
.family
!= CHIP_NAVI14
&&
1153 !(sscreen
->debug_flags
& DBG(NO_NGG
));
1154 sscreen
->use_ngg_streamout
= false;
1156 /* Only enable primitive binning on APUs by default. */
1157 if (sscreen
->info
.chip_class
>= GFX10
) {
1158 sscreen
->dpbb_allowed
= true;
1159 sscreen
->dfsm_allowed
= !sscreen
->info
.has_dedicated_vram
;
1160 } else if (sscreen
->info
.chip_class
== GFX9
) {
1161 sscreen
->dpbb_allowed
= !sscreen
->info
.has_dedicated_vram
;
1162 sscreen
->dfsm_allowed
= !sscreen
->info
.has_dedicated_vram
;
1165 /* Process DPBB enable flags. */
1166 if (sscreen
->debug_flags
& DBG(DPBB
)) {
1167 sscreen
->dpbb_allowed
= true;
1168 if (sscreen
->debug_flags
& DBG(DFSM
))
1169 sscreen
->dfsm_allowed
= true;
1172 /* Process DPBB disable flags. */
1173 if (sscreen
->debug_flags
& DBG(NO_DPBB
)) {
1174 sscreen
->dpbb_allowed
= false;
1175 sscreen
->dfsm_allowed
= false;
1176 } else if (sscreen
->debug_flags
& DBG(NO_DFSM
)) {
1177 sscreen
->dfsm_allowed
= false;
1180 /* While it would be nice not to have this flag, we are constrained
1181 * by the reality that LLVM 9.0 has buggy VGPR indexing on GFX9.
1183 sscreen
->llvm_has_working_vgpr_indexing
= sscreen
->info
.chip_class
!= GFX9
;
1185 sscreen
->dcc_msaa_allowed
=
1186 !(sscreen
->debug_flags
& DBG(NO_DCC_MSAA
));
1188 (void) simple_mtx_init(&sscreen
->shader_parts_mutex
, mtx_plain
);
1189 sscreen
->use_monolithic_shaders
=
1190 (sscreen
->debug_flags
& DBG(MONOLITHIC_SHADERS
)) != 0;
1192 sscreen
->barrier_flags
.cp_to_L2
= SI_CONTEXT_INV_SCACHE
|
1193 SI_CONTEXT_INV_VCACHE
;
1194 if (sscreen
->info
.chip_class
<= GFX8
) {
1195 sscreen
->barrier_flags
.cp_to_L2
|= SI_CONTEXT_INV_L2
;
1196 sscreen
->barrier_flags
.L2_to_cp
|= SI_CONTEXT_WB_L2
;
1199 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1200 sscreen
->debug_flags
|= DBG_ALL_SHADERS
;
1207 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1209 * s >= z >= c (ignoring this only wastes memory)
1214 * Only MSAA color and depth buffers are overriden.
1216 if (sscreen
->info
.has_eqaa_surface_allocator
) {
1217 const char *eqaa
= debug_get_option("EQAA", NULL
);
1220 if (eqaa
&& sscanf(eqaa
, "%u,%u,%u", &s
, &z
, &f
) == 3 && s
&& z
&& f
) {
1221 sscreen
->eqaa_force_coverage_samples
= s
;
1222 sscreen
->eqaa_force_z_samples
= z
;
1223 sscreen
->eqaa_force_color_samples
= f
;
1227 for (i
= 0; i
< num_comp_hi_threads
; i
++)
1228 si_init_compiler(sscreen
, &sscreen
->compiler
[i
]);
1229 for (i
= 0; i
< num_comp_lo_threads
; i
++)
1230 si_init_compiler(sscreen
, &sscreen
->compiler_lowp
[i
]);
1232 sscreen
->ge_wave_size
= 64;
1233 sscreen
->ps_wave_size
= 64;
1234 sscreen
->compute_wave_size
= 64;
1236 if (sscreen
->info
.chip_class
>= GFX10
) {
1237 /* Pixels shaders: Wave64 is recommended.
1238 * Compute shaders: There are piglit failures with Wave32.
1240 sscreen
->ge_wave_size
= 32;
1242 if (sscreen
->debug_flags
& DBG(W32_GE
))
1243 sscreen
->ge_wave_size
= 32;
1244 if (sscreen
->debug_flags
& DBG(W32_PS
))
1245 sscreen
->ps_wave_size
= 32;
1246 if (sscreen
->debug_flags
& DBG(W32_CS
))
1247 sscreen
->compute_wave_size
= 32;
1249 if (sscreen
->debug_flags
& DBG(W64_GE
))
1250 sscreen
->ge_wave_size
= 64;
1251 if (sscreen
->debug_flags
& DBG(W64_PS
))
1252 sscreen
->ps_wave_size
= 64;
1253 if (sscreen
->debug_flags
& DBG(W64_CS
))
1254 sscreen
->compute_wave_size
= 64;
1257 /* Create the auxiliary context. This must be done last. */
1258 sscreen
->aux_context
= si_create_context(&sscreen
->b
,
1259 (sscreen
->options
.aux_debug
? PIPE_CONTEXT_DEBUG
: 0) |
1260 (sscreen
->info
.has_graphics
? 0 : PIPE_CONTEXT_COMPUTE_ONLY
));
1261 if (sscreen
->options
.aux_debug
) {
1262 struct u_log_context
*log
= CALLOC_STRUCT(u_log_context
);
1263 u_log_context_init(log
);
1264 sscreen
->aux_context
->set_log_context(sscreen
->aux_context
, log
);
1267 if (sscreen
->debug_flags
& DBG(TEST_DMA
))
1268 si_test_dma(sscreen
);
1270 if (sscreen
->debug_flags
& DBG(TEST_DMA_PERF
)) {
1271 si_test_dma_perf(sscreen
);
1274 if (sscreen
->debug_flags
& (DBG(TEST_VMFAULT_CP
) |
1275 DBG(TEST_VMFAULT_SDMA
) |
1276 DBG(TEST_VMFAULT_SHADER
)))
1277 si_test_vmfault(sscreen
);
1279 if (sscreen
->debug_flags
& DBG(TEST_GDS
))
1280 si_test_gds((struct si_context
*)sscreen
->aux_context
);
1282 if (sscreen
->debug_flags
& DBG(TEST_GDS_MM
)) {
1283 si_test_gds_memory_management((struct si_context
*)sscreen
->aux_context
,
1284 32 * 1024, 4, RADEON_DOMAIN_GDS
);
1286 if (sscreen
->debug_flags
& DBG(TEST_GDS_OA_MM
)) {
1287 si_test_gds_memory_management((struct si_context
*)sscreen
->aux_context
,
1288 4, 1, RADEON_DOMAIN_OA
);
1294 struct pipe_screen
*radeonsi_screen_create(int fd
, const struct pipe_screen_config
*config
)
1296 drmVersionPtr version
= drmGetVersion(fd
);
1297 struct radeon_winsys
*rw
= NULL
;
1299 switch (version
->version_major
) {
1301 rw
= radeon_drm_winsys_create(fd
, config
, radeonsi_screen_create_impl
);
1304 rw
= amdgpu_winsys_create(fd
, config
, radeonsi_screen_create_impl
);
1308 drmFreeVersion(version
);
1309 return rw
? rw
->screen
: NULL
;