99fa2b40c7a8bbce47b8886f01bb27db60839b4c
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "si_pipe.h"
27
28 #include "driver_ddebug/dd_util.h"
29 #include "gallium/winsys/amdgpu/drm/amdgpu_public.h"
30 #include "gallium/winsys/radeon/drm/radeon_drm_public.h"
31 #include "radeon/radeon_uvd.h"
32 #include "si_compute.h"
33 #include "si_public.h"
34 #include "si_shader_internal.h"
35 #include "sid.h"
36 #include "util/disk_cache.h"
37 #include "util/u_log.h"
38 #include "util/u_memory.h"
39 #include "util/u_suballoc.h"
40 #include "util/u_tests.h"
41 #include "util/u_upload_mgr.h"
42 #include "util/xmlconfig.h"
43 #include "vl/vl_decoder.h"
44
45 #include <xf86drm.h>
46
47 static struct pipe_context *si_create_context(struct pipe_screen *screen, unsigned flags);
48
49 static const struct debug_named_value debug_options[] = {
50 /* Shader logging options: */
51 {"vs", DBG(VS), "Print vertex shaders"},
52 {"ps", DBG(PS), "Print pixel shaders"},
53 {"gs", DBG(GS), "Print geometry shaders"},
54 {"tcs", DBG(TCS), "Print tessellation control shaders"},
55 {"tes", DBG(TES), "Print tessellation evaluation shaders"},
56 {"cs", DBG(CS), "Print compute shaders"},
57 {"noir", DBG(NO_IR), "Don't print the LLVM IR"},
58 {"nonir", DBG(NO_NIR), "Don't print NIR when printing shaders"},
59 {"noasm", DBG(NO_ASM), "Don't print disassembled shaders"},
60 {"preoptir", DBG(PREOPT_IR), "Print the LLVM IR before initial optimizations"},
61
62 /* Shader compiler options the shader cache should be aware of: */
63 {"gisel", DBG(GISEL), "Enable LLVM global instruction selector."},
64 {"w32ge", DBG(W32_GE), "Use Wave32 for vertex, tessellation, and geometry shaders."},
65 {"w32ps", DBG(W32_PS), "Use Wave32 for pixel shaders."},
66 {"w32cs", DBG(W32_CS), "Use Wave32 for computes shaders."},
67 {"w64ge", DBG(W64_GE), "Use Wave64 for vertex, tessellation, and geometry shaders."},
68 {"w64ps", DBG(W64_PS), "Use Wave64 for pixel shaders."},
69 {"w64cs", DBG(W64_CS), "Use Wave64 for computes shaders."},
70 {"noinfinterp", DBG(KILL_PS_INF_INTERP), "Kill PS with infinite interp coeff"},
71
72 /* Shader compiler options (with no effect on the shader cache): */
73 {"checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR"},
74 {"mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand"},
75 {"nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants."},
76
77 /* Information logging options: */
78 {"info", DBG(INFO), "Print driver information"},
79 {"tex", DBG(TEX), "Print texture info"},
80 {"compute", DBG(COMPUTE), "Print compute info"},
81 {"vm", DBG(VM), "Print virtual addresses when creating resources"},
82 {"cache_stats", DBG(CACHE_STATS), "Print shader cache statistics."},
83
84 /* Driver options: */
85 {"forcedma", DBG(FORCE_SDMA), "Use SDMA for all operations when possible."},
86 {"nodma", DBG(NO_SDMA), "Disable SDMA"},
87 {"nodmaclear", DBG(NO_SDMA_CLEARS), "Disable SDMA clears"},
88 {"nodmacopyimage", DBG(NO_SDMA_COPY_IMAGE), "Disable SDMA image copies"},
89 {"nowc", DBG(NO_WC), "Disable GTT write combining"},
90 {"check_vm", DBG(CHECK_VM), "Check VM faults and dump debug info."},
91 {"reserve_vmid", DBG(RESERVE_VMID), "Force VMID reservation per context."},
92 {"zerovram", DBG(ZERO_VRAM), "Clear VRAM allocations."},
93
94 /* 3D engine options: */
95 {"nogfx", DBG(NO_GFX), "Disable graphics. Only multimedia compute paths can be used."},
96 {"nongg", DBG(NO_NGG), "Disable NGG and use the legacy pipeline."},
97 {"nggc", DBG(ALWAYS_NGG_CULLING), "Always use NGG culling even when it can hurt."},
98 {"nonggc", DBG(NO_NGG_CULLING), "Disable NGG culling."},
99 {"alwayspd", DBG(ALWAYS_PD), "Always enable the primitive discard compute shader."},
100 {"pd", DBG(PD), "Enable the primitive discard compute shader for large draw calls."},
101 {"nopd", DBG(NO_PD), "Disable the primitive discard compute shader."},
102 {"switch_on_eop", DBG(SWITCH_ON_EOP), "Program WD/IA to switch on end-of-packet."},
103 {"nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order rasterization"},
104 {"nodpbb", DBG(NO_DPBB), "Disable DPBB."},
105 {"nodfsm", DBG(NO_DFSM), "Disable DFSM."},
106 {"dpbb", DBG(DPBB), "Enable DPBB."},
107 {"dfsm", DBG(DFSM), "Enable DFSM."},
108 {"nohyperz", DBG(NO_HYPERZ), "Disable Hyper-Z"},
109 {"norbplus", DBG(NO_RB_PLUS), "Disable RB+."},
110 {"no2d", DBG(NO_2D_TILING), "Disable 2D tiling"},
111 {"notiling", DBG(NO_TILING), "Disable tiling"},
112 {"nodcc", DBG(NO_DCC), "Disable DCC."},
113 {"nodccclear", DBG(NO_DCC_CLEAR), "Disable DCC fast clear."},
114 {"nodccfb", DBG(NO_DCC_FB), "Disable separate DCC on the main framebuffer"},
115 {"nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA"},
116 {"nofmask", DBG(NO_FMASK), "Disable MSAA compression"},
117
118 DEBUG_NAMED_VALUE_END /* must be last */
119 };
120
121 static const struct debug_named_value test_options[] = {
122 /* Tests: */
123 {"testdma", DBG(TEST_DMA), "Invoke SDMA tests and exit."},
124 {"testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and exit."},
125 {"testvmfaultsdma", DBG(TEST_VMFAULT_SDMA), "Invoke a SDMA VM fault test and exit."},
126 {"testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM fault test and exit."},
127 {"testdmaperf", DBG(TEST_DMA_PERF), "Test DMA performance"},
128 {"testgds", DBG(TEST_GDS), "Test GDS."},
129 {"testgdsmm", DBG(TEST_GDS_MM), "Test GDS memory management."},
130 {"testgdsoamm", DBG(TEST_GDS_OA_MM), "Test GDS OA memory management."},
131
132 DEBUG_NAMED_VALUE_END /* must be last */
133 };
134
135 void si_init_compiler(struct si_screen *sscreen, struct ac_llvm_compiler *compiler)
136 {
137 /* Only create the less-optimizing version of the compiler on APUs
138 * predating Ryzen (Raven). */
139 bool create_low_opt_compiler =
140 !sscreen->info.has_dedicated_vram && sscreen->info.chip_class <= GFX8;
141
142 enum ac_target_machine_options tm_options =
143 (sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL : 0) |
144 (sscreen->info.chip_class <= GFX8 ? AC_TM_FORCE_DISABLE_XNACK :
145 sscreen->info.chip_class <= GFX10 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
146 (!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0) |
147 (sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0) |
148 (create_low_opt_compiler ? AC_TM_CREATE_LOW_OPT : 0);
149
150 ac_init_llvm_once();
151 ac_init_llvm_compiler(compiler, sscreen->info.family, tm_options);
152 compiler->passes = ac_create_llvm_passes(compiler->tm);
153
154 if (compiler->tm_wave32)
155 compiler->passes_wave32 = ac_create_llvm_passes(compiler->tm_wave32);
156 if (compiler->low_opt_tm)
157 compiler->low_opt_passes = ac_create_llvm_passes(compiler->low_opt_tm);
158 }
159
160 static void si_destroy_compiler(struct ac_llvm_compiler *compiler)
161 {
162 ac_destroy_llvm_compiler(compiler);
163 }
164
165 /*
166 * pipe_context
167 */
168 static void si_destroy_context(struct pipe_context *context)
169 {
170 struct si_context *sctx = (struct si_context *)context;
171 int i;
172
173 /* Unreference the framebuffer normally to disable related logic
174 * properly.
175 */
176 struct pipe_framebuffer_state fb = {};
177 if (context->set_framebuffer_state)
178 context->set_framebuffer_state(context, &fb);
179
180 si_release_all_descriptors(sctx);
181
182 if (sctx->chip_class >= GFX10 && sctx->has_graphics)
183 gfx10_destroy_query(sctx);
184
185 pipe_resource_reference(&sctx->esgs_ring, NULL);
186 pipe_resource_reference(&sctx->gsvs_ring, NULL);
187 pipe_resource_reference(&sctx->tess_rings, NULL);
188 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
189 pipe_resource_reference(&sctx->sample_pos_buffer, NULL);
190 si_resource_reference(&sctx->border_color_buffer, NULL);
191 free(sctx->border_color_table);
192 si_resource_reference(&sctx->scratch_buffer, NULL);
193 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
194 si_resource_reference(&sctx->wait_mem_scratch, NULL);
195 si_resource_reference(&sctx->small_prim_cull_info_buf, NULL);
196
197 si_pm4_free_state(sctx, sctx->cs_preamble_state, ~0);
198 if (sctx->cs_preamble_gs_rings)
199 si_pm4_free_state(sctx, sctx->cs_preamble_gs_rings, ~0);
200 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
201 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
202
203 if (sctx->fixed_func_tcs_shader.cso)
204 sctx->b.delete_tcs_state(&sctx->b, sctx->fixed_func_tcs_shader.cso);
205 if (sctx->custom_dsa_flush)
206 sctx->b.delete_depth_stencil_alpha_state(&sctx->b, sctx->custom_dsa_flush);
207 if (sctx->custom_blend_resolve)
208 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_resolve);
209 if (sctx->custom_blend_fmask_decompress)
210 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_fmask_decompress);
211 if (sctx->custom_blend_eliminate_fastclear)
212 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_eliminate_fastclear);
213 if (sctx->custom_blend_dcc_decompress)
214 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_dcc_decompress);
215 if (sctx->vs_blit_pos)
216 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos);
217 if (sctx->vs_blit_pos_layered)
218 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos_layered);
219 if (sctx->vs_blit_color)
220 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color);
221 if (sctx->vs_blit_color_layered)
222 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color_layered);
223 if (sctx->vs_blit_texcoord)
224 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_texcoord);
225 if (sctx->cs_clear_buffer)
226 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_buffer);
227 if (sctx->cs_copy_buffer)
228 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_buffer);
229 if (sctx->cs_copy_image)
230 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image);
231 if (sctx->cs_copy_image_1d_array)
232 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image_1d_array);
233 if (sctx->cs_clear_render_target)
234 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target);
235 if (sctx->cs_clear_render_target_1d_array)
236 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target_1d_array);
237 if (sctx->cs_clear_12bytes_buffer)
238 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_12bytes_buffer);
239 if (sctx->cs_dcc_decompress)
240 sctx->b.delete_compute_state(&sctx->b, sctx->cs_dcc_decompress);
241 if (sctx->cs_dcc_retile)
242 sctx->b.delete_compute_state(&sctx->b, sctx->cs_dcc_retile);
243
244 for (unsigned i = 0; i < ARRAY_SIZE(sctx->cs_fmask_expand); i++) {
245 for (unsigned j = 0; j < ARRAY_SIZE(sctx->cs_fmask_expand[i]); j++) {
246 if (sctx->cs_fmask_expand[i][j]) {
247 sctx->b.delete_compute_state(&sctx->b, sctx->cs_fmask_expand[i][j]);
248 }
249 }
250 }
251
252 if (sctx->blitter)
253 util_blitter_destroy(sctx->blitter);
254
255 /* Release DCC stats. */
256 for (int i = 0; i < ARRAY_SIZE(sctx->dcc_stats); i++) {
257 assert(!sctx->dcc_stats[i].query_active);
258
259 for (int j = 0; j < ARRAY_SIZE(sctx->dcc_stats[i].ps_stats); j++)
260 if (sctx->dcc_stats[i].ps_stats[j])
261 sctx->b.destroy_query(&sctx->b, sctx->dcc_stats[i].ps_stats[j]);
262
263 si_texture_reference(&sctx->dcc_stats[i].tex, NULL);
264 }
265
266 if (sctx->query_result_shader)
267 sctx->b.delete_compute_state(&sctx->b, sctx->query_result_shader);
268 if (sctx->sh_query_result_shader)
269 sctx->b.delete_compute_state(&sctx->b, sctx->sh_query_result_shader);
270
271 if (sctx->gfx_cs)
272 sctx->ws->cs_destroy(sctx->gfx_cs);
273 if (sctx->sdma_cs)
274 sctx->ws->cs_destroy(sctx->sdma_cs);
275 if (sctx->ctx)
276 sctx->ws->ctx_destroy(sctx->ctx);
277
278 if (sctx->b.stream_uploader)
279 u_upload_destroy(sctx->b.stream_uploader);
280 if (sctx->b.const_uploader)
281 u_upload_destroy(sctx->b.const_uploader);
282 if (sctx->cached_gtt_allocator)
283 u_upload_destroy(sctx->cached_gtt_allocator);
284
285 slab_destroy_child(&sctx->pool_transfers);
286 slab_destroy_child(&sctx->pool_transfers_unsync);
287
288 if (sctx->allocator_zeroed_memory)
289 u_suballocator_destroy(sctx->allocator_zeroed_memory);
290
291 sctx->ws->fence_reference(&sctx->last_gfx_fence, NULL);
292 sctx->ws->fence_reference(&sctx->last_sdma_fence, NULL);
293 sctx->ws->fence_reference(&sctx->last_ib_barrier_fence, NULL);
294 si_resource_reference(&sctx->eop_bug_scratch, NULL);
295 si_resource_reference(&sctx->index_ring, NULL);
296 si_resource_reference(&sctx->barrier_buf, NULL);
297 si_resource_reference(&sctx->last_ib_barrier_buf, NULL);
298 pb_reference(&sctx->gds, NULL);
299 pb_reference(&sctx->gds_oa, NULL);
300
301 si_destroy_compiler(&sctx->compiler);
302
303 si_saved_cs_reference(&sctx->current_saved_cs, NULL);
304
305 _mesa_hash_table_destroy(sctx->tex_handles, NULL);
306 _mesa_hash_table_destroy(sctx->img_handles, NULL);
307
308 util_dynarray_fini(&sctx->resident_tex_handles);
309 util_dynarray_fini(&sctx->resident_img_handles);
310 util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
311 util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
312 util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
313 si_unref_sdma_uploads(sctx);
314 free(sctx->sdma_uploads);
315 FREE(sctx);
316 }
317
318 static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx)
319 {
320 struct si_context *sctx = (struct si_context *)ctx;
321 struct si_screen *sscreen = sctx->screen;
322 enum pipe_reset_status status = sctx->ws->ctx_query_reset_status(sctx->ctx);
323
324 if (status != PIPE_NO_RESET) {
325 /* Call the gallium frontend to set a no-op API dispatch. */
326 if (sctx->device_reset_callback.reset) {
327 sctx->device_reset_callback.reset(sctx->device_reset_callback.data, status);
328 }
329
330 /* Re-create the auxiliary context, because it won't submit
331 * any new IBs due to a GPU reset.
332 */
333 simple_mtx_lock(&sscreen->aux_context_lock);
334
335 struct u_log_context *aux_log = ((struct si_context *)sscreen->aux_context)->log;
336 sscreen->aux_context->set_log_context(sscreen->aux_context, NULL);
337 sscreen->aux_context->destroy(sscreen->aux_context);
338
339 sscreen->aux_context = si_create_context(
340 &sscreen->b, (sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) |
341 (sscreen->info.has_graphics ? 0 : PIPE_CONTEXT_COMPUTE_ONLY));
342 sscreen->aux_context->set_log_context(sscreen->aux_context, aux_log);
343 simple_mtx_unlock(&sscreen->aux_context_lock);
344 }
345 return status;
346 }
347
348 static void si_set_device_reset_callback(struct pipe_context *ctx,
349 const struct pipe_device_reset_callback *cb)
350 {
351 struct si_context *sctx = (struct si_context *)ctx;
352
353 if (cb)
354 sctx->device_reset_callback = *cb;
355 else
356 memset(&sctx->device_reset_callback, 0, sizeof(sctx->device_reset_callback));
357 }
358
359 /* Apitrace profiling:
360 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
361 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
362 * and remember its number.
363 * 3) In Mesa, enable queries and performance counters around that draw
364 * call and print the results.
365 * 4) glretrace --benchmark --markers ..
366 */
367 static void si_emit_string_marker(struct pipe_context *ctx, const char *string, int len)
368 {
369 struct si_context *sctx = (struct si_context *)ctx;
370
371 dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
372
373 if (sctx->log)
374 u_log_printf(sctx->log, "\nString marker: %*s\n", len, string);
375 }
376
377 static void si_set_debug_callback(struct pipe_context *ctx, const struct pipe_debug_callback *cb)
378 {
379 struct si_context *sctx = (struct si_context *)ctx;
380 struct si_screen *screen = sctx->screen;
381
382 util_queue_finish(&screen->shader_compiler_queue);
383 util_queue_finish(&screen->shader_compiler_queue_low_priority);
384
385 if (cb)
386 sctx->debug = *cb;
387 else
388 memset(&sctx->debug, 0, sizeof(sctx->debug));
389 }
390
391 static void si_set_log_context(struct pipe_context *ctx, struct u_log_context *log)
392 {
393 struct si_context *sctx = (struct si_context *)ctx;
394 sctx->log = log;
395
396 if (log)
397 u_log_add_auto_logger(log, si_auto_log_cs, sctx);
398 }
399
400 static void si_set_context_param(struct pipe_context *ctx, enum pipe_context_param param,
401 unsigned value)
402 {
403 struct radeon_winsys *ws = ((struct si_context *)ctx)->ws;
404
405 switch (param) {
406 case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE:
407 ws->pin_threads_to_L3_cache(ws, value);
408 break;
409 default:;
410 }
411 }
412
413 static struct pipe_context *si_create_context(struct pipe_screen *screen, unsigned flags)
414 {
415 struct si_screen *sscreen = (struct si_screen *)screen;
416 STATIC_ASSERT(DBG_COUNT <= 64);
417
418 /* Don't create a context if it's not compute-only and hw is compute-only. */
419 if (!sscreen->info.has_graphics && !(flags & PIPE_CONTEXT_COMPUTE_ONLY))
420 return NULL;
421
422 struct si_context *sctx = CALLOC_STRUCT(si_context);
423 struct radeon_winsys *ws = sscreen->ws;
424 int shader, i;
425 bool stop_exec_on_failure = (flags & PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET) != 0;
426
427 if (!sctx)
428 return NULL;
429
430 sctx->has_graphics = sscreen->info.chip_class == GFX6 || !(flags & PIPE_CONTEXT_COMPUTE_ONLY);
431
432 if (flags & PIPE_CONTEXT_DEBUG)
433 sscreen->record_llvm_ir = true; /* racy but not critical */
434
435 sctx->b.screen = screen; /* this must be set first */
436 sctx->b.priv = NULL;
437 sctx->b.destroy = si_destroy_context;
438 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
439 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
440
441 slab_create_child(&sctx->pool_transfers, &sscreen->pool_transfers);
442 slab_create_child(&sctx->pool_transfers_unsync, &sscreen->pool_transfers);
443
444 sctx->ws = sscreen->ws;
445 sctx->family = sscreen->info.family;
446 sctx->chip_class = sscreen->info.chip_class;
447
448 if (sctx->chip_class == GFX7 || sctx->chip_class == GFX8 || sctx->chip_class == GFX9) {
449 sctx->eop_bug_scratch = si_resource(pipe_buffer_create(
450 &sscreen->b, 0, PIPE_USAGE_DEFAULT, 16 * sscreen->info.num_render_backends));
451 if (!sctx->eop_bug_scratch)
452 goto fail;
453 }
454
455 /* Initialize context allocators. */
456 sctx->allocator_zeroed_memory =
457 u_suballocator_create(&sctx->b, 128 * 1024, 0, PIPE_USAGE_DEFAULT,
458 SI_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_CLEAR, false);
459 if (!sctx->allocator_zeroed_memory)
460 goto fail;
461
462 sctx->b.stream_uploader =
463 u_upload_create(&sctx->b, 1024 * 1024, 0, PIPE_USAGE_STREAM, SI_RESOURCE_FLAG_READ_ONLY);
464 if (!sctx->b.stream_uploader)
465 goto fail;
466
467 sctx->cached_gtt_allocator = u_upload_create(&sctx->b, 16 * 1024, 0, PIPE_USAGE_STAGING, 0);
468 if (!sctx->cached_gtt_allocator)
469 goto fail;
470
471 sctx->ctx = sctx->ws->ctx_create(sctx->ws);
472 if (!sctx->ctx)
473 goto fail;
474
475 if (sscreen->info.num_rings[RING_DMA] && !(sscreen->debug_flags & DBG(NO_SDMA)) &&
476 /* SDMA causes corruption on RX 580:
477 * https://gitlab.freedesktop.org/mesa/mesa/-/issues/1399
478 * https://gitlab.freedesktop.org/mesa/mesa/-/issues/1889
479 */
480 (sctx->chip_class != GFX8 || sscreen->debug_flags & DBG(FORCE_SDMA)) &&
481 /* SDMA timeouts sometimes on gfx10 so disable it for now. See:
482 * https://bugs.freedesktop.org/show_bug.cgi?id=111481
483 * https://gitlab.freedesktop.org/mesa/mesa/-/issues/1907
484 */
485 (sctx->chip_class != GFX10 || sscreen->debug_flags & DBG(FORCE_SDMA))) {
486 sctx->sdma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA, (void *)si_flush_dma_cs, sctx,
487 stop_exec_on_failure);
488 }
489
490 bool use_sdma_upload = sscreen->info.has_dedicated_vram && sctx->sdma_cs;
491 sctx->b.const_uploader =
492 u_upload_create(&sctx->b, 256 * 1024, 0, PIPE_USAGE_DEFAULT,
493 SI_RESOURCE_FLAG_32BIT |
494 (use_sdma_upload ? SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA : 0));
495 if (!sctx->b.const_uploader)
496 goto fail;
497
498 if (use_sdma_upload)
499 u_upload_enable_flush_explicit(sctx->b.const_uploader);
500
501 sctx->gfx_cs = ws->cs_create(sctx->ctx, sctx->has_graphics ? RING_GFX : RING_COMPUTE,
502 (void *)si_flush_gfx_cs, sctx, stop_exec_on_failure);
503
504 /* Border colors. */
505 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS * sizeof(*sctx->border_color_table));
506 if (!sctx->border_color_table)
507 goto fail;
508
509 sctx->border_color_buffer = si_resource(pipe_buffer_create(
510 screen, 0, PIPE_USAGE_DEFAULT, SI_MAX_BORDER_COLORS * sizeof(*sctx->border_color_table)));
511 if (!sctx->border_color_buffer)
512 goto fail;
513
514 sctx->border_color_map =
515 ws->buffer_map(sctx->border_color_buffer->buf, NULL, PIPE_TRANSFER_WRITE);
516 if (!sctx->border_color_map)
517 goto fail;
518
519 sctx->ngg = sscreen->use_ngg;
520
521 /* Initialize context functions used by graphics and compute. */
522 if (sctx->chip_class >= GFX10)
523 sctx->emit_cache_flush = gfx10_emit_cache_flush;
524 else
525 sctx->emit_cache_flush = si_emit_cache_flush;
526
527 sctx->b.emit_string_marker = si_emit_string_marker;
528 sctx->b.set_debug_callback = si_set_debug_callback;
529 sctx->b.set_log_context = si_set_log_context;
530 sctx->b.set_context_param = si_set_context_param;
531 sctx->b.get_device_reset_status = si_get_reset_status;
532 sctx->b.set_device_reset_callback = si_set_device_reset_callback;
533
534 si_init_all_descriptors(sctx);
535 si_init_buffer_functions(sctx);
536 si_init_clear_functions(sctx);
537 si_init_blit_functions(sctx);
538 si_init_compute_functions(sctx);
539 si_init_compute_blit_functions(sctx);
540 si_init_debug_functions(sctx);
541 si_init_fence_functions(sctx);
542 si_init_query_functions(sctx);
543 si_init_state_compute_functions(sctx);
544 si_init_context_texture_functions(sctx);
545
546 /* Initialize graphics-only context functions. */
547 if (sctx->has_graphics) {
548 if (sctx->chip_class >= GFX10)
549 gfx10_init_query(sctx);
550 si_init_msaa_functions(sctx);
551 si_init_shader_functions(sctx);
552 si_init_state_functions(sctx);
553 si_init_cs_preamble_state(sctx);
554 si_init_streamout_functions(sctx);
555 si_init_viewport_functions(sctx);
556
557 sctx->blitter = util_blitter_create(&sctx->b);
558 if (sctx->blitter == NULL)
559 goto fail;
560 sctx->blitter->skip_viewport_restore = true;
561
562 /* Some states are expected to be always non-NULL. */
563 sctx->noop_blend = util_blitter_get_noop_blend_state(sctx->blitter);
564 sctx->queued.named.blend = sctx->noop_blend;
565
566 sctx->noop_dsa = util_blitter_get_noop_dsa_state(sctx->blitter);
567 sctx->queued.named.dsa = sctx->noop_dsa;
568
569 sctx->discard_rasterizer_state = util_blitter_get_discard_rasterizer_state(sctx->blitter);
570 sctx->queued.named.rasterizer = sctx->discard_rasterizer_state;
571
572 si_init_draw_functions(sctx);
573
574 /* If aux_context == NULL, we are initializing aux_context right now. */
575 bool is_aux_context = !sscreen->aux_context;
576 si_initialize_prim_discard_tunables(sscreen, is_aux_context,
577 &sctx->prim_discard_vertex_count_threshold,
578 &sctx->index_ring_size_per_ib);
579 }
580
581 /* Initialize SDMA functions. */
582 if (sctx->chip_class >= GFX7)
583 cik_init_sdma_functions(sctx);
584 else
585 sctx->dma_copy = si_resource_copy_region;
586
587 if (sscreen->debug_flags & DBG(FORCE_SDMA))
588 sctx->b.resource_copy_region = sctx->dma_copy;
589
590 sctx->sample_mask = 0xffff;
591
592 /* Initialize multimedia functions. */
593 if (sscreen->info.has_hw_decode) {
594 sctx->b.create_video_codec = si_uvd_create_decoder;
595 sctx->b.create_video_buffer = si_video_buffer_create;
596 } else {
597 sctx->b.create_video_codec = vl_create_decoder;
598 sctx->b.create_video_buffer = vl_video_buffer_create;
599 }
600
601 if (sctx->chip_class >= GFX9 || si_compute_prim_discard_enabled(sctx)) {
602 sctx->wait_mem_scratch = si_resource(pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 8));
603 if (!sctx->wait_mem_scratch)
604 goto fail;
605
606 /* Initialize the memory. */
607 si_cp_write_data(sctx, sctx->wait_mem_scratch, 0, 4, V_370_MEM, V_370_ME,
608 &sctx->wait_mem_number);
609 }
610
611 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
612 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
613 if (sctx->chip_class == GFX7) {
614 sctx->null_const_buf.buffer =
615 pipe_aligned_buffer_create(screen, SI_RESOURCE_FLAG_32BIT, PIPE_USAGE_DEFAULT, 16,
616 sctx->screen->info.tcc_cache_line_size);
617 if (!sctx->null_const_buf.buffer)
618 goto fail;
619 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
620
621 unsigned start_shader = sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE;
622 for (shader = start_shader; shader < SI_NUM_SHADERS; shader++) {
623 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
624 sctx->b.set_constant_buffer(&sctx->b, shader, i, &sctx->null_const_buf);
625 }
626 }
627
628 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &sctx->null_const_buf);
629 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &sctx->null_const_buf);
630 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &sctx->null_const_buf);
631 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE, &sctx->null_const_buf);
632 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &sctx->null_const_buf);
633 }
634
635 uint64_t max_threads_per_block;
636 screen->get_compute_param(screen, PIPE_SHADER_IR_NIR, PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
637 &max_threads_per_block);
638
639 /* The maximum number of scratch waves. Scratch space isn't divided
640 * evenly between CUs. The number is only a function of the number of CUs.
641 * We can decrease the constant to decrease the scratch buffer size.
642 *
643 * sctx->scratch_waves must be >= the maximum posible size of
644 * 1 threadgroup, so that the hw doesn't hang from being unable
645 * to start any.
646 *
647 * The recommended value is 4 per CU at most. Higher numbers don't
648 * bring much benefit, but they still occupy chip resources (think
649 * async compute). I've seen ~2% performance difference between 4 and 32.
650 */
651 sctx->scratch_waves =
652 MAX2(32 * sscreen->info.num_good_compute_units, max_threads_per_block / 64);
653
654 /* Bindless handles. */
655 sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer, _mesa_key_pointer_equal);
656 sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer, _mesa_key_pointer_equal);
657
658 util_dynarray_init(&sctx->resident_tex_handles, NULL);
659 util_dynarray_init(&sctx->resident_img_handles, NULL);
660 util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
661 util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
662 util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
663
664 sctx->sample_pos_buffer =
665 pipe_buffer_create(sctx->b.screen, 0, PIPE_USAGE_DEFAULT, sizeof(sctx->sample_positions));
666 pipe_buffer_write(&sctx->b, sctx->sample_pos_buffer, 0, sizeof(sctx->sample_positions),
667 &sctx->sample_positions);
668
669 /* this must be last */
670 si_begin_new_gfx_cs(sctx);
671
672 if (sctx->chip_class == GFX7) {
673 /* Clear the NULL constant buffer, because loads should return zeros.
674 * Note that this forces CP DMA to be used, because clover deadlocks
675 * for some reason when the compute codepath is used.
676 */
677 uint32_t clear_value = 0;
678 si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0, sctx->null_const_buf.buffer->width0,
679 &clear_value, 4, SI_COHERENCY_SHADER, true);
680 }
681 return &sctx->b;
682 fail:
683 fprintf(stderr, "radeonsi: Failed to create a context.\n");
684 si_destroy_context(&sctx->b);
685 return NULL;
686 }
687
688 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen, void *priv,
689 unsigned flags)
690 {
691 struct si_screen *sscreen = (struct si_screen *)screen;
692 struct pipe_context *ctx;
693 uint64_t total_ram;
694
695 if (sscreen->debug_flags & DBG(CHECK_VM))
696 flags |= PIPE_CONTEXT_DEBUG;
697
698 ctx = si_create_context(screen, flags);
699
700 if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
701 return ctx;
702
703 /* Clover (compute-only) is unsupported. */
704 if (flags & PIPE_CONTEXT_COMPUTE_ONLY)
705 return ctx;
706
707 /* When shaders are logged to stderr, asynchronous compilation is
708 * disabled too. */
709 if (sscreen->debug_flags & DBG_ALL_SHADERS)
710 return ctx;
711
712 /* Use asynchronous flushes only on amdgpu, since the radeon
713 * implementation for fence_server_sync is incomplete. */
714 struct pipe_context * tc = threaded_context_create(
715 ctx, &sscreen->pool_transfers, si_replace_buffer_storage,
716 sscreen->info.is_amdgpu ? si_create_fence : NULL,
717 &((struct si_context *)ctx)->tc);
718
719 if (tc && tc != ctx && os_get_total_physical_memory(&total_ram)) {
720 ((struct threaded_context *) tc)->bytes_mapped_limit = total_ram / 4;
721 }
722
723 return tc;
724 }
725
726 /*
727 * pipe_screen
728 */
729 static void si_destroy_screen(struct pipe_screen *pscreen)
730 {
731 struct si_screen *sscreen = (struct si_screen *)pscreen;
732 struct si_shader_part *parts[] = {sscreen->vs_prologs, sscreen->tcs_epilogs, sscreen->gs_prologs,
733 sscreen->ps_prologs, sscreen->ps_epilogs};
734 unsigned i;
735
736 if (!sscreen->ws->unref(sscreen->ws))
737 return;
738
739 if (sscreen->debug_flags & DBG(CACHE_STATS)) {
740 printf("live shader cache: hits = %u, misses = %u\n", sscreen->live_shader_cache.hits,
741 sscreen->live_shader_cache.misses);
742 printf("memory shader cache: hits = %u, misses = %u\n", sscreen->num_memory_shader_cache_hits,
743 sscreen->num_memory_shader_cache_misses);
744 printf("disk shader cache: hits = %u, misses = %u\n", sscreen->num_disk_shader_cache_hits,
745 sscreen->num_disk_shader_cache_misses);
746 }
747
748 simple_mtx_destroy(&sscreen->aux_context_lock);
749
750 struct u_log_context *aux_log = ((struct si_context *)sscreen->aux_context)->log;
751 if (aux_log) {
752 sscreen->aux_context->set_log_context(sscreen->aux_context, NULL);
753 u_log_context_destroy(aux_log);
754 FREE(aux_log);
755 }
756
757 sscreen->aux_context->destroy(sscreen->aux_context);
758
759 util_queue_destroy(&sscreen->shader_compiler_queue);
760 util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
761
762 /* Release the reference on glsl types of the compiler threads. */
763 glsl_type_singleton_decref();
764
765 for (i = 0; i < ARRAY_SIZE(sscreen->compiler); i++)
766 si_destroy_compiler(&sscreen->compiler[i]);
767
768 for (i = 0; i < ARRAY_SIZE(sscreen->compiler_lowp); i++)
769 si_destroy_compiler(&sscreen->compiler_lowp[i]);
770
771 /* Free shader parts. */
772 for (i = 0; i < ARRAY_SIZE(parts); i++) {
773 while (parts[i]) {
774 struct si_shader_part *part = parts[i];
775
776 parts[i] = part->next;
777 si_shader_binary_clean(&part->binary);
778 FREE(part);
779 }
780 }
781 simple_mtx_destroy(&sscreen->shader_parts_mutex);
782 si_destroy_shader_cache(sscreen);
783
784 si_destroy_perfcounters(sscreen);
785 si_gpu_load_kill_thread(sscreen);
786
787 simple_mtx_destroy(&sscreen->gpu_load_mutex);
788
789 slab_destroy_parent(&sscreen->pool_transfers);
790
791 disk_cache_destroy(sscreen->disk_shader_cache);
792 util_live_shader_cache_deinit(&sscreen->live_shader_cache);
793 sscreen->ws->destroy(sscreen->ws);
794 FREE(sscreen);
795 }
796
797 static void si_init_gs_info(struct si_screen *sscreen)
798 {
799 sscreen->gs_table_depth = ac_get_gs_table_depth(sscreen->info.chip_class, sscreen->info.family);
800 }
801
802 static void si_test_vmfault(struct si_screen *sscreen, uint64_t test_flags)
803 {
804 struct pipe_context *ctx = sscreen->aux_context;
805 struct si_context *sctx = (struct si_context *)ctx;
806 struct pipe_resource *buf = pipe_buffer_create_const0(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 64);
807
808 if (!buf) {
809 puts("Buffer allocation failed.");
810 exit(1);
811 }
812
813 si_resource(buf)->gpu_address = 0; /* cause a VM fault */
814
815 if (test_flags & DBG(TEST_VMFAULT_CP)) {
816 si_cp_dma_copy_buffer(sctx, buf, buf, 0, 4, 4, 0, SI_COHERENCY_NONE, L2_BYPASS);
817 ctx->flush(ctx, NULL, 0);
818 puts("VM fault test: CP - done.");
819 }
820 if (test_flags & DBG(TEST_VMFAULT_SDMA)) {
821 si_sdma_clear_buffer(sctx, buf, 0, 4, 0);
822 ctx->flush(ctx, NULL, 0);
823 puts("VM fault test: SDMA - done.");
824 }
825 if (test_flags & DBG(TEST_VMFAULT_SHADER)) {
826 util_test_constant_buffer(ctx, buf);
827 puts("VM fault test: Shader - done.");
828 }
829 exit(0);
830 }
831
832 static void si_test_gds_memory_management(struct si_context *sctx, unsigned alloc_size,
833 unsigned alignment, enum radeon_bo_domain domain)
834 {
835 struct radeon_winsys *ws = sctx->ws;
836 struct radeon_cmdbuf *cs[8];
837 struct pb_buffer *gds_bo[ARRAY_SIZE(cs)];
838
839 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
840 cs[i] = ws->cs_create(sctx->ctx, RING_COMPUTE, NULL, NULL, false);
841 gds_bo[i] = ws->buffer_create(ws, alloc_size, alignment, domain, 0);
842 assert(gds_bo[i]);
843 }
844
845 for (unsigned iterations = 0; iterations < 20000; iterations++) {
846 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
847 /* This clears GDS with CP DMA.
848 *
849 * We don't care if GDS is present. Just add some packet
850 * to make the GPU busy for a moment.
851 */
852 si_cp_dma_clear_buffer(
853 sctx, cs[i], NULL, 0, alloc_size, 0,
854 SI_CPDMA_SKIP_BO_LIST_UPDATE | SI_CPDMA_SKIP_CHECK_CS_SPACE | SI_CPDMA_SKIP_GFX_SYNC, 0,
855 0);
856
857 ws->cs_add_buffer(cs[i], gds_bo[i], RADEON_USAGE_READWRITE, domain, 0);
858 ws->cs_flush(cs[i], PIPE_FLUSH_ASYNC, NULL);
859 }
860 }
861 exit(0);
862 }
863
864 static void si_disk_cache_create(struct si_screen *sscreen)
865 {
866 /* Don't use the cache if shader dumping is enabled. */
867 if (sscreen->debug_flags & DBG_ALL_SHADERS)
868 return;
869
870 struct mesa_sha1 ctx;
871 unsigned char sha1[20];
872 char cache_id[20 * 2 + 1];
873
874 _mesa_sha1_init(&ctx);
875
876 if (!disk_cache_get_function_identifier(si_disk_cache_create, &ctx) ||
877 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
878 return;
879
880 _mesa_sha1_final(&ctx, sha1);
881 disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
882
883 /* These flags affect shader compilation. */
884 #define ALL_FLAGS (DBG(GISEL) | DBG(KILL_PS_INF_INTERP))
885 uint64_t shader_debug_flags = sscreen->debug_flags & ALL_FLAGS;
886
887 /* Add the high bits of 32-bit addresses, which affects
888 * how 32-bit addresses are expanded to 64 bits.
889 */
890 STATIC_ASSERT(ALL_FLAGS <= UINT_MAX);
891 assert((int16_t)sscreen->info.address32_hi == (int32_t)sscreen->info.address32_hi);
892 shader_debug_flags |= (uint64_t)(sscreen->info.address32_hi & 0xffff) << 32;
893
894 sscreen->disk_shader_cache = disk_cache_create(sscreen->info.name, cache_id, shader_debug_flags);
895 }
896
897 static void si_set_max_shader_compiler_threads(struct pipe_screen *screen, unsigned max_threads)
898 {
899 struct si_screen *sscreen = (struct si_screen *)screen;
900
901 /* This function doesn't allow a greater number of threads than
902 * the queue had at its creation. */
903 util_queue_adjust_num_threads(&sscreen->shader_compiler_queue, max_threads);
904 /* Don't change the number of threads on the low priority queue. */
905 }
906
907 static bool si_is_parallel_shader_compilation_finished(struct pipe_screen *screen, void *shader,
908 enum pipe_shader_type shader_type)
909 {
910 struct si_shader_selector *sel = (struct si_shader_selector *)shader;
911
912 return util_queue_fence_is_signalled(&sel->ready);
913 }
914
915 static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws,
916 const struct pipe_screen_config *config)
917 {
918 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
919 unsigned hw_threads, num_comp_hi_threads, num_comp_lo_threads;
920 uint64_t test_flags;
921
922 if (!sscreen) {
923 return NULL;
924 }
925
926 sscreen->ws = ws;
927 ws->query_info(ws, &sscreen->info);
928
929 if (sscreen->info.chip_class == GFX10_3 && LLVM_VERSION_MAJOR < 11) {
930 fprintf(stderr, "radeonsi: GFX 10.3 requires LLVM 11 or higher\n");
931 FREE(sscreen);
932 return NULL;
933 }
934
935 if (sscreen->info.chip_class == GFX10 && LLVM_VERSION_MAJOR < 9) {
936 fprintf(stderr, "radeonsi: Navi family support requires LLVM 9 or higher\n");
937 FREE(sscreen);
938 return NULL;
939 }
940
941 if (sscreen->info.chip_class >= GFX9) {
942 sscreen->se_tile_repeat = 32 * sscreen->info.max_se;
943 } else {
944 ac_get_raster_config(&sscreen->info, &sscreen->pa_sc_raster_config,
945 &sscreen->pa_sc_raster_config_1, &sscreen->se_tile_repeat);
946 }
947
948 sscreen->debug_flags = debug_get_flags_option("R600_DEBUG", debug_options, 0);
949 sscreen->debug_flags |= debug_get_flags_option("AMD_DEBUG", debug_options, 0);
950 test_flags = debug_get_flags_option("AMD_TEST", test_options, 0);
951
952 if (sscreen->debug_flags & DBG(NO_GFX))
953 sscreen->info.has_graphics = false;
954
955 /* Set functions first. */
956 sscreen->b.context_create = si_pipe_create_context;
957 sscreen->b.destroy = si_destroy_screen;
958 sscreen->b.set_max_shader_compiler_threads = si_set_max_shader_compiler_threads;
959 sscreen->b.is_parallel_shader_compilation_finished = si_is_parallel_shader_compilation_finished;
960 sscreen->b.finalize_nir = si_finalize_nir;
961
962 si_init_screen_get_functions(sscreen);
963 si_init_screen_buffer_functions(sscreen);
964 si_init_screen_fence_functions(sscreen);
965 si_init_screen_state_functions(sscreen);
966 si_init_screen_texture_functions(sscreen);
967 si_init_screen_query_functions(sscreen);
968 si_init_screen_live_shader_cache(sscreen);
969
970 /* Set these flags in debug_flags early, so that the shader cache takes
971 * them into account.
972 */
973 if (driQueryOptionb(config->options, "glsl_correct_derivatives_after_discard"))
974 sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
975
976 if (sscreen->debug_flags & DBG(INFO))
977 ac_print_gpu_info(&sscreen->info);
978
979 slab_create_parent(&sscreen->pool_transfers, sizeof(struct si_transfer), 64);
980
981 sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
982 if (sscreen->force_aniso == -1) {
983 sscreen->force_aniso = MIN2(16, debug_get_num_option("AMD_TEX_ANISO", -1));
984 }
985
986 if (sscreen->force_aniso >= 0) {
987 printf("radeonsi: Forcing anisotropy filter to %ix\n",
988 /* round down to a power of two */
989 1 << util_logbase2(sscreen->force_aniso));
990 }
991
992 (void)simple_mtx_init(&sscreen->aux_context_lock, mtx_plain);
993 (void)simple_mtx_init(&sscreen->gpu_load_mutex, mtx_plain);
994
995 si_init_gs_info(sscreen);
996 if (!si_init_shader_cache(sscreen)) {
997 FREE(sscreen);
998 return NULL;
999 }
1000
1001 {
1002 #define OPT_BOOL(name, dflt, description) \
1003 sscreen->options.name = driQueryOptionb(config->options, "radeonsi_" #name);
1004 #include "si_debug_options.h"
1005 }
1006
1007 if (sscreen->options.no_infinite_interp) {
1008 sscreen->debug_flags |= DBG(KILL_PS_INF_INTERP);
1009 }
1010
1011 si_disk_cache_create(sscreen);
1012
1013 /* Determine the number of shader compiler threads. */
1014 hw_threads = sysconf(_SC_NPROCESSORS_ONLN);
1015
1016 if (hw_threads >= 12) {
1017 num_comp_hi_threads = hw_threads * 3 / 4;
1018 num_comp_lo_threads = hw_threads / 3;
1019 } else if (hw_threads >= 6) {
1020 num_comp_hi_threads = hw_threads - 2;
1021 num_comp_lo_threads = hw_threads / 2;
1022 } else if (hw_threads >= 2) {
1023 num_comp_hi_threads = hw_threads - 1;
1024 num_comp_lo_threads = hw_threads / 2;
1025 } else {
1026 num_comp_hi_threads = 1;
1027 num_comp_lo_threads = 1;
1028 }
1029
1030 num_comp_hi_threads = MIN2(num_comp_hi_threads, ARRAY_SIZE(sscreen->compiler));
1031 num_comp_lo_threads = MIN2(num_comp_lo_threads, ARRAY_SIZE(sscreen->compiler_lowp));
1032
1033 /* Take a reference on the glsl types for the compiler threads. */
1034 glsl_type_singleton_init_or_ref();
1035
1036 if (!util_queue_init(
1037 &sscreen->shader_compiler_queue, "sh", 64, num_comp_hi_threads,
1038 UTIL_QUEUE_INIT_RESIZE_IF_FULL | UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY)) {
1039 si_destroy_shader_cache(sscreen);
1040 FREE(sscreen);
1041 glsl_type_singleton_decref();
1042 return NULL;
1043 }
1044
1045 if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority, "shlo", 64,
1046 num_comp_lo_threads,
1047 UTIL_QUEUE_INIT_RESIZE_IF_FULL | UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY |
1048 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
1049 si_destroy_shader_cache(sscreen);
1050 FREE(sscreen);
1051 glsl_type_singleton_decref();
1052 return NULL;
1053 }
1054
1055 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1056 si_init_perfcounters(sscreen);
1057
1058 unsigned prim_discard_vertex_count_threshold, tmp;
1059 si_initialize_prim_discard_tunables(sscreen, false, &prim_discard_vertex_count_threshold, &tmp);
1060 /* Compute-shader-based culling doesn't support VBOs in user SGPRs. */
1061 if (prim_discard_vertex_count_threshold == UINT_MAX)
1062 sscreen->num_vbos_in_user_sgprs = sscreen->info.chip_class >= GFX9 ? 5 : 1;
1063
1064 /* Determine tessellation ring info. */
1065 bool double_offchip_buffers = sscreen->info.chip_class >= GFX7 &&
1066 sscreen->info.family != CHIP_CARRIZO &&
1067 sscreen->info.family != CHIP_STONEY;
1068 /* This must be one less than the maximum number due to a hw limitation.
1069 * Various hardware bugs need this.
1070 */
1071 unsigned max_offchip_buffers_per_se;
1072
1073 if (sscreen->info.chip_class >= GFX10)
1074 max_offchip_buffers_per_se = 256;
1075 /* Only certain chips can use the maximum value. */
1076 else if (sscreen->info.family == CHIP_VEGA12 || sscreen->info.family == CHIP_VEGA20)
1077 max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1078 else
1079 max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
1080
1081 unsigned max_offchip_buffers = max_offchip_buffers_per_se * sscreen->info.max_se;
1082 unsigned offchip_granularity;
1083
1084 /* Hawaii has a bug with offchip buffers > 256 that can be worked
1085 * around by setting 4K granularity.
1086 */
1087 if (sscreen->info.family == CHIP_HAWAII) {
1088 sscreen->tess_offchip_block_dw_size = 4096;
1089 offchip_granularity = V_03093C_X_4K_DWORDS;
1090 } else {
1091 sscreen->tess_offchip_block_dw_size = 8192;
1092 offchip_granularity = V_03093C_X_8K_DWORDS;
1093 }
1094
1095 sscreen->tess_factor_ring_size = 32768 * sscreen->info.max_se;
1096 sscreen->tess_offchip_ring_size = max_offchip_buffers * sscreen->tess_offchip_block_dw_size * 4;
1097
1098 if (sscreen->info.chip_class >= GFX10_3) {
1099 sscreen->vgt_hs_offchip_param =
1100 S_03093C_OFFCHIP_BUFFERING_GFX103(max_offchip_buffers - 1) |
1101 S_03093C_OFFCHIP_GRANULARITY_GFX103(offchip_granularity);
1102 } else if (sscreen->info.chip_class >= GFX7) {
1103 if (sscreen->info.chip_class >= GFX8)
1104 --max_offchip_buffers;
1105 sscreen->vgt_hs_offchip_param = S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1106 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1107 } else {
1108 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
1109 sscreen->vgt_hs_offchip_param = S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1110 }
1111
1112 sscreen->has_draw_indirect_multi =
1113 (sscreen->info.family >= CHIP_POLARIS10) ||
1114 (sscreen->info.chip_class == GFX8 && sscreen->info.pfp_fw_version >= 121 &&
1115 sscreen->info.me_fw_version >= 87) ||
1116 (sscreen->info.chip_class == GFX7 && sscreen->info.pfp_fw_version >= 211 &&
1117 sscreen->info.me_fw_version >= 173) ||
1118 (sscreen->info.chip_class == GFX6 && sscreen->info.pfp_fw_version >= 79 &&
1119 sscreen->info.me_fw_version >= 142);
1120
1121 sscreen->has_out_of_order_rast =
1122 sscreen->info.has_out_of_order_rast && !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER));
1123 sscreen->assume_no_z_fights = driQueryOptionb(config->options, "radeonsi_assume_no_z_fights") ||
1124 driQueryOptionb(config->options, "allow_draw_out_of_order");
1125 sscreen->commutative_blend_add =
1126 driQueryOptionb(config->options, "radeonsi_commutative_blend_add") ||
1127 driQueryOptionb(config->options, "allow_draw_out_of_order");
1128
1129 sscreen->use_ngg = sscreen->info.chip_class >= GFX10 && sscreen->info.family != CHIP_NAVI14 &&
1130 !(sscreen->debug_flags & DBG(NO_NGG));
1131 sscreen->use_ngg_culling = sscreen->use_ngg && !(sscreen->debug_flags & DBG(NO_NGG_CULLING));
1132 sscreen->always_use_ngg_culling =
1133 sscreen->use_ngg_culling && sscreen->debug_flags & DBG(ALWAYS_NGG_CULLING);
1134 sscreen->use_ngg_streamout = false;
1135
1136 /* Only enable primitive binning on APUs by default. */
1137 if (sscreen->info.chip_class >= GFX10) {
1138 sscreen->dpbb_allowed = true;
1139 /* DFSM is not supported on GFX 10.3 and not beneficial on Navi1x. */
1140 } else if (sscreen->info.chip_class == GFX9) {
1141 sscreen->dpbb_allowed = !sscreen->info.has_dedicated_vram;
1142 sscreen->dfsm_allowed = !sscreen->info.has_dedicated_vram;
1143 }
1144
1145 /* Process DPBB enable flags. */
1146 if (sscreen->debug_flags & DBG(DPBB)) {
1147 sscreen->dpbb_allowed = true;
1148 if (sscreen->debug_flags & DBG(DFSM))
1149 sscreen->dfsm_allowed = true;
1150 }
1151
1152 /* Process DPBB disable flags. */
1153 if (sscreen->debug_flags & DBG(NO_DPBB)) {
1154 sscreen->dpbb_allowed = false;
1155 sscreen->dfsm_allowed = false;
1156 } else if (sscreen->debug_flags & DBG(NO_DFSM)) {
1157 sscreen->dfsm_allowed = false;
1158 }
1159
1160 /* While it would be nice not to have this flag, we are constrained
1161 * by the reality that LLVM 9.0 has buggy VGPR indexing on GFX9.
1162 */
1163 sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class != GFX9;
1164
1165 sscreen->dcc_msaa_allowed = !(sscreen->debug_flags & DBG(NO_DCC_MSAA));
1166
1167 (void)simple_mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1168 sscreen->use_monolithic_shaders = (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
1169
1170 sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SCACHE | SI_CONTEXT_INV_VCACHE;
1171 if (sscreen->info.chip_class <= GFX8) {
1172 sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_L2;
1173 sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WB_L2;
1174 }
1175
1176 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1177 sscreen->debug_flags |= DBG_ALL_SHADERS;
1178
1179 /* Syntax:
1180 * EQAA=s,z,c
1181 * Example:
1182 * EQAA=8,4,2
1183
1184 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1185 * Constraints:
1186 * s >= z >= c (ignoring this only wastes memory)
1187 * s = [2..16]
1188 * z = [2..8]
1189 * c = [2..8]
1190 *
1191 * Only MSAA color and depth buffers are overriden.
1192 */
1193 if (sscreen->info.has_eqaa_surface_allocator) {
1194 const char *eqaa = debug_get_option("EQAA", NULL);
1195 unsigned s, z, f;
1196
1197 if (eqaa && sscanf(eqaa, "%u,%u,%u", &s, &z, &f) == 3 && s && z && f) {
1198 sscreen->eqaa_force_coverage_samples = s;
1199 sscreen->eqaa_force_z_samples = z;
1200 sscreen->eqaa_force_color_samples = f;
1201 }
1202 }
1203
1204 sscreen->ge_wave_size = 64;
1205 sscreen->ps_wave_size = 64;
1206 sscreen->compute_wave_size = 64;
1207
1208 if (sscreen->info.chip_class >= GFX10) {
1209 /* Pixels shaders: Wave64 is recommended.
1210 * Compute shaders: There are piglit failures with Wave32.
1211 */
1212 sscreen->ge_wave_size = 32;
1213
1214 if (sscreen->debug_flags & DBG(W32_GE))
1215 sscreen->ge_wave_size = 32;
1216 if (sscreen->debug_flags & DBG(W32_PS))
1217 sscreen->ps_wave_size = 32;
1218 if (sscreen->debug_flags & DBG(W32_CS))
1219 sscreen->compute_wave_size = 32;
1220
1221 if (sscreen->debug_flags & DBG(W64_GE))
1222 sscreen->ge_wave_size = 64;
1223 if (sscreen->debug_flags & DBG(W64_PS))
1224 sscreen->ps_wave_size = 64;
1225 if (sscreen->debug_flags & DBG(W64_CS))
1226 sscreen->compute_wave_size = 64;
1227 }
1228
1229 /* Create the auxiliary context. This must be done last. */
1230 sscreen->aux_context = si_create_context(
1231 &sscreen->b, (sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) |
1232 (sscreen->info.has_graphics ? 0 : PIPE_CONTEXT_COMPUTE_ONLY));
1233 if (sscreen->options.aux_debug) {
1234 struct u_log_context *log = CALLOC_STRUCT(u_log_context);
1235 u_log_context_init(log);
1236 sscreen->aux_context->set_log_context(sscreen->aux_context, log);
1237 }
1238
1239 if (test_flags & DBG(TEST_DMA))
1240 si_test_dma(sscreen);
1241
1242 if (test_flags & DBG(TEST_DMA_PERF)) {
1243 si_test_dma_perf(sscreen);
1244 }
1245
1246 if (test_flags & (DBG(TEST_VMFAULT_CP) | DBG(TEST_VMFAULT_SDMA) | DBG(TEST_VMFAULT_SHADER)))
1247 si_test_vmfault(sscreen, test_flags);
1248
1249 if (test_flags & DBG(TEST_GDS))
1250 si_test_gds((struct si_context *)sscreen->aux_context);
1251
1252 if (test_flags & DBG(TEST_GDS_MM)) {
1253 si_test_gds_memory_management((struct si_context *)sscreen->aux_context, 32 * 1024, 4,
1254 RADEON_DOMAIN_GDS);
1255 }
1256 if (test_flags & DBG(TEST_GDS_OA_MM)) {
1257 si_test_gds_memory_management((struct si_context *)sscreen->aux_context, 4, 1,
1258 RADEON_DOMAIN_OA);
1259 }
1260
1261 STATIC_ASSERT(sizeof(union si_vgt_stages_key) == 4);
1262 return &sscreen->b;
1263 }
1264
1265 struct pipe_screen *radeonsi_screen_create(int fd, const struct pipe_screen_config *config)
1266 {
1267 drmVersionPtr version = drmGetVersion(fd);
1268 struct radeon_winsys *rw = NULL;
1269
1270 switch (version->version_major) {
1271 case 2:
1272 rw = radeon_drm_winsys_create(fd, config, radeonsi_screen_create_impl);
1273 break;
1274 case 3:
1275 rw = amdgpu_winsys_create(fd, config, radeonsi_screen_create_impl);
1276 break;
1277 }
1278
1279 drmFreeVersion(version);
1280 return rw ? rw->screen : NULL;
1281 }