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radeonsi/gfx10: double the number of tessellation offchip buffers per SE
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "si_pipe.h"
27 #include "si_public.h"
28 #include "si_shader_internal.h"
29 #include "si_compute.h"
30 #include "sid.h"
31
32 #include "ac_llvm_util.h"
33 #include "radeon/radeon_uvd.h"
34 #include "gallivm/lp_bld_misc.h"
35 #include "util/disk_cache.h"
36 #include "util/u_log.h"
37 #include "util/u_memory.h"
38 #include "util/u_suballoc.h"
39 #include "util/u_tests.h"
40 #include "util/u_upload_mgr.h"
41 #include "util/xmlconfig.h"
42 #include "vl/vl_decoder.h"
43 #include "driver_ddebug/dd_util.h"
44
45 #include "gallium/winsys/radeon/drm/radeon_drm_public.h"
46 #include "gallium/winsys/amdgpu/drm/amdgpu_public.h"
47 #include <xf86drm.h>
48
49 static const struct debug_named_value debug_options[] = {
50 /* Shader logging options: */
51 { "vs", DBG(VS), "Print vertex shaders" },
52 { "ps", DBG(PS), "Print pixel shaders" },
53 { "gs", DBG(GS), "Print geometry shaders" },
54 { "tcs", DBG(TCS), "Print tessellation control shaders" },
55 { "tes", DBG(TES), "Print tessellation evaluation shaders" },
56 { "cs", DBG(CS), "Print compute shaders" },
57 { "noir", DBG(NO_IR), "Don't print the LLVM IR"},
58 { "notgsi", DBG(NO_TGSI), "Don't print the TGSI"},
59 { "noasm", DBG(NO_ASM), "Don't print disassembled shaders"},
60 { "preoptir", DBG(PREOPT_IR), "Print the LLVM IR before initial optimizations" },
61
62 /* Shader compiler options the shader cache should be aware of: */
63 { "unsafemath", DBG(UNSAFE_MATH), "Enable unsafe math shader optimizations" },
64 { "sisched", DBG(SI_SCHED), "Enable LLVM SI Machine Instruction Scheduler." },
65 { "gisel", DBG(GISEL), "Enable LLVM global instruction selector." },
66
67 /* Shader compiler options (with no effect on the shader cache): */
68 { "checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR" },
69 { "mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand" },
70 { "nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants." },
71
72 /* Information logging options: */
73 { "info", DBG(INFO), "Print driver information" },
74 { "tex", DBG(TEX), "Print texture info" },
75 { "compute", DBG(COMPUTE), "Print compute info" },
76 { "vm", DBG(VM), "Print virtual addresses when creating resources" },
77
78 /* Driver options: */
79 { "forcedma", DBG(FORCE_DMA), "Use asynchronous DMA for all operations when possible." },
80 { "nodma", DBG(NO_ASYNC_DMA), "Disable asynchronous DMA" },
81 { "nowc", DBG(NO_WC), "Disable GTT write combining" },
82 { "check_vm", DBG(CHECK_VM), "Check VM faults and dump debug info." },
83 { "reserve_vmid", DBG(RESERVE_VMID), "Force VMID reservation per context." },
84 { "zerovram", DBG(ZERO_VRAM), "Clear VRAM allocations." },
85
86 /* 3D engine options: */
87 { "alwayspd", DBG(ALWAYS_PD), "Always enable the primitive discard compute shader." },
88 { "pd", DBG(PD), "Enable the primitive discard compute shader for large draw calls." },
89 { "nopd", DBG(NO_PD), "Disable the primitive discard compute shader." },
90 { "switch_on_eop", DBG(SWITCH_ON_EOP), "Program WD/IA to switch on end-of-packet." },
91 { "nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order rasterization" },
92 { "nodpbb", DBG(NO_DPBB), "Disable DPBB." },
93 { "nodfsm", DBG(NO_DFSM), "Disable DFSM." },
94 { "dpbb", DBG(DPBB), "Enable DPBB." },
95 { "dfsm", DBG(DFSM), "Enable DFSM." },
96 { "nohyperz", DBG(NO_HYPERZ), "Disable Hyper-Z" },
97 { "norbplus", DBG(NO_RB_PLUS), "Disable RB+." },
98 { "no2d", DBG(NO_2D_TILING), "Disable 2D tiling" },
99 { "notiling", DBG(NO_TILING), "Disable tiling" },
100 { "nodcc", DBG(NO_DCC), "Disable DCC." },
101 { "nodccclear", DBG(NO_DCC_CLEAR), "Disable DCC fast clear." },
102 { "nodccfb", DBG(NO_DCC_FB), "Disable separate DCC on the main framebuffer" },
103 { "nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA" },
104 { "nofmask", DBG(NO_FMASK), "Disable MSAA compression" },
105
106 /* Tests: */
107 { "testdma", DBG(TEST_DMA), "Invoke SDMA tests and exit." },
108 { "testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and exit." },
109 { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA), "Invoke a SDMA VM fault test and exit." },
110 { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM fault test and exit." },
111 { "testdmaperf", DBG(TEST_DMA_PERF), "Test DMA performance" },
112 { "testgds", DBG(TEST_GDS), "Test GDS." },
113 { "testgdsmm", DBG(TEST_GDS_MM), "Test GDS memory management." },
114 { "testgdsoamm", DBG(TEST_GDS_OA_MM), "Test GDS OA memory management." },
115
116 DEBUG_NAMED_VALUE_END /* must be last */
117 };
118
119 static void si_init_compiler(struct si_screen *sscreen,
120 struct ac_llvm_compiler *compiler)
121 {
122 /* Only create the less-optimizing version of the compiler on APUs
123 * predating Ryzen (Raven). */
124 bool create_low_opt_compiler = !sscreen->info.has_dedicated_vram &&
125 sscreen->info.chip_class <= GFX8;
126
127 enum ac_target_machine_options tm_options =
128 (sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
129 (sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL : 0) |
130 (sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
131 (sscreen->info.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
132 (!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0) |
133 (sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0) |
134 (create_low_opt_compiler ? AC_TM_CREATE_LOW_OPT : 0);
135
136 ac_init_llvm_once();
137 ac_init_llvm_compiler(compiler, sscreen->info.family, tm_options);
138 compiler->passes = ac_create_llvm_passes(compiler->tm);
139
140 if (compiler->low_opt_tm)
141 compiler->low_opt_passes = ac_create_llvm_passes(compiler->low_opt_tm);
142 }
143
144 static void si_destroy_compiler(struct ac_llvm_compiler *compiler)
145 {
146 ac_destroy_llvm_passes(compiler->passes);
147 ac_destroy_llvm_passes(compiler->low_opt_passes);
148 ac_destroy_llvm_compiler(compiler);
149 }
150
151 /*
152 * pipe_context
153 */
154 static void si_destroy_context(struct pipe_context *context)
155 {
156 struct si_context *sctx = (struct si_context *)context;
157 int i;
158
159 util_queue_finish(&sctx->screen->shader_compiler_queue);
160 util_queue_finish(&sctx->screen->shader_compiler_queue_low_priority);
161
162 /* Unreference the framebuffer normally to disable related logic
163 * properly.
164 */
165 struct pipe_framebuffer_state fb = {};
166 if (context->set_framebuffer_state)
167 context->set_framebuffer_state(context, &fb);
168
169 si_release_all_descriptors(sctx);
170
171 pipe_resource_reference(&sctx->esgs_ring, NULL);
172 pipe_resource_reference(&sctx->gsvs_ring, NULL);
173 pipe_resource_reference(&sctx->tess_rings, NULL);
174 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
175 pipe_resource_reference(&sctx->sample_pos_buffer, NULL);
176 si_resource_reference(&sctx->border_color_buffer, NULL);
177 free(sctx->border_color_table);
178 si_resource_reference(&sctx->scratch_buffer, NULL);
179 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
180 si_resource_reference(&sctx->wait_mem_scratch, NULL);
181
182 si_pm4_free_state(sctx, sctx->init_config, ~0);
183 if (sctx->init_config_gs_rings)
184 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
185 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
186 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
187
188 if (sctx->fixed_func_tcs_shader.cso)
189 sctx->b.delete_tcs_state(&sctx->b, sctx->fixed_func_tcs_shader.cso);
190 if (sctx->custom_dsa_flush)
191 sctx->b.delete_depth_stencil_alpha_state(&sctx->b, sctx->custom_dsa_flush);
192 if (sctx->custom_blend_resolve)
193 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_resolve);
194 if (sctx->custom_blend_fmask_decompress)
195 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_fmask_decompress);
196 if (sctx->custom_blend_eliminate_fastclear)
197 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_eliminate_fastclear);
198 if (sctx->custom_blend_dcc_decompress)
199 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_dcc_decompress);
200 if (sctx->vs_blit_pos)
201 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos);
202 if (sctx->vs_blit_pos_layered)
203 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos_layered);
204 if (sctx->vs_blit_color)
205 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color);
206 if (sctx->vs_blit_color_layered)
207 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color_layered);
208 if (sctx->vs_blit_texcoord)
209 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_texcoord);
210 if (sctx->cs_clear_buffer)
211 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_buffer);
212 if (sctx->cs_copy_buffer)
213 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_buffer);
214 if (sctx->cs_copy_image)
215 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image);
216 if (sctx->cs_copy_image_1d_array)
217 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image_1d_array);
218 if (sctx->cs_clear_render_target)
219 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target);
220 if (sctx->cs_clear_render_target_1d_array)
221 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target_1d_array);
222 if (sctx->cs_dcc_retile)
223 sctx->b.delete_compute_state(&sctx->b, sctx->cs_dcc_retile);
224
225 if (sctx->blitter)
226 util_blitter_destroy(sctx->blitter);
227
228 /* Release DCC stats. */
229 for (int i = 0; i < ARRAY_SIZE(sctx->dcc_stats); i++) {
230 assert(!sctx->dcc_stats[i].query_active);
231
232 for (int j = 0; j < ARRAY_SIZE(sctx->dcc_stats[i].ps_stats); j++)
233 if (sctx->dcc_stats[i].ps_stats[j])
234 sctx->b.destroy_query(&sctx->b,
235 sctx->dcc_stats[i].ps_stats[j]);
236
237 si_texture_reference(&sctx->dcc_stats[i].tex, NULL);
238 }
239
240 if (sctx->query_result_shader)
241 sctx->b.delete_compute_state(&sctx->b, sctx->query_result_shader);
242
243 if (sctx->gfx_cs)
244 sctx->ws->cs_destroy(sctx->gfx_cs);
245 if (sctx->dma_cs)
246 sctx->ws->cs_destroy(sctx->dma_cs);
247 if (sctx->ctx)
248 sctx->ws->ctx_destroy(sctx->ctx);
249
250 if (sctx->b.stream_uploader)
251 u_upload_destroy(sctx->b.stream_uploader);
252 if (sctx->b.const_uploader)
253 u_upload_destroy(sctx->b.const_uploader);
254 if (sctx->cached_gtt_allocator)
255 u_upload_destroy(sctx->cached_gtt_allocator);
256
257 slab_destroy_child(&sctx->pool_transfers);
258 slab_destroy_child(&sctx->pool_transfers_unsync);
259
260 if (sctx->allocator_zeroed_memory)
261 u_suballocator_destroy(sctx->allocator_zeroed_memory);
262
263 sctx->ws->fence_reference(&sctx->last_gfx_fence, NULL);
264 sctx->ws->fence_reference(&sctx->last_sdma_fence, NULL);
265 sctx->ws->fence_reference(&sctx->last_ib_barrier_fence, NULL);
266 si_resource_reference(&sctx->eop_bug_scratch, NULL);
267 si_resource_reference(&sctx->index_ring, NULL);
268 si_resource_reference(&sctx->barrier_buf, NULL);
269 si_resource_reference(&sctx->last_ib_barrier_buf, NULL);
270 pb_reference(&sctx->gds, NULL);
271 pb_reference(&sctx->gds_oa, NULL);
272
273 si_destroy_compiler(&sctx->compiler);
274
275 si_saved_cs_reference(&sctx->current_saved_cs, NULL);
276
277 _mesa_hash_table_destroy(sctx->tex_handles, NULL);
278 _mesa_hash_table_destroy(sctx->img_handles, NULL);
279
280 util_dynarray_fini(&sctx->resident_tex_handles);
281 util_dynarray_fini(&sctx->resident_img_handles);
282 util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
283 util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
284 util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
285 si_unref_sdma_uploads(sctx);
286 FREE(sctx);
287 }
288
289 static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx)
290 {
291 struct si_context *sctx = (struct si_context *)ctx;
292
293 return sctx->ws->ctx_query_reset_status(sctx->ctx);
294 }
295
296 static void si_set_device_reset_callback(struct pipe_context *ctx,
297 const struct pipe_device_reset_callback *cb)
298 {
299 struct si_context *sctx = (struct si_context *)ctx;
300
301 if (cb)
302 sctx->device_reset_callback = *cb;
303 else
304 memset(&sctx->device_reset_callback, 0,
305 sizeof(sctx->device_reset_callback));
306 }
307
308 bool si_check_device_reset(struct si_context *sctx)
309 {
310 enum pipe_reset_status status;
311
312 if (!sctx->device_reset_callback.reset)
313 return false;
314
315 status = sctx->ws->ctx_query_reset_status(sctx->ctx);
316 if (status == PIPE_NO_RESET)
317 return false;
318
319 sctx->device_reset_callback.reset(sctx->device_reset_callback.data, status);
320 return true;
321 }
322
323 /* Apitrace profiling:
324 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
325 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
326 * and remember its number.
327 * 3) In Mesa, enable queries and performance counters around that draw
328 * call and print the results.
329 * 4) glretrace --benchmark --markers ..
330 */
331 static void si_emit_string_marker(struct pipe_context *ctx,
332 const char *string, int len)
333 {
334 struct si_context *sctx = (struct si_context *)ctx;
335
336 dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
337
338 if (sctx->log)
339 u_log_printf(sctx->log, "\nString marker: %*s\n", len, string);
340 }
341
342 static void si_set_debug_callback(struct pipe_context *ctx,
343 const struct pipe_debug_callback *cb)
344 {
345 struct si_context *sctx = (struct si_context *)ctx;
346 struct si_screen *screen = sctx->screen;
347
348 util_queue_finish(&screen->shader_compiler_queue);
349 util_queue_finish(&screen->shader_compiler_queue_low_priority);
350
351 if (cb)
352 sctx->debug = *cb;
353 else
354 memset(&sctx->debug, 0, sizeof(sctx->debug));
355 }
356
357 static void si_set_log_context(struct pipe_context *ctx,
358 struct u_log_context *log)
359 {
360 struct si_context *sctx = (struct si_context *)ctx;
361 sctx->log = log;
362
363 if (log)
364 u_log_add_auto_logger(log, si_auto_log_cs, sctx);
365 }
366
367 static void si_set_context_param(struct pipe_context *ctx,
368 enum pipe_context_param param,
369 unsigned value)
370 {
371 struct radeon_winsys *ws = ((struct si_context *)ctx)->ws;
372
373 switch (param) {
374 case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE:
375 ws->pin_threads_to_L3_cache(ws, value);
376 break;
377 default:;
378 }
379 }
380
381 static struct pipe_context *si_create_context(struct pipe_screen *screen,
382 unsigned flags)
383 {
384 struct si_context *sctx = CALLOC_STRUCT(si_context);
385 struct si_screen* sscreen = (struct si_screen *)screen;
386 struct radeon_winsys *ws = sscreen->ws;
387 int shader, i;
388 bool stop_exec_on_failure = (flags & PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET) != 0;
389
390 if (!sctx)
391 return NULL;
392
393 sctx->has_graphics = sscreen->info.chip_class == GFX6 ||
394 !(flags & PIPE_CONTEXT_COMPUTE_ONLY);
395
396 if (flags & PIPE_CONTEXT_DEBUG)
397 sscreen->record_llvm_ir = true; /* racy but not critical */
398
399 sctx->b.screen = screen; /* this must be set first */
400 sctx->b.priv = NULL;
401 sctx->b.destroy = si_destroy_context;
402 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
403 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
404
405 slab_create_child(&sctx->pool_transfers, &sscreen->pool_transfers);
406 slab_create_child(&sctx->pool_transfers_unsync, &sscreen->pool_transfers);
407
408 sctx->ws = sscreen->ws;
409 sctx->family = sscreen->info.family;
410 sctx->chip_class = sscreen->info.chip_class;
411
412 if (sctx->chip_class == GFX7 ||
413 sctx->chip_class == GFX8 ||
414 sctx->chip_class == GFX9) {
415 sctx->eop_bug_scratch = si_resource(
416 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
417 16 * sscreen->info.num_render_backends));
418 if (!sctx->eop_bug_scratch)
419 goto fail;
420 }
421
422 /* Initialize context allocators. */
423 sctx->allocator_zeroed_memory =
424 u_suballocator_create(&sctx->b, 128 * 1024,
425 0, PIPE_USAGE_DEFAULT,
426 SI_RESOURCE_FLAG_UNMAPPABLE |
427 SI_RESOURCE_FLAG_CLEAR, false);
428 if (!sctx->allocator_zeroed_memory)
429 goto fail;
430
431 sctx->b.stream_uploader = u_upload_create(&sctx->b, 1024 * 1024,
432 0, PIPE_USAGE_STREAM,
433 SI_RESOURCE_FLAG_READ_ONLY);
434 if (!sctx->b.stream_uploader)
435 goto fail;
436
437 sctx->cached_gtt_allocator = u_upload_create(&sctx->b, 16 * 1024,
438 0, PIPE_USAGE_STAGING, 0);
439 if (!sctx->cached_gtt_allocator)
440 goto fail;
441
442 sctx->ctx = sctx->ws->ctx_create(sctx->ws);
443 if (!sctx->ctx)
444 goto fail;
445
446 if (sscreen->info.num_sdma_rings && !(sscreen->debug_flags & DBG(NO_ASYNC_DMA))) {
447 sctx->dma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA,
448 (void*)si_flush_dma_cs,
449 sctx, stop_exec_on_failure);
450 }
451
452 bool use_sdma_upload = sscreen->info.has_dedicated_vram && sctx->dma_cs;
453 sctx->b.const_uploader = u_upload_create(&sctx->b, 256 * 1024,
454 0, PIPE_USAGE_DEFAULT,
455 SI_RESOURCE_FLAG_32BIT |
456 (use_sdma_upload ?
457 SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA :
458 (sscreen->cpdma_prefetch_writes_memory ?
459 0 : SI_RESOURCE_FLAG_READ_ONLY)));
460 if (!sctx->b.const_uploader)
461 goto fail;
462
463 if (use_sdma_upload)
464 u_upload_enable_flush_explicit(sctx->b.const_uploader);
465
466 sctx->gfx_cs = ws->cs_create(sctx->ctx,
467 sctx->has_graphics ? RING_GFX : RING_COMPUTE,
468 (void*)si_flush_gfx_cs, sctx, stop_exec_on_failure);
469
470 /* Border colors. */
471 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
472 sizeof(*sctx->border_color_table));
473 if (!sctx->border_color_table)
474 goto fail;
475
476 sctx->border_color_buffer = si_resource(
477 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
478 SI_MAX_BORDER_COLORS *
479 sizeof(*sctx->border_color_table)));
480 if (!sctx->border_color_buffer)
481 goto fail;
482
483 sctx->border_color_map =
484 ws->buffer_map(sctx->border_color_buffer->buf,
485 NULL, PIPE_TRANSFER_WRITE);
486 if (!sctx->border_color_map)
487 goto fail;
488
489 if (sctx->chip_class >= GFX10)
490 sctx->ngg = !sscreen->options.disable_ngg;
491
492 /* Initialize context functions used by graphics and compute. */
493 if (sctx->chip_class >= GFX10)
494 sctx->emit_cache_flush = gfx10_emit_cache_flush;
495 else
496 sctx->emit_cache_flush = si_emit_cache_flush;
497
498 sctx->b.emit_string_marker = si_emit_string_marker;
499 sctx->b.set_debug_callback = si_set_debug_callback;
500 sctx->b.set_log_context = si_set_log_context;
501 sctx->b.set_context_param = si_set_context_param;
502 sctx->b.get_device_reset_status = si_get_reset_status;
503 sctx->b.set_device_reset_callback = si_set_device_reset_callback;
504
505 si_init_all_descriptors(sctx);
506 si_init_buffer_functions(sctx);
507 si_init_clear_functions(sctx);
508 si_init_blit_functions(sctx);
509 si_init_compute_functions(sctx);
510 si_init_compute_blit_functions(sctx);
511 si_init_debug_functions(sctx);
512 si_init_fence_functions(sctx);
513 si_init_query_functions(sctx);
514 si_init_state_compute_functions(sctx);
515
516 /* Initialize graphics-only context functions. */
517 if (sctx->has_graphics) {
518 si_init_context_texture_functions(sctx);
519 si_init_msaa_functions(sctx);
520 si_init_shader_functions(sctx);
521 si_init_state_functions(sctx);
522 si_init_streamout_functions(sctx);
523 si_init_viewport_functions(sctx);
524
525 sctx->blitter = util_blitter_create(&sctx->b);
526 if (sctx->blitter == NULL)
527 goto fail;
528 sctx->blitter->skip_viewport_restore = true;
529
530 si_init_draw_functions(sctx);
531 si_initialize_prim_discard_tunables(sctx);
532 }
533
534 /* Initialize SDMA functions. */
535 if (sctx->chip_class >= GFX7)
536 cik_init_sdma_functions(sctx);
537 else
538 si_init_dma_functions(sctx);
539
540 if (sscreen->debug_flags & DBG(FORCE_DMA))
541 sctx->b.resource_copy_region = sctx->dma_copy;
542
543 sctx->sample_mask = 0xffff;
544
545 /* Initialize multimedia functions. */
546 if (sscreen->info.has_hw_decode) {
547 sctx->b.create_video_codec = si_uvd_create_decoder;
548 sctx->b.create_video_buffer = si_video_buffer_create;
549 } else {
550 sctx->b.create_video_codec = vl_create_decoder;
551 sctx->b.create_video_buffer = vl_video_buffer_create;
552 }
553
554 if (sctx->chip_class >= GFX9) {
555 sctx->wait_mem_scratch = si_resource(
556 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 8));
557 if (!sctx->wait_mem_scratch)
558 goto fail;
559
560 /* Initialize the memory. */
561 si_cp_write_data(sctx, sctx->wait_mem_scratch, 0, 4,
562 V_370_MEM, V_370_ME, &sctx->wait_mem_number);
563 }
564
565 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
566 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
567 if (sctx->chip_class == GFX7) {
568 sctx->null_const_buf.buffer =
569 pipe_aligned_buffer_create(screen,
570 SI_RESOURCE_FLAG_32BIT,
571 PIPE_USAGE_DEFAULT, 16,
572 sctx->screen->info.tcc_cache_line_size);
573 if (!sctx->null_const_buf.buffer)
574 goto fail;
575 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
576
577 unsigned start_shader = sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE;
578 for (shader = start_shader; shader < SI_NUM_SHADERS; shader++) {
579 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
580 sctx->b.set_constant_buffer(&sctx->b, shader, i,
581 &sctx->null_const_buf);
582 }
583 }
584
585 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
586 &sctx->null_const_buf);
587 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
588 &sctx->null_const_buf);
589 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
590 &sctx->null_const_buf);
591 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
592 &sctx->null_const_buf);
593 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
594 &sctx->null_const_buf);
595 }
596
597 uint64_t max_threads_per_block;
598 screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
599 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
600 &max_threads_per_block);
601
602 /* The maximum number of scratch waves. Scratch space isn't divided
603 * evenly between CUs. The number is only a function of the number of CUs.
604 * We can decrease the constant to decrease the scratch buffer size.
605 *
606 * sctx->scratch_waves must be >= the maximum posible size of
607 * 1 threadgroup, so that the hw doesn't hang from being unable
608 * to start any.
609 *
610 * The recommended value is 4 per CU at most. Higher numbers don't
611 * bring much benefit, but they still occupy chip resources (think
612 * async compute). I've seen ~2% performance difference between 4 and 32.
613 */
614 sctx->scratch_waves = MAX2(32 * sscreen->info.num_good_compute_units,
615 max_threads_per_block / 64);
616
617 si_init_compiler(sscreen, &sctx->compiler);
618
619 /* Bindless handles. */
620 sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
621 _mesa_key_pointer_equal);
622 sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
623 _mesa_key_pointer_equal);
624
625 util_dynarray_init(&sctx->resident_tex_handles, NULL);
626 util_dynarray_init(&sctx->resident_img_handles, NULL);
627 util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
628 util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
629 util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
630
631 sctx->sample_pos_buffer =
632 pipe_buffer_create(sctx->b.screen, 0, PIPE_USAGE_DEFAULT,
633 sizeof(sctx->sample_positions));
634 pipe_buffer_write(&sctx->b, sctx->sample_pos_buffer, 0,
635 sizeof(sctx->sample_positions), &sctx->sample_positions);
636
637 /* this must be last */
638 si_begin_new_gfx_cs(sctx);
639
640 if (sctx->chip_class == GFX7) {
641 /* Clear the NULL constant buffer, because loads should return zeros.
642 * Note that this forces CP DMA to be used, because clover deadlocks
643 * for some reason when the compute codepath is used.
644 */
645 uint32_t clear_value = 0;
646 si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0,
647 sctx->null_const_buf.buffer->width0,
648 &clear_value, 4, SI_COHERENCY_SHADER, true);
649 }
650 return &sctx->b;
651 fail:
652 fprintf(stderr, "radeonsi: Failed to create a context.\n");
653 si_destroy_context(&sctx->b);
654 return NULL;
655 }
656
657 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
658 void *priv, unsigned flags)
659 {
660 struct si_screen *sscreen = (struct si_screen *)screen;
661 struct pipe_context *ctx;
662
663 if (sscreen->debug_flags & DBG(CHECK_VM))
664 flags |= PIPE_CONTEXT_DEBUG;
665
666 ctx = si_create_context(screen, flags);
667
668 if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
669 return ctx;
670
671 /* Clover (compute-only) is unsupported. */
672 if (flags & PIPE_CONTEXT_COMPUTE_ONLY)
673 return ctx;
674
675 /* When shaders are logged to stderr, asynchronous compilation is
676 * disabled too. */
677 if (sscreen->debug_flags & DBG_ALL_SHADERS)
678 return ctx;
679
680 /* Use asynchronous flushes only on amdgpu, since the radeon
681 * implementation for fence_server_sync is incomplete. */
682 return threaded_context_create(ctx, &sscreen->pool_transfers,
683 si_replace_buffer_storage,
684 sscreen->info.is_amdgpu ? si_create_fence : NULL,
685 &((struct si_context*)ctx)->tc);
686 }
687
688 /*
689 * pipe_screen
690 */
691 static void si_destroy_screen(struct pipe_screen* pscreen)
692 {
693 struct si_screen *sscreen = (struct si_screen *)pscreen;
694 struct si_shader_part *parts[] = {
695 sscreen->vs_prologs,
696 sscreen->tcs_epilogs,
697 sscreen->gs_prologs,
698 sscreen->ps_prologs,
699 sscreen->ps_epilogs
700 };
701 unsigned i;
702
703 if (!sscreen->ws->unref(sscreen->ws))
704 return;
705
706 mtx_destroy(&sscreen->aux_context_lock);
707
708 struct u_log_context *aux_log = ((struct si_context *)sscreen->aux_context)->log;
709 if (aux_log) {
710 sscreen->aux_context->set_log_context(sscreen->aux_context, NULL);
711 u_log_context_destroy(aux_log);
712 FREE(aux_log);
713 }
714
715 sscreen->aux_context->destroy(sscreen->aux_context);
716
717 util_queue_destroy(&sscreen->shader_compiler_queue);
718 util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
719
720 for (i = 0; i < ARRAY_SIZE(sscreen->compiler); i++)
721 si_destroy_compiler(&sscreen->compiler[i]);
722
723 for (i = 0; i < ARRAY_SIZE(sscreen->compiler_lowp); i++)
724 si_destroy_compiler(&sscreen->compiler_lowp[i]);
725
726 /* Free shader parts. */
727 for (i = 0; i < ARRAY_SIZE(parts); i++) {
728 while (parts[i]) {
729 struct si_shader_part *part = parts[i];
730
731 parts[i] = part->next;
732 si_shader_binary_clean(&part->binary);
733 FREE(part);
734 }
735 }
736 mtx_destroy(&sscreen->shader_parts_mutex);
737 si_destroy_shader_cache(sscreen);
738
739 si_destroy_perfcounters(sscreen);
740 si_gpu_load_kill_thread(sscreen);
741
742 mtx_destroy(&sscreen->gpu_load_mutex);
743
744 slab_destroy_parent(&sscreen->pool_transfers);
745
746 disk_cache_destroy(sscreen->disk_shader_cache);
747 sscreen->ws->destroy(sscreen->ws);
748 FREE(sscreen);
749 }
750
751 static void si_init_gs_info(struct si_screen *sscreen)
752 {
753 sscreen->gs_table_depth = ac_get_gs_table_depth(sscreen->info.chip_class,
754 sscreen->info.family);
755 }
756
757 static void si_test_vmfault(struct si_screen *sscreen)
758 {
759 struct pipe_context *ctx = sscreen->aux_context;
760 struct si_context *sctx = (struct si_context *)ctx;
761 struct pipe_resource *buf =
762 pipe_buffer_create_const0(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 64);
763
764 if (!buf) {
765 puts("Buffer allocation failed.");
766 exit(1);
767 }
768
769 si_resource(buf)->gpu_address = 0; /* cause a VM fault */
770
771 if (sscreen->debug_flags & DBG(TEST_VMFAULT_CP)) {
772 si_cp_dma_copy_buffer(sctx, buf, buf, 0, 4, 4, 0,
773 SI_COHERENCY_NONE, L2_BYPASS);
774 ctx->flush(ctx, NULL, 0);
775 puts("VM fault test: CP - done.");
776 }
777 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SDMA)) {
778 si_sdma_clear_buffer(sctx, buf, 0, 4, 0);
779 ctx->flush(ctx, NULL, 0);
780 puts("VM fault test: SDMA - done.");
781 }
782 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SHADER)) {
783 util_test_constant_buffer(ctx, buf);
784 puts("VM fault test: Shader - done.");
785 }
786 exit(0);
787 }
788
789 static void si_test_gds_memory_management(struct si_context *sctx,
790 unsigned alloc_size, unsigned alignment,
791 enum radeon_bo_domain domain)
792 {
793 struct radeon_winsys *ws = sctx->ws;
794 struct radeon_cmdbuf *cs[8];
795 struct pb_buffer *gds_bo[ARRAY_SIZE(cs)];
796
797 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
798 cs[i] = ws->cs_create(sctx->ctx, RING_COMPUTE,
799 NULL, NULL, false);
800 gds_bo[i] = ws->buffer_create(ws, alloc_size, alignment, domain, 0);
801 assert(gds_bo[i]);
802 }
803
804 for (unsigned iterations = 0; iterations < 20000; iterations++) {
805 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
806 /* This clears GDS with CP DMA.
807 *
808 * We don't care if GDS is present. Just add some packet
809 * to make the GPU busy for a moment.
810 */
811 si_cp_dma_clear_buffer(sctx, cs[i], NULL, 0, alloc_size, 0,
812 SI_CPDMA_SKIP_BO_LIST_UPDATE |
813 SI_CPDMA_SKIP_CHECK_CS_SPACE |
814 SI_CPDMA_SKIP_GFX_SYNC, 0, 0);
815
816 ws->cs_add_buffer(cs[i], gds_bo[i], domain,
817 RADEON_USAGE_READWRITE, 0);
818 ws->cs_flush(cs[i], PIPE_FLUSH_ASYNC, NULL);
819 }
820 }
821 exit(0);
822 }
823
824 static void si_disk_cache_create(struct si_screen *sscreen)
825 {
826 /* Don't use the cache if shader dumping is enabled. */
827 if (sscreen->debug_flags & DBG_ALL_SHADERS)
828 return;
829
830 struct mesa_sha1 ctx;
831 unsigned char sha1[20];
832 char cache_id[20 * 2 + 1];
833
834 _mesa_sha1_init(&ctx);
835
836 if (!disk_cache_get_function_identifier(si_disk_cache_create, &ctx) ||
837 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo,
838 &ctx))
839 return;
840
841 _mesa_sha1_final(&ctx, sha1);
842 disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
843
844 /* These flags affect shader compilation. */
845 #define ALL_FLAGS (DBG(FS_CORRECT_DERIVS_AFTER_KILL) | \
846 DBG(SI_SCHED) | \
847 DBG(GISEL) | \
848 DBG(UNSAFE_MATH))
849 uint64_t shader_debug_flags = sscreen->debug_flags &
850 ALL_FLAGS;
851
852 /* Add the high bits of 32-bit addresses, which affects
853 * how 32-bit addresses are expanded to 64 bits.
854 */
855 STATIC_ASSERT(ALL_FLAGS <= UINT_MAX);
856 assert((int16_t)sscreen->info.address32_hi == (int32_t)sscreen->info.address32_hi);
857 shader_debug_flags |= (uint64_t)(sscreen->info.address32_hi & 0xffff) << 32;
858
859 if (sscreen->options.enable_nir)
860 shader_debug_flags |= 1ull << 48;
861
862 sscreen->disk_shader_cache =
863 disk_cache_create(sscreen->info.name,
864 cache_id,
865 shader_debug_flags);
866 }
867
868 static void si_set_max_shader_compiler_threads(struct pipe_screen *screen,
869 unsigned max_threads)
870 {
871 struct si_screen *sscreen = (struct si_screen *)screen;
872
873 /* This function doesn't allow a greater number of threads than
874 * the queue had at its creation. */
875 util_queue_adjust_num_threads(&sscreen->shader_compiler_queue,
876 max_threads);
877 /* Don't change the number of threads on the low priority queue. */
878 }
879
880 static bool si_is_parallel_shader_compilation_finished(struct pipe_screen *screen,
881 void *shader,
882 unsigned shader_type)
883 {
884 if (shader_type == PIPE_SHADER_COMPUTE) {
885 struct si_compute *cs = (struct si_compute*)shader;
886
887 return util_queue_fence_is_signalled(&cs->ready);
888 }
889 struct si_shader_selector *sel = (struct si_shader_selector *)shader;
890
891 return util_queue_fence_is_signalled(&sel->ready);
892 }
893
894 static struct pipe_screen *
895 radeonsi_screen_create_impl(struct radeon_winsys *ws,
896 const struct pipe_screen_config *config)
897 {
898 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
899 unsigned hw_threads, num_comp_hi_threads, num_comp_lo_threads, i;
900
901 if (!sscreen) {
902 return NULL;
903 }
904
905 sscreen->ws = ws;
906 ws->query_info(ws, &sscreen->info);
907
908 if (sscreen->info.chip_class == GFX10 && HAVE_LLVM < 0x0900) {
909 fprintf(stderr, "radeonsi: Navi family support requires LLVM 9 or higher\n");
910 FREE(sscreen);
911 return NULL;
912 }
913
914 if (sscreen->info.chip_class >= GFX9) {
915 sscreen->se_tile_repeat = 32 * sscreen->info.max_se;
916 } else {
917 ac_get_raster_config(&sscreen->info,
918 &sscreen->pa_sc_raster_config,
919 &sscreen->pa_sc_raster_config_1,
920 &sscreen->se_tile_repeat);
921 }
922
923 sscreen->debug_flags = debug_get_flags_option("R600_DEBUG",
924 debug_options, 0);
925 sscreen->debug_flags |= debug_get_flags_option("AMD_DEBUG",
926 debug_options, 0);
927
928 /* Set functions first. */
929 sscreen->b.context_create = si_pipe_create_context;
930 sscreen->b.destroy = si_destroy_screen;
931 sscreen->b.set_max_shader_compiler_threads =
932 si_set_max_shader_compiler_threads;
933 sscreen->b.is_parallel_shader_compilation_finished =
934 si_is_parallel_shader_compilation_finished;
935
936 si_init_screen_get_functions(sscreen);
937 si_init_screen_buffer_functions(sscreen);
938 si_init_screen_fence_functions(sscreen);
939 si_init_screen_state_functions(sscreen);
940 si_init_screen_texture_functions(sscreen);
941 si_init_screen_query_functions(sscreen);
942
943 /* Set these flags in debug_flags early, so that the shader cache takes
944 * them into account.
945 */
946 if (driQueryOptionb(config->options,
947 "glsl_correct_derivatives_after_discard"))
948 sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
949 if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
950 sscreen->debug_flags |= DBG(SI_SCHED);
951
952 if (sscreen->debug_flags & DBG(INFO))
953 ac_print_gpu_info(&sscreen->info);
954
955 slab_create_parent(&sscreen->pool_transfers,
956 sizeof(struct si_transfer), 64);
957
958 sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
959 if (sscreen->force_aniso == -1) {
960 sscreen->force_aniso = MIN2(16, debug_get_num_option("AMD_TEX_ANISO", -1));
961 }
962
963 if (sscreen->force_aniso >= 0) {
964 printf("radeonsi: Forcing anisotropy filter to %ix\n",
965 /* round down to a power of two */
966 1 << util_logbase2(sscreen->force_aniso));
967 }
968
969 (void) mtx_init(&sscreen->aux_context_lock, mtx_plain);
970 (void) mtx_init(&sscreen->gpu_load_mutex, mtx_plain);
971
972 si_init_gs_info(sscreen);
973 if (!si_init_shader_cache(sscreen)) {
974 FREE(sscreen);
975 return NULL;
976 }
977
978 si_disk_cache_create(sscreen);
979
980 /* Determine the number of shader compiler threads. */
981 hw_threads = sysconf(_SC_NPROCESSORS_ONLN);
982
983 if (hw_threads >= 12) {
984 num_comp_hi_threads = hw_threads * 3 / 4;
985 num_comp_lo_threads = hw_threads / 3;
986 } else if (hw_threads >= 6) {
987 num_comp_hi_threads = hw_threads - 2;
988 num_comp_lo_threads = hw_threads / 2;
989 } else if (hw_threads >= 2) {
990 num_comp_hi_threads = hw_threads - 1;
991 num_comp_lo_threads = hw_threads / 2;
992 } else {
993 num_comp_hi_threads = 1;
994 num_comp_lo_threads = 1;
995 }
996
997 num_comp_hi_threads = MIN2(num_comp_hi_threads,
998 ARRAY_SIZE(sscreen->compiler));
999 num_comp_lo_threads = MIN2(num_comp_lo_threads,
1000 ARRAY_SIZE(sscreen->compiler_lowp));
1001
1002 if (!util_queue_init(&sscreen->shader_compiler_queue, "sh",
1003 64, num_comp_hi_threads,
1004 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1005 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY)) {
1006 si_destroy_shader_cache(sscreen);
1007 FREE(sscreen);
1008 return NULL;
1009 }
1010
1011 if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
1012 "shlo",
1013 64, num_comp_lo_threads,
1014 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1015 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY |
1016 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
1017 si_destroy_shader_cache(sscreen);
1018 FREE(sscreen);
1019 return NULL;
1020 }
1021
1022 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1023 si_init_perfcounters(sscreen);
1024
1025 /* Determine tessellation ring info. */
1026 bool double_offchip_buffers = sscreen->info.chip_class >= GFX7 &&
1027 sscreen->info.family != CHIP_CARRIZO &&
1028 sscreen->info.family != CHIP_STONEY;
1029 /* This must be one less than the maximum number due to a hw limitation.
1030 * Various hardware bugs need this.
1031 */
1032 unsigned max_offchip_buffers_per_se;
1033
1034 if (sscreen->info.chip_class >= GFX10)
1035 max_offchip_buffers_per_se = 256;
1036 /* Only certain chips can use the maximum value. */
1037 else if (sscreen->info.family == CHIP_VEGA12 ||
1038 sscreen->info.family == CHIP_VEGA20)
1039 max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1040 else
1041 max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
1042
1043 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1044 sscreen->info.max_se;
1045 unsigned offchip_granularity;
1046
1047 /* Hawaii has a bug with offchip buffers > 256 that can be worked
1048 * around by setting 4K granularity.
1049 */
1050 if (sscreen->info.family == CHIP_HAWAII) {
1051 sscreen->tess_offchip_block_dw_size = 4096;
1052 offchip_granularity = V_03093C_X_4K_DWORDS;
1053 } else {
1054 sscreen->tess_offchip_block_dw_size = 8192;
1055 offchip_granularity = V_03093C_X_8K_DWORDS;
1056 }
1057
1058 sscreen->tess_factor_ring_size = 32768 * sscreen->info.max_se;
1059 assert(((sscreen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
1060 sscreen->tess_offchip_ring_size = max_offchip_buffers *
1061 sscreen->tess_offchip_block_dw_size * 4;
1062
1063 if (sscreen->info.chip_class >= GFX7) {
1064 if (sscreen->info.chip_class >= GFX8)
1065 --max_offchip_buffers;
1066 sscreen->vgt_hs_offchip_param =
1067 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1068 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1069 } else {
1070 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
1071 sscreen->vgt_hs_offchip_param =
1072 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1073 }
1074
1075 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
1076 * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
1077 * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel.*/
1078 sscreen->has_clear_state = sscreen->info.chip_class >= GFX7 &&
1079 sscreen->info.is_amdgpu;
1080
1081 sscreen->has_distributed_tess =
1082 sscreen->info.chip_class >= GFX8 &&
1083 sscreen->info.max_se >= 2;
1084
1085 sscreen->has_draw_indirect_multi =
1086 (sscreen->info.family >= CHIP_POLARIS10) ||
1087 (sscreen->info.chip_class == GFX8 &&
1088 sscreen->info.pfp_fw_version >= 121 &&
1089 sscreen->info.me_fw_version >= 87) ||
1090 (sscreen->info.chip_class == GFX7 &&
1091 sscreen->info.pfp_fw_version >= 211 &&
1092 sscreen->info.me_fw_version >= 173) ||
1093 (sscreen->info.chip_class == GFX6 &&
1094 sscreen->info.pfp_fw_version >= 79 &&
1095 sscreen->info.me_fw_version >= 142);
1096
1097 sscreen->has_out_of_order_rast = sscreen->info.chip_class >= GFX8 &&
1098 sscreen->info.max_se >= 2 &&
1099 !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER));
1100 sscreen->assume_no_z_fights =
1101 driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
1102 sscreen->commutative_blend_add =
1103 driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
1104
1105 {
1106 #define OPT_BOOL(name, dflt, description) \
1107 sscreen->options.name = \
1108 driQueryOptionb(config->options, "radeonsi_"#name);
1109 #include "si_debug_options.h"
1110 }
1111
1112 sscreen->has_gfx9_scissor_bug = sscreen->info.family == CHIP_VEGA10 ||
1113 sscreen->info.family == CHIP_RAVEN;
1114 sscreen->has_msaa_sample_loc_bug = (sscreen->info.family >= CHIP_POLARIS10 &&
1115 sscreen->info.family <= CHIP_POLARIS12) ||
1116 sscreen->info.family == CHIP_VEGA10 ||
1117 sscreen->info.family == CHIP_RAVEN;
1118 sscreen->has_ls_vgpr_init_bug = sscreen->info.family == CHIP_VEGA10 ||
1119 sscreen->info.family == CHIP_RAVEN;
1120 sscreen->has_dcc_constant_encode = sscreen->info.family == CHIP_RAVEN2;
1121
1122 /* Only enable primitive binning on APUs by default. */
1123 sscreen->dpbb_allowed = sscreen->info.family == CHIP_RAVEN ||
1124 sscreen->info.family == CHIP_RAVEN2;
1125
1126 sscreen->dfsm_allowed = sscreen->info.family == CHIP_RAVEN ||
1127 sscreen->info.family == CHIP_RAVEN2;
1128
1129 /* Process DPBB enable flags. */
1130 if (sscreen->debug_flags & DBG(DPBB)) {
1131 sscreen->dpbb_allowed = true;
1132 if (sscreen->debug_flags & DBG(DFSM))
1133 sscreen->dfsm_allowed = true;
1134 }
1135
1136 /* Process DPBB disable flags. */
1137 if (sscreen->debug_flags & DBG(NO_DPBB)) {
1138 sscreen->dpbb_allowed = false;
1139 sscreen->dfsm_allowed = false;
1140 } else if (sscreen->debug_flags & DBG(NO_DFSM)) {
1141 sscreen->dfsm_allowed = false;
1142 }
1143
1144 /* While it would be nice not to have this flag, we are constrained
1145 * by the reality that LLVM 9.0 has buggy VGPR indexing on GFX9.
1146 */
1147 sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class != GFX9;
1148
1149 /* Some chips have RB+ registers, but don't support RB+. Those must
1150 * always disable it.
1151 */
1152 if (sscreen->info.family == CHIP_STONEY ||
1153 sscreen->info.chip_class >= GFX9) {
1154 sscreen->has_rbplus = true;
1155
1156 sscreen->rbplus_allowed =
1157 !(sscreen->debug_flags & DBG(NO_RB_PLUS)) &&
1158 (sscreen->info.family == CHIP_STONEY ||
1159 sscreen->info.family == CHIP_VEGA12 ||
1160 sscreen->info.family == CHIP_RAVEN ||
1161 sscreen->info.family == CHIP_RAVEN2);
1162 }
1163
1164 sscreen->dcc_msaa_allowed =
1165 !(sscreen->debug_flags & DBG(NO_DCC_MSAA));
1166
1167 sscreen->cpdma_prefetch_writes_memory = sscreen->info.chip_class <= GFX8;
1168
1169 (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1170 sscreen->use_monolithic_shaders =
1171 (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
1172
1173 sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SCACHE |
1174 SI_CONTEXT_INV_VCACHE;
1175 if (sscreen->info.chip_class <= GFX8) {
1176 sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_L2;
1177 sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WB_L2;
1178 }
1179
1180 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1181 sscreen->debug_flags |= DBG_ALL_SHADERS;
1182
1183 /* Syntax:
1184 * EQAA=s,z,c
1185 * Example:
1186 * EQAA=8,4,2
1187
1188 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1189 * Constraints:
1190 * s >= z >= c (ignoring this only wastes memory)
1191 * s = [2..16]
1192 * z = [2..8]
1193 * c = [2..8]
1194 *
1195 * Only MSAA color and depth buffers are overriden.
1196 */
1197 if (sscreen->info.has_eqaa_surface_allocator) {
1198 const char *eqaa = debug_get_option("EQAA", NULL);
1199 unsigned s,z,f;
1200
1201 if (eqaa && sscanf(eqaa, "%u,%u,%u", &s, &z, &f) == 3 && s && z && f) {
1202 sscreen->eqaa_force_coverage_samples = s;
1203 sscreen->eqaa_force_z_samples = z;
1204 sscreen->eqaa_force_color_samples = f;
1205 }
1206 }
1207
1208 for (i = 0; i < num_comp_hi_threads; i++)
1209 si_init_compiler(sscreen, &sscreen->compiler[i]);
1210 for (i = 0; i < num_comp_lo_threads; i++)
1211 si_init_compiler(sscreen, &sscreen->compiler_lowp[i]);
1212
1213 /* Create the auxiliary context. This must be done last. */
1214 sscreen->aux_context = si_create_context(
1215 &sscreen->b, sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0);
1216 if (sscreen->options.aux_debug) {
1217 struct u_log_context *log = CALLOC_STRUCT(u_log_context);
1218 u_log_context_init(log);
1219 sscreen->aux_context->set_log_context(sscreen->aux_context, log);
1220 }
1221
1222 if (sscreen->debug_flags & DBG(TEST_DMA))
1223 si_test_dma(sscreen);
1224
1225 if (sscreen->debug_flags & DBG(TEST_DMA_PERF)) {
1226 si_test_dma_perf(sscreen);
1227 }
1228
1229 if (sscreen->debug_flags & (DBG(TEST_VMFAULT_CP) |
1230 DBG(TEST_VMFAULT_SDMA) |
1231 DBG(TEST_VMFAULT_SHADER)))
1232 si_test_vmfault(sscreen);
1233
1234 if (sscreen->debug_flags & DBG(TEST_GDS))
1235 si_test_gds((struct si_context*)sscreen->aux_context);
1236
1237 if (sscreen->debug_flags & DBG(TEST_GDS_MM)) {
1238 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1239 32 * 1024, 4, RADEON_DOMAIN_GDS);
1240 }
1241 if (sscreen->debug_flags & DBG(TEST_GDS_OA_MM)) {
1242 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1243 4, 1, RADEON_DOMAIN_OA);
1244 }
1245
1246 return &sscreen->b;
1247 }
1248
1249 struct pipe_screen *radeonsi_screen_create(int fd, const struct pipe_screen_config *config)
1250 {
1251 drmVersionPtr version = drmGetVersion(fd);
1252 struct radeon_winsys *rw = NULL;
1253
1254 switch (version->version_major) {
1255 case 2:
1256 rw = radeon_drm_winsys_create(fd, config, radeonsi_screen_create_impl);
1257 break;
1258 case 3:
1259 rw = amdgpu_winsys_create(fd, config, radeonsi_screen_create_impl);
1260 break;
1261 }
1262
1263 drmFreeVersion(version);
1264 return rw ? rw->screen : NULL;
1265 }