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radeonsi/gfx10: add debug options to enable/disable Wave32
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "si_pipe.h"
27 #include "si_public.h"
28 #include "si_shader_internal.h"
29 #include "si_compute.h"
30 #include "sid.h"
31
32 #include "ac_llvm_util.h"
33 #include "radeon/radeon_uvd.h"
34 #include "gallivm/lp_bld_misc.h"
35 #include "util/disk_cache.h"
36 #include "util/u_log.h"
37 #include "util/u_memory.h"
38 #include "util/u_suballoc.h"
39 #include "util/u_tests.h"
40 #include "util/u_upload_mgr.h"
41 #include "util/xmlconfig.h"
42 #include "vl/vl_decoder.h"
43 #include "driver_ddebug/dd_util.h"
44
45 #include "gallium/winsys/radeon/drm/radeon_drm_public.h"
46 #include "gallium/winsys/amdgpu/drm/amdgpu_public.h"
47 #include <xf86drm.h>
48
49 static const struct debug_named_value debug_options[] = {
50 /* Shader logging options: */
51 { "vs", DBG(VS), "Print vertex shaders" },
52 { "ps", DBG(PS), "Print pixel shaders" },
53 { "gs", DBG(GS), "Print geometry shaders" },
54 { "tcs", DBG(TCS), "Print tessellation control shaders" },
55 { "tes", DBG(TES), "Print tessellation evaluation shaders" },
56 { "cs", DBG(CS), "Print compute shaders" },
57 { "noir", DBG(NO_IR), "Don't print the LLVM IR"},
58 { "notgsi", DBG(NO_TGSI), "Don't print the TGSI"},
59 { "noasm", DBG(NO_ASM), "Don't print disassembled shaders"},
60 { "preoptir", DBG(PREOPT_IR), "Print the LLVM IR before initial optimizations" },
61
62 /* Shader compiler options the shader cache should be aware of: */
63 { "unsafemath", DBG(UNSAFE_MATH), "Enable unsafe math shader optimizations" },
64 { "sisched", DBG(SI_SCHED), "Enable LLVM SI Machine Instruction Scheduler." },
65 { "gisel", DBG(GISEL), "Enable LLVM global instruction selector." },
66 { "w32ge", DBG(W32_GE), "Use Wave32 for vertex, tessellation, and geometry shaders." },
67 { "w32ps", DBG(W32_PS), "Use Wave32 for pixel shaders." },
68 { "w32cs", DBG(W32_CS), "Use Wave32 for computes shaders." },
69 { "w64ge", DBG(W64_GE), "Use Wave64 for vertex, tessellation, and geometry shaders." },
70 { "w64ps", DBG(W64_PS), "Use Wave64 for pixel shaders." },
71 { "w64cs", DBG(W64_CS), "Use Wave64 for computes shaders." },
72
73 /* Shader compiler options (with no effect on the shader cache): */
74 { "checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR" },
75 { "mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand" },
76 { "nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants." },
77
78 /* Information logging options: */
79 { "info", DBG(INFO), "Print driver information" },
80 { "tex", DBG(TEX), "Print texture info" },
81 { "compute", DBG(COMPUTE), "Print compute info" },
82 { "vm", DBG(VM), "Print virtual addresses when creating resources" },
83
84 /* Driver options: */
85 { "forcedma", DBG(FORCE_DMA), "Use asynchronous DMA for all operations when possible." },
86 { "nodma", DBG(NO_ASYNC_DMA), "Disable asynchronous DMA" },
87 { "nowc", DBG(NO_WC), "Disable GTT write combining" },
88 { "check_vm", DBG(CHECK_VM), "Check VM faults and dump debug info." },
89 { "reserve_vmid", DBG(RESERVE_VMID), "Force VMID reservation per context." },
90 { "zerovram", DBG(ZERO_VRAM), "Clear VRAM allocations." },
91
92 /* 3D engine options: */
93 { "alwayspd", DBG(ALWAYS_PD), "Always enable the primitive discard compute shader." },
94 { "pd", DBG(PD), "Enable the primitive discard compute shader for large draw calls." },
95 { "nopd", DBG(NO_PD), "Disable the primitive discard compute shader." },
96 { "switch_on_eop", DBG(SWITCH_ON_EOP), "Program WD/IA to switch on end-of-packet." },
97 { "nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order rasterization" },
98 { "nodpbb", DBG(NO_DPBB), "Disable DPBB." },
99 { "nodfsm", DBG(NO_DFSM), "Disable DFSM." },
100 { "dpbb", DBG(DPBB), "Enable DPBB." },
101 { "dfsm", DBG(DFSM), "Enable DFSM." },
102 { "nohyperz", DBG(NO_HYPERZ), "Disable Hyper-Z" },
103 { "norbplus", DBG(NO_RB_PLUS), "Disable RB+." },
104 { "no2d", DBG(NO_2D_TILING), "Disable 2D tiling" },
105 { "notiling", DBG(NO_TILING), "Disable tiling" },
106 { "nodcc", DBG(NO_DCC), "Disable DCC." },
107 { "nodccclear", DBG(NO_DCC_CLEAR), "Disable DCC fast clear." },
108 { "nodccfb", DBG(NO_DCC_FB), "Disable separate DCC on the main framebuffer" },
109 { "nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA" },
110 { "nofmask", DBG(NO_FMASK), "Disable MSAA compression" },
111
112 /* Tests: */
113 { "testdma", DBG(TEST_DMA), "Invoke SDMA tests and exit." },
114 { "testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and exit." },
115 { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA), "Invoke a SDMA VM fault test and exit." },
116 { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM fault test and exit." },
117 { "testdmaperf", DBG(TEST_DMA_PERF), "Test DMA performance" },
118 { "testgds", DBG(TEST_GDS), "Test GDS." },
119 { "testgdsmm", DBG(TEST_GDS_MM), "Test GDS memory management." },
120 { "testgdsoamm", DBG(TEST_GDS_OA_MM), "Test GDS OA memory management." },
121
122 DEBUG_NAMED_VALUE_END /* must be last */
123 };
124
125 static void si_init_compiler(struct si_screen *sscreen,
126 struct ac_llvm_compiler *compiler)
127 {
128 /* Only create the less-optimizing version of the compiler on APUs
129 * predating Ryzen (Raven). */
130 bool create_low_opt_compiler = !sscreen->info.has_dedicated_vram &&
131 sscreen->info.chip_class <= GFX8;
132
133 enum ac_target_machine_options tm_options =
134 (sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
135 (sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL : 0) |
136 (sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
137 (sscreen->info.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
138 (!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0) |
139 (sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0) |
140 (create_low_opt_compiler ? AC_TM_CREATE_LOW_OPT : 0);
141
142 ac_init_llvm_once();
143 ac_init_llvm_compiler(compiler, sscreen->info.family, tm_options);
144 compiler->passes = ac_create_llvm_passes(compiler->tm);
145
146 if (compiler->tm_wave32)
147 compiler->passes_wave32 = ac_create_llvm_passes(compiler->tm_wave32);
148 if (compiler->low_opt_tm)
149 compiler->low_opt_passes = ac_create_llvm_passes(compiler->low_opt_tm);
150 }
151
152 static void si_destroy_compiler(struct ac_llvm_compiler *compiler)
153 {
154 ac_destroy_llvm_compiler(compiler);
155 }
156
157 /*
158 * pipe_context
159 */
160 static void si_destroy_context(struct pipe_context *context)
161 {
162 struct si_context *sctx = (struct si_context *)context;
163 int i;
164
165 util_queue_finish(&sctx->screen->shader_compiler_queue);
166 util_queue_finish(&sctx->screen->shader_compiler_queue_low_priority);
167
168 /* Unreference the framebuffer normally to disable related logic
169 * properly.
170 */
171 struct pipe_framebuffer_state fb = {};
172 if (context->set_framebuffer_state)
173 context->set_framebuffer_state(context, &fb);
174
175 si_release_all_descriptors(sctx);
176
177 if (sctx->chip_class >= GFX10)
178 gfx10_destroy_query(sctx);
179
180 pipe_resource_reference(&sctx->esgs_ring, NULL);
181 pipe_resource_reference(&sctx->gsvs_ring, NULL);
182 pipe_resource_reference(&sctx->tess_rings, NULL);
183 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
184 pipe_resource_reference(&sctx->sample_pos_buffer, NULL);
185 si_resource_reference(&sctx->border_color_buffer, NULL);
186 free(sctx->border_color_table);
187 si_resource_reference(&sctx->scratch_buffer, NULL);
188 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
189 si_resource_reference(&sctx->wait_mem_scratch, NULL);
190
191 si_pm4_free_state(sctx, sctx->init_config, ~0);
192 if (sctx->init_config_gs_rings)
193 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
194 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
195 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
196
197 if (sctx->fixed_func_tcs_shader.cso)
198 sctx->b.delete_tcs_state(&sctx->b, sctx->fixed_func_tcs_shader.cso);
199 if (sctx->custom_dsa_flush)
200 sctx->b.delete_depth_stencil_alpha_state(&sctx->b, sctx->custom_dsa_flush);
201 if (sctx->custom_blend_resolve)
202 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_resolve);
203 if (sctx->custom_blend_fmask_decompress)
204 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_fmask_decompress);
205 if (sctx->custom_blend_eliminate_fastclear)
206 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_eliminate_fastclear);
207 if (sctx->custom_blend_dcc_decompress)
208 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_dcc_decompress);
209 if (sctx->vs_blit_pos)
210 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos);
211 if (sctx->vs_blit_pos_layered)
212 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos_layered);
213 if (sctx->vs_blit_color)
214 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color);
215 if (sctx->vs_blit_color_layered)
216 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color_layered);
217 if (sctx->vs_blit_texcoord)
218 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_texcoord);
219 if (sctx->cs_clear_buffer)
220 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_buffer);
221 if (sctx->cs_copy_buffer)
222 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_buffer);
223 if (sctx->cs_copy_image)
224 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image);
225 if (sctx->cs_copy_image_1d_array)
226 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image_1d_array);
227 if (sctx->cs_clear_render_target)
228 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target);
229 if (sctx->cs_clear_render_target_1d_array)
230 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target_1d_array);
231 if (sctx->cs_dcc_retile)
232 sctx->b.delete_compute_state(&sctx->b, sctx->cs_dcc_retile);
233
234 if (sctx->blitter)
235 util_blitter_destroy(sctx->blitter);
236
237 /* Release DCC stats. */
238 for (int i = 0; i < ARRAY_SIZE(sctx->dcc_stats); i++) {
239 assert(!sctx->dcc_stats[i].query_active);
240
241 for (int j = 0; j < ARRAY_SIZE(sctx->dcc_stats[i].ps_stats); j++)
242 if (sctx->dcc_stats[i].ps_stats[j])
243 sctx->b.destroy_query(&sctx->b,
244 sctx->dcc_stats[i].ps_stats[j]);
245
246 si_texture_reference(&sctx->dcc_stats[i].tex, NULL);
247 }
248
249 if (sctx->query_result_shader)
250 sctx->b.delete_compute_state(&sctx->b, sctx->query_result_shader);
251 if (sctx->sh_query_result_shader)
252 sctx->b.delete_compute_state(&sctx->b, sctx->sh_query_result_shader);
253
254 if (sctx->gfx_cs)
255 sctx->ws->cs_destroy(sctx->gfx_cs);
256 if (sctx->dma_cs)
257 sctx->ws->cs_destroy(sctx->dma_cs);
258 if (sctx->ctx)
259 sctx->ws->ctx_destroy(sctx->ctx);
260
261 if (sctx->b.stream_uploader)
262 u_upload_destroy(sctx->b.stream_uploader);
263 if (sctx->b.const_uploader)
264 u_upload_destroy(sctx->b.const_uploader);
265 if (sctx->cached_gtt_allocator)
266 u_upload_destroy(sctx->cached_gtt_allocator);
267
268 slab_destroy_child(&sctx->pool_transfers);
269 slab_destroy_child(&sctx->pool_transfers_unsync);
270
271 if (sctx->allocator_zeroed_memory)
272 u_suballocator_destroy(sctx->allocator_zeroed_memory);
273
274 sctx->ws->fence_reference(&sctx->last_gfx_fence, NULL);
275 sctx->ws->fence_reference(&sctx->last_sdma_fence, NULL);
276 sctx->ws->fence_reference(&sctx->last_ib_barrier_fence, NULL);
277 si_resource_reference(&sctx->eop_bug_scratch, NULL);
278 si_resource_reference(&sctx->index_ring, NULL);
279 si_resource_reference(&sctx->barrier_buf, NULL);
280 si_resource_reference(&sctx->last_ib_barrier_buf, NULL);
281 pb_reference(&sctx->gds, NULL);
282 pb_reference(&sctx->gds_oa, NULL);
283
284 si_destroy_compiler(&sctx->compiler);
285
286 si_saved_cs_reference(&sctx->current_saved_cs, NULL);
287
288 _mesa_hash_table_destroy(sctx->tex_handles, NULL);
289 _mesa_hash_table_destroy(sctx->img_handles, NULL);
290
291 util_dynarray_fini(&sctx->resident_tex_handles);
292 util_dynarray_fini(&sctx->resident_img_handles);
293 util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
294 util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
295 util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
296 si_unref_sdma_uploads(sctx);
297 FREE(sctx);
298 }
299
300 static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx)
301 {
302 struct si_context *sctx = (struct si_context *)ctx;
303
304 return sctx->ws->ctx_query_reset_status(sctx->ctx);
305 }
306
307 static void si_set_device_reset_callback(struct pipe_context *ctx,
308 const struct pipe_device_reset_callback *cb)
309 {
310 struct si_context *sctx = (struct si_context *)ctx;
311
312 if (cb)
313 sctx->device_reset_callback = *cb;
314 else
315 memset(&sctx->device_reset_callback, 0,
316 sizeof(sctx->device_reset_callback));
317 }
318
319 bool si_check_device_reset(struct si_context *sctx)
320 {
321 enum pipe_reset_status status;
322
323 if (!sctx->device_reset_callback.reset)
324 return false;
325
326 status = sctx->ws->ctx_query_reset_status(sctx->ctx);
327 if (status == PIPE_NO_RESET)
328 return false;
329
330 sctx->device_reset_callback.reset(sctx->device_reset_callback.data, status);
331 return true;
332 }
333
334 /* Apitrace profiling:
335 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
336 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
337 * and remember its number.
338 * 3) In Mesa, enable queries and performance counters around that draw
339 * call and print the results.
340 * 4) glretrace --benchmark --markers ..
341 */
342 static void si_emit_string_marker(struct pipe_context *ctx,
343 const char *string, int len)
344 {
345 struct si_context *sctx = (struct si_context *)ctx;
346
347 dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
348
349 if (sctx->log)
350 u_log_printf(sctx->log, "\nString marker: %*s\n", len, string);
351 }
352
353 static void si_set_debug_callback(struct pipe_context *ctx,
354 const struct pipe_debug_callback *cb)
355 {
356 struct si_context *sctx = (struct si_context *)ctx;
357 struct si_screen *screen = sctx->screen;
358
359 util_queue_finish(&screen->shader_compiler_queue);
360 util_queue_finish(&screen->shader_compiler_queue_low_priority);
361
362 if (cb)
363 sctx->debug = *cb;
364 else
365 memset(&sctx->debug, 0, sizeof(sctx->debug));
366 }
367
368 static void si_set_log_context(struct pipe_context *ctx,
369 struct u_log_context *log)
370 {
371 struct si_context *sctx = (struct si_context *)ctx;
372 sctx->log = log;
373
374 if (log)
375 u_log_add_auto_logger(log, si_auto_log_cs, sctx);
376 }
377
378 static void si_set_context_param(struct pipe_context *ctx,
379 enum pipe_context_param param,
380 unsigned value)
381 {
382 struct radeon_winsys *ws = ((struct si_context *)ctx)->ws;
383
384 switch (param) {
385 case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE:
386 ws->pin_threads_to_L3_cache(ws, value);
387 break;
388 default:;
389 }
390 }
391
392 static struct pipe_context *si_create_context(struct pipe_screen *screen,
393 unsigned flags)
394 {
395 struct si_context *sctx = CALLOC_STRUCT(si_context);
396 struct si_screen* sscreen = (struct si_screen *)screen;
397 struct radeon_winsys *ws = sscreen->ws;
398 int shader, i;
399 bool stop_exec_on_failure = (flags & PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET) != 0;
400
401 if (!sctx)
402 return NULL;
403
404 sctx->has_graphics = sscreen->info.chip_class == GFX6 ||
405 !(flags & PIPE_CONTEXT_COMPUTE_ONLY);
406
407 if (flags & PIPE_CONTEXT_DEBUG)
408 sscreen->record_llvm_ir = true; /* racy but not critical */
409
410 sctx->b.screen = screen; /* this must be set first */
411 sctx->b.priv = NULL;
412 sctx->b.destroy = si_destroy_context;
413 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
414 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
415
416 slab_create_child(&sctx->pool_transfers, &sscreen->pool_transfers);
417 slab_create_child(&sctx->pool_transfers_unsync, &sscreen->pool_transfers);
418
419 sctx->ws = sscreen->ws;
420 sctx->family = sscreen->info.family;
421 sctx->chip_class = sscreen->info.chip_class;
422
423 if (sctx->chip_class == GFX7 ||
424 sctx->chip_class == GFX8 ||
425 sctx->chip_class == GFX9) {
426 sctx->eop_bug_scratch = si_resource(
427 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
428 16 * sscreen->info.num_render_backends));
429 if (!sctx->eop_bug_scratch)
430 goto fail;
431 }
432
433 /* Initialize context allocators. */
434 sctx->allocator_zeroed_memory =
435 u_suballocator_create(&sctx->b, 128 * 1024,
436 0, PIPE_USAGE_DEFAULT,
437 SI_RESOURCE_FLAG_UNMAPPABLE |
438 SI_RESOURCE_FLAG_CLEAR, false);
439 if (!sctx->allocator_zeroed_memory)
440 goto fail;
441
442 sctx->b.stream_uploader = u_upload_create(&sctx->b, 1024 * 1024,
443 0, PIPE_USAGE_STREAM,
444 SI_RESOURCE_FLAG_READ_ONLY);
445 if (!sctx->b.stream_uploader)
446 goto fail;
447
448 sctx->cached_gtt_allocator = u_upload_create(&sctx->b, 16 * 1024,
449 0, PIPE_USAGE_STAGING, 0);
450 if (!sctx->cached_gtt_allocator)
451 goto fail;
452
453 sctx->ctx = sctx->ws->ctx_create(sctx->ws);
454 if (!sctx->ctx)
455 goto fail;
456
457 if (sscreen->info.num_sdma_rings && !(sscreen->debug_flags & DBG(NO_ASYNC_DMA))) {
458 sctx->dma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA,
459 (void*)si_flush_dma_cs,
460 sctx, stop_exec_on_failure);
461 }
462
463 bool use_sdma_upload = sscreen->info.has_dedicated_vram && sctx->dma_cs;
464 sctx->b.const_uploader = u_upload_create(&sctx->b, 256 * 1024,
465 0, PIPE_USAGE_DEFAULT,
466 SI_RESOURCE_FLAG_32BIT |
467 (use_sdma_upload ?
468 SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA : 0));
469 if (!sctx->b.const_uploader)
470 goto fail;
471
472 if (use_sdma_upload)
473 u_upload_enable_flush_explicit(sctx->b.const_uploader);
474
475 sctx->gfx_cs = ws->cs_create(sctx->ctx,
476 sctx->has_graphics ? RING_GFX : RING_COMPUTE,
477 (void*)si_flush_gfx_cs, sctx, stop_exec_on_failure);
478
479 /* Border colors. */
480 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
481 sizeof(*sctx->border_color_table));
482 if (!sctx->border_color_table)
483 goto fail;
484
485 sctx->border_color_buffer = si_resource(
486 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
487 SI_MAX_BORDER_COLORS *
488 sizeof(*sctx->border_color_table)));
489 if (!sctx->border_color_buffer)
490 goto fail;
491
492 sctx->border_color_map =
493 ws->buffer_map(sctx->border_color_buffer->buf,
494 NULL, PIPE_TRANSFER_WRITE);
495 if (!sctx->border_color_map)
496 goto fail;
497
498 sctx->ngg = sctx->chip_class >= GFX10;
499
500 /* Initialize context functions used by graphics and compute. */
501 if (sctx->chip_class >= GFX10)
502 sctx->emit_cache_flush = gfx10_emit_cache_flush;
503 else
504 sctx->emit_cache_flush = si_emit_cache_flush;
505
506 sctx->b.emit_string_marker = si_emit_string_marker;
507 sctx->b.set_debug_callback = si_set_debug_callback;
508 sctx->b.set_log_context = si_set_log_context;
509 sctx->b.set_context_param = si_set_context_param;
510 sctx->b.get_device_reset_status = si_get_reset_status;
511 sctx->b.set_device_reset_callback = si_set_device_reset_callback;
512
513 si_init_all_descriptors(sctx);
514 si_init_buffer_functions(sctx);
515 si_init_clear_functions(sctx);
516 si_init_blit_functions(sctx);
517 si_init_compute_functions(sctx);
518 si_init_compute_blit_functions(sctx);
519 si_init_debug_functions(sctx);
520 si_init_fence_functions(sctx);
521 si_init_query_functions(sctx);
522 si_init_state_compute_functions(sctx);
523
524 /* Initialize graphics-only context functions. */
525 if (sctx->has_graphics) {
526 si_init_context_texture_functions(sctx);
527 if (sctx->chip_class >= GFX10)
528 gfx10_init_query(sctx);
529 si_init_msaa_functions(sctx);
530 si_init_shader_functions(sctx);
531 si_init_state_functions(sctx);
532 si_init_streamout_functions(sctx);
533 si_init_viewport_functions(sctx);
534
535 sctx->blitter = util_blitter_create(&sctx->b);
536 if (sctx->blitter == NULL)
537 goto fail;
538 sctx->blitter->skip_viewport_restore = true;
539
540 si_init_draw_functions(sctx);
541 si_initialize_prim_discard_tunables(sctx);
542 }
543
544 /* Initialize SDMA functions. */
545 if (sctx->chip_class >= GFX7)
546 cik_init_sdma_functions(sctx);
547 else
548 si_init_dma_functions(sctx);
549
550 if (sscreen->debug_flags & DBG(FORCE_DMA))
551 sctx->b.resource_copy_region = sctx->dma_copy;
552
553 sctx->sample_mask = 0xffff;
554
555 /* Initialize multimedia functions. */
556 if (sscreen->info.has_hw_decode) {
557 sctx->b.create_video_codec = si_uvd_create_decoder;
558 sctx->b.create_video_buffer = si_video_buffer_create;
559 } else {
560 sctx->b.create_video_codec = vl_create_decoder;
561 sctx->b.create_video_buffer = vl_video_buffer_create;
562 }
563
564 if (sctx->chip_class >= GFX9) {
565 sctx->wait_mem_scratch = si_resource(
566 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 8));
567 if (!sctx->wait_mem_scratch)
568 goto fail;
569
570 /* Initialize the memory. */
571 si_cp_write_data(sctx, sctx->wait_mem_scratch, 0, 4,
572 V_370_MEM, V_370_ME, &sctx->wait_mem_number);
573 }
574
575 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
576 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
577 if (sctx->chip_class == GFX7) {
578 sctx->null_const_buf.buffer =
579 pipe_aligned_buffer_create(screen,
580 SI_RESOURCE_FLAG_32BIT,
581 PIPE_USAGE_DEFAULT, 16,
582 sctx->screen->info.tcc_cache_line_size);
583 if (!sctx->null_const_buf.buffer)
584 goto fail;
585 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
586
587 unsigned start_shader = sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE;
588 for (shader = start_shader; shader < SI_NUM_SHADERS; shader++) {
589 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
590 sctx->b.set_constant_buffer(&sctx->b, shader, i,
591 &sctx->null_const_buf);
592 }
593 }
594
595 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
596 &sctx->null_const_buf);
597 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
598 &sctx->null_const_buf);
599 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
600 &sctx->null_const_buf);
601 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
602 &sctx->null_const_buf);
603 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
604 &sctx->null_const_buf);
605 }
606
607 uint64_t max_threads_per_block;
608 screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
609 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
610 &max_threads_per_block);
611
612 /* The maximum number of scratch waves. Scratch space isn't divided
613 * evenly between CUs. The number is only a function of the number of CUs.
614 * We can decrease the constant to decrease the scratch buffer size.
615 *
616 * sctx->scratch_waves must be >= the maximum posible size of
617 * 1 threadgroup, so that the hw doesn't hang from being unable
618 * to start any.
619 *
620 * The recommended value is 4 per CU at most. Higher numbers don't
621 * bring much benefit, but they still occupy chip resources (think
622 * async compute). I've seen ~2% performance difference between 4 and 32.
623 */
624 sctx->scratch_waves = MAX2(32 * sscreen->info.num_good_compute_units,
625 max_threads_per_block / 64);
626
627 si_init_compiler(sscreen, &sctx->compiler);
628
629 /* Bindless handles. */
630 sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
631 _mesa_key_pointer_equal);
632 sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
633 _mesa_key_pointer_equal);
634
635 util_dynarray_init(&sctx->resident_tex_handles, NULL);
636 util_dynarray_init(&sctx->resident_img_handles, NULL);
637 util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
638 util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
639 util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
640
641 sctx->sample_pos_buffer =
642 pipe_buffer_create(sctx->b.screen, 0, PIPE_USAGE_DEFAULT,
643 sizeof(sctx->sample_positions));
644 pipe_buffer_write(&sctx->b, sctx->sample_pos_buffer, 0,
645 sizeof(sctx->sample_positions), &sctx->sample_positions);
646
647 /* this must be last */
648 si_begin_new_gfx_cs(sctx);
649
650 if (sctx->chip_class == GFX7) {
651 /* Clear the NULL constant buffer, because loads should return zeros.
652 * Note that this forces CP DMA to be used, because clover deadlocks
653 * for some reason when the compute codepath is used.
654 */
655 uint32_t clear_value = 0;
656 si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0,
657 sctx->null_const_buf.buffer->width0,
658 &clear_value, 4, SI_COHERENCY_SHADER, true);
659 }
660 return &sctx->b;
661 fail:
662 fprintf(stderr, "radeonsi: Failed to create a context.\n");
663 si_destroy_context(&sctx->b);
664 return NULL;
665 }
666
667 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
668 void *priv, unsigned flags)
669 {
670 struct si_screen *sscreen = (struct si_screen *)screen;
671 struct pipe_context *ctx;
672
673 if (sscreen->debug_flags & DBG(CHECK_VM))
674 flags |= PIPE_CONTEXT_DEBUG;
675
676 ctx = si_create_context(screen, flags);
677
678 if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
679 return ctx;
680
681 /* Clover (compute-only) is unsupported. */
682 if (flags & PIPE_CONTEXT_COMPUTE_ONLY)
683 return ctx;
684
685 /* When shaders are logged to stderr, asynchronous compilation is
686 * disabled too. */
687 if (sscreen->debug_flags & DBG_ALL_SHADERS)
688 return ctx;
689
690 /* Use asynchronous flushes only on amdgpu, since the radeon
691 * implementation for fence_server_sync is incomplete. */
692 return threaded_context_create(ctx, &sscreen->pool_transfers,
693 si_replace_buffer_storage,
694 sscreen->info.is_amdgpu ? si_create_fence : NULL,
695 &((struct si_context*)ctx)->tc);
696 }
697
698 /*
699 * pipe_screen
700 */
701 static void si_destroy_screen(struct pipe_screen* pscreen)
702 {
703 struct si_screen *sscreen = (struct si_screen *)pscreen;
704 struct si_shader_part *parts[] = {
705 sscreen->vs_prologs,
706 sscreen->tcs_epilogs,
707 sscreen->gs_prologs,
708 sscreen->ps_prologs,
709 sscreen->ps_epilogs
710 };
711 unsigned i;
712
713 if (!sscreen->ws->unref(sscreen->ws))
714 return;
715
716 mtx_destroy(&sscreen->aux_context_lock);
717
718 struct u_log_context *aux_log = ((struct si_context *)sscreen->aux_context)->log;
719 if (aux_log) {
720 sscreen->aux_context->set_log_context(sscreen->aux_context, NULL);
721 u_log_context_destroy(aux_log);
722 FREE(aux_log);
723 }
724
725 sscreen->aux_context->destroy(sscreen->aux_context);
726
727 util_queue_destroy(&sscreen->shader_compiler_queue);
728 util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
729
730 for (i = 0; i < ARRAY_SIZE(sscreen->compiler); i++)
731 si_destroy_compiler(&sscreen->compiler[i]);
732
733 for (i = 0; i < ARRAY_SIZE(sscreen->compiler_lowp); i++)
734 si_destroy_compiler(&sscreen->compiler_lowp[i]);
735
736 /* Free shader parts. */
737 for (i = 0; i < ARRAY_SIZE(parts); i++) {
738 while (parts[i]) {
739 struct si_shader_part *part = parts[i];
740
741 parts[i] = part->next;
742 si_shader_binary_clean(&part->binary);
743 FREE(part);
744 }
745 }
746 mtx_destroy(&sscreen->shader_parts_mutex);
747 si_destroy_shader_cache(sscreen);
748
749 si_destroy_perfcounters(sscreen);
750 si_gpu_load_kill_thread(sscreen);
751
752 mtx_destroy(&sscreen->gpu_load_mutex);
753
754 slab_destroy_parent(&sscreen->pool_transfers);
755
756 disk_cache_destroy(sscreen->disk_shader_cache);
757 sscreen->ws->destroy(sscreen->ws);
758 FREE(sscreen);
759 }
760
761 static void si_init_gs_info(struct si_screen *sscreen)
762 {
763 sscreen->gs_table_depth = ac_get_gs_table_depth(sscreen->info.chip_class,
764 sscreen->info.family);
765 }
766
767 static void si_test_vmfault(struct si_screen *sscreen)
768 {
769 struct pipe_context *ctx = sscreen->aux_context;
770 struct si_context *sctx = (struct si_context *)ctx;
771 struct pipe_resource *buf =
772 pipe_buffer_create_const0(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 64);
773
774 if (!buf) {
775 puts("Buffer allocation failed.");
776 exit(1);
777 }
778
779 si_resource(buf)->gpu_address = 0; /* cause a VM fault */
780
781 if (sscreen->debug_flags & DBG(TEST_VMFAULT_CP)) {
782 si_cp_dma_copy_buffer(sctx, buf, buf, 0, 4, 4, 0,
783 SI_COHERENCY_NONE, L2_BYPASS);
784 ctx->flush(ctx, NULL, 0);
785 puts("VM fault test: CP - done.");
786 }
787 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SDMA)) {
788 si_sdma_clear_buffer(sctx, buf, 0, 4, 0);
789 ctx->flush(ctx, NULL, 0);
790 puts("VM fault test: SDMA - done.");
791 }
792 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SHADER)) {
793 util_test_constant_buffer(ctx, buf);
794 puts("VM fault test: Shader - done.");
795 }
796 exit(0);
797 }
798
799 static void si_test_gds_memory_management(struct si_context *sctx,
800 unsigned alloc_size, unsigned alignment,
801 enum radeon_bo_domain domain)
802 {
803 struct radeon_winsys *ws = sctx->ws;
804 struct radeon_cmdbuf *cs[8];
805 struct pb_buffer *gds_bo[ARRAY_SIZE(cs)];
806
807 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
808 cs[i] = ws->cs_create(sctx->ctx, RING_COMPUTE,
809 NULL, NULL, false);
810 gds_bo[i] = ws->buffer_create(ws, alloc_size, alignment, domain, 0);
811 assert(gds_bo[i]);
812 }
813
814 for (unsigned iterations = 0; iterations < 20000; iterations++) {
815 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
816 /* This clears GDS with CP DMA.
817 *
818 * We don't care if GDS is present. Just add some packet
819 * to make the GPU busy for a moment.
820 */
821 si_cp_dma_clear_buffer(sctx, cs[i], NULL, 0, alloc_size, 0,
822 SI_CPDMA_SKIP_BO_LIST_UPDATE |
823 SI_CPDMA_SKIP_CHECK_CS_SPACE |
824 SI_CPDMA_SKIP_GFX_SYNC, 0, 0);
825
826 ws->cs_add_buffer(cs[i], gds_bo[i], domain,
827 RADEON_USAGE_READWRITE, 0);
828 ws->cs_flush(cs[i], PIPE_FLUSH_ASYNC, NULL);
829 }
830 }
831 exit(0);
832 }
833
834 static void si_disk_cache_create(struct si_screen *sscreen)
835 {
836 /* Don't use the cache if shader dumping is enabled. */
837 if (sscreen->debug_flags & DBG_ALL_SHADERS)
838 return;
839
840 struct mesa_sha1 ctx;
841 unsigned char sha1[20];
842 char cache_id[20 * 2 + 1];
843
844 _mesa_sha1_init(&ctx);
845
846 if (!disk_cache_get_function_identifier(si_disk_cache_create, &ctx) ||
847 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo,
848 &ctx))
849 return;
850
851 _mesa_sha1_final(&ctx, sha1);
852 disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
853
854 /* These flags affect shader compilation. */
855 #define ALL_FLAGS (DBG(FS_CORRECT_DERIVS_AFTER_KILL) | \
856 DBG(SI_SCHED) | \
857 DBG(GISEL) | \
858 DBG(UNSAFE_MATH) | \
859 DBG(W32_GE) | \
860 DBG(W32_PS) | \
861 DBG(W32_CS) | \
862 DBG(W64_GE) | \
863 DBG(W64_PS) | \
864 DBG(W64_CS))
865 uint64_t shader_debug_flags = sscreen->debug_flags & ALL_FLAGS;
866
867 if (sscreen->options.enable_nir) {
868 STATIC_ASSERT((ALL_FLAGS & (1u << 31)) == 0);
869 shader_debug_flags |= 1u << 31;
870 }
871
872 /* Add the high bits of 32-bit addresses, which affects
873 * how 32-bit addresses are expanded to 64 bits.
874 */
875 STATIC_ASSERT(ALL_FLAGS <= UINT_MAX);
876 assert((int16_t)sscreen->info.address32_hi == (int32_t)sscreen->info.address32_hi);
877 shader_debug_flags |= (uint64_t)(sscreen->info.address32_hi & 0xffff) << 32;
878
879 sscreen->disk_shader_cache =
880 disk_cache_create(sscreen->info.name,
881 cache_id,
882 shader_debug_flags);
883 }
884
885 static void si_set_max_shader_compiler_threads(struct pipe_screen *screen,
886 unsigned max_threads)
887 {
888 struct si_screen *sscreen = (struct si_screen *)screen;
889
890 /* This function doesn't allow a greater number of threads than
891 * the queue had at its creation. */
892 util_queue_adjust_num_threads(&sscreen->shader_compiler_queue,
893 max_threads);
894 /* Don't change the number of threads on the low priority queue. */
895 }
896
897 static bool si_is_parallel_shader_compilation_finished(struct pipe_screen *screen,
898 void *shader,
899 enum pipe_shader_type shader_type)
900 {
901 struct si_shader_selector *sel = (struct si_shader_selector *)shader;
902
903 return util_queue_fence_is_signalled(&sel->ready);
904 }
905
906 static struct pipe_screen *
907 radeonsi_screen_create_impl(struct radeon_winsys *ws,
908 const struct pipe_screen_config *config)
909 {
910 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
911 unsigned hw_threads, num_comp_hi_threads, num_comp_lo_threads, i;
912
913 if (!sscreen) {
914 return NULL;
915 }
916
917 sscreen->ws = ws;
918 ws->query_info(ws, &sscreen->info);
919
920 if (sscreen->info.chip_class == GFX10 && HAVE_LLVM < 0x0900) {
921 fprintf(stderr, "radeonsi: Navi family support requires LLVM 9 or higher\n");
922 FREE(sscreen);
923 return NULL;
924 }
925
926 if (sscreen->info.chip_class >= GFX9) {
927 sscreen->se_tile_repeat = 32 * sscreen->info.max_se;
928 } else {
929 ac_get_raster_config(&sscreen->info,
930 &sscreen->pa_sc_raster_config,
931 &sscreen->pa_sc_raster_config_1,
932 &sscreen->se_tile_repeat);
933 }
934
935 sscreen->debug_flags = debug_get_flags_option("R600_DEBUG",
936 debug_options, 0);
937 sscreen->debug_flags |= debug_get_flags_option("AMD_DEBUG",
938 debug_options, 0);
939
940 /* Set functions first. */
941 sscreen->b.context_create = si_pipe_create_context;
942 sscreen->b.destroy = si_destroy_screen;
943 sscreen->b.set_max_shader_compiler_threads =
944 si_set_max_shader_compiler_threads;
945 sscreen->b.is_parallel_shader_compilation_finished =
946 si_is_parallel_shader_compilation_finished;
947
948 si_init_screen_get_functions(sscreen);
949 si_init_screen_buffer_functions(sscreen);
950 si_init_screen_fence_functions(sscreen);
951 si_init_screen_state_functions(sscreen);
952 si_init_screen_texture_functions(sscreen);
953 si_init_screen_query_functions(sscreen);
954
955 /* Set these flags in debug_flags early, so that the shader cache takes
956 * them into account.
957 */
958 if (driQueryOptionb(config->options,
959 "glsl_correct_derivatives_after_discard"))
960 sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
961 if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
962 sscreen->debug_flags |= DBG(SI_SCHED);
963
964 if (sscreen->debug_flags & DBG(INFO))
965 ac_print_gpu_info(&sscreen->info);
966
967 slab_create_parent(&sscreen->pool_transfers,
968 sizeof(struct si_transfer), 64);
969
970 sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
971 if (sscreen->force_aniso == -1) {
972 sscreen->force_aniso = MIN2(16, debug_get_num_option("AMD_TEX_ANISO", -1));
973 }
974
975 if (sscreen->force_aniso >= 0) {
976 printf("radeonsi: Forcing anisotropy filter to %ix\n",
977 /* round down to a power of two */
978 1 << util_logbase2(sscreen->force_aniso));
979 }
980
981 (void) mtx_init(&sscreen->aux_context_lock, mtx_plain);
982 (void) mtx_init(&sscreen->gpu_load_mutex, mtx_plain);
983
984 si_init_gs_info(sscreen);
985 if (!si_init_shader_cache(sscreen)) {
986 FREE(sscreen);
987 return NULL;
988 }
989
990 si_disk_cache_create(sscreen);
991
992 /* Determine the number of shader compiler threads. */
993 hw_threads = sysconf(_SC_NPROCESSORS_ONLN);
994
995 if (hw_threads >= 12) {
996 num_comp_hi_threads = hw_threads * 3 / 4;
997 num_comp_lo_threads = hw_threads / 3;
998 } else if (hw_threads >= 6) {
999 num_comp_hi_threads = hw_threads - 2;
1000 num_comp_lo_threads = hw_threads / 2;
1001 } else if (hw_threads >= 2) {
1002 num_comp_hi_threads = hw_threads - 1;
1003 num_comp_lo_threads = hw_threads / 2;
1004 } else {
1005 num_comp_hi_threads = 1;
1006 num_comp_lo_threads = 1;
1007 }
1008
1009 num_comp_hi_threads = MIN2(num_comp_hi_threads,
1010 ARRAY_SIZE(sscreen->compiler));
1011 num_comp_lo_threads = MIN2(num_comp_lo_threads,
1012 ARRAY_SIZE(sscreen->compiler_lowp));
1013
1014 if (!util_queue_init(&sscreen->shader_compiler_queue, "sh",
1015 64, num_comp_hi_threads,
1016 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1017 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY)) {
1018 si_destroy_shader_cache(sscreen);
1019 FREE(sscreen);
1020 return NULL;
1021 }
1022
1023 if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
1024 "shlo",
1025 64, num_comp_lo_threads,
1026 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1027 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY |
1028 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
1029 si_destroy_shader_cache(sscreen);
1030 FREE(sscreen);
1031 return NULL;
1032 }
1033
1034 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1035 si_init_perfcounters(sscreen);
1036
1037 /* Determine tessellation ring info. */
1038 bool double_offchip_buffers = sscreen->info.chip_class >= GFX7 &&
1039 sscreen->info.family != CHIP_CARRIZO &&
1040 sscreen->info.family != CHIP_STONEY;
1041 /* This must be one less than the maximum number due to a hw limitation.
1042 * Various hardware bugs need this.
1043 */
1044 unsigned max_offchip_buffers_per_se;
1045
1046 if (sscreen->info.chip_class >= GFX10)
1047 max_offchip_buffers_per_se = 256;
1048 /* Only certain chips can use the maximum value. */
1049 else if (sscreen->info.family == CHIP_VEGA12 ||
1050 sscreen->info.family == CHIP_VEGA20)
1051 max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1052 else
1053 max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
1054
1055 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1056 sscreen->info.max_se;
1057 unsigned offchip_granularity;
1058
1059 /* Hawaii has a bug with offchip buffers > 256 that can be worked
1060 * around by setting 4K granularity.
1061 */
1062 if (sscreen->info.family == CHIP_HAWAII) {
1063 sscreen->tess_offchip_block_dw_size = 4096;
1064 offchip_granularity = V_03093C_X_4K_DWORDS;
1065 } else {
1066 sscreen->tess_offchip_block_dw_size = 8192;
1067 offchip_granularity = V_03093C_X_8K_DWORDS;
1068 }
1069
1070 sscreen->tess_factor_ring_size = 32768 * sscreen->info.max_se;
1071 assert(((sscreen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
1072 sscreen->tess_offchip_ring_size = max_offchip_buffers *
1073 sscreen->tess_offchip_block_dw_size * 4;
1074
1075 if (sscreen->info.chip_class >= GFX7) {
1076 if (sscreen->info.chip_class >= GFX8)
1077 --max_offchip_buffers;
1078 sscreen->vgt_hs_offchip_param =
1079 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1080 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1081 } else {
1082 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
1083 sscreen->vgt_hs_offchip_param =
1084 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1085 }
1086
1087 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
1088 * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
1089 * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel. */
1090 sscreen->has_clear_state = sscreen->info.chip_class >= GFX7 &&
1091 sscreen->info.chip_class <= GFX9 &&
1092 sscreen->info.is_amdgpu;
1093
1094 sscreen->has_distributed_tess =
1095 sscreen->info.chip_class >= GFX8 &&
1096 sscreen->info.max_se >= 2;
1097
1098 sscreen->has_draw_indirect_multi =
1099 (sscreen->info.family >= CHIP_POLARIS10) ||
1100 (sscreen->info.chip_class == GFX8 &&
1101 sscreen->info.pfp_fw_version >= 121 &&
1102 sscreen->info.me_fw_version >= 87) ||
1103 (sscreen->info.chip_class == GFX7 &&
1104 sscreen->info.pfp_fw_version >= 211 &&
1105 sscreen->info.me_fw_version >= 173) ||
1106 (sscreen->info.chip_class == GFX6 &&
1107 sscreen->info.pfp_fw_version >= 79 &&
1108 sscreen->info.me_fw_version >= 142);
1109
1110 sscreen->has_out_of_order_rast = sscreen->info.chip_class >= GFX8 &&
1111 sscreen->info.max_se >= 2 &&
1112 !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER));
1113 sscreen->assume_no_z_fights =
1114 driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
1115 sscreen->commutative_blend_add =
1116 driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
1117
1118 {
1119 #define OPT_BOOL(name, dflt, description) \
1120 sscreen->options.name = \
1121 driQueryOptionb(config->options, "radeonsi_"#name);
1122 #include "si_debug_options.h"
1123 }
1124
1125 sscreen->has_gfx9_scissor_bug = sscreen->info.family == CHIP_VEGA10 ||
1126 sscreen->info.family == CHIP_RAVEN;
1127 sscreen->has_msaa_sample_loc_bug = (sscreen->info.family >= CHIP_POLARIS10 &&
1128 sscreen->info.family <= CHIP_POLARIS12) ||
1129 sscreen->info.family == CHIP_VEGA10 ||
1130 sscreen->info.family == CHIP_RAVEN;
1131 sscreen->has_ls_vgpr_init_bug = sscreen->info.family == CHIP_VEGA10 ||
1132 sscreen->info.family == CHIP_RAVEN;
1133 sscreen->has_dcc_constant_encode = sscreen->info.family == CHIP_RAVEN2 ||
1134 sscreen->info.chip_class >= GFX10;
1135
1136 /* Only enable primitive binning on APUs by default. */
1137 if (sscreen->info.chip_class >= GFX10) {
1138 sscreen->dpbb_allowed = true;
1139 sscreen->dfsm_allowed = !sscreen->info.has_dedicated_vram;
1140 } else if (sscreen->info.chip_class == GFX9) {
1141 sscreen->dpbb_allowed = !sscreen->info.has_dedicated_vram;
1142 sscreen->dfsm_allowed = !sscreen->info.has_dedicated_vram;
1143 }
1144
1145 /* Process DPBB enable flags. */
1146 if (sscreen->debug_flags & DBG(DPBB)) {
1147 sscreen->dpbb_allowed = true;
1148 if (sscreen->debug_flags & DBG(DFSM))
1149 sscreen->dfsm_allowed = true;
1150 }
1151
1152 /* Process DPBB disable flags. */
1153 if (sscreen->debug_flags & DBG(NO_DPBB)) {
1154 sscreen->dpbb_allowed = false;
1155 sscreen->dfsm_allowed = false;
1156 } else if (sscreen->debug_flags & DBG(NO_DFSM)) {
1157 sscreen->dfsm_allowed = false;
1158 }
1159
1160 /* While it would be nice not to have this flag, we are constrained
1161 * by the reality that LLVM 9.0 has buggy VGPR indexing on GFX9.
1162 */
1163 sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class != GFX9;
1164
1165 /* Some chips have RB+ registers, but don't support RB+. Those must
1166 * always disable it.
1167 */
1168 if (sscreen->info.family == CHIP_STONEY ||
1169 sscreen->info.chip_class >= GFX9) {
1170 sscreen->has_rbplus = true;
1171
1172 sscreen->rbplus_allowed =
1173 !(sscreen->debug_flags & DBG(NO_RB_PLUS)) &&
1174 (sscreen->info.family == CHIP_STONEY ||
1175 sscreen->info.family == CHIP_VEGA12 ||
1176 sscreen->info.family == CHIP_RAVEN ||
1177 sscreen->info.family == CHIP_RAVEN2);
1178 }
1179
1180 sscreen->dcc_msaa_allowed =
1181 !(sscreen->debug_flags & DBG(NO_DCC_MSAA));
1182
1183 sscreen->cpdma_prefetch_writes_memory = sscreen->info.chip_class <= GFX8;
1184
1185 (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1186 sscreen->use_monolithic_shaders =
1187 (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
1188
1189 sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SCACHE |
1190 SI_CONTEXT_INV_VCACHE;
1191 if (sscreen->info.chip_class <= GFX8) {
1192 sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_L2;
1193 sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WB_L2;
1194 }
1195
1196 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1197 sscreen->debug_flags |= DBG_ALL_SHADERS;
1198
1199 /* Syntax:
1200 * EQAA=s,z,c
1201 * Example:
1202 * EQAA=8,4,2
1203
1204 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1205 * Constraints:
1206 * s >= z >= c (ignoring this only wastes memory)
1207 * s = [2..16]
1208 * z = [2..8]
1209 * c = [2..8]
1210 *
1211 * Only MSAA color and depth buffers are overriden.
1212 */
1213 if (sscreen->info.has_eqaa_surface_allocator) {
1214 const char *eqaa = debug_get_option("EQAA", NULL);
1215 unsigned s,z,f;
1216
1217 if (eqaa && sscanf(eqaa, "%u,%u,%u", &s, &z, &f) == 3 && s && z && f) {
1218 sscreen->eqaa_force_coverage_samples = s;
1219 sscreen->eqaa_force_z_samples = z;
1220 sscreen->eqaa_force_color_samples = f;
1221 }
1222 }
1223
1224 for (i = 0; i < num_comp_hi_threads; i++)
1225 si_init_compiler(sscreen, &sscreen->compiler[i]);
1226 for (i = 0; i < num_comp_lo_threads; i++)
1227 si_init_compiler(sscreen, &sscreen->compiler_lowp[i]);
1228
1229 sscreen->ge_wave_size = 64;
1230 sscreen->ps_wave_size = 64;
1231 sscreen->compute_wave_size = 64;
1232
1233 if (sscreen->info.chip_class >= GFX10) {
1234 if (sscreen->debug_flags & DBG(W32_GE))
1235 sscreen->ge_wave_size = 32;
1236 if (sscreen->debug_flags & DBG(W32_PS))
1237 sscreen->ps_wave_size = 32;
1238 if (sscreen->debug_flags & DBG(W32_CS))
1239 sscreen->compute_wave_size = 32;
1240
1241 if (sscreen->debug_flags & DBG(W64_GE))
1242 sscreen->ge_wave_size = 64;
1243 if (sscreen->debug_flags & DBG(W64_PS))
1244 sscreen->ps_wave_size = 64;
1245 if (sscreen->debug_flags & DBG(W64_CS))
1246 sscreen->compute_wave_size = 64;
1247 }
1248
1249 /* Create the auxiliary context. This must be done last. */
1250 sscreen->aux_context = si_create_context(
1251 &sscreen->b, sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0);
1252 if (sscreen->options.aux_debug) {
1253 struct u_log_context *log = CALLOC_STRUCT(u_log_context);
1254 u_log_context_init(log);
1255 sscreen->aux_context->set_log_context(sscreen->aux_context, log);
1256 }
1257
1258 if (sscreen->debug_flags & DBG(TEST_DMA))
1259 si_test_dma(sscreen);
1260
1261 if (sscreen->debug_flags & DBG(TEST_DMA_PERF)) {
1262 si_test_dma_perf(sscreen);
1263 }
1264
1265 if (sscreen->debug_flags & (DBG(TEST_VMFAULT_CP) |
1266 DBG(TEST_VMFAULT_SDMA) |
1267 DBG(TEST_VMFAULT_SHADER)))
1268 si_test_vmfault(sscreen);
1269
1270 if (sscreen->debug_flags & DBG(TEST_GDS))
1271 si_test_gds((struct si_context*)sscreen->aux_context);
1272
1273 if (sscreen->debug_flags & DBG(TEST_GDS_MM)) {
1274 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1275 32 * 1024, 4, RADEON_DOMAIN_GDS);
1276 }
1277 if (sscreen->debug_flags & DBG(TEST_GDS_OA_MM)) {
1278 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1279 4, 1, RADEON_DOMAIN_OA);
1280 }
1281
1282 return &sscreen->b;
1283 }
1284
1285 struct pipe_screen *radeonsi_screen_create(int fd, const struct pipe_screen_config *config)
1286 {
1287 drmVersionPtr version = drmGetVersion(fd);
1288 struct radeon_winsys *rw = NULL;
1289
1290 switch (version->version_major) {
1291 case 2:
1292 rw = radeon_drm_winsys_create(fd, config, radeonsi_screen_create_impl);
1293 break;
1294 case 3:
1295 rw = amdgpu_winsys_create(fd, config, radeonsi_screen_create_impl);
1296 break;
1297 }
1298
1299 drmFreeVersion(version);
1300 return rw ? rw->screen : NULL;
1301 }