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radeonsi: put up to 5 VBO descriptors into user SGPRs
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "si_pipe.h"
27 #include "si_public.h"
28 #include "si_shader_internal.h"
29 #include "si_compute.h"
30 #include "sid.h"
31
32 #include "ac_llvm_util.h"
33 #include "radeon/radeon_uvd.h"
34 #include "util/disk_cache.h"
35 #include "util/u_log.h"
36 #include "util/u_memory.h"
37 #include "util/u_suballoc.h"
38 #include "util/u_tests.h"
39 #include "util/u_upload_mgr.h"
40 #include "util/xmlconfig.h"
41 #include "vl/vl_decoder.h"
42 #include "driver_ddebug/dd_util.h"
43
44 #include "gallium/winsys/radeon/drm/radeon_drm_public.h"
45 #include "gallium/winsys/amdgpu/drm/amdgpu_public.h"
46 #include <xf86drm.h>
47
48 #include <llvm/Config/llvm-config.h>
49
50 static struct pipe_context *si_create_context(struct pipe_screen *screen,
51 unsigned flags);
52
53 static const struct debug_named_value debug_options[] = {
54 /* Shader logging options: */
55 { "vs", DBG(VS), "Print vertex shaders" },
56 { "ps", DBG(PS), "Print pixel shaders" },
57 { "gs", DBG(GS), "Print geometry shaders" },
58 { "tcs", DBG(TCS), "Print tessellation control shaders" },
59 { "tes", DBG(TES), "Print tessellation evaluation shaders" },
60 { "cs", DBG(CS), "Print compute shaders" },
61 { "noir", DBG(NO_IR), "Don't print the LLVM IR"},
62 { "notgsi", DBG(NO_TGSI), "Don't print the TGSI"},
63 { "noasm", DBG(NO_ASM), "Don't print disassembled shaders"},
64 { "preoptir", DBG(PREOPT_IR), "Print the LLVM IR before initial optimizations" },
65
66 /* Shader compiler options the shader cache should be aware of: */
67 { "sisched", DBG(SI_SCHED), "Enable LLVM SI Machine Instruction Scheduler." },
68 { "gisel", DBG(GISEL), "Enable LLVM global instruction selector." },
69 { "w32ge", DBG(W32_GE), "Use Wave32 for vertex, tessellation, and geometry shaders." },
70 { "w32ps", DBG(W32_PS), "Use Wave32 for pixel shaders." },
71 { "w32cs", DBG(W32_CS), "Use Wave32 for computes shaders." },
72 { "w64ge", DBG(W64_GE), "Use Wave64 for vertex, tessellation, and geometry shaders." },
73 { "w64ps", DBG(W64_PS), "Use Wave64 for pixel shaders." },
74 { "w64cs", DBG(W64_CS), "Use Wave64 for computes shaders." },
75
76 /* Shader compiler options (with no effect on the shader cache): */
77 { "checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR" },
78 { "mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand" },
79 { "nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants." },
80
81 /* Information logging options: */
82 { "info", DBG(INFO), "Print driver information" },
83 { "tex", DBG(TEX), "Print texture info" },
84 { "compute", DBG(COMPUTE), "Print compute info" },
85 { "vm", DBG(VM), "Print virtual addresses when creating resources" },
86
87 /* Driver options: */
88 { "forcedma", DBG(FORCE_SDMA), "Use SDMA for all operations when possible." },
89 { "nodma", DBG(NO_SDMA), "Disable SDMA" },
90 { "nodmaclear", DBG(NO_SDMA_CLEARS), "Disable SDMA clears" },
91 { "nodmacopyimage", DBG(NO_SDMA_COPY_IMAGE), "Disable SDMA image copies" },
92 { "nowc", DBG(NO_WC), "Disable GTT write combining" },
93 { "check_vm", DBG(CHECK_VM), "Check VM faults and dump debug info." },
94 { "reserve_vmid", DBG(RESERVE_VMID), "Force VMID reservation per context." },
95 { "zerovram", DBG(ZERO_VRAM), "Clear VRAM allocations." },
96
97 /* 3D engine options: */
98 { "nogfx", DBG(NO_GFX), "Disable graphics. Only multimedia compute paths can be used." },
99 { "nongg", DBG(NO_NGG), "Disable NGG and use the legacy pipeline." },
100 { "alwayspd", DBG(ALWAYS_PD), "Always enable the primitive discard compute shader." },
101 { "pd", DBG(PD), "Enable the primitive discard compute shader for large draw calls." },
102 { "nopd", DBG(NO_PD), "Disable the primitive discard compute shader." },
103 { "switch_on_eop", DBG(SWITCH_ON_EOP), "Program WD/IA to switch on end-of-packet." },
104 { "nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order rasterization" },
105 { "nodpbb", DBG(NO_DPBB), "Disable DPBB." },
106 { "nodfsm", DBG(NO_DFSM), "Disable DFSM." },
107 { "dpbb", DBG(DPBB), "Enable DPBB." },
108 { "dfsm", DBG(DFSM), "Enable DFSM." },
109 { "nohyperz", DBG(NO_HYPERZ), "Disable Hyper-Z" },
110 { "norbplus", DBG(NO_RB_PLUS), "Disable RB+." },
111 { "no2d", DBG(NO_2D_TILING), "Disable 2D tiling" },
112 { "notiling", DBG(NO_TILING), "Disable tiling" },
113 { "nodcc", DBG(NO_DCC), "Disable DCC." },
114 { "nodccclear", DBG(NO_DCC_CLEAR), "Disable DCC fast clear." },
115 { "nodccfb", DBG(NO_DCC_FB), "Disable separate DCC on the main framebuffer" },
116 { "nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA" },
117 { "nofmask", DBG(NO_FMASK), "Disable MSAA compression" },
118
119 /* Tests: */
120 { "testdma", DBG(TEST_DMA), "Invoke SDMA tests and exit." },
121 { "testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and exit." },
122 { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA), "Invoke a SDMA VM fault test and exit." },
123 { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM fault test and exit." },
124 { "testdmaperf", DBG(TEST_DMA_PERF), "Test DMA performance" },
125 { "testgds", DBG(TEST_GDS), "Test GDS." },
126 { "testgdsmm", DBG(TEST_GDS_MM), "Test GDS memory management." },
127 { "testgdsoamm", DBG(TEST_GDS_OA_MM), "Test GDS OA memory management." },
128
129 DEBUG_NAMED_VALUE_END /* must be last */
130 };
131
132 void si_init_compiler(struct si_screen *sscreen, struct ac_llvm_compiler *compiler)
133 {
134 /* Only create the less-optimizing version of the compiler on APUs
135 * predating Ryzen (Raven). */
136 bool create_low_opt_compiler = !sscreen->info.has_dedicated_vram &&
137 sscreen->info.chip_class <= GFX8;
138
139 enum ac_target_machine_options tm_options =
140 (sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
141 (sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL : 0) |
142 (sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
143 (sscreen->info.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
144 (!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0) |
145 (sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0) |
146 (create_low_opt_compiler ? AC_TM_CREATE_LOW_OPT : 0);
147
148 ac_init_llvm_once();
149 ac_init_llvm_compiler(compiler, sscreen->info.family, tm_options);
150 compiler->passes = ac_create_llvm_passes(compiler->tm);
151
152 if (compiler->tm_wave32)
153 compiler->passes_wave32 = ac_create_llvm_passes(compiler->tm_wave32);
154 if (compiler->low_opt_tm)
155 compiler->low_opt_passes = ac_create_llvm_passes(compiler->low_opt_tm);
156 }
157
158 static void si_destroy_compiler(struct ac_llvm_compiler *compiler)
159 {
160 ac_destroy_llvm_compiler(compiler);
161 }
162
163 /*
164 * pipe_context
165 */
166 static void si_destroy_context(struct pipe_context *context)
167 {
168 struct si_context *sctx = (struct si_context *)context;
169 int i;
170
171 util_queue_finish(&sctx->screen->shader_compiler_queue);
172 util_queue_finish(&sctx->screen->shader_compiler_queue_low_priority);
173
174 /* Unreference the framebuffer normally to disable related logic
175 * properly.
176 */
177 struct pipe_framebuffer_state fb = {};
178 if (context->set_framebuffer_state)
179 context->set_framebuffer_state(context, &fb);
180
181 si_release_all_descriptors(sctx);
182
183 if (sctx->chip_class >= GFX10 && sctx->has_graphics)
184 gfx10_destroy_query(sctx);
185
186 pipe_resource_reference(&sctx->esgs_ring, NULL);
187 pipe_resource_reference(&sctx->gsvs_ring, NULL);
188 pipe_resource_reference(&sctx->tess_rings, NULL);
189 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
190 pipe_resource_reference(&sctx->sample_pos_buffer, NULL);
191 si_resource_reference(&sctx->border_color_buffer, NULL);
192 free(sctx->border_color_table);
193 si_resource_reference(&sctx->scratch_buffer, NULL);
194 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
195 si_resource_reference(&sctx->wait_mem_scratch, NULL);
196
197 si_pm4_free_state(sctx, sctx->init_config, ~0);
198 if (sctx->init_config_gs_rings)
199 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
200 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
201 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
202
203 if (sctx->fixed_func_tcs_shader.cso)
204 sctx->b.delete_tcs_state(&sctx->b, sctx->fixed_func_tcs_shader.cso);
205 if (sctx->custom_dsa_flush)
206 sctx->b.delete_depth_stencil_alpha_state(&sctx->b, sctx->custom_dsa_flush);
207 if (sctx->custom_blend_resolve)
208 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_resolve);
209 if (sctx->custom_blend_fmask_decompress)
210 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_fmask_decompress);
211 if (sctx->custom_blend_eliminate_fastclear)
212 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_eliminate_fastclear);
213 if (sctx->custom_blend_dcc_decompress)
214 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_dcc_decompress);
215 if (sctx->vs_blit_pos)
216 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos);
217 if (sctx->vs_blit_pos_layered)
218 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos_layered);
219 if (sctx->vs_blit_color)
220 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color);
221 if (sctx->vs_blit_color_layered)
222 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color_layered);
223 if (sctx->vs_blit_texcoord)
224 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_texcoord);
225 if (sctx->cs_clear_buffer)
226 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_buffer);
227 if (sctx->cs_copy_buffer)
228 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_buffer);
229 if (sctx->cs_copy_image)
230 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image);
231 if (sctx->cs_copy_image_1d_array)
232 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image_1d_array);
233 if (sctx->cs_clear_render_target)
234 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target);
235 if (sctx->cs_clear_render_target_1d_array)
236 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target_1d_array);
237 if (sctx->cs_clear_12bytes_buffer)
238 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_12bytes_buffer);
239 if (sctx->cs_dcc_retile)
240 sctx->b.delete_compute_state(&sctx->b, sctx->cs_dcc_retile);
241
242 for (unsigned i = 0; i < ARRAY_SIZE(sctx->cs_fmask_expand); i++) {
243 for (unsigned j = 0; j < ARRAY_SIZE(sctx->cs_fmask_expand[i]); j++) {
244 if (sctx->cs_fmask_expand[i][j]) {
245 sctx->b.delete_compute_state(&sctx->b,
246 sctx->cs_fmask_expand[i][j]);
247 }
248 }
249 }
250
251 if (sctx->blitter)
252 util_blitter_destroy(sctx->blitter);
253
254 /* Release DCC stats. */
255 for (int i = 0; i < ARRAY_SIZE(sctx->dcc_stats); i++) {
256 assert(!sctx->dcc_stats[i].query_active);
257
258 for (int j = 0; j < ARRAY_SIZE(sctx->dcc_stats[i].ps_stats); j++)
259 if (sctx->dcc_stats[i].ps_stats[j])
260 sctx->b.destroy_query(&sctx->b,
261 sctx->dcc_stats[i].ps_stats[j]);
262
263 si_texture_reference(&sctx->dcc_stats[i].tex, NULL);
264 }
265
266 if (sctx->query_result_shader)
267 sctx->b.delete_compute_state(&sctx->b, sctx->query_result_shader);
268 if (sctx->sh_query_result_shader)
269 sctx->b.delete_compute_state(&sctx->b, sctx->sh_query_result_shader);
270
271 if (sctx->gfx_cs)
272 sctx->ws->cs_destroy(sctx->gfx_cs);
273 if (sctx->sdma_cs)
274 sctx->ws->cs_destroy(sctx->sdma_cs);
275 if (sctx->ctx)
276 sctx->ws->ctx_destroy(sctx->ctx);
277
278 if (sctx->b.stream_uploader)
279 u_upload_destroy(sctx->b.stream_uploader);
280 if (sctx->b.const_uploader)
281 u_upload_destroy(sctx->b.const_uploader);
282 if (sctx->cached_gtt_allocator)
283 u_upload_destroy(sctx->cached_gtt_allocator);
284
285 slab_destroy_child(&sctx->pool_transfers);
286 slab_destroy_child(&sctx->pool_transfers_unsync);
287
288 if (sctx->allocator_zeroed_memory)
289 u_suballocator_destroy(sctx->allocator_zeroed_memory);
290
291 sctx->ws->fence_reference(&sctx->last_gfx_fence, NULL);
292 sctx->ws->fence_reference(&sctx->last_sdma_fence, NULL);
293 sctx->ws->fence_reference(&sctx->last_ib_barrier_fence, NULL);
294 si_resource_reference(&sctx->eop_bug_scratch, NULL);
295 si_resource_reference(&sctx->index_ring, NULL);
296 si_resource_reference(&sctx->barrier_buf, NULL);
297 si_resource_reference(&sctx->last_ib_barrier_buf, NULL);
298 pb_reference(&sctx->gds, NULL);
299 pb_reference(&sctx->gds_oa, NULL);
300
301 si_destroy_compiler(&sctx->compiler);
302
303 si_saved_cs_reference(&sctx->current_saved_cs, NULL);
304
305 _mesa_hash_table_destroy(sctx->tex_handles, NULL);
306 _mesa_hash_table_destroy(sctx->img_handles, NULL);
307
308 util_dynarray_fini(&sctx->resident_tex_handles);
309 util_dynarray_fini(&sctx->resident_img_handles);
310 util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
311 util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
312 util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
313 si_unref_sdma_uploads(sctx);
314 free(sctx->sdma_uploads);
315 FREE(sctx);
316 }
317
318 static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx)
319 {
320 struct si_context *sctx = (struct si_context *)ctx;
321 struct si_screen *sscreen = sctx->screen;
322 enum pipe_reset_status status = sctx->ws->ctx_query_reset_status(sctx->ctx);
323
324 if (status != PIPE_NO_RESET) {
325 /* Call the state tracker to set a no-op API dispatch. */
326 if (sctx->device_reset_callback.reset) {
327 sctx->device_reset_callback.reset(sctx->device_reset_callback.data,
328 status);
329 }
330
331 /* Re-create the auxiliary context, because it won't submit
332 * any new IBs due to a GPU reset.
333 */
334 simple_mtx_lock(&sscreen->aux_context_lock);
335
336 struct u_log_context *aux_log = ((struct si_context *)sscreen->aux_context)->log;
337 sscreen->aux_context->set_log_context(sscreen->aux_context, NULL);
338 sscreen->aux_context->destroy(sscreen->aux_context);
339
340 sscreen->aux_context = si_create_context(&sscreen->b,
341 (sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) |
342 (sscreen->info.has_graphics ? 0 : PIPE_CONTEXT_COMPUTE_ONLY));
343 sscreen->aux_context->set_log_context(sscreen->aux_context, aux_log);
344 simple_mtx_unlock(&sscreen->aux_context_lock);
345 }
346 return status;
347 }
348
349 static void si_set_device_reset_callback(struct pipe_context *ctx,
350 const struct pipe_device_reset_callback *cb)
351 {
352 struct si_context *sctx = (struct si_context *)ctx;
353
354 if (cb)
355 sctx->device_reset_callback = *cb;
356 else
357 memset(&sctx->device_reset_callback, 0,
358 sizeof(sctx->device_reset_callback));
359 }
360
361 /* Apitrace profiling:
362 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
363 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
364 * and remember its number.
365 * 3) In Mesa, enable queries and performance counters around that draw
366 * call and print the results.
367 * 4) glretrace --benchmark --markers ..
368 */
369 static void si_emit_string_marker(struct pipe_context *ctx,
370 const char *string, int len)
371 {
372 struct si_context *sctx = (struct si_context *)ctx;
373
374 dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
375
376 if (sctx->log)
377 u_log_printf(sctx->log, "\nString marker: %*s\n", len, string);
378 }
379
380 static void si_set_debug_callback(struct pipe_context *ctx,
381 const struct pipe_debug_callback *cb)
382 {
383 struct si_context *sctx = (struct si_context *)ctx;
384 struct si_screen *screen = sctx->screen;
385
386 util_queue_finish(&screen->shader_compiler_queue);
387 util_queue_finish(&screen->shader_compiler_queue_low_priority);
388
389 if (cb)
390 sctx->debug = *cb;
391 else
392 memset(&sctx->debug, 0, sizeof(sctx->debug));
393 }
394
395 static void si_set_log_context(struct pipe_context *ctx,
396 struct u_log_context *log)
397 {
398 struct si_context *sctx = (struct si_context *)ctx;
399 sctx->log = log;
400
401 if (log)
402 u_log_add_auto_logger(log, si_auto_log_cs, sctx);
403 }
404
405 static void si_set_context_param(struct pipe_context *ctx,
406 enum pipe_context_param param,
407 unsigned value)
408 {
409 struct radeon_winsys *ws = ((struct si_context *)ctx)->ws;
410
411 switch (param) {
412 case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE:
413 ws->pin_threads_to_L3_cache(ws, value);
414 break;
415 default:;
416 }
417 }
418
419 static struct pipe_context *si_create_context(struct pipe_screen *screen,
420 unsigned flags)
421 {
422 struct si_screen* sscreen = (struct si_screen *)screen;
423
424 /* Don't create a context if it's not compute-only and hw is compute-only. */
425 if (!sscreen->info.has_graphics &&
426 !(flags & PIPE_CONTEXT_COMPUTE_ONLY))
427 return NULL;
428
429 struct si_context *sctx = CALLOC_STRUCT(si_context);
430 struct radeon_winsys *ws = sscreen->ws;
431 int shader, i;
432 bool stop_exec_on_failure = (flags & PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET) != 0;
433
434 if (!sctx)
435 return NULL;
436
437 sctx->has_graphics = sscreen->info.chip_class == GFX6 ||
438 !(flags & PIPE_CONTEXT_COMPUTE_ONLY);
439
440 if (flags & PIPE_CONTEXT_DEBUG)
441 sscreen->record_llvm_ir = true; /* racy but not critical */
442
443 sctx->b.screen = screen; /* this must be set first */
444 sctx->b.priv = NULL;
445 sctx->b.destroy = si_destroy_context;
446 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
447 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
448
449 slab_create_child(&sctx->pool_transfers, &sscreen->pool_transfers);
450 slab_create_child(&sctx->pool_transfers_unsync, &sscreen->pool_transfers);
451
452 sctx->ws = sscreen->ws;
453 sctx->family = sscreen->info.family;
454 sctx->chip_class = sscreen->info.chip_class;
455
456 if (sctx->chip_class == GFX7 ||
457 sctx->chip_class == GFX8 ||
458 sctx->chip_class == GFX9) {
459 sctx->eop_bug_scratch = si_resource(
460 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
461 16 * sscreen->info.num_render_backends));
462 if (!sctx->eop_bug_scratch)
463 goto fail;
464 }
465
466 /* Initialize context allocators. */
467 sctx->allocator_zeroed_memory =
468 u_suballocator_create(&sctx->b, 128 * 1024,
469 0, PIPE_USAGE_DEFAULT,
470 SI_RESOURCE_FLAG_UNMAPPABLE |
471 SI_RESOURCE_FLAG_CLEAR, false);
472 if (!sctx->allocator_zeroed_memory)
473 goto fail;
474
475 sctx->b.stream_uploader = u_upload_create(&sctx->b, 1024 * 1024,
476 0, PIPE_USAGE_STREAM,
477 SI_RESOURCE_FLAG_READ_ONLY);
478 if (!sctx->b.stream_uploader)
479 goto fail;
480
481 sctx->cached_gtt_allocator = u_upload_create(&sctx->b, 16 * 1024,
482 0, PIPE_USAGE_STAGING, 0);
483 if (!sctx->cached_gtt_allocator)
484 goto fail;
485
486 sctx->ctx = sctx->ws->ctx_create(sctx->ws);
487 if (!sctx->ctx)
488 goto fail;
489
490 if (sscreen->info.num_rings[RING_DMA] &&
491 !(sscreen->debug_flags & DBG(NO_SDMA)) &&
492 /* SDMA causes corruption on RX 580:
493 * https://gitlab.freedesktop.org/mesa/mesa/issues/1399
494 * https://gitlab.freedesktop.org/mesa/mesa/issues/1889
495 */
496 (sctx->chip_class != GFX8 || sscreen->debug_flags & DBG(FORCE_SDMA)) &&
497 /* SDMA timeouts sometimes on gfx10 so disable it for now. See:
498 * https://bugs.freedesktop.org/show_bug.cgi?id=111481
499 * https://gitlab.freedesktop.org/mesa/mesa/issues/1907
500 */
501 (sctx->chip_class != GFX10 || sscreen->debug_flags & DBG(FORCE_SDMA))) {
502 sctx->sdma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA,
503 (void*)si_flush_dma_cs,
504 sctx, stop_exec_on_failure);
505 }
506
507 bool use_sdma_upload = sscreen->info.has_dedicated_vram && sctx->sdma_cs;
508 sctx->b.const_uploader = u_upload_create(&sctx->b, 256 * 1024,
509 0, PIPE_USAGE_DEFAULT,
510 SI_RESOURCE_FLAG_32BIT |
511 (use_sdma_upload ?
512 SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA : 0));
513 if (!sctx->b.const_uploader)
514 goto fail;
515
516 if (use_sdma_upload)
517 u_upload_enable_flush_explicit(sctx->b.const_uploader);
518
519 sctx->gfx_cs = ws->cs_create(sctx->ctx,
520 sctx->has_graphics ? RING_GFX : RING_COMPUTE,
521 (void*)si_flush_gfx_cs, sctx, stop_exec_on_failure);
522
523 /* Border colors. */
524 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
525 sizeof(*sctx->border_color_table));
526 if (!sctx->border_color_table)
527 goto fail;
528
529 sctx->border_color_buffer = si_resource(
530 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
531 SI_MAX_BORDER_COLORS *
532 sizeof(*sctx->border_color_table)));
533 if (!sctx->border_color_buffer)
534 goto fail;
535
536 sctx->border_color_map =
537 ws->buffer_map(sctx->border_color_buffer->buf,
538 NULL, PIPE_TRANSFER_WRITE);
539 if (!sctx->border_color_map)
540 goto fail;
541
542 sctx->ngg = sscreen->use_ngg;
543
544 /* Initialize context functions used by graphics and compute. */
545 if (sctx->chip_class >= GFX10)
546 sctx->emit_cache_flush = gfx10_emit_cache_flush;
547 else
548 sctx->emit_cache_flush = si_emit_cache_flush;
549
550 sctx->b.emit_string_marker = si_emit_string_marker;
551 sctx->b.set_debug_callback = si_set_debug_callback;
552 sctx->b.set_log_context = si_set_log_context;
553 sctx->b.set_context_param = si_set_context_param;
554 sctx->b.get_device_reset_status = si_get_reset_status;
555 sctx->b.set_device_reset_callback = si_set_device_reset_callback;
556
557 si_init_all_descriptors(sctx);
558 si_init_buffer_functions(sctx);
559 si_init_clear_functions(sctx);
560 si_init_blit_functions(sctx);
561 si_init_compute_functions(sctx);
562 si_init_compute_blit_functions(sctx);
563 si_init_debug_functions(sctx);
564 si_init_fence_functions(sctx);
565 si_init_query_functions(sctx);
566 si_init_state_compute_functions(sctx);
567 si_init_context_texture_functions(sctx);
568
569 /* Initialize graphics-only context functions. */
570 if (sctx->has_graphics) {
571 if (sctx->chip_class >= GFX10)
572 gfx10_init_query(sctx);
573 si_init_msaa_functions(sctx);
574 si_init_shader_functions(sctx);
575 si_init_state_functions(sctx);
576 si_init_streamout_functions(sctx);
577 si_init_viewport_functions(sctx);
578
579 sctx->blitter = util_blitter_create(&sctx->b);
580 if (sctx->blitter == NULL)
581 goto fail;
582 sctx->blitter->skip_viewport_restore = true;
583
584 /* Some states are expected to be always non-NULL. */
585 sctx->noop_blend = util_blitter_get_noop_blend_state(sctx->blitter);
586 sctx->queued.named.blend = sctx->noop_blend;
587
588 sctx->noop_dsa = util_blitter_get_noop_dsa_state(sctx->blitter);
589 sctx->queued.named.dsa = sctx->noop_dsa;
590
591 sctx->discard_rasterizer_state =
592 util_blitter_get_discard_rasterizer_state(sctx->blitter);
593 sctx->queued.named.rasterizer = sctx->discard_rasterizer_state;
594
595 si_init_draw_functions(sctx);
596 si_initialize_prim_discard_tunables(sctx);
597 }
598
599 /* Initialize SDMA functions. */
600 if (sctx->chip_class >= GFX7)
601 cik_init_sdma_functions(sctx);
602 else
603 sctx->dma_copy = si_resource_copy_region;
604
605 if (sscreen->debug_flags & DBG(FORCE_SDMA))
606 sctx->b.resource_copy_region = sctx->dma_copy;
607
608 sctx->sample_mask = 0xffff;
609
610 /* Initialize multimedia functions. */
611 if (sscreen->info.has_hw_decode) {
612 sctx->b.create_video_codec = si_uvd_create_decoder;
613 sctx->b.create_video_buffer = si_video_buffer_create;
614 } else {
615 sctx->b.create_video_codec = vl_create_decoder;
616 sctx->b.create_video_buffer = vl_video_buffer_create;
617 }
618
619 if (sctx->chip_class >= GFX9) {
620 sctx->wait_mem_scratch = si_resource(
621 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 8));
622 if (!sctx->wait_mem_scratch)
623 goto fail;
624
625 /* Initialize the memory. */
626 si_cp_write_data(sctx, sctx->wait_mem_scratch, 0, 4,
627 V_370_MEM, V_370_ME, &sctx->wait_mem_number);
628 }
629
630 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
631 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
632 if (sctx->chip_class == GFX7) {
633 sctx->null_const_buf.buffer =
634 pipe_aligned_buffer_create(screen,
635 SI_RESOURCE_FLAG_32BIT,
636 PIPE_USAGE_DEFAULT, 16,
637 sctx->screen->info.tcc_cache_line_size);
638 if (!sctx->null_const_buf.buffer)
639 goto fail;
640 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
641
642 unsigned start_shader = sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE;
643 for (shader = start_shader; shader < SI_NUM_SHADERS; shader++) {
644 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
645 sctx->b.set_constant_buffer(&sctx->b, shader, i,
646 &sctx->null_const_buf);
647 }
648 }
649
650 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
651 &sctx->null_const_buf);
652 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
653 &sctx->null_const_buf);
654 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
655 &sctx->null_const_buf);
656 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
657 &sctx->null_const_buf);
658 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
659 &sctx->null_const_buf);
660 }
661
662 uint64_t max_threads_per_block;
663 screen->get_compute_param(screen, PIPE_SHADER_IR_NIR,
664 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
665 &max_threads_per_block);
666
667 /* The maximum number of scratch waves. Scratch space isn't divided
668 * evenly between CUs. The number is only a function of the number of CUs.
669 * We can decrease the constant to decrease the scratch buffer size.
670 *
671 * sctx->scratch_waves must be >= the maximum posible size of
672 * 1 threadgroup, so that the hw doesn't hang from being unable
673 * to start any.
674 *
675 * The recommended value is 4 per CU at most. Higher numbers don't
676 * bring much benefit, but they still occupy chip resources (think
677 * async compute). I've seen ~2% performance difference between 4 and 32.
678 */
679 sctx->scratch_waves = MAX2(32 * sscreen->info.num_good_compute_units,
680 max_threads_per_block / 64);
681
682 /* Bindless handles. */
683 sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
684 _mesa_key_pointer_equal);
685 sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
686 _mesa_key_pointer_equal);
687
688 util_dynarray_init(&sctx->resident_tex_handles, NULL);
689 util_dynarray_init(&sctx->resident_img_handles, NULL);
690 util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
691 util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
692 util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
693
694 sctx->sample_pos_buffer =
695 pipe_buffer_create(sctx->b.screen, 0, PIPE_USAGE_DEFAULT,
696 sizeof(sctx->sample_positions));
697 pipe_buffer_write(&sctx->b, sctx->sample_pos_buffer, 0,
698 sizeof(sctx->sample_positions), &sctx->sample_positions);
699
700 /* this must be last */
701 si_begin_new_gfx_cs(sctx);
702
703 if (sctx->chip_class == GFX7) {
704 /* Clear the NULL constant buffer, because loads should return zeros.
705 * Note that this forces CP DMA to be used, because clover deadlocks
706 * for some reason when the compute codepath is used.
707 */
708 uint32_t clear_value = 0;
709 si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0,
710 sctx->null_const_buf.buffer->width0,
711 &clear_value, 4, SI_COHERENCY_SHADER, true);
712 }
713 return &sctx->b;
714 fail:
715 fprintf(stderr, "radeonsi: Failed to create a context.\n");
716 si_destroy_context(&sctx->b);
717 return NULL;
718 }
719
720 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
721 void *priv, unsigned flags)
722 {
723 struct si_screen *sscreen = (struct si_screen *)screen;
724 struct pipe_context *ctx;
725
726 if (sscreen->debug_flags & DBG(CHECK_VM))
727 flags |= PIPE_CONTEXT_DEBUG;
728
729 ctx = si_create_context(screen, flags);
730
731 if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
732 return ctx;
733
734 /* Clover (compute-only) is unsupported. */
735 if (flags & PIPE_CONTEXT_COMPUTE_ONLY)
736 return ctx;
737
738 /* When shaders are logged to stderr, asynchronous compilation is
739 * disabled too. */
740 if (sscreen->debug_flags & DBG_ALL_SHADERS)
741 return ctx;
742
743 /* Use asynchronous flushes only on amdgpu, since the radeon
744 * implementation for fence_server_sync is incomplete. */
745 return threaded_context_create(ctx, &sscreen->pool_transfers,
746 si_replace_buffer_storage,
747 sscreen->info.is_amdgpu ? si_create_fence : NULL,
748 &((struct si_context*)ctx)->tc);
749 }
750
751 /*
752 * pipe_screen
753 */
754 static void si_destroy_screen(struct pipe_screen* pscreen)
755 {
756 struct si_screen *sscreen = (struct si_screen *)pscreen;
757 struct si_shader_part *parts[] = {
758 sscreen->vs_prologs,
759 sscreen->tcs_epilogs,
760 sscreen->gs_prologs,
761 sscreen->ps_prologs,
762 sscreen->ps_epilogs
763 };
764 unsigned i;
765
766 if (!sscreen->ws->unref(sscreen->ws))
767 return;
768
769 simple_mtx_destroy(&sscreen->aux_context_lock);
770
771 struct u_log_context *aux_log = ((struct si_context *)sscreen->aux_context)->log;
772 if (aux_log) {
773 sscreen->aux_context->set_log_context(sscreen->aux_context, NULL);
774 u_log_context_destroy(aux_log);
775 FREE(aux_log);
776 }
777
778 sscreen->aux_context->destroy(sscreen->aux_context);
779
780 util_queue_destroy(&sscreen->shader_compiler_queue);
781 util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
782
783 /* Release the reference on glsl types of the compiler threads. */
784 glsl_type_singleton_decref();
785
786 for (i = 0; i < ARRAY_SIZE(sscreen->compiler); i++)
787 si_destroy_compiler(&sscreen->compiler[i]);
788
789 for (i = 0; i < ARRAY_SIZE(sscreen->compiler_lowp); i++)
790 si_destroy_compiler(&sscreen->compiler_lowp[i]);
791
792 /* Free shader parts. */
793 for (i = 0; i < ARRAY_SIZE(parts); i++) {
794 while (parts[i]) {
795 struct si_shader_part *part = parts[i];
796
797 parts[i] = part->next;
798 si_shader_binary_clean(&part->binary);
799 FREE(part);
800 }
801 }
802 simple_mtx_destroy(&sscreen->shader_parts_mutex);
803 si_destroy_shader_cache(sscreen);
804
805 si_destroy_perfcounters(sscreen);
806 si_gpu_load_kill_thread(sscreen);
807
808 simple_mtx_destroy(&sscreen->gpu_load_mutex);
809
810 slab_destroy_parent(&sscreen->pool_transfers);
811
812 disk_cache_destroy(sscreen->disk_shader_cache);
813 sscreen->ws->destroy(sscreen->ws);
814 FREE(sscreen);
815 }
816
817 static void si_init_gs_info(struct si_screen *sscreen)
818 {
819 sscreen->gs_table_depth = ac_get_gs_table_depth(sscreen->info.chip_class,
820 sscreen->info.family);
821 }
822
823 static void si_test_vmfault(struct si_screen *sscreen)
824 {
825 struct pipe_context *ctx = sscreen->aux_context;
826 struct si_context *sctx = (struct si_context *)ctx;
827 struct pipe_resource *buf =
828 pipe_buffer_create_const0(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 64);
829
830 if (!buf) {
831 puts("Buffer allocation failed.");
832 exit(1);
833 }
834
835 si_resource(buf)->gpu_address = 0; /* cause a VM fault */
836
837 if (sscreen->debug_flags & DBG(TEST_VMFAULT_CP)) {
838 si_cp_dma_copy_buffer(sctx, buf, buf, 0, 4, 4, 0,
839 SI_COHERENCY_NONE, L2_BYPASS);
840 ctx->flush(ctx, NULL, 0);
841 puts("VM fault test: CP - done.");
842 }
843 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SDMA)) {
844 si_sdma_clear_buffer(sctx, buf, 0, 4, 0);
845 ctx->flush(ctx, NULL, 0);
846 puts("VM fault test: SDMA - done.");
847 }
848 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SHADER)) {
849 util_test_constant_buffer(ctx, buf);
850 puts("VM fault test: Shader - done.");
851 }
852 exit(0);
853 }
854
855 static void si_test_gds_memory_management(struct si_context *sctx,
856 unsigned alloc_size, unsigned alignment,
857 enum radeon_bo_domain domain)
858 {
859 struct radeon_winsys *ws = sctx->ws;
860 struct radeon_cmdbuf *cs[8];
861 struct pb_buffer *gds_bo[ARRAY_SIZE(cs)];
862
863 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
864 cs[i] = ws->cs_create(sctx->ctx, RING_COMPUTE,
865 NULL, NULL, false);
866 gds_bo[i] = ws->buffer_create(ws, alloc_size, alignment, domain, 0);
867 assert(gds_bo[i]);
868 }
869
870 for (unsigned iterations = 0; iterations < 20000; iterations++) {
871 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
872 /* This clears GDS with CP DMA.
873 *
874 * We don't care if GDS is present. Just add some packet
875 * to make the GPU busy for a moment.
876 */
877 si_cp_dma_clear_buffer(sctx, cs[i], NULL, 0, alloc_size, 0,
878 SI_CPDMA_SKIP_BO_LIST_UPDATE |
879 SI_CPDMA_SKIP_CHECK_CS_SPACE |
880 SI_CPDMA_SKIP_GFX_SYNC, 0, 0);
881
882 ws->cs_add_buffer(cs[i], gds_bo[i], domain,
883 RADEON_USAGE_READWRITE, 0);
884 ws->cs_flush(cs[i], PIPE_FLUSH_ASYNC, NULL);
885 }
886 }
887 exit(0);
888 }
889
890 static void si_disk_cache_create(struct si_screen *sscreen)
891 {
892 /* Don't use the cache if shader dumping is enabled. */
893 if (sscreen->debug_flags & DBG_ALL_SHADERS)
894 return;
895
896 struct mesa_sha1 ctx;
897 unsigned char sha1[20];
898 char cache_id[20 * 2 + 1];
899
900 _mesa_sha1_init(&ctx);
901
902 if (!disk_cache_get_function_identifier(si_disk_cache_create, &ctx) ||
903 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo,
904 &ctx))
905 return;
906
907 _mesa_sha1_final(&ctx, sha1);
908 disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
909
910 /* These flags affect shader compilation. */
911 #define ALL_FLAGS (DBG(SI_SCHED) | DBG(GISEL))
912 uint64_t shader_debug_flags = sscreen->debug_flags & ALL_FLAGS;
913
914 /* Add the high bits of 32-bit addresses, which affects
915 * how 32-bit addresses are expanded to 64 bits.
916 */
917 STATIC_ASSERT(ALL_FLAGS <= UINT_MAX);
918 assert((int16_t)sscreen->info.address32_hi == (int32_t)sscreen->info.address32_hi);
919 shader_debug_flags |= (uint64_t)(sscreen->info.address32_hi & 0xffff) << 32;
920
921 sscreen->disk_shader_cache =
922 disk_cache_create(sscreen->info.name,
923 cache_id,
924 shader_debug_flags);
925 }
926
927 static void si_set_max_shader_compiler_threads(struct pipe_screen *screen,
928 unsigned max_threads)
929 {
930 struct si_screen *sscreen = (struct si_screen *)screen;
931
932 /* This function doesn't allow a greater number of threads than
933 * the queue had at its creation. */
934 util_queue_adjust_num_threads(&sscreen->shader_compiler_queue,
935 max_threads);
936 /* Don't change the number of threads on the low priority queue. */
937 }
938
939 static bool si_is_parallel_shader_compilation_finished(struct pipe_screen *screen,
940 void *shader,
941 enum pipe_shader_type shader_type)
942 {
943 struct si_shader_selector *sel = (struct si_shader_selector *)shader;
944
945 return util_queue_fence_is_signalled(&sel->ready);
946 }
947
948 static struct pipe_screen *
949 radeonsi_screen_create_impl(struct radeon_winsys *ws,
950 const struct pipe_screen_config *config)
951 {
952 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
953 unsigned hw_threads, num_comp_hi_threads, num_comp_lo_threads;
954
955 if (!sscreen) {
956 return NULL;
957 }
958
959 sscreen->ws = ws;
960 ws->query_info(ws, &sscreen->info);
961
962 if (sscreen->info.chip_class == GFX10 && LLVM_VERSION_MAJOR < 9) {
963 fprintf(stderr, "radeonsi: Navi family support requires LLVM 9 or higher\n");
964 FREE(sscreen);
965 return NULL;
966 }
967
968 if (sscreen->info.chip_class >= GFX9) {
969 sscreen->se_tile_repeat = 32 * sscreen->info.max_se;
970 } else {
971 ac_get_raster_config(&sscreen->info,
972 &sscreen->pa_sc_raster_config,
973 &sscreen->pa_sc_raster_config_1,
974 &sscreen->se_tile_repeat);
975 }
976
977 sscreen->debug_flags = debug_get_flags_option("R600_DEBUG",
978 debug_options, 0);
979 sscreen->debug_flags |= debug_get_flags_option("AMD_DEBUG",
980 debug_options, 0);
981
982 if (sscreen->debug_flags & DBG(NO_GFX))
983 sscreen->info.has_graphics = false;
984
985 /* Set functions first. */
986 sscreen->b.context_create = si_pipe_create_context;
987 sscreen->b.destroy = si_destroy_screen;
988 sscreen->b.set_max_shader_compiler_threads =
989 si_set_max_shader_compiler_threads;
990 sscreen->b.is_parallel_shader_compilation_finished =
991 si_is_parallel_shader_compilation_finished;
992 sscreen->b.finalize_nir = si_finalize_nir;
993
994 si_init_screen_get_functions(sscreen);
995 si_init_screen_buffer_functions(sscreen);
996 si_init_screen_fence_functions(sscreen);
997 si_init_screen_state_functions(sscreen);
998 si_init_screen_texture_functions(sscreen);
999 si_init_screen_query_functions(sscreen);
1000
1001 /* Set these flags in debug_flags early, so that the shader cache takes
1002 * them into account.
1003 */
1004 if (driQueryOptionb(config->options,
1005 "glsl_correct_derivatives_after_discard"))
1006 sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
1007 if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
1008 sscreen->debug_flags |= DBG(SI_SCHED);
1009
1010 if (sscreen->debug_flags & DBG(INFO))
1011 ac_print_gpu_info(&sscreen->info);
1012
1013 slab_create_parent(&sscreen->pool_transfers,
1014 sizeof(struct si_transfer), 64);
1015
1016 sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1017 if (sscreen->force_aniso == -1) {
1018 sscreen->force_aniso = MIN2(16, debug_get_num_option("AMD_TEX_ANISO", -1));
1019 }
1020
1021 if (sscreen->force_aniso >= 0) {
1022 printf("radeonsi: Forcing anisotropy filter to %ix\n",
1023 /* round down to a power of two */
1024 1 << util_logbase2(sscreen->force_aniso));
1025 }
1026
1027 (void) simple_mtx_init(&sscreen->aux_context_lock, mtx_plain);
1028 (void) simple_mtx_init(&sscreen->gpu_load_mutex, mtx_plain);
1029
1030 si_init_gs_info(sscreen);
1031 if (!si_init_shader_cache(sscreen)) {
1032 FREE(sscreen);
1033 return NULL;
1034 }
1035
1036 {
1037 #define OPT_BOOL(name, dflt, description) \
1038 sscreen->options.name = \
1039 driQueryOptionb(config->options, "radeonsi_"#name);
1040 #include "si_debug_options.h"
1041 }
1042
1043 si_disk_cache_create(sscreen);
1044
1045 /* Determine the number of shader compiler threads. */
1046 hw_threads = sysconf(_SC_NPROCESSORS_ONLN);
1047
1048 if (hw_threads >= 12) {
1049 num_comp_hi_threads = hw_threads * 3 / 4;
1050 num_comp_lo_threads = hw_threads / 3;
1051 } else if (hw_threads >= 6) {
1052 num_comp_hi_threads = hw_threads - 2;
1053 num_comp_lo_threads = hw_threads / 2;
1054 } else if (hw_threads >= 2) {
1055 num_comp_hi_threads = hw_threads - 1;
1056 num_comp_lo_threads = hw_threads / 2;
1057 } else {
1058 num_comp_hi_threads = 1;
1059 num_comp_lo_threads = 1;
1060 }
1061
1062 num_comp_hi_threads = MIN2(num_comp_hi_threads,
1063 ARRAY_SIZE(sscreen->compiler));
1064 num_comp_lo_threads = MIN2(num_comp_lo_threads,
1065 ARRAY_SIZE(sscreen->compiler_lowp));
1066
1067 /* Take a reference on the glsl types for the compiler threads. */
1068 glsl_type_singleton_init_or_ref();
1069
1070 if (!util_queue_init(&sscreen->shader_compiler_queue, "sh",
1071 64, num_comp_hi_threads,
1072 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1073 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY)) {
1074 si_destroy_shader_cache(sscreen);
1075 FREE(sscreen);
1076 glsl_type_singleton_decref();
1077 return NULL;
1078 }
1079
1080 if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
1081 "shlo",
1082 64, num_comp_lo_threads,
1083 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1084 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY |
1085 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
1086 si_destroy_shader_cache(sscreen);
1087 FREE(sscreen);
1088 glsl_type_singleton_decref();
1089 return NULL;
1090 }
1091
1092 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1093 si_init_perfcounters(sscreen);
1094
1095 sscreen->num_vbos_in_user_sgprs = sscreen->info.chip_class >= GFX9 ? 5 : 1;
1096
1097 /* Determine tessellation ring info. */
1098 bool double_offchip_buffers = sscreen->info.chip_class >= GFX7 &&
1099 sscreen->info.family != CHIP_CARRIZO &&
1100 sscreen->info.family != CHIP_STONEY;
1101 /* This must be one less than the maximum number due to a hw limitation.
1102 * Various hardware bugs need this.
1103 */
1104 unsigned max_offchip_buffers_per_se;
1105
1106 if (sscreen->info.chip_class >= GFX10)
1107 max_offchip_buffers_per_se = 256;
1108 /* Only certain chips can use the maximum value. */
1109 else if (sscreen->info.family == CHIP_VEGA12 ||
1110 sscreen->info.family == CHIP_VEGA20)
1111 max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1112 else
1113 max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
1114
1115 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1116 sscreen->info.max_se;
1117 unsigned offchip_granularity;
1118
1119 /* Hawaii has a bug with offchip buffers > 256 that can be worked
1120 * around by setting 4K granularity.
1121 */
1122 if (sscreen->info.family == CHIP_HAWAII) {
1123 sscreen->tess_offchip_block_dw_size = 4096;
1124 offchip_granularity = V_03093C_X_4K_DWORDS;
1125 } else {
1126 sscreen->tess_offchip_block_dw_size = 8192;
1127 offchip_granularity = V_03093C_X_8K_DWORDS;
1128 }
1129
1130 sscreen->tess_factor_ring_size = 32768 * sscreen->info.max_se;
1131 sscreen->tess_offchip_ring_size = max_offchip_buffers *
1132 sscreen->tess_offchip_block_dw_size * 4;
1133
1134 if (sscreen->info.chip_class >= GFX7) {
1135 if (sscreen->info.chip_class >= GFX8)
1136 --max_offchip_buffers;
1137 sscreen->vgt_hs_offchip_param =
1138 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1139 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1140 } else {
1141 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
1142 sscreen->vgt_hs_offchip_param =
1143 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1144 }
1145
1146 sscreen->has_draw_indirect_multi =
1147 (sscreen->info.family >= CHIP_POLARIS10) ||
1148 (sscreen->info.chip_class == GFX8 &&
1149 sscreen->info.pfp_fw_version >= 121 &&
1150 sscreen->info.me_fw_version >= 87) ||
1151 (sscreen->info.chip_class == GFX7 &&
1152 sscreen->info.pfp_fw_version >= 211 &&
1153 sscreen->info.me_fw_version >= 173) ||
1154 (sscreen->info.chip_class == GFX6 &&
1155 sscreen->info.pfp_fw_version >= 79 &&
1156 sscreen->info.me_fw_version >= 142);
1157
1158 sscreen->has_out_of_order_rast = sscreen->info.has_out_of_order_rast &&
1159 !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER));
1160 sscreen->assume_no_z_fights =
1161 driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
1162 sscreen->commutative_blend_add =
1163 driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
1164
1165 sscreen->use_ngg = sscreen->info.chip_class >= GFX10 &&
1166 sscreen->info.family != CHIP_NAVI14 &&
1167 !(sscreen->debug_flags & DBG(NO_NGG));
1168 sscreen->use_ngg_streamout = false;
1169
1170 /* Only enable primitive binning on APUs by default. */
1171 if (sscreen->info.chip_class >= GFX10) {
1172 sscreen->dpbb_allowed = true;
1173 sscreen->dfsm_allowed = !sscreen->info.has_dedicated_vram;
1174 } else if (sscreen->info.chip_class == GFX9) {
1175 sscreen->dpbb_allowed = !sscreen->info.has_dedicated_vram;
1176 sscreen->dfsm_allowed = !sscreen->info.has_dedicated_vram;
1177 }
1178
1179 /* Process DPBB enable flags. */
1180 if (sscreen->debug_flags & DBG(DPBB)) {
1181 sscreen->dpbb_allowed = true;
1182 if (sscreen->debug_flags & DBG(DFSM))
1183 sscreen->dfsm_allowed = true;
1184 }
1185
1186 /* Process DPBB disable flags. */
1187 if (sscreen->debug_flags & DBG(NO_DPBB)) {
1188 sscreen->dpbb_allowed = false;
1189 sscreen->dfsm_allowed = false;
1190 } else if (sscreen->debug_flags & DBG(NO_DFSM)) {
1191 sscreen->dfsm_allowed = false;
1192 }
1193
1194 /* While it would be nice not to have this flag, we are constrained
1195 * by the reality that LLVM 9.0 has buggy VGPR indexing on GFX9.
1196 */
1197 sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class != GFX9;
1198
1199 sscreen->dcc_msaa_allowed =
1200 !(sscreen->debug_flags & DBG(NO_DCC_MSAA));
1201
1202 (void) simple_mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1203 sscreen->use_monolithic_shaders =
1204 (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
1205
1206 sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SCACHE |
1207 SI_CONTEXT_INV_VCACHE;
1208 if (sscreen->info.chip_class <= GFX8) {
1209 sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_L2;
1210 sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WB_L2;
1211 }
1212
1213 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1214 sscreen->debug_flags |= DBG_ALL_SHADERS;
1215
1216 /* Syntax:
1217 * EQAA=s,z,c
1218 * Example:
1219 * EQAA=8,4,2
1220
1221 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1222 * Constraints:
1223 * s >= z >= c (ignoring this only wastes memory)
1224 * s = [2..16]
1225 * z = [2..8]
1226 * c = [2..8]
1227 *
1228 * Only MSAA color and depth buffers are overriden.
1229 */
1230 if (sscreen->info.has_eqaa_surface_allocator) {
1231 const char *eqaa = debug_get_option("EQAA", NULL);
1232 unsigned s,z,f;
1233
1234 if (eqaa && sscanf(eqaa, "%u,%u,%u", &s, &z, &f) == 3 && s && z && f) {
1235 sscreen->eqaa_force_coverage_samples = s;
1236 sscreen->eqaa_force_z_samples = z;
1237 sscreen->eqaa_force_color_samples = f;
1238 }
1239 }
1240
1241 sscreen->ge_wave_size = 64;
1242 sscreen->ps_wave_size = 64;
1243 sscreen->compute_wave_size = 64;
1244
1245 if (sscreen->info.chip_class >= GFX10) {
1246 /* Pixels shaders: Wave64 is recommended.
1247 * Compute shaders: There are piglit failures with Wave32.
1248 */
1249 sscreen->ge_wave_size = 32;
1250
1251 if (sscreen->debug_flags & DBG(W32_GE))
1252 sscreen->ge_wave_size = 32;
1253 if (sscreen->debug_flags & DBG(W32_PS))
1254 sscreen->ps_wave_size = 32;
1255 if (sscreen->debug_flags & DBG(W32_CS))
1256 sscreen->compute_wave_size = 32;
1257
1258 if (sscreen->debug_flags & DBG(W64_GE))
1259 sscreen->ge_wave_size = 64;
1260 if (sscreen->debug_flags & DBG(W64_PS))
1261 sscreen->ps_wave_size = 64;
1262 if (sscreen->debug_flags & DBG(W64_CS))
1263 sscreen->compute_wave_size = 64;
1264 }
1265
1266 /* Create the auxiliary context. This must be done last. */
1267 sscreen->aux_context = si_create_context(&sscreen->b,
1268 (sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) |
1269 (sscreen->info.has_graphics ? 0 : PIPE_CONTEXT_COMPUTE_ONLY));
1270 if (sscreen->options.aux_debug) {
1271 struct u_log_context *log = CALLOC_STRUCT(u_log_context);
1272 u_log_context_init(log);
1273 sscreen->aux_context->set_log_context(sscreen->aux_context, log);
1274 }
1275
1276 if (sscreen->debug_flags & DBG(TEST_DMA))
1277 si_test_dma(sscreen);
1278
1279 if (sscreen->debug_flags & DBG(TEST_DMA_PERF)) {
1280 si_test_dma_perf(sscreen);
1281 }
1282
1283 if (sscreen->debug_flags & (DBG(TEST_VMFAULT_CP) |
1284 DBG(TEST_VMFAULT_SDMA) |
1285 DBG(TEST_VMFAULT_SHADER)))
1286 si_test_vmfault(sscreen);
1287
1288 if (sscreen->debug_flags & DBG(TEST_GDS))
1289 si_test_gds((struct si_context*)sscreen->aux_context);
1290
1291 if (sscreen->debug_flags & DBG(TEST_GDS_MM)) {
1292 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1293 32 * 1024, 4, RADEON_DOMAIN_GDS);
1294 }
1295 if (sscreen->debug_flags & DBG(TEST_GDS_OA_MM)) {
1296 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1297 4, 1, RADEON_DOMAIN_OA);
1298 }
1299
1300 return &sscreen->b;
1301 }
1302
1303 struct pipe_screen *radeonsi_screen_create(int fd, const struct pipe_screen_config *config)
1304 {
1305 drmVersionPtr version = drmGetVersion(fd);
1306 struct radeon_winsys *rw = NULL;
1307
1308 switch (version->version_major) {
1309 case 2:
1310 rw = radeon_drm_winsys_create(fd, config, radeonsi_screen_create_impl);
1311 break;
1312 case 3:
1313 rw = amdgpu_winsys_create(fd, config, radeonsi_screen_create_impl);
1314 break;
1315 }
1316
1317 drmFreeVersion(version);
1318 return rw ? rw->screen : NULL;
1319 }