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radeonsi: add AMD_DEBUG=nogfx for testing
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "si_pipe.h"
27 #include "si_public.h"
28 #include "si_shader_internal.h"
29 #include "si_compute.h"
30 #include "sid.h"
31
32 #include "ac_llvm_util.h"
33 #include "radeon/radeon_uvd.h"
34 #include "gallivm/lp_bld_misc.h"
35 #include "util/disk_cache.h"
36 #include "util/u_log.h"
37 #include "util/u_memory.h"
38 #include "util/u_suballoc.h"
39 #include "util/u_tests.h"
40 #include "util/u_upload_mgr.h"
41 #include "util/xmlconfig.h"
42 #include "vl/vl_decoder.h"
43 #include "driver_ddebug/dd_util.h"
44
45 #include "gallium/winsys/radeon/drm/radeon_drm_public.h"
46 #include "gallium/winsys/amdgpu/drm/amdgpu_public.h"
47 #include <xf86drm.h>
48
49 static const struct debug_named_value debug_options[] = {
50 /* Shader logging options: */
51 { "vs", DBG(VS), "Print vertex shaders" },
52 { "ps", DBG(PS), "Print pixel shaders" },
53 { "gs", DBG(GS), "Print geometry shaders" },
54 { "tcs", DBG(TCS), "Print tessellation control shaders" },
55 { "tes", DBG(TES), "Print tessellation evaluation shaders" },
56 { "cs", DBG(CS), "Print compute shaders" },
57 { "noir", DBG(NO_IR), "Don't print the LLVM IR"},
58 { "notgsi", DBG(NO_TGSI), "Don't print the TGSI"},
59 { "noasm", DBG(NO_ASM), "Don't print disassembled shaders"},
60 { "preoptir", DBG(PREOPT_IR), "Print the LLVM IR before initial optimizations" },
61
62 /* Shader compiler options the shader cache should be aware of: */
63 { "unsafemath", DBG(UNSAFE_MATH), "Enable unsafe math shader optimizations" },
64 { "sisched", DBG(SI_SCHED), "Enable LLVM SI Machine Instruction Scheduler." },
65 { "gisel", DBG(GISEL), "Enable LLVM global instruction selector." },
66 { "w32ge", DBG(W32_GE), "Use Wave32 for vertex, tessellation, and geometry shaders." },
67 { "w32ps", DBG(W32_PS), "Use Wave32 for pixel shaders." },
68 { "w32cs", DBG(W32_CS), "Use Wave32 for computes shaders." },
69 { "w64ge", DBG(W64_GE), "Use Wave64 for vertex, tessellation, and geometry shaders." },
70 { "w64ps", DBG(W64_PS), "Use Wave64 for pixel shaders." },
71 { "w64cs", DBG(W64_CS), "Use Wave64 for computes shaders." },
72
73 /* Shader compiler options (with no effect on the shader cache): */
74 { "checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR" },
75 { "mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand" },
76 { "nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants." },
77
78 /* Information logging options: */
79 { "info", DBG(INFO), "Print driver information" },
80 { "tex", DBG(TEX), "Print texture info" },
81 { "compute", DBG(COMPUTE), "Print compute info" },
82 { "vm", DBG(VM), "Print virtual addresses when creating resources" },
83
84 /* Driver options: */
85 { "forcedma", DBG(FORCE_DMA), "Use asynchronous DMA for all operations when possible." },
86 { "nodma", DBG(NO_ASYNC_DMA), "Disable asynchronous DMA" },
87 { "nowc", DBG(NO_WC), "Disable GTT write combining" },
88 { "check_vm", DBG(CHECK_VM), "Check VM faults and dump debug info." },
89 { "reserve_vmid", DBG(RESERVE_VMID), "Force VMID reservation per context." },
90 { "zerovram", DBG(ZERO_VRAM), "Clear VRAM allocations." },
91
92 /* 3D engine options: */
93 { "nogfx", DBG(NO_GFX), "Disable graphics. Only multimedia compute paths can be used." },
94 { "alwayspd", DBG(ALWAYS_PD), "Always enable the primitive discard compute shader." },
95 { "pd", DBG(PD), "Enable the primitive discard compute shader for large draw calls." },
96 { "nopd", DBG(NO_PD), "Disable the primitive discard compute shader." },
97 { "switch_on_eop", DBG(SWITCH_ON_EOP), "Program WD/IA to switch on end-of-packet." },
98 { "nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order rasterization" },
99 { "nodpbb", DBG(NO_DPBB), "Disable DPBB." },
100 { "nodfsm", DBG(NO_DFSM), "Disable DFSM." },
101 { "dpbb", DBG(DPBB), "Enable DPBB." },
102 { "dfsm", DBG(DFSM), "Enable DFSM." },
103 { "nohyperz", DBG(NO_HYPERZ), "Disable Hyper-Z" },
104 { "norbplus", DBG(NO_RB_PLUS), "Disable RB+." },
105 { "no2d", DBG(NO_2D_TILING), "Disable 2D tiling" },
106 { "notiling", DBG(NO_TILING), "Disable tiling" },
107 { "nodcc", DBG(NO_DCC), "Disable DCC." },
108 { "nodccclear", DBG(NO_DCC_CLEAR), "Disable DCC fast clear." },
109 { "nodccfb", DBG(NO_DCC_FB), "Disable separate DCC on the main framebuffer" },
110 { "nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA" },
111 { "nofmask", DBG(NO_FMASK), "Disable MSAA compression" },
112
113 /* Tests: */
114 { "testdma", DBG(TEST_DMA), "Invoke SDMA tests and exit." },
115 { "testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and exit." },
116 { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA), "Invoke a SDMA VM fault test and exit." },
117 { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM fault test and exit." },
118 { "testdmaperf", DBG(TEST_DMA_PERF), "Test DMA performance" },
119 { "testgds", DBG(TEST_GDS), "Test GDS." },
120 { "testgdsmm", DBG(TEST_GDS_MM), "Test GDS memory management." },
121 { "testgdsoamm", DBG(TEST_GDS_OA_MM), "Test GDS OA memory management." },
122
123 DEBUG_NAMED_VALUE_END /* must be last */
124 };
125
126 static void si_init_compiler(struct si_screen *sscreen,
127 struct ac_llvm_compiler *compiler)
128 {
129 /* Only create the less-optimizing version of the compiler on APUs
130 * predating Ryzen (Raven). */
131 bool create_low_opt_compiler = !sscreen->info.has_dedicated_vram &&
132 sscreen->info.chip_class <= GFX8;
133
134 enum ac_target_machine_options tm_options =
135 (sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
136 (sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL : 0) |
137 (sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
138 (sscreen->info.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
139 (!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0) |
140 (sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0) |
141 (create_low_opt_compiler ? AC_TM_CREATE_LOW_OPT : 0);
142
143 ac_init_llvm_once();
144 ac_init_llvm_compiler(compiler, sscreen->info.family, tm_options);
145 compiler->passes = ac_create_llvm_passes(compiler->tm);
146
147 if (compiler->tm_wave32)
148 compiler->passes_wave32 = ac_create_llvm_passes(compiler->tm_wave32);
149 if (compiler->low_opt_tm)
150 compiler->low_opt_passes = ac_create_llvm_passes(compiler->low_opt_tm);
151 }
152
153 static void si_destroy_compiler(struct ac_llvm_compiler *compiler)
154 {
155 ac_destroy_llvm_compiler(compiler);
156 }
157
158 /*
159 * pipe_context
160 */
161 static void si_destroy_context(struct pipe_context *context)
162 {
163 struct si_context *sctx = (struct si_context *)context;
164 int i;
165
166 util_queue_finish(&sctx->screen->shader_compiler_queue);
167 util_queue_finish(&sctx->screen->shader_compiler_queue_low_priority);
168
169 /* Unreference the framebuffer normally to disable related logic
170 * properly.
171 */
172 struct pipe_framebuffer_state fb = {};
173 if (context->set_framebuffer_state)
174 context->set_framebuffer_state(context, &fb);
175
176 si_release_all_descriptors(sctx);
177
178 if (sctx->chip_class >= GFX10)
179 gfx10_destroy_query(sctx);
180
181 pipe_resource_reference(&sctx->esgs_ring, NULL);
182 pipe_resource_reference(&sctx->gsvs_ring, NULL);
183 pipe_resource_reference(&sctx->tess_rings, NULL);
184 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
185 pipe_resource_reference(&sctx->sample_pos_buffer, NULL);
186 si_resource_reference(&sctx->border_color_buffer, NULL);
187 free(sctx->border_color_table);
188 si_resource_reference(&sctx->scratch_buffer, NULL);
189 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
190 si_resource_reference(&sctx->wait_mem_scratch, NULL);
191
192 si_pm4_free_state(sctx, sctx->init_config, ~0);
193 if (sctx->init_config_gs_rings)
194 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
195 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
196 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
197
198 if (sctx->fixed_func_tcs_shader.cso)
199 sctx->b.delete_tcs_state(&sctx->b, sctx->fixed_func_tcs_shader.cso);
200 if (sctx->custom_dsa_flush)
201 sctx->b.delete_depth_stencil_alpha_state(&sctx->b, sctx->custom_dsa_flush);
202 if (sctx->custom_blend_resolve)
203 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_resolve);
204 if (sctx->custom_blend_fmask_decompress)
205 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_fmask_decompress);
206 if (sctx->custom_blend_eliminate_fastclear)
207 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_eliminate_fastclear);
208 if (sctx->custom_blend_dcc_decompress)
209 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_dcc_decompress);
210 if (sctx->vs_blit_pos)
211 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos);
212 if (sctx->vs_blit_pos_layered)
213 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos_layered);
214 if (sctx->vs_blit_color)
215 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color);
216 if (sctx->vs_blit_color_layered)
217 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color_layered);
218 if (sctx->vs_blit_texcoord)
219 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_texcoord);
220 if (sctx->cs_clear_buffer)
221 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_buffer);
222 if (sctx->cs_copy_buffer)
223 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_buffer);
224 if (sctx->cs_copy_image)
225 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image);
226 if (sctx->cs_copy_image_1d_array)
227 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image_1d_array);
228 if (sctx->cs_clear_render_target)
229 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target);
230 if (sctx->cs_clear_render_target_1d_array)
231 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target_1d_array);
232 if (sctx->cs_dcc_retile)
233 sctx->b.delete_compute_state(&sctx->b, sctx->cs_dcc_retile);
234
235 if (sctx->blitter)
236 util_blitter_destroy(sctx->blitter);
237
238 /* Release DCC stats. */
239 for (int i = 0; i < ARRAY_SIZE(sctx->dcc_stats); i++) {
240 assert(!sctx->dcc_stats[i].query_active);
241
242 for (int j = 0; j < ARRAY_SIZE(sctx->dcc_stats[i].ps_stats); j++)
243 if (sctx->dcc_stats[i].ps_stats[j])
244 sctx->b.destroy_query(&sctx->b,
245 sctx->dcc_stats[i].ps_stats[j]);
246
247 si_texture_reference(&sctx->dcc_stats[i].tex, NULL);
248 }
249
250 if (sctx->query_result_shader)
251 sctx->b.delete_compute_state(&sctx->b, sctx->query_result_shader);
252 if (sctx->sh_query_result_shader)
253 sctx->b.delete_compute_state(&sctx->b, sctx->sh_query_result_shader);
254
255 if (sctx->gfx_cs)
256 sctx->ws->cs_destroy(sctx->gfx_cs);
257 if (sctx->dma_cs)
258 sctx->ws->cs_destroy(sctx->dma_cs);
259 if (sctx->ctx)
260 sctx->ws->ctx_destroy(sctx->ctx);
261
262 if (sctx->b.stream_uploader)
263 u_upload_destroy(sctx->b.stream_uploader);
264 if (sctx->b.const_uploader)
265 u_upload_destroy(sctx->b.const_uploader);
266 if (sctx->cached_gtt_allocator)
267 u_upload_destroy(sctx->cached_gtt_allocator);
268
269 slab_destroy_child(&sctx->pool_transfers);
270 slab_destroy_child(&sctx->pool_transfers_unsync);
271
272 if (sctx->allocator_zeroed_memory)
273 u_suballocator_destroy(sctx->allocator_zeroed_memory);
274
275 sctx->ws->fence_reference(&sctx->last_gfx_fence, NULL);
276 sctx->ws->fence_reference(&sctx->last_sdma_fence, NULL);
277 sctx->ws->fence_reference(&sctx->last_ib_barrier_fence, NULL);
278 si_resource_reference(&sctx->eop_bug_scratch, NULL);
279 si_resource_reference(&sctx->index_ring, NULL);
280 si_resource_reference(&sctx->barrier_buf, NULL);
281 si_resource_reference(&sctx->last_ib_barrier_buf, NULL);
282 pb_reference(&sctx->gds, NULL);
283 pb_reference(&sctx->gds_oa, NULL);
284
285 si_destroy_compiler(&sctx->compiler);
286
287 si_saved_cs_reference(&sctx->current_saved_cs, NULL);
288
289 _mesa_hash_table_destroy(sctx->tex_handles, NULL);
290 _mesa_hash_table_destroy(sctx->img_handles, NULL);
291
292 util_dynarray_fini(&sctx->resident_tex_handles);
293 util_dynarray_fini(&sctx->resident_img_handles);
294 util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
295 util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
296 util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
297 si_unref_sdma_uploads(sctx);
298 FREE(sctx);
299 }
300
301 static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx)
302 {
303 struct si_context *sctx = (struct si_context *)ctx;
304
305 return sctx->ws->ctx_query_reset_status(sctx->ctx);
306 }
307
308 static void si_set_device_reset_callback(struct pipe_context *ctx,
309 const struct pipe_device_reset_callback *cb)
310 {
311 struct si_context *sctx = (struct si_context *)ctx;
312
313 if (cb)
314 sctx->device_reset_callback = *cb;
315 else
316 memset(&sctx->device_reset_callback, 0,
317 sizeof(sctx->device_reset_callback));
318 }
319
320 bool si_check_device_reset(struct si_context *sctx)
321 {
322 enum pipe_reset_status status;
323
324 if (!sctx->device_reset_callback.reset)
325 return false;
326
327 status = sctx->ws->ctx_query_reset_status(sctx->ctx);
328 if (status == PIPE_NO_RESET)
329 return false;
330
331 sctx->device_reset_callback.reset(sctx->device_reset_callback.data, status);
332 return true;
333 }
334
335 /* Apitrace profiling:
336 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
337 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
338 * and remember its number.
339 * 3) In Mesa, enable queries and performance counters around that draw
340 * call and print the results.
341 * 4) glretrace --benchmark --markers ..
342 */
343 static void si_emit_string_marker(struct pipe_context *ctx,
344 const char *string, int len)
345 {
346 struct si_context *sctx = (struct si_context *)ctx;
347
348 dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
349
350 if (sctx->log)
351 u_log_printf(sctx->log, "\nString marker: %*s\n", len, string);
352 }
353
354 static void si_set_debug_callback(struct pipe_context *ctx,
355 const struct pipe_debug_callback *cb)
356 {
357 struct si_context *sctx = (struct si_context *)ctx;
358 struct si_screen *screen = sctx->screen;
359
360 util_queue_finish(&screen->shader_compiler_queue);
361 util_queue_finish(&screen->shader_compiler_queue_low_priority);
362
363 if (cb)
364 sctx->debug = *cb;
365 else
366 memset(&sctx->debug, 0, sizeof(sctx->debug));
367 }
368
369 static void si_set_log_context(struct pipe_context *ctx,
370 struct u_log_context *log)
371 {
372 struct si_context *sctx = (struct si_context *)ctx;
373 sctx->log = log;
374
375 if (log)
376 u_log_add_auto_logger(log, si_auto_log_cs, sctx);
377 }
378
379 static void si_set_context_param(struct pipe_context *ctx,
380 enum pipe_context_param param,
381 unsigned value)
382 {
383 struct radeon_winsys *ws = ((struct si_context *)ctx)->ws;
384
385 switch (param) {
386 case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE:
387 ws->pin_threads_to_L3_cache(ws, value);
388 break;
389 default:;
390 }
391 }
392
393 static struct pipe_context *si_create_context(struct pipe_screen *screen,
394 unsigned flags)
395 {
396 struct si_screen* sscreen = (struct si_screen *)screen;
397
398 /* Don't create a context if it's not compute-only and hw is compute-only. */
399 if (!sscreen->info.has_graphics &&
400 !(flags & PIPE_CONTEXT_COMPUTE_ONLY))
401 return NULL;
402
403 struct si_context *sctx = CALLOC_STRUCT(si_context);
404 struct radeon_winsys *ws = sscreen->ws;
405 int shader, i;
406 bool stop_exec_on_failure = (flags & PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET) != 0;
407
408 if (!sctx)
409 return NULL;
410
411 sctx->has_graphics = sscreen->info.chip_class == GFX6 ||
412 !(flags & PIPE_CONTEXT_COMPUTE_ONLY);
413
414 if (flags & PIPE_CONTEXT_DEBUG)
415 sscreen->record_llvm_ir = true; /* racy but not critical */
416
417 sctx->b.screen = screen; /* this must be set first */
418 sctx->b.priv = NULL;
419 sctx->b.destroy = si_destroy_context;
420 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
421 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
422
423 slab_create_child(&sctx->pool_transfers, &sscreen->pool_transfers);
424 slab_create_child(&sctx->pool_transfers_unsync, &sscreen->pool_transfers);
425
426 sctx->ws = sscreen->ws;
427 sctx->family = sscreen->info.family;
428 sctx->chip_class = sscreen->info.chip_class;
429
430 if (sctx->chip_class == GFX7 ||
431 sctx->chip_class == GFX8 ||
432 sctx->chip_class == GFX9) {
433 sctx->eop_bug_scratch = si_resource(
434 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
435 16 * sscreen->info.num_render_backends));
436 if (!sctx->eop_bug_scratch)
437 goto fail;
438 }
439
440 /* Initialize context allocators. */
441 sctx->allocator_zeroed_memory =
442 u_suballocator_create(&sctx->b, 128 * 1024,
443 0, PIPE_USAGE_DEFAULT,
444 SI_RESOURCE_FLAG_UNMAPPABLE |
445 SI_RESOURCE_FLAG_CLEAR, false);
446 if (!sctx->allocator_zeroed_memory)
447 goto fail;
448
449 sctx->b.stream_uploader = u_upload_create(&sctx->b, 1024 * 1024,
450 0, PIPE_USAGE_STREAM,
451 SI_RESOURCE_FLAG_READ_ONLY);
452 if (!sctx->b.stream_uploader)
453 goto fail;
454
455 sctx->cached_gtt_allocator = u_upload_create(&sctx->b, 16 * 1024,
456 0, PIPE_USAGE_STAGING, 0);
457 if (!sctx->cached_gtt_allocator)
458 goto fail;
459
460 sctx->ctx = sctx->ws->ctx_create(sctx->ws);
461 if (!sctx->ctx)
462 goto fail;
463
464 if (sscreen->info.num_sdma_rings && !(sscreen->debug_flags & DBG(NO_ASYNC_DMA))) {
465 sctx->dma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA,
466 (void*)si_flush_dma_cs,
467 sctx, stop_exec_on_failure);
468 }
469
470 bool use_sdma_upload = sscreen->info.has_dedicated_vram && sctx->dma_cs;
471 sctx->b.const_uploader = u_upload_create(&sctx->b, 256 * 1024,
472 0, PIPE_USAGE_DEFAULT,
473 SI_RESOURCE_FLAG_32BIT |
474 (use_sdma_upload ?
475 SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA : 0));
476 if (!sctx->b.const_uploader)
477 goto fail;
478
479 if (use_sdma_upload)
480 u_upload_enable_flush_explicit(sctx->b.const_uploader);
481
482 sctx->gfx_cs = ws->cs_create(sctx->ctx,
483 sctx->has_graphics ? RING_GFX : RING_COMPUTE,
484 (void*)si_flush_gfx_cs, sctx, stop_exec_on_failure);
485
486 /* Border colors. */
487 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
488 sizeof(*sctx->border_color_table));
489 if (!sctx->border_color_table)
490 goto fail;
491
492 sctx->border_color_buffer = si_resource(
493 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
494 SI_MAX_BORDER_COLORS *
495 sizeof(*sctx->border_color_table)));
496 if (!sctx->border_color_buffer)
497 goto fail;
498
499 sctx->border_color_map =
500 ws->buffer_map(sctx->border_color_buffer->buf,
501 NULL, PIPE_TRANSFER_WRITE);
502 if (!sctx->border_color_map)
503 goto fail;
504
505 sctx->ngg = sctx->chip_class >= GFX10;
506
507 /* Initialize context functions used by graphics and compute. */
508 if (sctx->chip_class >= GFX10)
509 sctx->emit_cache_flush = gfx10_emit_cache_flush;
510 else
511 sctx->emit_cache_flush = si_emit_cache_flush;
512
513 sctx->b.emit_string_marker = si_emit_string_marker;
514 sctx->b.set_debug_callback = si_set_debug_callback;
515 sctx->b.set_log_context = si_set_log_context;
516 sctx->b.set_context_param = si_set_context_param;
517 sctx->b.get_device_reset_status = si_get_reset_status;
518 sctx->b.set_device_reset_callback = si_set_device_reset_callback;
519
520 si_init_all_descriptors(sctx);
521 si_init_buffer_functions(sctx);
522 si_init_clear_functions(sctx);
523 si_init_blit_functions(sctx);
524 si_init_compute_functions(sctx);
525 si_init_compute_blit_functions(sctx);
526 si_init_debug_functions(sctx);
527 si_init_fence_functions(sctx);
528 si_init_query_functions(sctx);
529 si_init_state_compute_functions(sctx);
530 si_init_context_texture_functions(sctx);
531
532 /* Initialize graphics-only context functions. */
533 if (sctx->has_graphics) {
534 if (sctx->chip_class >= GFX10)
535 gfx10_init_query(sctx);
536 si_init_msaa_functions(sctx);
537 si_init_shader_functions(sctx);
538 si_init_state_functions(sctx);
539 si_init_streamout_functions(sctx);
540 si_init_viewport_functions(sctx);
541
542 sctx->blitter = util_blitter_create(&sctx->b);
543 if (sctx->blitter == NULL)
544 goto fail;
545 sctx->blitter->skip_viewport_restore = true;
546
547 si_init_draw_functions(sctx);
548 si_initialize_prim_discard_tunables(sctx);
549 }
550
551 /* Initialize SDMA functions. */
552 if (sctx->chip_class >= GFX7)
553 cik_init_sdma_functions(sctx);
554 else
555 si_init_dma_functions(sctx);
556
557 if (sscreen->debug_flags & DBG(FORCE_DMA))
558 sctx->b.resource_copy_region = sctx->dma_copy;
559
560 sctx->sample_mask = 0xffff;
561
562 /* Initialize multimedia functions. */
563 if (sscreen->info.has_hw_decode) {
564 sctx->b.create_video_codec = si_uvd_create_decoder;
565 sctx->b.create_video_buffer = si_video_buffer_create;
566 } else {
567 sctx->b.create_video_codec = vl_create_decoder;
568 sctx->b.create_video_buffer = vl_video_buffer_create;
569 }
570
571 if (sctx->chip_class >= GFX9) {
572 sctx->wait_mem_scratch = si_resource(
573 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 8));
574 if (!sctx->wait_mem_scratch)
575 goto fail;
576
577 /* Initialize the memory. */
578 si_cp_write_data(sctx, sctx->wait_mem_scratch, 0, 4,
579 V_370_MEM, V_370_ME, &sctx->wait_mem_number);
580 }
581
582 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
583 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
584 if (sctx->chip_class == GFX7) {
585 sctx->null_const_buf.buffer =
586 pipe_aligned_buffer_create(screen,
587 SI_RESOURCE_FLAG_32BIT,
588 PIPE_USAGE_DEFAULT, 16,
589 sctx->screen->info.tcc_cache_line_size);
590 if (!sctx->null_const_buf.buffer)
591 goto fail;
592 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
593
594 unsigned start_shader = sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE;
595 for (shader = start_shader; shader < SI_NUM_SHADERS; shader++) {
596 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
597 sctx->b.set_constant_buffer(&sctx->b, shader, i,
598 &sctx->null_const_buf);
599 }
600 }
601
602 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
603 &sctx->null_const_buf);
604 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
605 &sctx->null_const_buf);
606 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
607 &sctx->null_const_buf);
608 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
609 &sctx->null_const_buf);
610 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
611 &sctx->null_const_buf);
612 }
613
614 uint64_t max_threads_per_block;
615 screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
616 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
617 &max_threads_per_block);
618
619 /* The maximum number of scratch waves. Scratch space isn't divided
620 * evenly between CUs. The number is only a function of the number of CUs.
621 * We can decrease the constant to decrease the scratch buffer size.
622 *
623 * sctx->scratch_waves must be >= the maximum posible size of
624 * 1 threadgroup, so that the hw doesn't hang from being unable
625 * to start any.
626 *
627 * The recommended value is 4 per CU at most. Higher numbers don't
628 * bring much benefit, but they still occupy chip resources (think
629 * async compute). I've seen ~2% performance difference between 4 and 32.
630 */
631 sctx->scratch_waves = MAX2(32 * sscreen->info.num_good_compute_units,
632 max_threads_per_block / 64);
633
634 si_init_compiler(sscreen, &sctx->compiler);
635
636 /* Bindless handles. */
637 sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
638 _mesa_key_pointer_equal);
639 sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
640 _mesa_key_pointer_equal);
641
642 util_dynarray_init(&sctx->resident_tex_handles, NULL);
643 util_dynarray_init(&sctx->resident_img_handles, NULL);
644 util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
645 util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
646 util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
647
648 sctx->sample_pos_buffer =
649 pipe_buffer_create(sctx->b.screen, 0, PIPE_USAGE_DEFAULT,
650 sizeof(sctx->sample_positions));
651 pipe_buffer_write(&sctx->b, sctx->sample_pos_buffer, 0,
652 sizeof(sctx->sample_positions), &sctx->sample_positions);
653
654 /* this must be last */
655 si_begin_new_gfx_cs(sctx);
656
657 if (sctx->chip_class == GFX7) {
658 /* Clear the NULL constant buffer, because loads should return zeros.
659 * Note that this forces CP DMA to be used, because clover deadlocks
660 * for some reason when the compute codepath is used.
661 */
662 uint32_t clear_value = 0;
663 si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0,
664 sctx->null_const_buf.buffer->width0,
665 &clear_value, 4, SI_COHERENCY_SHADER, true);
666 }
667 return &sctx->b;
668 fail:
669 fprintf(stderr, "radeonsi: Failed to create a context.\n");
670 si_destroy_context(&sctx->b);
671 return NULL;
672 }
673
674 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
675 void *priv, unsigned flags)
676 {
677 struct si_screen *sscreen = (struct si_screen *)screen;
678 struct pipe_context *ctx;
679
680 if (sscreen->debug_flags & DBG(CHECK_VM))
681 flags |= PIPE_CONTEXT_DEBUG;
682
683 ctx = si_create_context(screen, flags);
684
685 if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
686 return ctx;
687
688 /* Clover (compute-only) is unsupported. */
689 if (flags & PIPE_CONTEXT_COMPUTE_ONLY)
690 return ctx;
691
692 /* When shaders are logged to stderr, asynchronous compilation is
693 * disabled too. */
694 if (sscreen->debug_flags & DBG_ALL_SHADERS)
695 return ctx;
696
697 /* Use asynchronous flushes only on amdgpu, since the radeon
698 * implementation for fence_server_sync is incomplete. */
699 return threaded_context_create(ctx, &sscreen->pool_transfers,
700 si_replace_buffer_storage,
701 sscreen->info.is_amdgpu ? si_create_fence : NULL,
702 &((struct si_context*)ctx)->tc);
703 }
704
705 /*
706 * pipe_screen
707 */
708 static void si_destroy_screen(struct pipe_screen* pscreen)
709 {
710 struct si_screen *sscreen = (struct si_screen *)pscreen;
711 struct si_shader_part *parts[] = {
712 sscreen->vs_prologs,
713 sscreen->tcs_epilogs,
714 sscreen->gs_prologs,
715 sscreen->ps_prologs,
716 sscreen->ps_epilogs
717 };
718 unsigned i;
719
720 if (!sscreen->ws->unref(sscreen->ws))
721 return;
722
723 mtx_destroy(&sscreen->aux_context_lock);
724
725 struct u_log_context *aux_log = ((struct si_context *)sscreen->aux_context)->log;
726 if (aux_log) {
727 sscreen->aux_context->set_log_context(sscreen->aux_context, NULL);
728 u_log_context_destroy(aux_log);
729 FREE(aux_log);
730 }
731
732 sscreen->aux_context->destroy(sscreen->aux_context);
733
734 util_queue_destroy(&sscreen->shader_compiler_queue);
735 util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
736
737 for (i = 0; i < ARRAY_SIZE(sscreen->compiler); i++)
738 si_destroy_compiler(&sscreen->compiler[i]);
739
740 for (i = 0; i < ARRAY_SIZE(sscreen->compiler_lowp); i++)
741 si_destroy_compiler(&sscreen->compiler_lowp[i]);
742
743 /* Free shader parts. */
744 for (i = 0; i < ARRAY_SIZE(parts); i++) {
745 while (parts[i]) {
746 struct si_shader_part *part = parts[i];
747
748 parts[i] = part->next;
749 si_shader_binary_clean(&part->binary);
750 FREE(part);
751 }
752 }
753 mtx_destroy(&sscreen->shader_parts_mutex);
754 si_destroy_shader_cache(sscreen);
755
756 si_destroy_perfcounters(sscreen);
757 si_gpu_load_kill_thread(sscreen);
758
759 mtx_destroy(&sscreen->gpu_load_mutex);
760
761 slab_destroy_parent(&sscreen->pool_transfers);
762
763 disk_cache_destroy(sscreen->disk_shader_cache);
764 sscreen->ws->destroy(sscreen->ws);
765 FREE(sscreen);
766 }
767
768 static void si_init_gs_info(struct si_screen *sscreen)
769 {
770 sscreen->gs_table_depth = ac_get_gs_table_depth(sscreen->info.chip_class,
771 sscreen->info.family);
772 }
773
774 static void si_test_vmfault(struct si_screen *sscreen)
775 {
776 struct pipe_context *ctx = sscreen->aux_context;
777 struct si_context *sctx = (struct si_context *)ctx;
778 struct pipe_resource *buf =
779 pipe_buffer_create_const0(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 64);
780
781 if (!buf) {
782 puts("Buffer allocation failed.");
783 exit(1);
784 }
785
786 si_resource(buf)->gpu_address = 0; /* cause a VM fault */
787
788 if (sscreen->debug_flags & DBG(TEST_VMFAULT_CP)) {
789 si_cp_dma_copy_buffer(sctx, buf, buf, 0, 4, 4, 0,
790 SI_COHERENCY_NONE, L2_BYPASS);
791 ctx->flush(ctx, NULL, 0);
792 puts("VM fault test: CP - done.");
793 }
794 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SDMA)) {
795 si_sdma_clear_buffer(sctx, buf, 0, 4, 0);
796 ctx->flush(ctx, NULL, 0);
797 puts("VM fault test: SDMA - done.");
798 }
799 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SHADER)) {
800 util_test_constant_buffer(ctx, buf);
801 puts("VM fault test: Shader - done.");
802 }
803 exit(0);
804 }
805
806 static void si_test_gds_memory_management(struct si_context *sctx,
807 unsigned alloc_size, unsigned alignment,
808 enum radeon_bo_domain domain)
809 {
810 struct radeon_winsys *ws = sctx->ws;
811 struct radeon_cmdbuf *cs[8];
812 struct pb_buffer *gds_bo[ARRAY_SIZE(cs)];
813
814 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
815 cs[i] = ws->cs_create(sctx->ctx, RING_COMPUTE,
816 NULL, NULL, false);
817 gds_bo[i] = ws->buffer_create(ws, alloc_size, alignment, domain, 0);
818 assert(gds_bo[i]);
819 }
820
821 for (unsigned iterations = 0; iterations < 20000; iterations++) {
822 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
823 /* This clears GDS with CP DMA.
824 *
825 * We don't care if GDS is present. Just add some packet
826 * to make the GPU busy for a moment.
827 */
828 si_cp_dma_clear_buffer(sctx, cs[i], NULL, 0, alloc_size, 0,
829 SI_CPDMA_SKIP_BO_LIST_UPDATE |
830 SI_CPDMA_SKIP_CHECK_CS_SPACE |
831 SI_CPDMA_SKIP_GFX_SYNC, 0, 0);
832
833 ws->cs_add_buffer(cs[i], gds_bo[i], domain,
834 RADEON_USAGE_READWRITE, 0);
835 ws->cs_flush(cs[i], PIPE_FLUSH_ASYNC, NULL);
836 }
837 }
838 exit(0);
839 }
840
841 static void si_disk_cache_create(struct si_screen *sscreen)
842 {
843 /* Don't use the cache if shader dumping is enabled. */
844 if (sscreen->debug_flags & DBG_ALL_SHADERS)
845 return;
846
847 struct mesa_sha1 ctx;
848 unsigned char sha1[20];
849 char cache_id[20 * 2 + 1];
850
851 _mesa_sha1_init(&ctx);
852
853 if (!disk_cache_get_function_identifier(si_disk_cache_create, &ctx) ||
854 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo,
855 &ctx))
856 return;
857
858 _mesa_sha1_final(&ctx, sha1);
859 disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
860
861 /* These flags affect shader compilation. */
862 #define ALL_FLAGS (DBG(FS_CORRECT_DERIVS_AFTER_KILL) | \
863 DBG(SI_SCHED) | \
864 DBG(GISEL) | \
865 DBG(UNSAFE_MATH) | \
866 DBG(W32_GE) | \
867 DBG(W32_PS) | \
868 DBG(W32_CS) | \
869 DBG(W64_GE) | \
870 DBG(W64_PS) | \
871 DBG(W64_CS))
872 uint64_t shader_debug_flags = sscreen->debug_flags & ALL_FLAGS;
873
874 if (sscreen->options.enable_nir) {
875 STATIC_ASSERT((ALL_FLAGS & (1u << 31)) == 0);
876 shader_debug_flags |= 1u << 31;
877 }
878
879 /* Add the high bits of 32-bit addresses, which affects
880 * how 32-bit addresses are expanded to 64 bits.
881 */
882 STATIC_ASSERT(ALL_FLAGS <= UINT_MAX);
883 assert((int16_t)sscreen->info.address32_hi == (int32_t)sscreen->info.address32_hi);
884 shader_debug_flags |= (uint64_t)(sscreen->info.address32_hi & 0xffff) << 32;
885
886 sscreen->disk_shader_cache =
887 disk_cache_create(sscreen->info.name,
888 cache_id,
889 shader_debug_flags);
890 }
891
892 static void si_set_max_shader_compiler_threads(struct pipe_screen *screen,
893 unsigned max_threads)
894 {
895 struct si_screen *sscreen = (struct si_screen *)screen;
896
897 /* This function doesn't allow a greater number of threads than
898 * the queue had at its creation. */
899 util_queue_adjust_num_threads(&sscreen->shader_compiler_queue,
900 max_threads);
901 /* Don't change the number of threads on the low priority queue. */
902 }
903
904 static bool si_is_parallel_shader_compilation_finished(struct pipe_screen *screen,
905 void *shader,
906 enum pipe_shader_type shader_type)
907 {
908 struct si_shader_selector *sel = (struct si_shader_selector *)shader;
909
910 return util_queue_fence_is_signalled(&sel->ready);
911 }
912
913 static struct pipe_screen *
914 radeonsi_screen_create_impl(struct radeon_winsys *ws,
915 const struct pipe_screen_config *config)
916 {
917 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
918 unsigned hw_threads, num_comp_hi_threads, num_comp_lo_threads, i;
919
920 if (!sscreen) {
921 return NULL;
922 }
923
924 sscreen->ws = ws;
925 ws->query_info(ws, &sscreen->info);
926
927 if (sscreen->info.chip_class == GFX10 && HAVE_LLVM < 0x0900) {
928 fprintf(stderr, "radeonsi: Navi family support requires LLVM 9 or higher\n");
929 FREE(sscreen);
930 return NULL;
931 }
932
933 if (sscreen->info.chip_class >= GFX9) {
934 sscreen->se_tile_repeat = 32 * sscreen->info.max_se;
935 } else {
936 ac_get_raster_config(&sscreen->info,
937 &sscreen->pa_sc_raster_config,
938 &sscreen->pa_sc_raster_config_1,
939 &sscreen->se_tile_repeat);
940 }
941
942 sscreen->debug_flags = debug_get_flags_option("R600_DEBUG",
943 debug_options, 0);
944 sscreen->debug_flags |= debug_get_flags_option("AMD_DEBUG",
945 debug_options, 0);
946
947 if (sscreen->debug_flags & DBG(NO_GFX))
948 sscreen->info.has_graphics = false;
949
950 /* Set functions first. */
951 sscreen->b.context_create = si_pipe_create_context;
952 sscreen->b.destroy = si_destroy_screen;
953 sscreen->b.set_max_shader_compiler_threads =
954 si_set_max_shader_compiler_threads;
955 sscreen->b.is_parallel_shader_compilation_finished =
956 si_is_parallel_shader_compilation_finished;
957
958 si_init_screen_get_functions(sscreen);
959 si_init_screen_buffer_functions(sscreen);
960 si_init_screen_fence_functions(sscreen);
961 si_init_screen_state_functions(sscreen);
962 si_init_screen_texture_functions(sscreen);
963 si_init_screen_query_functions(sscreen);
964
965 /* Set these flags in debug_flags early, so that the shader cache takes
966 * them into account.
967 */
968 if (driQueryOptionb(config->options,
969 "glsl_correct_derivatives_after_discard"))
970 sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
971 if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
972 sscreen->debug_flags |= DBG(SI_SCHED);
973
974 if (sscreen->debug_flags & DBG(INFO))
975 ac_print_gpu_info(&sscreen->info);
976
977 slab_create_parent(&sscreen->pool_transfers,
978 sizeof(struct si_transfer), 64);
979
980 sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
981 if (sscreen->force_aniso == -1) {
982 sscreen->force_aniso = MIN2(16, debug_get_num_option("AMD_TEX_ANISO", -1));
983 }
984
985 if (sscreen->force_aniso >= 0) {
986 printf("radeonsi: Forcing anisotropy filter to %ix\n",
987 /* round down to a power of two */
988 1 << util_logbase2(sscreen->force_aniso));
989 }
990
991 (void) mtx_init(&sscreen->aux_context_lock, mtx_plain);
992 (void) mtx_init(&sscreen->gpu_load_mutex, mtx_plain);
993
994 si_init_gs_info(sscreen);
995 if (!si_init_shader_cache(sscreen)) {
996 FREE(sscreen);
997 return NULL;
998 }
999
1000 si_disk_cache_create(sscreen);
1001
1002 /* Determine the number of shader compiler threads. */
1003 hw_threads = sysconf(_SC_NPROCESSORS_ONLN);
1004
1005 if (hw_threads >= 12) {
1006 num_comp_hi_threads = hw_threads * 3 / 4;
1007 num_comp_lo_threads = hw_threads / 3;
1008 } else if (hw_threads >= 6) {
1009 num_comp_hi_threads = hw_threads - 2;
1010 num_comp_lo_threads = hw_threads / 2;
1011 } else if (hw_threads >= 2) {
1012 num_comp_hi_threads = hw_threads - 1;
1013 num_comp_lo_threads = hw_threads / 2;
1014 } else {
1015 num_comp_hi_threads = 1;
1016 num_comp_lo_threads = 1;
1017 }
1018
1019 num_comp_hi_threads = MIN2(num_comp_hi_threads,
1020 ARRAY_SIZE(sscreen->compiler));
1021 num_comp_lo_threads = MIN2(num_comp_lo_threads,
1022 ARRAY_SIZE(sscreen->compiler_lowp));
1023
1024 if (!util_queue_init(&sscreen->shader_compiler_queue, "sh",
1025 64, num_comp_hi_threads,
1026 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1027 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY)) {
1028 si_destroy_shader_cache(sscreen);
1029 FREE(sscreen);
1030 return NULL;
1031 }
1032
1033 if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
1034 "shlo",
1035 64, num_comp_lo_threads,
1036 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1037 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY |
1038 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
1039 si_destroy_shader_cache(sscreen);
1040 FREE(sscreen);
1041 return NULL;
1042 }
1043
1044 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1045 si_init_perfcounters(sscreen);
1046
1047 /* Determine tessellation ring info. */
1048 bool double_offchip_buffers = sscreen->info.chip_class >= GFX7 &&
1049 sscreen->info.family != CHIP_CARRIZO &&
1050 sscreen->info.family != CHIP_STONEY;
1051 /* This must be one less than the maximum number due to a hw limitation.
1052 * Various hardware bugs need this.
1053 */
1054 unsigned max_offchip_buffers_per_se;
1055
1056 if (sscreen->info.chip_class >= GFX10)
1057 max_offchip_buffers_per_se = 256;
1058 /* Only certain chips can use the maximum value. */
1059 else if (sscreen->info.family == CHIP_VEGA12 ||
1060 sscreen->info.family == CHIP_VEGA20)
1061 max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1062 else
1063 max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
1064
1065 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1066 sscreen->info.max_se;
1067 unsigned offchip_granularity;
1068
1069 /* Hawaii has a bug with offchip buffers > 256 that can be worked
1070 * around by setting 4K granularity.
1071 */
1072 if (sscreen->info.family == CHIP_HAWAII) {
1073 sscreen->tess_offchip_block_dw_size = 4096;
1074 offchip_granularity = V_03093C_X_4K_DWORDS;
1075 } else {
1076 sscreen->tess_offchip_block_dw_size = 8192;
1077 offchip_granularity = V_03093C_X_8K_DWORDS;
1078 }
1079
1080 sscreen->tess_factor_ring_size = 32768 * sscreen->info.max_se;
1081 assert(((sscreen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
1082 sscreen->tess_offchip_ring_size = max_offchip_buffers *
1083 sscreen->tess_offchip_block_dw_size * 4;
1084
1085 if (sscreen->info.chip_class >= GFX7) {
1086 if (sscreen->info.chip_class >= GFX8)
1087 --max_offchip_buffers;
1088 sscreen->vgt_hs_offchip_param =
1089 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1090 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1091 } else {
1092 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
1093 sscreen->vgt_hs_offchip_param =
1094 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1095 }
1096
1097 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
1098 * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
1099 * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel. */
1100 sscreen->has_clear_state = sscreen->info.chip_class >= GFX7 &&
1101 sscreen->info.is_amdgpu;
1102
1103 sscreen->has_distributed_tess =
1104 sscreen->info.chip_class >= GFX8 &&
1105 sscreen->info.max_se >= 2;
1106
1107 sscreen->has_draw_indirect_multi =
1108 (sscreen->info.family >= CHIP_POLARIS10) ||
1109 (sscreen->info.chip_class == GFX8 &&
1110 sscreen->info.pfp_fw_version >= 121 &&
1111 sscreen->info.me_fw_version >= 87) ||
1112 (sscreen->info.chip_class == GFX7 &&
1113 sscreen->info.pfp_fw_version >= 211 &&
1114 sscreen->info.me_fw_version >= 173) ||
1115 (sscreen->info.chip_class == GFX6 &&
1116 sscreen->info.pfp_fw_version >= 79 &&
1117 sscreen->info.me_fw_version >= 142);
1118
1119 sscreen->has_out_of_order_rast = sscreen->info.chip_class >= GFX8 &&
1120 sscreen->info.max_se >= 2 &&
1121 !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER));
1122 sscreen->assume_no_z_fights =
1123 driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
1124 sscreen->commutative_blend_add =
1125 driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
1126
1127 {
1128 #define OPT_BOOL(name, dflt, description) \
1129 sscreen->options.name = \
1130 driQueryOptionb(config->options, "radeonsi_"#name);
1131 #include "si_debug_options.h"
1132 }
1133
1134 sscreen->has_gfx9_scissor_bug = sscreen->info.family == CHIP_VEGA10 ||
1135 sscreen->info.family == CHIP_RAVEN;
1136 sscreen->has_msaa_sample_loc_bug = (sscreen->info.family >= CHIP_POLARIS10 &&
1137 sscreen->info.family <= CHIP_POLARIS12) ||
1138 sscreen->info.family == CHIP_VEGA10 ||
1139 sscreen->info.family == CHIP_RAVEN;
1140 sscreen->has_ls_vgpr_init_bug = sscreen->info.family == CHIP_VEGA10 ||
1141 sscreen->info.family == CHIP_RAVEN;
1142 sscreen->has_dcc_constant_encode = sscreen->info.family == CHIP_RAVEN2 ||
1143 sscreen->info.chip_class >= GFX10;
1144
1145 /* Only enable primitive binning on APUs by default. */
1146 if (sscreen->info.chip_class >= GFX10) {
1147 sscreen->dpbb_allowed = true;
1148 sscreen->dfsm_allowed = !sscreen->info.has_dedicated_vram;
1149 } else if (sscreen->info.chip_class == GFX9) {
1150 sscreen->dpbb_allowed = !sscreen->info.has_dedicated_vram;
1151 sscreen->dfsm_allowed = !sscreen->info.has_dedicated_vram;
1152 }
1153
1154 /* Process DPBB enable flags. */
1155 if (sscreen->debug_flags & DBG(DPBB)) {
1156 sscreen->dpbb_allowed = true;
1157 if (sscreen->debug_flags & DBG(DFSM))
1158 sscreen->dfsm_allowed = true;
1159 }
1160
1161 /* Process DPBB disable flags. */
1162 if (sscreen->debug_flags & DBG(NO_DPBB)) {
1163 sscreen->dpbb_allowed = false;
1164 sscreen->dfsm_allowed = false;
1165 } else if (sscreen->debug_flags & DBG(NO_DFSM)) {
1166 sscreen->dfsm_allowed = false;
1167 }
1168
1169 /* While it would be nice not to have this flag, we are constrained
1170 * by the reality that LLVM 9.0 has buggy VGPR indexing on GFX9.
1171 */
1172 sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class != GFX9;
1173
1174 /* Some chips have RB+ registers, but don't support RB+. Those must
1175 * always disable it.
1176 */
1177 if (sscreen->info.family == CHIP_STONEY ||
1178 sscreen->info.chip_class >= GFX9) {
1179 sscreen->has_rbplus = true;
1180
1181 sscreen->rbplus_allowed =
1182 !(sscreen->debug_flags & DBG(NO_RB_PLUS)) &&
1183 (sscreen->info.family == CHIP_STONEY ||
1184 sscreen->info.family == CHIP_VEGA12 ||
1185 sscreen->info.family == CHIP_RAVEN ||
1186 sscreen->info.family == CHIP_RAVEN2);
1187 }
1188
1189 sscreen->dcc_msaa_allowed =
1190 !(sscreen->debug_flags & DBG(NO_DCC_MSAA));
1191
1192 sscreen->cpdma_prefetch_writes_memory = sscreen->info.chip_class <= GFX8;
1193
1194 (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1195 sscreen->use_monolithic_shaders =
1196 (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
1197
1198 sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SCACHE |
1199 SI_CONTEXT_INV_VCACHE;
1200 if (sscreen->info.chip_class <= GFX8) {
1201 sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_L2;
1202 sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WB_L2;
1203 }
1204
1205 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1206 sscreen->debug_flags |= DBG_ALL_SHADERS;
1207
1208 /* Syntax:
1209 * EQAA=s,z,c
1210 * Example:
1211 * EQAA=8,4,2
1212
1213 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1214 * Constraints:
1215 * s >= z >= c (ignoring this only wastes memory)
1216 * s = [2..16]
1217 * z = [2..8]
1218 * c = [2..8]
1219 *
1220 * Only MSAA color and depth buffers are overriden.
1221 */
1222 if (sscreen->info.has_eqaa_surface_allocator) {
1223 const char *eqaa = debug_get_option("EQAA", NULL);
1224 unsigned s,z,f;
1225
1226 if (eqaa && sscanf(eqaa, "%u,%u,%u", &s, &z, &f) == 3 && s && z && f) {
1227 sscreen->eqaa_force_coverage_samples = s;
1228 sscreen->eqaa_force_z_samples = z;
1229 sscreen->eqaa_force_color_samples = f;
1230 }
1231 }
1232
1233 for (i = 0; i < num_comp_hi_threads; i++)
1234 si_init_compiler(sscreen, &sscreen->compiler[i]);
1235 for (i = 0; i < num_comp_lo_threads; i++)
1236 si_init_compiler(sscreen, &sscreen->compiler_lowp[i]);
1237
1238 sscreen->ge_wave_size = 64;
1239 sscreen->ps_wave_size = 64;
1240 sscreen->compute_wave_size = 64;
1241
1242 if (sscreen->info.chip_class >= GFX10) {
1243 /* Pixels shaders: Wave64 is recommended.
1244 * Compute shaders: There are piglit failures with Wave32.
1245 */
1246 sscreen->ge_wave_size = 32;
1247
1248 if (sscreen->debug_flags & DBG(W32_GE))
1249 sscreen->ge_wave_size = 32;
1250 if (sscreen->debug_flags & DBG(W32_PS))
1251 sscreen->ps_wave_size = 32;
1252 if (sscreen->debug_flags & DBG(W32_CS))
1253 sscreen->compute_wave_size = 32;
1254
1255 if (sscreen->debug_flags & DBG(W64_GE))
1256 sscreen->ge_wave_size = 64;
1257 if (sscreen->debug_flags & DBG(W64_PS))
1258 sscreen->ps_wave_size = 64;
1259 if (sscreen->debug_flags & DBG(W64_CS))
1260 sscreen->compute_wave_size = 64;
1261 }
1262
1263 /* Create the auxiliary context. This must be done last. */
1264 sscreen->aux_context = si_create_context(&sscreen->b,
1265 (sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) |
1266 (sscreen->info.has_graphics ? 0 : PIPE_CONTEXT_COMPUTE_ONLY));
1267 if (sscreen->options.aux_debug) {
1268 struct u_log_context *log = CALLOC_STRUCT(u_log_context);
1269 u_log_context_init(log);
1270 sscreen->aux_context->set_log_context(sscreen->aux_context, log);
1271 }
1272
1273 if (sscreen->debug_flags & DBG(TEST_DMA))
1274 si_test_dma(sscreen);
1275
1276 if (sscreen->debug_flags & DBG(TEST_DMA_PERF)) {
1277 si_test_dma_perf(sscreen);
1278 }
1279
1280 if (sscreen->debug_flags & (DBG(TEST_VMFAULT_CP) |
1281 DBG(TEST_VMFAULT_SDMA) |
1282 DBG(TEST_VMFAULT_SHADER)))
1283 si_test_vmfault(sscreen);
1284
1285 if (sscreen->debug_flags & DBG(TEST_GDS))
1286 si_test_gds((struct si_context*)sscreen->aux_context);
1287
1288 if (sscreen->debug_flags & DBG(TEST_GDS_MM)) {
1289 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1290 32 * 1024, 4, RADEON_DOMAIN_GDS);
1291 }
1292 if (sscreen->debug_flags & DBG(TEST_GDS_OA_MM)) {
1293 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1294 4, 1, RADEON_DOMAIN_OA);
1295 }
1296
1297 return &sscreen->b;
1298 }
1299
1300 struct pipe_screen *radeonsi_screen_create(int fd, const struct pipe_screen_config *config)
1301 {
1302 drmVersionPtr version = drmGetVersion(fd);
1303 struct radeon_winsys *rw = NULL;
1304
1305 switch (version->version_major) {
1306 case 2:
1307 rw = radeon_drm_winsys_create(fd, config, radeonsi_screen_create_impl);
1308 break;
1309 case 3:
1310 rw = amdgpu_winsys_create(fd, config, radeonsi_screen_create_impl);
1311 break;
1312 }
1313
1314 drmFreeVersion(version);
1315 return rw ? rw->screen : NULL;
1316 }