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radeonsi: remove AMD_DEBUG=sisched option
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "si_pipe.h"
27 #include "si_public.h"
28 #include "si_shader_internal.h"
29 #include "si_compute.h"
30 #include "sid.h"
31
32 #include "radeon/radeon_uvd.h"
33 #include "util/disk_cache.h"
34 #include "util/u_log.h"
35 #include "util/u_memory.h"
36 #include "util/u_suballoc.h"
37 #include "util/u_tests.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/xmlconfig.h"
40 #include "vl/vl_decoder.h"
41 #include "driver_ddebug/dd_util.h"
42
43 #include "gallium/winsys/radeon/drm/radeon_drm_public.h"
44 #include "gallium/winsys/amdgpu/drm/amdgpu_public.h"
45 #include <xf86drm.h>
46
47 static struct pipe_context *si_create_context(struct pipe_screen *screen,
48 unsigned flags);
49
50 static const struct debug_named_value debug_options[] = {
51 /* Shader logging options: */
52 { "vs", DBG(VS), "Print vertex shaders" },
53 { "ps", DBG(PS), "Print pixel shaders" },
54 { "gs", DBG(GS), "Print geometry shaders" },
55 { "tcs", DBG(TCS), "Print tessellation control shaders" },
56 { "tes", DBG(TES), "Print tessellation evaluation shaders" },
57 { "cs", DBG(CS), "Print compute shaders" },
58 { "noir", DBG(NO_IR), "Don't print the LLVM IR"},
59 { "nonir", DBG(NO_NIR), "Don't print NIR when printing shaders"},
60 { "noasm", DBG(NO_ASM), "Don't print disassembled shaders"},
61 { "preoptir", DBG(PREOPT_IR), "Print the LLVM IR before initial optimizations" },
62
63 /* Shader compiler options the shader cache should be aware of: */
64 { "gisel", DBG(GISEL), "Enable LLVM global instruction selector." },
65 { "w32ge", DBG(W32_GE), "Use Wave32 for vertex, tessellation, and geometry shaders." },
66 { "w32ps", DBG(W32_PS), "Use Wave32 for pixel shaders." },
67 { "w32cs", DBG(W32_CS), "Use Wave32 for computes shaders." },
68 { "w64ge", DBG(W64_GE), "Use Wave64 for vertex, tessellation, and geometry shaders." },
69 { "w64ps", DBG(W64_PS), "Use Wave64 for pixel shaders." },
70 { "w64cs", DBG(W64_CS), "Use Wave64 for computes shaders." },
71
72 /* Shader compiler options (with no effect on the shader cache): */
73 { "checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR" },
74 { "mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand" },
75 { "nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants." },
76
77 /* Information logging options: */
78 { "info", DBG(INFO), "Print driver information" },
79 { "tex", DBG(TEX), "Print texture info" },
80 { "compute", DBG(COMPUTE), "Print compute info" },
81 { "vm", DBG(VM), "Print virtual addresses when creating resources" },
82 { "cache_stats", DBG(CACHE_STATS), "Print shader cache statistics." },
83
84 /* Driver options: */
85 { "forcedma", DBG(FORCE_SDMA), "Use SDMA for all operations when possible." },
86 { "nodma", DBG(NO_SDMA), "Disable SDMA" },
87 { "nodmaclear", DBG(NO_SDMA_CLEARS), "Disable SDMA clears" },
88 { "nodmacopyimage", DBG(NO_SDMA_COPY_IMAGE), "Disable SDMA image copies" },
89 { "nowc", DBG(NO_WC), "Disable GTT write combining" },
90 { "check_vm", DBG(CHECK_VM), "Check VM faults and dump debug info." },
91 { "reserve_vmid", DBG(RESERVE_VMID), "Force VMID reservation per context." },
92 { "zerovram", DBG(ZERO_VRAM), "Clear VRAM allocations." },
93
94 /* 3D engine options: */
95 { "nogfx", DBG(NO_GFX), "Disable graphics. Only multimedia compute paths can be used." },
96 { "nongg", DBG(NO_NGG), "Disable NGG and use the legacy pipeline." },
97 { "nggc", DBG(ALWAYS_NGG_CULLING), "Always use NGG culling even when it can hurt." },
98 { "nonggc", DBG(NO_NGG_CULLING), "Disable NGG culling." },
99 { "alwayspd", DBG(ALWAYS_PD), "Always enable the primitive discard compute shader." },
100 { "pd", DBG(PD), "Enable the primitive discard compute shader for large draw calls." },
101 { "nopd", DBG(NO_PD), "Disable the primitive discard compute shader." },
102 { "switch_on_eop", DBG(SWITCH_ON_EOP), "Program WD/IA to switch on end-of-packet." },
103 { "nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order rasterization" },
104 { "nodpbb", DBG(NO_DPBB), "Disable DPBB." },
105 { "nodfsm", DBG(NO_DFSM), "Disable DFSM." },
106 { "dpbb", DBG(DPBB), "Enable DPBB." },
107 { "dfsm", DBG(DFSM), "Enable DFSM." },
108 { "nohyperz", DBG(NO_HYPERZ), "Disable Hyper-Z" },
109 { "norbplus", DBG(NO_RB_PLUS), "Disable RB+." },
110 { "no2d", DBG(NO_2D_TILING), "Disable 2D tiling" },
111 { "notiling", DBG(NO_TILING), "Disable tiling" },
112 { "nodcc", DBG(NO_DCC), "Disable DCC." },
113 { "nodccclear", DBG(NO_DCC_CLEAR), "Disable DCC fast clear." },
114 { "nodccfb", DBG(NO_DCC_FB), "Disable separate DCC on the main framebuffer" },
115 { "nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA" },
116 { "nofmask", DBG(NO_FMASK), "Disable MSAA compression" },
117
118 DEBUG_NAMED_VALUE_END /* must be last */
119 };
120
121 static const struct debug_named_value test_options[] = {
122 /* Tests: */
123 { "testdma", DBG(TEST_DMA), "Invoke SDMA tests and exit." },
124 { "testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and exit." },
125 { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA), "Invoke a SDMA VM fault test and exit." },
126 { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM fault test and exit." },
127 { "testdmaperf", DBG(TEST_DMA_PERF), "Test DMA performance" },
128 { "testgds", DBG(TEST_GDS), "Test GDS." },
129 { "testgdsmm", DBG(TEST_GDS_MM), "Test GDS memory management." },
130 { "testgdsoamm", DBG(TEST_GDS_OA_MM), "Test GDS OA memory management." },
131
132 DEBUG_NAMED_VALUE_END /* must be last */
133 };
134
135 void si_init_compiler(struct si_screen *sscreen, struct ac_llvm_compiler *compiler)
136 {
137 /* Only create the less-optimizing version of the compiler on APUs
138 * predating Ryzen (Raven). */
139 bool create_low_opt_compiler = !sscreen->info.has_dedicated_vram &&
140 sscreen->info.chip_class <= GFX8;
141
142 enum ac_target_machine_options tm_options =
143 (sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL : 0) |
144 (sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
145 (sscreen->info.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
146 (!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0) |
147 (sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0) |
148 (create_low_opt_compiler ? AC_TM_CREATE_LOW_OPT : 0);
149
150 ac_init_llvm_once();
151 ac_init_llvm_compiler(compiler, sscreen->info.family, tm_options);
152 compiler->passes = ac_create_llvm_passes(compiler->tm);
153
154 if (compiler->tm_wave32)
155 compiler->passes_wave32 = ac_create_llvm_passes(compiler->tm_wave32);
156 if (compiler->low_opt_tm)
157 compiler->low_opt_passes = ac_create_llvm_passes(compiler->low_opt_tm);
158 }
159
160 static void si_destroy_compiler(struct ac_llvm_compiler *compiler)
161 {
162 ac_destroy_llvm_compiler(compiler);
163 }
164
165 /*
166 * pipe_context
167 */
168 static void si_destroy_context(struct pipe_context *context)
169 {
170 struct si_context *sctx = (struct si_context *)context;
171 int i;
172
173 /* Unreference the framebuffer normally to disable related logic
174 * properly.
175 */
176 struct pipe_framebuffer_state fb = {};
177 if (context->set_framebuffer_state)
178 context->set_framebuffer_state(context, &fb);
179
180 si_release_all_descriptors(sctx);
181
182 if (sctx->chip_class >= GFX10 && sctx->has_graphics)
183 gfx10_destroy_query(sctx);
184
185 pipe_resource_reference(&sctx->esgs_ring, NULL);
186 pipe_resource_reference(&sctx->gsvs_ring, NULL);
187 pipe_resource_reference(&sctx->tess_rings, NULL);
188 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
189 pipe_resource_reference(&sctx->sample_pos_buffer, NULL);
190 si_resource_reference(&sctx->border_color_buffer, NULL);
191 free(sctx->border_color_table);
192 si_resource_reference(&sctx->scratch_buffer, NULL);
193 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
194 si_resource_reference(&sctx->wait_mem_scratch, NULL);
195 si_resource_reference(&sctx->small_prim_cull_info_buf, NULL);
196
197 si_pm4_free_state(sctx, sctx->init_config, ~0);
198 if (sctx->init_config_gs_rings)
199 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
200 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
201 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
202
203 if (sctx->fixed_func_tcs_shader.cso)
204 sctx->b.delete_tcs_state(&sctx->b, sctx->fixed_func_tcs_shader.cso);
205 if (sctx->custom_dsa_flush)
206 sctx->b.delete_depth_stencil_alpha_state(&sctx->b, sctx->custom_dsa_flush);
207 if (sctx->custom_blend_resolve)
208 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_resolve);
209 if (sctx->custom_blend_fmask_decompress)
210 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_fmask_decompress);
211 if (sctx->custom_blend_eliminate_fastclear)
212 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_eliminate_fastclear);
213 if (sctx->custom_blend_dcc_decompress)
214 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_dcc_decompress);
215 if (sctx->vs_blit_pos)
216 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos);
217 if (sctx->vs_blit_pos_layered)
218 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos_layered);
219 if (sctx->vs_blit_color)
220 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color);
221 if (sctx->vs_blit_color_layered)
222 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color_layered);
223 if (sctx->vs_blit_texcoord)
224 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_texcoord);
225 if (sctx->cs_clear_buffer)
226 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_buffer);
227 if (sctx->cs_copy_buffer)
228 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_buffer);
229 if (sctx->cs_copy_image)
230 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image);
231 if (sctx->cs_copy_image_1d_array)
232 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image_1d_array);
233 if (sctx->cs_clear_render_target)
234 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target);
235 if (sctx->cs_clear_render_target_1d_array)
236 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target_1d_array);
237 if (sctx->cs_clear_12bytes_buffer)
238 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_12bytes_buffer);
239 if (sctx->cs_dcc_retile)
240 sctx->b.delete_compute_state(&sctx->b, sctx->cs_dcc_retile);
241
242 for (unsigned i = 0; i < ARRAY_SIZE(sctx->cs_fmask_expand); i++) {
243 for (unsigned j = 0; j < ARRAY_SIZE(sctx->cs_fmask_expand[i]); j++) {
244 if (sctx->cs_fmask_expand[i][j]) {
245 sctx->b.delete_compute_state(&sctx->b,
246 sctx->cs_fmask_expand[i][j]);
247 }
248 }
249 }
250
251 if (sctx->blitter)
252 util_blitter_destroy(sctx->blitter);
253
254 /* Release DCC stats. */
255 for (int i = 0; i < ARRAY_SIZE(sctx->dcc_stats); i++) {
256 assert(!sctx->dcc_stats[i].query_active);
257
258 for (int j = 0; j < ARRAY_SIZE(sctx->dcc_stats[i].ps_stats); j++)
259 if (sctx->dcc_stats[i].ps_stats[j])
260 sctx->b.destroy_query(&sctx->b,
261 sctx->dcc_stats[i].ps_stats[j]);
262
263 si_texture_reference(&sctx->dcc_stats[i].tex, NULL);
264 }
265
266 if (sctx->query_result_shader)
267 sctx->b.delete_compute_state(&sctx->b, sctx->query_result_shader);
268 if (sctx->sh_query_result_shader)
269 sctx->b.delete_compute_state(&sctx->b, sctx->sh_query_result_shader);
270
271 if (sctx->gfx_cs)
272 sctx->ws->cs_destroy(sctx->gfx_cs);
273 if (sctx->sdma_cs)
274 sctx->ws->cs_destroy(sctx->sdma_cs);
275 if (sctx->ctx)
276 sctx->ws->ctx_destroy(sctx->ctx);
277
278 if (sctx->b.stream_uploader)
279 u_upload_destroy(sctx->b.stream_uploader);
280 if (sctx->b.const_uploader)
281 u_upload_destroy(sctx->b.const_uploader);
282 if (sctx->cached_gtt_allocator)
283 u_upload_destroy(sctx->cached_gtt_allocator);
284
285 slab_destroy_child(&sctx->pool_transfers);
286 slab_destroy_child(&sctx->pool_transfers_unsync);
287
288 if (sctx->allocator_zeroed_memory)
289 u_suballocator_destroy(sctx->allocator_zeroed_memory);
290
291 sctx->ws->fence_reference(&sctx->last_gfx_fence, NULL);
292 sctx->ws->fence_reference(&sctx->last_sdma_fence, NULL);
293 sctx->ws->fence_reference(&sctx->last_ib_barrier_fence, NULL);
294 si_resource_reference(&sctx->eop_bug_scratch, NULL);
295 si_resource_reference(&sctx->index_ring, NULL);
296 si_resource_reference(&sctx->barrier_buf, NULL);
297 si_resource_reference(&sctx->last_ib_barrier_buf, NULL);
298 pb_reference(&sctx->gds, NULL);
299 pb_reference(&sctx->gds_oa, NULL);
300
301 si_destroy_compiler(&sctx->compiler);
302
303 si_saved_cs_reference(&sctx->current_saved_cs, NULL);
304
305 _mesa_hash_table_destroy(sctx->tex_handles, NULL);
306 _mesa_hash_table_destroy(sctx->img_handles, NULL);
307
308 util_dynarray_fini(&sctx->resident_tex_handles);
309 util_dynarray_fini(&sctx->resident_img_handles);
310 util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
311 util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
312 util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
313 si_unref_sdma_uploads(sctx);
314 free(sctx->sdma_uploads);
315 FREE(sctx);
316 }
317
318 static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx)
319 {
320 struct si_context *sctx = (struct si_context *)ctx;
321 struct si_screen *sscreen = sctx->screen;
322 enum pipe_reset_status status = sctx->ws->ctx_query_reset_status(sctx->ctx);
323
324 if (status != PIPE_NO_RESET) {
325 /* Call the state tracker to set a no-op API dispatch. */
326 if (sctx->device_reset_callback.reset) {
327 sctx->device_reset_callback.reset(sctx->device_reset_callback.data,
328 status);
329 }
330
331 /* Re-create the auxiliary context, because it won't submit
332 * any new IBs due to a GPU reset.
333 */
334 simple_mtx_lock(&sscreen->aux_context_lock);
335
336 struct u_log_context *aux_log = ((struct si_context *)sscreen->aux_context)->log;
337 sscreen->aux_context->set_log_context(sscreen->aux_context, NULL);
338 sscreen->aux_context->destroy(sscreen->aux_context);
339
340 sscreen->aux_context = si_create_context(&sscreen->b,
341 (sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) |
342 (sscreen->info.has_graphics ? 0 : PIPE_CONTEXT_COMPUTE_ONLY));
343 sscreen->aux_context->set_log_context(sscreen->aux_context, aux_log);
344 simple_mtx_unlock(&sscreen->aux_context_lock);
345 }
346 return status;
347 }
348
349 static void si_set_device_reset_callback(struct pipe_context *ctx,
350 const struct pipe_device_reset_callback *cb)
351 {
352 struct si_context *sctx = (struct si_context *)ctx;
353
354 if (cb)
355 sctx->device_reset_callback = *cb;
356 else
357 memset(&sctx->device_reset_callback, 0,
358 sizeof(sctx->device_reset_callback));
359 }
360
361 /* Apitrace profiling:
362 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
363 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
364 * and remember its number.
365 * 3) In Mesa, enable queries and performance counters around that draw
366 * call and print the results.
367 * 4) glretrace --benchmark --markers ..
368 */
369 static void si_emit_string_marker(struct pipe_context *ctx,
370 const char *string, int len)
371 {
372 struct si_context *sctx = (struct si_context *)ctx;
373
374 dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
375
376 if (sctx->log)
377 u_log_printf(sctx->log, "\nString marker: %*s\n", len, string);
378 }
379
380 static void si_set_debug_callback(struct pipe_context *ctx,
381 const struct pipe_debug_callback *cb)
382 {
383 struct si_context *sctx = (struct si_context *)ctx;
384 struct si_screen *screen = sctx->screen;
385
386 util_queue_finish(&screen->shader_compiler_queue);
387 util_queue_finish(&screen->shader_compiler_queue_low_priority);
388
389 if (cb)
390 sctx->debug = *cb;
391 else
392 memset(&sctx->debug, 0, sizeof(sctx->debug));
393 }
394
395 static void si_set_log_context(struct pipe_context *ctx,
396 struct u_log_context *log)
397 {
398 struct si_context *sctx = (struct si_context *)ctx;
399 sctx->log = log;
400
401 if (log)
402 u_log_add_auto_logger(log, si_auto_log_cs, sctx);
403 }
404
405 static void si_set_context_param(struct pipe_context *ctx,
406 enum pipe_context_param param,
407 unsigned value)
408 {
409 struct radeon_winsys *ws = ((struct si_context *)ctx)->ws;
410
411 switch (param) {
412 case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE:
413 ws->pin_threads_to_L3_cache(ws, value);
414 break;
415 default:;
416 }
417 }
418
419 static struct pipe_context *si_create_context(struct pipe_screen *screen,
420 unsigned flags)
421 {
422 struct si_screen* sscreen = (struct si_screen *)screen;
423 STATIC_ASSERT(DBG_COUNT <= 64);
424
425 /* Don't create a context if it's not compute-only and hw is compute-only. */
426 if (!sscreen->info.has_graphics &&
427 !(flags & PIPE_CONTEXT_COMPUTE_ONLY))
428 return NULL;
429
430 struct si_context *sctx = CALLOC_STRUCT(si_context);
431 struct radeon_winsys *ws = sscreen->ws;
432 int shader, i;
433 bool stop_exec_on_failure = (flags & PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET) != 0;
434
435 if (!sctx)
436 return NULL;
437
438 sctx->has_graphics = sscreen->info.chip_class == GFX6 ||
439 !(flags & PIPE_CONTEXT_COMPUTE_ONLY);
440
441 if (flags & PIPE_CONTEXT_DEBUG)
442 sscreen->record_llvm_ir = true; /* racy but not critical */
443
444 sctx->b.screen = screen; /* this must be set first */
445 sctx->b.priv = NULL;
446 sctx->b.destroy = si_destroy_context;
447 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
448 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
449
450 slab_create_child(&sctx->pool_transfers, &sscreen->pool_transfers);
451 slab_create_child(&sctx->pool_transfers_unsync, &sscreen->pool_transfers);
452
453 sctx->ws = sscreen->ws;
454 sctx->family = sscreen->info.family;
455 sctx->chip_class = sscreen->info.chip_class;
456
457 if (sctx->chip_class == GFX7 ||
458 sctx->chip_class == GFX8 ||
459 sctx->chip_class == GFX9) {
460 sctx->eop_bug_scratch = si_resource(
461 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
462 16 * sscreen->info.num_render_backends));
463 if (!sctx->eop_bug_scratch)
464 goto fail;
465 }
466
467 /* Initialize context allocators. */
468 sctx->allocator_zeroed_memory =
469 u_suballocator_create(&sctx->b, 128 * 1024,
470 0, PIPE_USAGE_DEFAULT,
471 SI_RESOURCE_FLAG_UNMAPPABLE |
472 SI_RESOURCE_FLAG_CLEAR, false);
473 if (!sctx->allocator_zeroed_memory)
474 goto fail;
475
476 sctx->b.stream_uploader = u_upload_create(&sctx->b, 1024 * 1024,
477 0, PIPE_USAGE_STREAM,
478 SI_RESOURCE_FLAG_READ_ONLY);
479 if (!sctx->b.stream_uploader)
480 goto fail;
481
482 sctx->cached_gtt_allocator = u_upload_create(&sctx->b, 16 * 1024,
483 0, PIPE_USAGE_STAGING, 0);
484 if (!sctx->cached_gtt_allocator)
485 goto fail;
486
487 sctx->ctx = sctx->ws->ctx_create(sctx->ws);
488 if (!sctx->ctx)
489 goto fail;
490
491 if (sscreen->info.num_rings[RING_DMA] &&
492 !(sscreen->debug_flags & DBG(NO_SDMA)) &&
493 /* SDMA causes corruption on RX 580:
494 * https://gitlab.freedesktop.org/mesa/mesa/issues/1399
495 * https://gitlab.freedesktop.org/mesa/mesa/issues/1889
496 */
497 (sctx->chip_class != GFX8 || sscreen->debug_flags & DBG(FORCE_SDMA)) &&
498 /* SDMA timeouts sometimes on gfx10 so disable it for now. See:
499 * https://bugs.freedesktop.org/show_bug.cgi?id=111481
500 * https://gitlab.freedesktop.org/mesa/mesa/issues/1907
501 */
502 (sctx->chip_class != GFX10 || sscreen->debug_flags & DBG(FORCE_SDMA))) {
503 sctx->sdma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA,
504 (void*)si_flush_dma_cs,
505 sctx, stop_exec_on_failure);
506 }
507
508 bool use_sdma_upload = sscreen->info.has_dedicated_vram && sctx->sdma_cs;
509 sctx->b.const_uploader = u_upload_create(&sctx->b, 256 * 1024,
510 0, PIPE_USAGE_DEFAULT,
511 SI_RESOURCE_FLAG_32BIT |
512 (use_sdma_upload ?
513 SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA : 0));
514 if (!sctx->b.const_uploader)
515 goto fail;
516
517 if (use_sdma_upload)
518 u_upload_enable_flush_explicit(sctx->b.const_uploader);
519
520 sctx->gfx_cs = ws->cs_create(sctx->ctx,
521 sctx->has_graphics ? RING_GFX : RING_COMPUTE,
522 (void*)si_flush_gfx_cs, sctx, stop_exec_on_failure);
523
524 /* Border colors. */
525 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
526 sizeof(*sctx->border_color_table));
527 if (!sctx->border_color_table)
528 goto fail;
529
530 sctx->border_color_buffer = si_resource(
531 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
532 SI_MAX_BORDER_COLORS *
533 sizeof(*sctx->border_color_table)));
534 if (!sctx->border_color_buffer)
535 goto fail;
536
537 sctx->border_color_map =
538 ws->buffer_map(sctx->border_color_buffer->buf,
539 NULL, PIPE_TRANSFER_WRITE);
540 if (!sctx->border_color_map)
541 goto fail;
542
543 sctx->ngg = sscreen->use_ngg;
544
545 /* Initialize context functions used by graphics and compute. */
546 if (sctx->chip_class >= GFX10)
547 sctx->emit_cache_flush = gfx10_emit_cache_flush;
548 else
549 sctx->emit_cache_flush = si_emit_cache_flush;
550
551 sctx->b.emit_string_marker = si_emit_string_marker;
552 sctx->b.set_debug_callback = si_set_debug_callback;
553 sctx->b.set_log_context = si_set_log_context;
554 sctx->b.set_context_param = si_set_context_param;
555 sctx->b.get_device_reset_status = si_get_reset_status;
556 sctx->b.set_device_reset_callback = si_set_device_reset_callback;
557
558 si_init_all_descriptors(sctx);
559 si_init_buffer_functions(sctx);
560 si_init_clear_functions(sctx);
561 si_init_blit_functions(sctx);
562 si_init_compute_functions(sctx);
563 si_init_compute_blit_functions(sctx);
564 si_init_debug_functions(sctx);
565 si_init_fence_functions(sctx);
566 si_init_query_functions(sctx);
567 si_init_state_compute_functions(sctx);
568 si_init_context_texture_functions(sctx);
569
570 /* Initialize graphics-only context functions. */
571 if (sctx->has_graphics) {
572 if (sctx->chip_class >= GFX10)
573 gfx10_init_query(sctx);
574 si_init_msaa_functions(sctx);
575 si_init_shader_functions(sctx);
576 si_init_state_functions(sctx);
577 si_init_streamout_functions(sctx);
578 si_init_viewport_functions(sctx);
579
580 sctx->blitter = util_blitter_create(&sctx->b);
581 if (sctx->blitter == NULL)
582 goto fail;
583 sctx->blitter->skip_viewport_restore = true;
584
585 /* Some states are expected to be always non-NULL. */
586 sctx->noop_blend = util_blitter_get_noop_blend_state(sctx->blitter);
587 sctx->queued.named.blend = sctx->noop_blend;
588
589 sctx->noop_dsa = util_blitter_get_noop_dsa_state(sctx->blitter);
590 sctx->queued.named.dsa = sctx->noop_dsa;
591
592 sctx->discard_rasterizer_state =
593 util_blitter_get_discard_rasterizer_state(sctx->blitter);
594 sctx->queued.named.rasterizer = sctx->discard_rasterizer_state;
595
596 si_init_draw_functions(sctx);
597
598 /* If aux_context == NULL, we are initializing aux_context right now. */
599 bool is_aux_context = !sscreen->aux_context;
600 si_initialize_prim_discard_tunables(sscreen, is_aux_context,
601 &sctx->prim_discard_vertex_count_threshold,
602 &sctx->index_ring_size_per_ib);
603 }
604
605 /* Initialize SDMA functions. */
606 if (sctx->chip_class >= GFX7)
607 cik_init_sdma_functions(sctx);
608 else
609 sctx->dma_copy = si_resource_copy_region;
610
611 if (sscreen->debug_flags & DBG(FORCE_SDMA))
612 sctx->b.resource_copy_region = sctx->dma_copy;
613
614 sctx->sample_mask = 0xffff;
615
616 /* Initialize multimedia functions. */
617 if (sscreen->info.has_hw_decode) {
618 sctx->b.create_video_codec = si_uvd_create_decoder;
619 sctx->b.create_video_buffer = si_video_buffer_create;
620 } else {
621 sctx->b.create_video_codec = vl_create_decoder;
622 sctx->b.create_video_buffer = vl_video_buffer_create;
623 }
624
625 if (sctx->chip_class >= GFX9) {
626 sctx->wait_mem_scratch = si_resource(
627 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 8));
628 if (!sctx->wait_mem_scratch)
629 goto fail;
630
631 /* Initialize the memory. */
632 si_cp_write_data(sctx, sctx->wait_mem_scratch, 0, 4,
633 V_370_MEM, V_370_ME, &sctx->wait_mem_number);
634 }
635
636 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
637 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
638 if (sctx->chip_class == GFX7) {
639 sctx->null_const_buf.buffer =
640 pipe_aligned_buffer_create(screen,
641 SI_RESOURCE_FLAG_32BIT,
642 PIPE_USAGE_DEFAULT, 16,
643 sctx->screen->info.tcc_cache_line_size);
644 if (!sctx->null_const_buf.buffer)
645 goto fail;
646 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
647
648 unsigned start_shader = sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE;
649 for (shader = start_shader; shader < SI_NUM_SHADERS; shader++) {
650 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
651 sctx->b.set_constant_buffer(&sctx->b, shader, i,
652 &sctx->null_const_buf);
653 }
654 }
655
656 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
657 &sctx->null_const_buf);
658 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
659 &sctx->null_const_buf);
660 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
661 &sctx->null_const_buf);
662 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
663 &sctx->null_const_buf);
664 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
665 &sctx->null_const_buf);
666 }
667
668 uint64_t max_threads_per_block;
669 screen->get_compute_param(screen, PIPE_SHADER_IR_NIR,
670 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
671 &max_threads_per_block);
672
673 /* The maximum number of scratch waves. Scratch space isn't divided
674 * evenly between CUs. The number is only a function of the number of CUs.
675 * We can decrease the constant to decrease the scratch buffer size.
676 *
677 * sctx->scratch_waves must be >= the maximum posible size of
678 * 1 threadgroup, so that the hw doesn't hang from being unable
679 * to start any.
680 *
681 * The recommended value is 4 per CU at most. Higher numbers don't
682 * bring much benefit, but they still occupy chip resources (think
683 * async compute). I've seen ~2% performance difference between 4 and 32.
684 */
685 sctx->scratch_waves = MAX2(32 * sscreen->info.num_good_compute_units,
686 max_threads_per_block / 64);
687
688 /* Bindless handles. */
689 sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
690 _mesa_key_pointer_equal);
691 sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
692 _mesa_key_pointer_equal);
693
694 util_dynarray_init(&sctx->resident_tex_handles, NULL);
695 util_dynarray_init(&sctx->resident_img_handles, NULL);
696 util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
697 util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
698 util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
699
700 sctx->sample_pos_buffer =
701 pipe_buffer_create(sctx->b.screen, 0, PIPE_USAGE_DEFAULT,
702 sizeof(sctx->sample_positions));
703 pipe_buffer_write(&sctx->b, sctx->sample_pos_buffer, 0,
704 sizeof(sctx->sample_positions), &sctx->sample_positions);
705
706 /* this must be last */
707 si_begin_new_gfx_cs(sctx);
708
709 if (sctx->chip_class == GFX7) {
710 /* Clear the NULL constant buffer, because loads should return zeros.
711 * Note that this forces CP DMA to be used, because clover deadlocks
712 * for some reason when the compute codepath is used.
713 */
714 uint32_t clear_value = 0;
715 si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0,
716 sctx->null_const_buf.buffer->width0,
717 &clear_value, 4, SI_COHERENCY_SHADER, true);
718 }
719 return &sctx->b;
720 fail:
721 fprintf(stderr, "radeonsi: Failed to create a context.\n");
722 si_destroy_context(&sctx->b);
723 return NULL;
724 }
725
726 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
727 void *priv, unsigned flags)
728 {
729 struct si_screen *sscreen = (struct si_screen *)screen;
730 struct pipe_context *ctx;
731
732 if (sscreen->debug_flags & DBG(CHECK_VM))
733 flags |= PIPE_CONTEXT_DEBUG;
734
735 ctx = si_create_context(screen, flags);
736
737 if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
738 return ctx;
739
740 /* Clover (compute-only) is unsupported. */
741 if (flags & PIPE_CONTEXT_COMPUTE_ONLY)
742 return ctx;
743
744 /* When shaders are logged to stderr, asynchronous compilation is
745 * disabled too. */
746 if (sscreen->debug_flags & DBG_ALL_SHADERS)
747 return ctx;
748
749 /* Use asynchronous flushes only on amdgpu, since the radeon
750 * implementation for fence_server_sync is incomplete. */
751 return threaded_context_create(ctx, &sscreen->pool_transfers,
752 si_replace_buffer_storage,
753 sscreen->info.is_amdgpu ? si_create_fence : NULL,
754 &((struct si_context*)ctx)->tc);
755 }
756
757 /*
758 * pipe_screen
759 */
760 static void si_destroy_screen(struct pipe_screen* pscreen)
761 {
762 struct si_screen *sscreen = (struct si_screen *)pscreen;
763 struct si_shader_part *parts[] = {
764 sscreen->vs_prologs,
765 sscreen->tcs_epilogs,
766 sscreen->gs_prologs,
767 sscreen->ps_prologs,
768 sscreen->ps_epilogs
769 };
770 unsigned i;
771
772 if (!sscreen->ws->unref(sscreen->ws))
773 return;
774
775 if (sscreen->debug_flags & DBG(CACHE_STATS)) {
776 printf("live shader cache: hits = %u, misses = %u\n",
777 sscreen->live_shader_cache.hits,
778 sscreen->live_shader_cache.misses);
779 printf("memory shader cache: hits = %u, misses = %u\n",
780 sscreen->num_memory_shader_cache_hits,
781 sscreen->num_memory_shader_cache_misses);
782 printf("disk shader cache: hits = %u, misses = %u\n",
783 sscreen->num_disk_shader_cache_hits,
784 sscreen->num_disk_shader_cache_misses);
785 }
786
787 simple_mtx_destroy(&sscreen->aux_context_lock);
788
789 struct u_log_context *aux_log = ((struct si_context *)sscreen->aux_context)->log;
790 if (aux_log) {
791 sscreen->aux_context->set_log_context(sscreen->aux_context, NULL);
792 u_log_context_destroy(aux_log);
793 FREE(aux_log);
794 }
795
796 sscreen->aux_context->destroy(sscreen->aux_context);
797
798 util_queue_destroy(&sscreen->shader_compiler_queue);
799 util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
800
801 /* Release the reference on glsl types of the compiler threads. */
802 glsl_type_singleton_decref();
803
804 for (i = 0; i < ARRAY_SIZE(sscreen->compiler); i++)
805 si_destroy_compiler(&sscreen->compiler[i]);
806
807 for (i = 0; i < ARRAY_SIZE(sscreen->compiler_lowp); i++)
808 si_destroy_compiler(&sscreen->compiler_lowp[i]);
809
810 /* Free shader parts. */
811 for (i = 0; i < ARRAY_SIZE(parts); i++) {
812 while (parts[i]) {
813 struct si_shader_part *part = parts[i];
814
815 parts[i] = part->next;
816 si_shader_binary_clean(&part->binary);
817 FREE(part);
818 }
819 }
820 simple_mtx_destroy(&sscreen->shader_parts_mutex);
821 si_destroy_shader_cache(sscreen);
822
823 si_destroy_perfcounters(sscreen);
824 si_gpu_load_kill_thread(sscreen);
825
826 simple_mtx_destroy(&sscreen->gpu_load_mutex);
827
828 slab_destroy_parent(&sscreen->pool_transfers);
829
830 disk_cache_destroy(sscreen->disk_shader_cache);
831 util_live_shader_cache_deinit(&sscreen->live_shader_cache);
832 sscreen->ws->destroy(sscreen->ws);
833 FREE(sscreen);
834 }
835
836 static void si_init_gs_info(struct si_screen *sscreen)
837 {
838 sscreen->gs_table_depth = ac_get_gs_table_depth(sscreen->info.chip_class,
839 sscreen->info.family);
840 }
841
842 static void si_test_vmfault(struct si_screen *sscreen, uint64_t test_flags)
843 {
844 struct pipe_context *ctx = sscreen->aux_context;
845 struct si_context *sctx = (struct si_context *)ctx;
846 struct pipe_resource *buf =
847 pipe_buffer_create_const0(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 64);
848
849 if (!buf) {
850 puts("Buffer allocation failed.");
851 exit(1);
852 }
853
854 si_resource(buf)->gpu_address = 0; /* cause a VM fault */
855
856 if (test_flags & DBG(TEST_VMFAULT_CP)) {
857 si_cp_dma_copy_buffer(sctx, buf, buf, 0, 4, 4, 0,
858 SI_COHERENCY_NONE, L2_BYPASS);
859 ctx->flush(ctx, NULL, 0);
860 puts("VM fault test: CP - done.");
861 }
862 if (test_flags & DBG(TEST_VMFAULT_SDMA)) {
863 si_sdma_clear_buffer(sctx, buf, 0, 4, 0);
864 ctx->flush(ctx, NULL, 0);
865 puts("VM fault test: SDMA - done.");
866 }
867 if (test_flags & DBG(TEST_VMFAULT_SHADER)) {
868 util_test_constant_buffer(ctx, buf);
869 puts("VM fault test: Shader - done.");
870 }
871 exit(0);
872 }
873
874 static void si_test_gds_memory_management(struct si_context *sctx,
875 unsigned alloc_size, unsigned alignment,
876 enum radeon_bo_domain domain)
877 {
878 struct radeon_winsys *ws = sctx->ws;
879 struct radeon_cmdbuf *cs[8];
880 struct pb_buffer *gds_bo[ARRAY_SIZE(cs)];
881
882 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
883 cs[i] = ws->cs_create(sctx->ctx, RING_COMPUTE,
884 NULL, NULL, false);
885 gds_bo[i] = ws->buffer_create(ws, alloc_size, alignment, domain, 0);
886 assert(gds_bo[i]);
887 }
888
889 for (unsigned iterations = 0; iterations < 20000; iterations++) {
890 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
891 /* This clears GDS with CP DMA.
892 *
893 * We don't care if GDS is present. Just add some packet
894 * to make the GPU busy for a moment.
895 */
896 si_cp_dma_clear_buffer(sctx, cs[i], NULL, 0, alloc_size, 0,
897 SI_CPDMA_SKIP_BO_LIST_UPDATE |
898 SI_CPDMA_SKIP_CHECK_CS_SPACE |
899 SI_CPDMA_SKIP_GFX_SYNC, 0, 0);
900
901 ws->cs_add_buffer(cs[i], gds_bo[i], domain,
902 RADEON_USAGE_READWRITE, 0);
903 ws->cs_flush(cs[i], PIPE_FLUSH_ASYNC, NULL);
904 }
905 }
906 exit(0);
907 }
908
909 static void si_disk_cache_create(struct si_screen *sscreen)
910 {
911 /* Don't use the cache if shader dumping is enabled. */
912 if (sscreen->debug_flags & DBG_ALL_SHADERS)
913 return;
914
915 struct mesa_sha1 ctx;
916 unsigned char sha1[20];
917 char cache_id[20 * 2 + 1];
918
919 _mesa_sha1_init(&ctx);
920
921 if (!disk_cache_get_function_identifier(si_disk_cache_create, &ctx) ||
922 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo,
923 &ctx))
924 return;
925
926 _mesa_sha1_final(&ctx, sha1);
927 disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
928
929 /* These flags affect shader compilation. */
930 #define ALL_FLAGS (DBG(GISEL))
931 uint64_t shader_debug_flags = sscreen->debug_flags & ALL_FLAGS;
932
933 /* Add the high bits of 32-bit addresses, which affects
934 * how 32-bit addresses are expanded to 64 bits.
935 */
936 STATIC_ASSERT(ALL_FLAGS <= UINT_MAX);
937 assert((int16_t)sscreen->info.address32_hi == (int32_t)sscreen->info.address32_hi);
938 shader_debug_flags |= (uint64_t)(sscreen->info.address32_hi & 0xffff) << 32;
939
940 sscreen->disk_shader_cache =
941 disk_cache_create(sscreen->info.name,
942 cache_id,
943 shader_debug_flags);
944 }
945
946 static void si_set_max_shader_compiler_threads(struct pipe_screen *screen,
947 unsigned max_threads)
948 {
949 struct si_screen *sscreen = (struct si_screen *)screen;
950
951 /* This function doesn't allow a greater number of threads than
952 * the queue had at its creation. */
953 util_queue_adjust_num_threads(&sscreen->shader_compiler_queue,
954 max_threads);
955 /* Don't change the number of threads on the low priority queue. */
956 }
957
958 static bool si_is_parallel_shader_compilation_finished(struct pipe_screen *screen,
959 void *shader,
960 enum pipe_shader_type shader_type)
961 {
962 struct si_shader_selector *sel = (struct si_shader_selector *)shader;
963
964 return util_queue_fence_is_signalled(&sel->ready);
965 }
966
967 static struct pipe_screen *
968 radeonsi_screen_create_impl(struct radeon_winsys *ws,
969 const struct pipe_screen_config *config)
970 {
971 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
972 unsigned hw_threads, num_comp_hi_threads, num_comp_lo_threads;
973 uint64_t test_flags;
974
975 if (!sscreen) {
976 return NULL;
977 }
978
979 sscreen->ws = ws;
980 ws->query_info(ws, &sscreen->info);
981
982 if (sscreen->info.chip_class == GFX10 && LLVM_VERSION_MAJOR < 9) {
983 fprintf(stderr, "radeonsi: Navi family support requires LLVM 9 or higher\n");
984 FREE(sscreen);
985 return NULL;
986 }
987
988 if (sscreen->info.chip_class >= GFX9) {
989 sscreen->se_tile_repeat = 32 * sscreen->info.max_se;
990 } else {
991 ac_get_raster_config(&sscreen->info,
992 &sscreen->pa_sc_raster_config,
993 &sscreen->pa_sc_raster_config_1,
994 &sscreen->se_tile_repeat);
995 }
996
997 sscreen->debug_flags = debug_get_flags_option("R600_DEBUG",
998 debug_options, 0);
999 sscreen->debug_flags |= debug_get_flags_option("AMD_DEBUG",
1000 debug_options, 0);
1001 test_flags = debug_get_flags_option("AMD_TEST",
1002 test_options, 0);
1003
1004 if (sscreen->debug_flags & DBG(NO_GFX))
1005 sscreen->info.has_graphics = false;
1006
1007 /* Set functions first. */
1008 sscreen->b.context_create = si_pipe_create_context;
1009 sscreen->b.destroy = si_destroy_screen;
1010 sscreen->b.set_max_shader_compiler_threads =
1011 si_set_max_shader_compiler_threads;
1012 sscreen->b.is_parallel_shader_compilation_finished =
1013 si_is_parallel_shader_compilation_finished;
1014 sscreen->b.finalize_nir = si_finalize_nir;
1015
1016 si_init_screen_get_functions(sscreen);
1017 si_init_screen_buffer_functions(sscreen);
1018 si_init_screen_fence_functions(sscreen);
1019 si_init_screen_state_functions(sscreen);
1020 si_init_screen_texture_functions(sscreen);
1021 si_init_screen_query_functions(sscreen);
1022 si_init_screen_live_shader_cache(sscreen);
1023
1024 /* Set these flags in debug_flags early, so that the shader cache takes
1025 * them into account.
1026 */
1027 if (driQueryOptionb(config->options,
1028 "glsl_correct_derivatives_after_discard"))
1029 sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
1030
1031 if (sscreen->debug_flags & DBG(INFO))
1032 ac_print_gpu_info(&sscreen->info);
1033
1034 slab_create_parent(&sscreen->pool_transfers,
1035 sizeof(struct si_transfer), 64);
1036
1037 sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1038 if (sscreen->force_aniso == -1) {
1039 sscreen->force_aniso = MIN2(16, debug_get_num_option("AMD_TEX_ANISO", -1));
1040 }
1041
1042 if (sscreen->force_aniso >= 0) {
1043 printf("radeonsi: Forcing anisotropy filter to %ix\n",
1044 /* round down to a power of two */
1045 1 << util_logbase2(sscreen->force_aniso));
1046 }
1047
1048 (void) simple_mtx_init(&sscreen->aux_context_lock, mtx_plain);
1049 (void) simple_mtx_init(&sscreen->gpu_load_mutex, mtx_plain);
1050
1051 si_init_gs_info(sscreen);
1052 if (!si_init_shader_cache(sscreen)) {
1053 FREE(sscreen);
1054 return NULL;
1055 }
1056
1057 {
1058 #define OPT_BOOL(name, dflt, description) \
1059 sscreen->options.name = \
1060 driQueryOptionb(config->options, "radeonsi_"#name);
1061 #include "si_debug_options.h"
1062 }
1063
1064 si_disk_cache_create(sscreen);
1065
1066 /* Determine the number of shader compiler threads. */
1067 hw_threads = sysconf(_SC_NPROCESSORS_ONLN);
1068
1069 if (hw_threads >= 12) {
1070 num_comp_hi_threads = hw_threads * 3 / 4;
1071 num_comp_lo_threads = hw_threads / 3;
1072 } else if (hw_threads >= 6) {
1073 num_comp_hi_threads = hw_threads - 2;
1074 num_comp_lo_threads = hw_threads / 2;
1075 } else if (hw_threads >= 2) {
1076 num_comp_hi_threads = hw_threads - 1;
1077 num_comp_lo_threads = hw_threads / 2;
1078 } else {
1079 num_comp_hi_threads = 1;
1080 num_comp_lo_threads = 1;
1081 }
1082
1083 num_comp_hi_threads = MIN2(num_comp_hi_threads,
1084 ARRAY_SIZE(sscreen->compiler));
1085 num_comp_lo_threads = MIN2(num_comp_lo_threads,
1086 ARRAY_SIZE(sscreen->compiler_lowp));
1087
1088 /* Take a reference on the glsl types for the compiler threads. */
1089 glsl_type_singleton_init_or_ref();
1090
1091 if (!util_queue_init(&sscreen->shader_compiler_queue, "sh",
1092 64, num_comp_hi_threads,
1093 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1094 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY)) {
1095 si_destroy_shader_cache(sscreen);
1096 FREE(sscreen);
1097 glsl_type_singleton_decref();
1098 return NULL;
1099 }
1100
1101 if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
1102 "shlo",
1103 64, num_comp_lo_threads,
1104 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1105 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY |
1106 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
1107 si_destroy_shader_cache(sscreen);
1108 FREE(sscreen);
1109 glsl_type_singleton_decref();
1110 return NULL;
1111 }
1112
1113 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1114 si_init_perfcounters(sscreen);
1115
1116 unsigned prim_discard_vertex_count_threshold, tmp;
1117 si_initialize_prim_discard_tunables(sscreen, false,
1118 &prim_discard_vertex_count_threshold,
1119 &tmp);
1120 /* Compute-shader-based culling doesn't support VBOs in user SGPRs. */
1121 if (prim_discard_vertex_count_threshold == UINT_MAX)
1122 sscreen->num_vbos_in_user_sgprs = sscreen->info.chip_class >= GFX9 ? 5 : 1;
1123
1124 /* Determine tessellation ring info. */
1125 bool double_offchip_buffers = sscreen->info.chip_class >= GFX7 &&
1126 sscreen->info.family != CHIP_CARRIZO &&
1127 sscreen->info.family != CHIP_STONEY;
1128 /* This must be one less than the maximum number due to a hw limitation.
1129 * Various hardware bugs need this.
1130 */
1131 unsigned max_offchip_buffers_per_se;
1132
1133 if (sscreen->info.chip_class >= GFX10)
1134 max_offchip_buffers_per_se = 256;
1135 /* Only certain chips can use the maximum value. */
1136 else if (sscreen->info.family == CHIP_VEGA12 ||
1137 sscreen->info.family == CHIP_VEGA20)
1138 max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1139 else
1140 max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
1141
1142 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1143 sscreen->info.max_se;
1144 unsigned offchip_granularity;
1145
1146 /* Hawaii has a bug with offchip buffers > 256 that can be worked
1147 * around by setting 4K granularity.
1148 */
1149 if (sscreen->info.family == CHIP_HAWAII) {
1150 sscreen->tess_offchip_block_dw_size = 4096;
1151 offchip_granularity = V_03093C_X_4K_DWORDS;
1152 } else {
1153 sscreen->tess_offchip_block_dw_size = 8192;
1154 offchip_granularity = V_03093C_X_8K_DWORDS;
1155 }
1156
1157 sscreen->tess_factor_ring_size = 32768 * sscreen->info.max_se;
1158 sscreen->tess_offchip_ring_size = max_offchip_buffers *
1159 sscreen->tess_offchip_block_dw_size * 4;
1160
1161 if (sscreen->info.chip_class >= GFX7) {
1162 if (sscreen->info.chip_class >= GFX8)
1163 --max_offchip_buffers;
1164 sscreen->vgt_hs_offchip_param =
1165 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1166 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1167 } else {
1168 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
1169 sscreen->vgt_hs_offchip_param =
1170 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1171 }
1172
1173 sscreen->has_draw_indirect_multi =
1174 (sscreen->info.family >= CHIP_POLARIS10) ||
1175 (sscreen->info.chip_class == GFX8 &&
1176 sscreen->info.pfp_fw_version >= 121 &&
1177 sscreen->info.me_fw_version >= 87) ||
1178 (sscreen->info.chip_class == GFX7 &&
1179 sscreen->info.pfp_fw_version >= 211 &&
1180 sscreen->info.me_fw_version >= 173) ||
1181 (sscreen->info.chip_class == GFX6 &&
1182 sscreen->info.pfp_fw_version >= 79 &&
1183 sscreen->info.me_fw_version >= 142);
1184
1185 sscreen->has_out_of_order_rast = sscreen->info.has_out_of_order_rast &&
1186 !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER));
1187 sscreen->assume_no_z_fights =
1188 driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
1189 sscreen->commutative_blend_add =
1190 driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
1191
1192 sscreen->use_ngg = sscreen->info.chip_class >= GFX10 &&
1193 sscreen->info.family != CHIP_NAVI14 &&
1194 !(sscreen->debug_flags & DBG(NO_NGG));
1195 sscreen->use_ngg_culling = sscreen->use_ngg &&
1196 !(sscreen->debug_flags & DBG(NO_NGG_CULLING));
1197 sscreen->always_use_ngg_culling = sscreen->use_ngg_culling &&
1198 sscreen->debug_flags & DBG(ALWAYS_NGG_CULLING);
1199 sscreen->use_ngg_streamout = false;
1200
1201 /* Only enable primitive binning on APUs by default. */
1202 if (sscreen->info.chip_class >= GFX10) {
1203 sscreen->dpbb_allowed = true;
1204 sscreen->dfsm_allowed = !sscreen->info.has_dedicated_vram;
1205 } else if (sscreen->info.chip_class == GFX9) {
1206 sscreen->dpbb_allowed = !sscreen->info.has_dedicated_vram;
1207 sscreen->dfsm_allowed = !sscreen->info.has_dedicated_vram;
1208 }
1209
1210 /* Process DPBB enable flags. */
1211 if (sscreen->debug_flags & DBG(DPBB)) {
1212 sscreen->dpbb_allowed = true;
1213 if (sscreen->debug_flags & DBG(DFSM))
1214 sscreen->dfsm_allowed = true;
1215 }
1216
1217 /* Process DPBB disable flags. */
1218 if (sscreen->debug_flags & DBG(NO_DPBB)) {
1219 sscreen->dpbb_allowed = false;
1220 sscreen->dfsm_allowed = false;
1221 } else if (sscreen->debug_flags & DBG(NO_DFSM)) {
1222 sscreen->dfsm_allowed = false;
1223 }
1224
1225 /* While it would be nice not to have this flag, we are constrained
1226 * by the reality that LLVM 9.0 has buggy VGPR indexing on GFX9.
1227 */
1228 sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class != GFX9;
1229
1230 sscreen->dcc_msaa_allowed =
1231 !(sscreen->debug_flags & DBG(NO_DCC_MSAA));
1232
1233 (void) simple_mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1234 sscreen->use_monolithic_shaders =
1235 (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
1236
1237 sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SCACHE |
1238 SI_CONTEXT_INV_VCACHE;
1239 if (sscreen->info.chip_class <= GFX8) {
1240 sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_L2;
1241 sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WB_L2;
1242 }
1243
1244 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1245 sscreen->debug_flags |= DBG_ALL_SHADERS;
1246
1247 /* Syntax:
1248 * EQAA=s,z,c
1249 * Example:
1250 * EQAA=8,4,2
1251
1252 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1253 * Constraints:
1254 * s >= z >= c (ignoring this only wastes memory)
1255 * s = [2..16]
1256 * z = [2..8]
1257 * c = [2..8]
1258 *
1259 * Only MSAA color and depth buffers are overriden.
1260 */
1261 if (sscreen->info.has_eqaa_surface_allocator) {
1262 const char *eqaa = debug_get_option("EQAA", NULL);
1263 unsigned s,z,f;
1264
1265 if (eqaa && sscanf(eqaa, "%u,%u,%u", &s, &z, &f) == 3 && s && z && f) {
1266 sscreen->eqaa_force_coverage_samples = s;
1267 sscreen->eqaa_force_z_samples = z;
1268 sscreen->eqaa_force_color_samples = f;
1269 }
1270 }
1271
1272 sscreen->ge_wave_size = 64;
1273 sscreen->ps_wave_size = 64;
1274 sscreen->compute_wave_size = 64;
1275
1276 if (sscreen->info.chip_class >= GFX10) {
1277 /* Pixels shaders: Wave64 is recommended.
1278 * Compute shaders: There are piglit failures with Wave32.
1279 */
1280 sscreen->ge_wave_size = 32;
1281
1282 if (sscreen->debug_flags & DBG(W32_GE))
1283 sscreen->ge_wave_size = 32;
1284 if (sscreen->debug_flags & DBG(W32_PS))
1285 sscreen->ps_wave_size = 32;
1286 if (sscreen->debug_flags & DBG(W32_CS))
1287 sscreen->compute_wave_size = 32;
1288
1289 if (sscreen->debug_flags & DBG(W64_GE))
1290 sscreen->ge_wave_size = 64;
1291 if (sscreen->debug_flags & DBG(W64_PS))
1292 sscreen->ps_wave_size = 64;
1293 if (sscreen->debug_flags & DBG(W64_CS))
1294 sscreen->compute_wave_size = 64;
1295 }
1296
1297 /* Create the auxiliary context. This must be done last. */
1298 sscreen->aux_context = si_create_context(&sscreen->b,
1299 (sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) |
1300 (sscreen->info.has_graphics ? 0 : PIPE_CONTEXT_COMPUTE_ONLY));
1301 if (sscreen->options.aux_debug) {
1302 struct u_log_context *log = CALLOC_STRUCT(u_log_context);
1303 u_log_context_init(log);
1304 sscreen->aux_context->set_log_context(sscreen->aux_context, log);
1305 }
1306
1307 if (test_flags & DBG(TEST_DMA))
1308 si_test_dma(sscreen);
1309
1310 if (test_flags & DBG(TEST_DMA_PERF)) {
1311 si_test_dma_perf(sscreen);
1312 }
1313
1314 if (test_flags & (DBG(TEST_VMFAULT_CP) |
1315 DBG(TEST_VMFAULT_SDMA) |
1316 DBG(TEST_VMFAULT_SHADER)))
1317 si_test_vmfault(sscreen, test_flags);
1318
1319 if (test_flags & DBG(TEST_GDS))
1320 si_test_gds((struct si_context*)sscreen->aux_context);
1321
1322 if (test_flags & DBG(TEST_GDS_MM)) {
1323 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1324 32 * 1024, 4, RADEON_DOMAIN_GDS);
1325 }
1326 if (test_flags & DBG(TEST_GDS_OA_MM)) {
1327 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1328 4, 1, RADEON_DOMAIN_OA);
1329 }
1330
1331 STATIC_ASSERT(sizeof(union si_vgt_stages_key) == 4);
1332 return &sscreen->b;
1333 }
1334
1335 struct pipe_screen *radeonsi_screen_create(int fd, const struct pipe_screen_config *config)
1336 {
1337 drmVersionPtr version = drmGetVersion(fd);
1338 struct radeon_winsys *rw = NULL;
1339
1340 switch (version->version_major) {
1341 case 2:
1342 rw = radeon_drm_winsys_create(fd, config, radeonsi_screen_create_impl);
1343 break;
1344 case 3:
1345 rw = amdgpu_winsys_create(fd, config, radeonsi_screen_create_impl);
1346 break;
1347 }
1348
1349 drmFreeVersion(version);
1350 return rw ? rw->screen : NULL;
1351 }