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radeonsi: don't wait for shader compilation to finish when destroying a context
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "si_pipe.h"
27 #include "si_public.h"
28 #include "si_shader_internal.h"
29 #include "si_compute.h"
30 #include "sid.h"
31
32 #include "radeon/radeon_uvd.h"
33 #include "util/disk_cache.h"
34 #include "util/u_log.h"
35 #include "util/u_memory.h"
36 #include "util/u_suballoc.h"
37 #include "util/u_tests.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/xmlconfig.h"
40 #include "vl/vl_decoder.h"
41 #include "driver_ddebug/dd_util.h"
42
43 #include "gallium/winsys/radeon/drm/radeon_drm_public.h"
44 #include "gallium/winsys/amdgpu/drm/amdgpu_public.h"
45 #include <xf86drm.h>
46
47 static struct pipe_context *si_create_context(struct pipe_screen *screen,
48 unsigned flags);
49
50 static const struct debug_named_value debug_options[] = {
51 /* Shader logging options: */
52 { "vs", DBG(VS), "Print vertex shaders" },
53 { "ps", DBG(PS), "Print pixel shaders" },
54 { "gs", DBG(GS), "Print geometry shaders" },
55 { "tcs", DBG(TCS), "Print tessellation control shaders" },
56 { "tes", DBG(TES), "Print tessellation evaluation shaders" },
57 { "cs", DBG(CS), "Print compute shaders" },
58 { "noir", DBG(NO_IR), "Don't print the LLVM IR"},
59 { "nonir", DBG(NO_NIR), "Don't print NIR when printing shaders"},
60 { "noasm", DBG(NO_ASM), "Don't print disassembled shaders"},
61 { "preoptir", DBG(PREOPT_IR), "Print the LLVM IR before initial optimizations" },
62
63 /* Shader compiler options the shader cache should be aware of: */
64 { "sisched", DBG(SI_SCHED), "Enable LLVM SI Machine Instruction Scheduler." },
65 { "gisel", DBG(GISEL), "Enable LLVM global instruction selector." },
66 { "w32ge", DBG(W32_GE), "Use Wave32 for vertex, tessellation, and geometry shaders." },
67 { "w32ps", DBG(W32_PS), "Use Wave32 for pixel shaders." },
68 { "w32cs", DBG(W32_CS), "Use Wave32 for computes shaders." },
69 { "w64ge", DBG(W64_GE), "Use Wave64 for vertex, tessellation, and geometry shaders." },
70 { "w64ps", DBG(W64_PS), "Use Wave64 for pixel shaders." },
71 { "w64cs", DBG(W64_CS), "Use Wave64 for computes shaders." },
72
73 /* Shader compiler options (with no effect on the shader cache): */
74 { "checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR" },
75 { "mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand" },
76 { "nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants." },
77
78 /* Information logging options: */
79 { "info", DBG(INFO), "Print driver information" },
80 { "tex", DBG(TEX), "Print texture info" },
81 { "compute", DBG(COMPUTE), "Print compute info" },
82 { "vm", DBG(VM), "Print virtual addresses when creating resources" },
83 { "cache_stats", DBG(CACHE_STATS), "Print shader cache statistics." },
84
85 /* Driver options: */
86 { "forcedma", DBG(FORCE_SDMA), "Use SDMA for all operations when possible." },
87 { "nodma", DBG(NO_SDMA), "Disable SDMA" },
88 { "nodmaclear", DBG(NO_SDMA_CLEARS), "Disable SDMA clears" },
89 { "nodmacopyimage", DBG(NO_SDMA_COPY_IMAGE), "Disable SDMA image copies" },
90 { "nowc", DBG(NO_WC), "Disable GTT write combining" },
91 { "check_vm", DBG(CHECK_VM), "Check VM faults and dump debug info." },
92 { "reserve_vmid", DBG(RESERVE_VMID), "Force VMID reservation per context." },
93 { "zerovram", DBG(ZERO_VRAM), "Clear VRAM allocations." },
94
95 /* 3D engine options: */
96 { "nogfx", DBG(NO_GFX), "Disable graphics. Only multimedia compute paths can be used." },
97 { "nongg", DBG(NO_NGG), "Disable NGG and use the legacy pipeline." },
98 { "nggc", DBG(ALWAYS_NGG_CULLING), "Always use NGG culling even when it can hurt." },
99 { "nonggc", DBG(NO_NGG_CULLING), "Disable NGG culling." },
100 { "alwayspd", DBG(ALWAYS_PD), "Always enable the primitive discard compute shader." },
101 { "pd", DBG(PD), "Enable the primitive discard compute shader for large draw calls." },
102 { "nopd", DBG(NO_PD), "Disable the primitive discard compute shader." },
103 { "switch_on_eop", DBG(SWITCH_ON_EOP), "Program WD/IA to switch on end-of-packet." },
104 { "nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order rasterization" },
105 { "nodpbb", DBG(NO_DPBB), "Disable DPBB." },
106 { "nodfsm", DBG(NO_DFSM), "Disable DFSM." },
107 { "dpbb", DBG(DPBB), "Enable DPBB." },
108 { "dfsm", DBG(DFSM), "Enable DFSM." },
109 { "nohyperz", DBG(NO_HYPERZ), "Disable Hyper-Z" },
110 { "norbplus", DBG(NO_RB_PLUS), "Disable RB+." },
111 { "no2d", DBG(NO_2D_TILING), "Disable 2D tiling" },
112 { "notiling", DBG(NO_TILING), "Disable tiling" },
113 { "nodcc", DBG(NO_DCC), "Disable DCC." },
114 { "nodccclear", DBG(NO_DCC_CLEAR), "Disable DCC fast clear." },
115 { "nodccfb", DBG(NO_DCC_FB), "Disable separate DCC on the main framebuffer" },
116 { "nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA" },
117 { "nofmask", DBG(NO_FMASK), "Disable MSAA compression" },
118
119 DEBUG_NAMED_VALUE_END /* must be last */
120 };
121
122 static const struct debug_named_value test_options[] = {
123 /* Tests: */
124 { "testdma", DBG(TEST_DMA), "Invoke SDMA tests and exit." },
125 { "testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and exit." },
126 { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA), "Invoke a SDMA VM fault test and exit." },
127 { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM fault test and exit." },
128 { "testdmaperf", DBG(TEST_DMA_PERF), "Test DMA performance" },
129 { "testgds", DBG(TEST_GDS), "Test GDS." },
130 { "testgdsmm", DBG(TEST_GDS_MM), "Test GDS memory management." },
131 { "testgdsoamm", DBG(TEST_GDS_OA_MM), "Test GDS OA memory management." },
132
133 DEBUG_NAMED_VALUE_END /* must be last */
134 };
135
136 void si_init_compiler(struct si_screen *sscreen, struct ac_llvm_compiler *compiler)
137 {
138 /* Only create the less-optimizing version of the compiler on APUs
139 * predating Ryzen (Raven). */
140 bool create_low_opt_compiler = !sscreen->info.has_dedicated_vram &&
141 sscreen->info.chip_class <= GFX8;
142
143 enum ac_target_machine_options tm_options =
144 (sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
145 (sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL : 0) |
146 (sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
147 (sscreen->info.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
148 (!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0) |
149 (sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0) |
150 (create_low_opt_compiler ? AC_TM_CREATE_LOW_OPT : 0);
151
152 ac_init_llvm_once();
153 ac_init_llvm_compiler(compiler, sscreen->info.family, tm_options);
154 compiler->passes = ac_create_llvm_passes(compiler->tm);
155
156 if (compiler->tm_wave32)
157 compiler->passes_wave32 = ac_create_llvm_passes(compiler->tm_wave32);
158 if (compiler->low_opt_tm)
159 compiler->low_opt_passes = ac_create_llvm_passes(compiler->low_opt_tm);
160 }
161
162 static void si_destroy_compiler(struct ac_llvm_compiler *compiler)
163 {
164 ac_destroy_llvm_compiler(compiler);
165 }
166
167 /*
168 * pipe_context
169 */
170 static void si_destroy_context(struct pipe_context *context)
171 {
172 struct si_context *sctx = (struct si_context *)context;
173 int i;
174
175 /* Unreference the framebuffer normally to disable related logic
176 * properly.
177 */
178 struct pipe_framebuffer_state fb = {};
179 if (context->set_framebuffer_state)
180 context->set_framebuffer_state(context, &fb);
181
182 si_release_all_descriptors(sctx);
183
184 if (sctx->chip_class >= GFX10 && sctx->has_graphics)
185 gfx10_destroy_query(sctx);
186
187 pipe_resource_reference(&sctx->esgs_ring, NULL);
188 pipe_resource_reference(&sctx->gsvs_ring, NULL);
189 pipe_resource_reference(&sctx->tess_rings, NULL);
190 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
191 pipe_resource_reference(&sctx->sample_pos_buffer, NULL);
192 si_resource_reference(&sctx->border_color_buffer, NULL);
193 free(sctx->border_color_table);
194 si_resource_reference(&sctx->scratch_buffer, NULL);
195 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
196 si_resource_reference(&sctx->wait_mem_scratch, NULL);
197 si_resource_reference(&sctx->small_prim_cull_info_buf, NULL);
198
199 si_pm4_free_state(sctx, sctx->init_config, ~0);
200 if (sctx->init_config_gs_rings)
201 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
202 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
203 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
204
205 if (sctx->fixed_func_tcs_shader.cso)
206 sctx->b.delete_tcs_state(&sctx->b, sctx->fixed_func_tcs_shader.cso);
207 if (sctx->custom_dsa_flush)
208 sctx->b.delete_depth_stencil_alpha_state(&sctx->b, sctx->custom_dsa_flush);
209 if (sctx->custom_blend_resolve)
210 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_resolve);
211 if (sctx->custom_blend_fmask_decompress)
212 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_fmask_decompress);
213 if (sctx->custom_blend_eliminate_fastclear)
214 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_eliminate_fastclear);
215 if (sctx->custom_blend_dcc_decompress)
216 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_dcc_decompress);
217 if (sctx->vs_blit_pos)
218 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos);
219 if (sctx->vs_blit_pos_layered)
220 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos_layered);
221 if (sctx->vs_blit_color)
222 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color);
223 if (sctx->vs_blit_color_layered)
224 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color_layered);
225 if (sctx->vs_blit_texcoord)
226 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_texcoord);
227 if (sctx->cs_clear_buffer)
228 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_buffer);
229 if (sctx->cs_copy_buffer)
230 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_buffer);
231 if (sctx->cs_copy_image)
232 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image);
233 if (sctx->cs_copy_image_1d_array)
234 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image_1d_array);
235 if (sctx->cs_clear_render_target)
236 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target);
237 if (sctx->cs_clear_render_target_1d_array)
238 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target_1d_array);
239 if (sctx->cs_clear_12bytes_buffer)
240 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_12bytes_buffer);
241 if (sctx->cs_dcc_retile)
242 sctx->b.delete_compute_state(&sctx->b, sctx->cs_dcc_retile);
243
244 for (unsigned i = 0; i < ARRAY_SIZE(sctx->cs_fmask_expand); i++) {
245 for (unsigned j = 0; j < ARRAY_SIZE(sctx->cs_fmask_expand[i]); j++) {
246 if (sctx->cs_fmask_expand[i][j]) {
247 sctx->b.delete_compute_state(&sctx->b,
248 sctx->cs_fmask_expand[i][j]);
249 }
250 }
251 }
252
253 if (sctx->blitter)
254 util_blitter_destroy(sctx->blitter);
255
256 /* Release DCC stats. */
257 for (int i = 0; i < ARRAY_SIZE(sctx->dcc_stats); i++) {
258 assert(!sctx->dcc_stats[i].query_active);
259
260 for (int j = 0; j < ARRAY_SIZE(sctx->dcc_stats[i].ps_stats); j++)
261 if (sctx->dcc_stats[i].ps_stats[j])
262 sctx->b.destroy_query(&sctx->b,
263 sctx->dcc_stats[i].ps_stats[j]);
264
265 si_texture_reference(&sctx->dcc_stats[i].tex, NULL);
266 }
267
268 if (sctx->query_result_shader)
269 sctx->b.delete_compute_state(&sctx->b, sctx->query_result_shader);
270 if (sctx->sh_query_result_shader)
271 sctx->b.delete_compute_state(&sctx->b, sctx->sh_query_result_shader);
272
273 if (sctx->gfx_cs)
274 sctx->ws->cs_destroy(sctx->gfx_cs);
275 if (sctx->sdma_cs)
276 sctx->ws->cs_destroy(sctx->sdma_cs);
277 if (sctx->ctx)
278 sctx->ws->ctx_destroy(sctx->ctx);
279
280 if (sctx->b.stream_uploader)
281 u_upload_destroy(sctx->b.stream_uploader);
282 if (sctx->b.const_uploader)
283 u_upload_destroy(sctx->b.const_uploader);
284 if (sctx->cached_gtt_allocator)
285 u_upload_destroy(sctx->cached_gtt_allocator);
286
287 slab_destroy_child(&sctx->pool_transfers);
288 slab_destroy_child(&sctx->pool_transfers_unsync);
289
290 if (sctx->allocator_zeroed_memory)
291 u_suballocator_destroy(sctx->allocator_zeroed_memory);
292
293 sctx->ws->fence_reference(&sctx->last_gfx_fence, NULL);
294 sctx->ws->fence_reference(&sctx->last_sdma_fence, NULL);
295 sctx->ws->fence_reference(&sctx->last_ib_barrier_fence, NULL);
296 si_resource_reference(&sctx->eop_bug_scratch, NULL);
297 si_resource_reference(&sctx->index_ring, NULL);
298 si_resource_reference(&sctx->barrier_buf, NULL);
299 si_resource_reference(&sctx->last_ib_barrier_buf, NULL);
300 pb_reference(&sctx->gds, NULL);
301 pb_reference(&sctx->gds_oa, NULL);
302
303 si_destroy_compiler(&sctx->compiler);
304
305 si_saved_cs_reference(&sctx->current_saved_cs, NULL);
306
307 _mesa_hash_table_destroy(sctx->tex_handles, NULL);
308 _mesa_hash_table_destroy(sctx->img_handles, NULL);
309
310 util_dynarray_fini(&sctx->resident_tex_handles);
311 util_dynarray_fini(&sctx->resident_img_handles);
312 util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
313 util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
314 util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
315 si_unref_sdma_uploads(sctx);
316 free(sctx->sdma_uploads);
317 FREE(sctx);
318 }
319
320 static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx)
321 {
322 struct si_context *sctx = (struct si_context *)ctx;
323 struct si_screen *sscreen = sctx->screen;
324 enum pipe_reset_status status = sctx->ws->ctx_query_reset_status(sctx->ctx);
325
326 if (status != PIPE_NO_RESET) {
327 /* Call the state tracker to set a no-op API dispatch. */
328 if (sctx->device_reset_callback.reset) {
329 sctx->device_reset_callback.reset(sctx->device_reset_callback.data,
330 status);
331 }
332
333 /* Re-create the auxiliary context, because it won't submit
334 * any new IBs due to a GPU reset.
335 */
336 simple_mtx_lock(&sscreen->aux_context_lock);
337
338 struct u_log_context *aux_log = ((struct si_context *)sscreen->aux_context)->log;
339 sscreen->aux_context->set_log_context(sscreen->aux_context, NULL);
340 sscreen->aux_context->destroy(sscreen->aux_context);
341
342 sscreen->aux_context = si_create_context(&sscreen->b,
343 (sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) |
344 (sscreen->info.has_graphics ? 0 : PIPE_CONTEXT_COMPUTE_ONLY));
345 sscreen->aux_context->set_log_context(sscreen->aux_context, aux_log);
346 simple_mtx_unlock(&sscreen->aux_context_lock);
347 }
348 return status;
349 }
350
351 static void si_set_device_reset_callback(struct pipe_context *ctx,
352 const struct pipe_device_reset_callback *cb)
353 {
354 struct si_context *sctx = (struct si_context *)ctx;
355
356 if (cb)
357 sctx->device_reset_callback = *cb;
358 else
359 memset(&sctx->device_reset_callback, 0,
360 sizeof(sctx->device_reset_callback));
361 }
362
363 /* Apitrace profiling:
364 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
365 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
366 * and remember its number.
367 * 3) In Mesa, enable queries and performance counters around that draw
368 * call and print the results.
369 * 4) glretrace --benchmark --markers ..
370 */
371 static void si_emit_string_marker(struct pipe_context *ctx,
372 const char *string, int len)
373 {
374 struct si_context *sctx = (struct si_context *)ctx;
375
376 dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
377
378 if (sctx->log)
379 u_log_printf(sctx->log, "\nString marker: %*s\n", len, string);
380 }
381
382 static void si_set_debug_callback(struct pipe_context *ctx,
383 const struct pipe_debug_callback *cb)
384 {
385 struct si_context *sctx = (struct si_context *)ctx;
386 struct si_screen *screen = sctx->screen;
387
388 util_queue_finish(&screen->shader_compiler_queue);
389 util_queue_finish(&screen->shader_compiler_queue_low_priority);
390
391 if (cb)
392 sctx->debug = *cb;
393 else
394 memset(&sctx->debug, 0, sizeof(sctx->debug));
395 }
396
397 static void si_set_log_context(struct pipe_context *ctx,
398 struct u_log_context *log)
399 {
400 struct si_context *sctx = (struct si_context *)ctx;
401 sctx->log = log;
402
403 if (log)
404 u_log_add_auto_logger(log, si_auto_log_cs, sctx);
405 }
406
407 static void si_set_context_param(struct pipe_context *ctx,
408 enum pipe_context_param param,
409 unsigned value)
410 {
411 struct radeon_winsys *ws = ((struct si_context *)ctx)->ws;
412
413 switch (param) {
414 case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE:
415 ws->pin_threads_to_L3_cache(ws, value);
416 break;
417 default:;
418 }
419 }
420
421 static struct pipe_context *si_create_context(struct pipe_screen *screen,
422 unsigned flags)
423 {
424 struct si_screen* sscreen = (struct si_screen *)screen;
425 STATIC_ASSERT(DBG_COUNT <= 64);
426
427 /* Don't create a context if it's not compute-only and hw is compute-only. */
428 if (!sscreen->info.has_graphics &&
429 !(flags & PIPE_CONTEXT_COMPUTE_ONLY))
430 return NULL;
431
432 struct si_context *sctx = CALLOC_STRUCT(si_context);
433 struct radeon_winsys *ws = sscreen->ws;
434 int shader, i;
435 bool stop_exec_on_failure = (flags & PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET) != 0;
436
437 if (!sctx)
438 return NULL;
439
440 sctx->has_graphics = sscreen->info.chip_class == GFX6 ||
441 !(flags & PIPE_CONTEXT_COMPUTE_ONLY);
442
443 if (flags & PIPE_CONTEXT_DEBUG)
444 sscreen->record_llvm_ir = true; /* racy but not critical */
445
446 sctx->b.screen = screen; /* this must be set first */
447 sctx->b.priv = NULL;
448 sctx->b.destroy = si_destroy_context;
449 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
450 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
451
452 slab_create_child(&sctx->pool_transfers, &sscreen->pool_transfers);
453 slab_create_child(&sctx->pool_transfers_unsync, &sscreen->pool_transfers);
454
455 sctx->ws = sscreen->ws;
456 sctx->family = sscreen->info.family;
457 sctx->chip_class = sscreen->info.chip_class;
458
459 if (sctx->chip_class == GFX7 ||
460 sctx->chip_class == GFX8 ||
461 sctx->chip_class == GFX9) {
462 sctx->eop_bug_scratch = si_resource(
463 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
464 16 * sscreen->info.num_render_backends));
465 if (!sctx->eop_bug_scratch)
466 goto fail;
467 }
468
469 /* Initialize context allocators. */
470 sctx->allocator_zeroed_memory =
471 u_suballocator_create(&sctx->b, 128 * 1024,
472 0, PIPE_USAGE_DEFAULT,
473 SI_RESOURCE_FLAG_UNMAPPABLE |
474 SI_RESOURCE_FLAG_CLEAR, false);
475 if (!sctx->allocator_zeroed_memory)
476 goto fail;
477
478 sctx->b.stream_uploader = u_upload_create(&sctx->b, 1024 * 1024,
479 0, PIPE_USAGE_STREAM,
480 SI_RESOURCE_FLAG_READ_ONLY);
481 if (!sctx->b.stream_uploader)
482 goto fail;
483
484 sctx->cached_gtt_allocator = u_upload_create(&sctx->b, 16 * 1024,
485 0, PIPE_USAGE_STAGING, 0);
486 if (!sctx->cached_gtt_allocator)
487 goto fail;
488
489 sctx->ctx = sctx->ws->ctx_create(sctx->ws);
490 if (!sctx->ctx)
491 goto fail;
492
493 if (sscreen->info.num_rings[RING_DMA] &&
494 !(sscreen->debug_flags & DBG(NO_SDMA)) &&
495 /* SDMA causes corruption on RX 580:
496 * https://gitlab.freedesktop.org/mesa/mesa/issues/1399
497 * https://gitlab.freedesktop.org/mesa/mesa/issues/1889
498 */
499 (sctx->chip_class != GFX8 || sscreen->debug_flags & DBG(FORCE_SDMA)) &&
500 /* SDMA timeouts sometimes on gfx10 so disable it for now. See:
501 * https://bugs.freedesktop.org/show_bug.cgi?id=111481
502 * https://gitlab.freedesktop.org/mesa/mesa/issues/1907
503 */
504 (sctx->chip_class != GFX10 || sscreen->debug_flags & DBG(FORCE_SDMA))) {
505 sctx->sdma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA,
506 (void*)si_flush_dma_cs,
507 sctx, stop_exec_on_failure);
508 }
509
510 bool use_sdma_upload = sscreen->info.has_dedicated_vram && sctx->sdma_cs;
511 sctx->b.const_uploader = u_upload_create(&sctx->b, 256 * 1024,
512 0, PIPE_USAGE_DEFAULT,
513 SI_RESOURCE_FLAG_32BIT |
514 (use_sdma_upload ?
515 SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA : 0));
516 if (!sctx->b.const_uploader)
517 goto fail;
518
519 if (use_sdma_upload)
520 u_upload_enable_flush_explicit(sctx->b.const_uploader);
521
522 sctx->gfx_cs = ws->cs_create(sctx->ctx,
523 sctx->has_graphics ? RING_GFX : RING_COMPUTE,
524 (void*)si_flush_gfx_cs, sctx, stop_exec_on_failure);
525
526 /* Border colors. */
527 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
528 sizeof(*sctx->border_color_table));
529 if (!sctx->border_color_table)
530 goto fail;
531
532 sctx->border_color_buffer = si_resource(
533 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
534 SI_MAX_BORDER_COLORS *
535 sizeof(*sctx->border_color_table)));
536 if (!sctx->border_color_buffer)
537 goto fail;
538
539 sctx->border_color_map =
540 ws->buffer_map(sctx->border_color_buffer->buf,
541 NULL, PIPE_TRANSFER_WRITE);
542 if (!sctx->border_color_map)
543 goto fail;
544
545 sctx->ngg = sscreen->use_ngg;
546
547 /* Initialize context functions used by graphics and compute. */
548 if (sctx->chip_class >= GFX10)
549 sctx->emit_cache_flush = gfx10_emit_cache_flush;
550 else
551 sctx->emit_cache_flush = si_emit_cache_flush;
552
553 sctx->b.emit_string_marker = si_emit_string_marker;
554 sctx->b.set_debug_callback = si_set_debug_callback;
555 sctx->b.set_log_context = si_set_log_context;
556 sctx->b.set_context_param = si_set_context_param;
557 sctx->b.get_device_reset_status = si_get_reset_status;
558 sctx->b.set_device_reset_callback = si_set_device_reset_callback;
559
560 si_init_all_descriptors(sctx);
561 si_init_buffer_functions(sctx);
562 si_init_clear_functions(sctx);
563 si_init_blit_functions(sctx);
564 si_init_compute_functions(sctx);
565 si_init_compute_blit_functions(sctx);
566 si_init_debug_functions(sctx);
567 si_init_fence_functions(sctx);
568 si_init_query_functions(sctx);
569 si_init_state_compute_functions(sctx);
570 si_init_context_texture_functions(sctx);
571
572 /* Initialize graphics-only context functions. */
573 if (sctx->has_graphics) {
574 if (sctx->chip_class >= GFX10)
575 gfx10_init_query(sctx);
576 si_init_msaa_functions(sctx);
577 si_init_shader_functions(sctx);
578 si_init_state_functions(sctx);
579 si_init_streamout_functions(sctx);
580 si_init_viewport_functions(sctx);
581
582 sctx->blitter = util_blitter_create(&sctx->b);
583 if (sctx->blitter == NULL)
584 goto fail;
585 sctx->blitter->skip_viewport_restore = true;
586
587 /* Some states are expected to be always non-NULL. */
588 sctx->noop_blend = util_blitter_get_noop_blend_state(sctx->blitter);
589 sctx->queued.named.blend = sctx->noop_blend;
590
591 sctx->noop_dsa = util_blitter_get_noop_dsa_state(sctx->blitter);
592 sctx->queued.named.dsa = sctx->noop_dsa;
593
594 sctx->discard_rasterizer_state =
595 util_blitter_get_discard_rasterizer_state(sctx->blitter);
596 sctx->queued.named.rasterizer = sctx->discard_rasterizer_state;
597
598 si_init_draw_functions(sctx);
599
600 /* If aux_context == NULL, we are initializing aux_context right now. */
601 bool is_aux_context = !sscreen->aux_context;
602 si_initialize_prim_discard_tunables(sscreen, is_aux_context,
603 &sctx->prim_discard_vertex_count_threshold,
604 &sctx->index_ring_size_per_ib);
605 }
606
607 /* Initialize SDMA functions. */
608 if (sctx->chip_class >= GFX7)
609 cik_init_sdma_functions(sctx);
610 else
611 sctx->dma_copy = si_resource_copy_region;
612
613 if (sscreen->debug_flags & DBG(FORCE_SDMA))
614 sctx->b.resource_copy_region = sctx->dma_copy;
615
616 sctx->sample_mask = 0xffff;
617
618 /* Initialize multimedia functions. */
619 if (sscreen->info.has_hw_decode) {
620 sctx->b.create_video_codec = si_uvd_create_decoder;
621 sctx->b.create_video_buffer = si_video_buffer_create;
622 } else {
623 sctx->b.create_video_codec = vl_create_decoder;
624 sctx->b.create_video_buffer = vl_video_buffer_create;
625 }
626
627 if (sctx->chip_class >= GFX9) {
628 sctx->wait_mem_scratch = si_resource(
629 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 8));
630 if (!sctx->wait_mem_scratch)
631 goto fail;
632
633 /* Initialize the memory. */
634 si_cp_write_data(sctx, sctx->wait_mem_scratch, 0, 4,
635 V_370_MEM, V_370_ME, &sctx->wait_mem_number);
636 }
637
638 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
639 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
640 if (sctx->chip_class == GFX7) {
641 sctx->null_const_buf.buffer =
642 pipe_aligned_buffer_create(screen,
643 SI_RESOURCE_FLAG_32BIT,
644 PIPE_USAGE_DEFAULT, 16,
645 sctx->screen->info.tcc_cache_line_size);
646 if (!sctx->null_const_buf.buffer)
647 goto fail;
648 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
649
650 unsigned start_shader = sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE;
651 for (shader = start_shader; shader < SI_NUM_SHADERS; shader++) {
652 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
653 sctx->b.set_constant_buffer(&sctx->b, shader, i,
654 &sctx->null_const_buf);
655 }
656 }
657
658 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
659 &sctx->null_const_buf);
660 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
661 &sctx->null_const_buf);
662 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
663 &sctx->null_const_buf);
664 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
665 &sctx->null_const_buf);
666 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
667 &sctx->null_const_buf);
668 }
669
670 uint64_t max_threads_per_block;
671 screen->get_compute_param(screen, PIPE_SHADER_IR_NIR,
672 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
673 &max_threads_per_block);
674
675 /* The maximum number of scratch waves. Scratch space isn't divided
676 * evenly between CUs. The number is only a function of the number of CUs.
677 * We can decrease the constant to decrease the scratch buffer size.
678 *
679 * sctx->scratch_waves must be >= the maximum posible size of
680 * 1 threadgroup, so that the hw doesn't hang from being unable
681 * to start any.
682 *
683 * The recommended value is 4 per CU at most. Higher numbers don't
684 * bring much benefit, but they still occupy chip resources (think
685 * async compute). I've seen ~2% performance difference between 4 and 32.
686 */
687 sctx->scratch_waves = MAX2(32 * sscreen->info.num_good_compute_units,
688 max_threads_per_block / 64);
689
690 /* Bindless handles. */
691 sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
692 _mesa_key_pointer_equal);
693 sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
694 _mesa_key_pointer_equal);
695
696 util_dynarray_init(&sctx->resident_tex_handles, NULL);
697 util_dynarray_init(&sctx->resident_img_handles, NULL);
698 util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
699 util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
700 util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
701
702 sctx->sample_pos_buffer =
703 pipe_buffer_create(sctx->b.screen, 0, PIPE_USAGE_DEFAULT,
704 sizeof(sctx->sample_positions));
705 pipe_buffer_write(&sctx->b, sctx->sample_pos_buffer, 0,
706 sizeof(sctx->sample_positions), &sctx->sample_positions);
707
708 /* this must be last */
709 si_begin_new_gfx_cs(sctx);
710
711 if (sctx->chip_class == GFX7) {
712 /* Clear the NULL constant buffer, because loads should return zeros.
713 * Note that this forces CP DMA to be used, because clover deadlocks
714 * for some reason when the compute codepath is used.
715 */
716 uint32_t clear_value = 0;
717 si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0,
718 sctx->null_const_buf.buffer->width0,
719 &clear_value, 4, SI_COHERENCY_SHADER, true);
720 }
721 return &sctx->b;
722 fail:
723 fprintf(stderr, "radeonsi: Failed to create a context.\n");
724 si_destroy_context(&sctx->b);
725 return NULL;
726 }
727
728 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
729 void *priv, unsigned flags)
730 {
731 struct si_screen *sscreen = (struct si_screen *)screen;
732 struct pipe_context *ctx;
733
734 if (sscreen->debug_flags & DBG(CHECK_VM))
735 flags |= PIPE_CONTEXT_DEBUG;
736
737 ctx = si_create_context(screen, flags);
738
739 if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
740 return ctx;
741
742 /* Clover (compute-only) is unsupported. */
743 if (flags & PIPE_CONTEXT_COMPUTE_ONLY)
744 return ctx;
745
746 /* When shaders are logged to stderr, asynchronous compilation is
747 * disabled too. */
748 if (sscreen->debug_flags & DBG_ALL_SHADERS)
749 return ctx;
750
751 /* Use asynchronous flushes only on amdgpu, since the radeon
752 * implementation for fence_server_sync is incomplete. */
753 return threaded_context_create(ctx, &sscreen->pool_transfers,
754 si_replace_buffer_storage,
755 sscreen->info.is_amdgpu ? si_create_fence : NULL,
756 &((struct si_context*)ctx)->tc);
757 }
758
759 /*
760 * pipe_screen
761 */
762 static void si_destroy_screen(struct pipe_screen* pscreen)
763 {
764 struct si_screen *sscreen = (struct si_screen *)pscreen;
765 struct si_shader_part *parts[] = {
766 sscreen->vs_prologs,
767 sscreen->tcs_epilogs,
768 sscreen->gs_prologs,
769 sscreen->ps_prologs,
770 sscreen->ps_epilogs
771 };
772 unsigned i;
773
774 if (!sscreen->ws->unref(sscreen->ws))
775 return;
776
777 if (sscreen->debug_flags & DBG(CACHE_STATS)) {
778 printf("live shader cache: hits = %u, misses = %u\n",
779 sscreen->live_shader_cache.hits,
780 sscreen->live_shader_cache.misses);
781 printf("memory shader cache: hits = %u, misses = %u\n",
782 sscreen->num_memory_shader_cache_hits,
783 sscreen->num_memory_shader_cache_misses);
784 printf("disk shader cache: hits = %u, misses = %u\n",
785 sscreen->num_disk_shader_cache_hits,
786 sscreen->num_disk_shader_cache_misses);
787 }
788
789 simple_mtx_destroy(&sscreen->aux_context_lock);
790
791 struct u_log_context *aux_log = ((struct si_context *)sscreen->aux_context)->log;
792 if (aux_log) {
793 sscreen->aux_context->set_log_context(sscreen->aux_context, NULL);
794 u_log_context_destroy(aux_log);
795 FREE(aux_log);
796 }
797
798 sscreen->aux_context->destroy(sscreen->aux_context);
799
800 util_queue_destroy(&sscreen->shader_compiler_queue);
801 util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
802
803 /* Release the reference on glsl types of the compiler threads. */
804 glsl_type_singleton_decref();
805
806 for (i = 0; i < ARRAY_SIZE(sscreen->compiler); i++)
807 si_destroy_compiler(&sscreen->compiler[i]);
808
809 for (i = 0; i < ARRAY_SIZE(sscreen->compiler_lowp); i++)
810 si_destroy_compiler(&sscreen->compiler_lowp[i]);
811
812 /* Free shader parts. */
813 for (i = 0; i < ARRAY_SIZE(parts); i++) {
814 while (parts[i]) {
815 struct si_shader_part *part = parts[i];
816
817 parts[i] = part->next;
818 si_shader_binary_clean(&part->binary);
819 FREE(part);
820 }
821 }
822 simple_mtx_destroy(&sscreen->shader_parts_mutex);
823 si_destroy_shader_cache(sscreen);
824
825 si_destroy_perfcounters(sscreen);
826 si_gpu_load_kill_thread(sscreen);
827
828 simple_mtx_destroy(&sscreen->gpu_load_mutex);
829
830 slab_destroy_parent(&sscreen->pool_transfers);
831
832 disk_cache_destroy(sscreen->disk_shader_cache);
833 util_live_shader_cache_deinit(&sscreen->live_shader_cache);
834 sscreen->ws->destroy(sscreen->ws);
835 FREE(sscreen);
836 }
837
838 static void si_init_gs_info(struct si_screen *sscreen)
839 {
840 sscreen->gs_table_depth = ac_get_gs_table_depth(sscreen->info.chip_class,
841 sscreen->info.family);
842 }
843
844 static void si_test_vmfault(struct si_screen *sscreen, uint64_t test_flags)
845 {
846 struct pipe_context *ctx = sscreen->aux_context;
847 struct si_context *sctx = (struct si_context *)ctx;
848 struct pipe_resource *buf =
849 pipe_buffer_create_const0(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 64);
850
851 if (!buf) {
852 puts("Buffer allocation failed.");
853 exit(1);
854 }
855
856 si_resource(buf)->gpu_address = 0; /* cause a VM fault */
857
858 if (test_flags & DBG(TEST_VMFAULT_CP)) {
859 si_cp_dma_copy_buffer(sctx, buf, buf, 0, 4, 4, 0,
860 SI_COHERENCY_NONE, L2_BYPASS);
861 ctx->flush(ctx, NULL, 0);
862 puts("VM fault test: CP - done.");
863 }
864 if (test_flags & DBG(TEST_VMFAULT_SDMA)) {
865 si_sdma_clear_buffer(sctx, buf, 0, 4, 0);
866 ctx->flush(ctx, NULL, 0);
867 puts("VM fault test: SDMA - done.");
868 }
869 if (test_flags & DBG(TEST_VMFAULT_SHADER)) {
870 util_test_constant_buffer(ctx, buf);
871 puts("VM fault test: Shader - done.");
872 }
873 exit(0);
874 }
875
876 static void si_test_gds_memory_management(struct si_context *sctx,
877 unsigned alloc_size, unsigned alignment,
878 enum radeon_bo_domain domain)
879 {
880 struct radeon_winsys *ws = sctx->ws;
881 struct radeon_cmdbuf *cs[8];
882 struct pb_buffer *gds_bo[ARRAY_SIZE(cs)];
883
884 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
885 cs[i] = ws->cs_create(sctx->ctx, RING_COMPUTE,
886 NULL, NULL, false);
887 gds_bo[i] = ws->buffer_create(ws, alloc_size, alignment, domain, 0);
888 assert(gds_bo[i]);
889 }
890
891 for (unsigned iterations = 0; iterations < 20000; iterations++) {
892 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
893 /* This clears GDS with CP DMA.
894 *
895 * We don't care if GDS is present. Just add some packet
896 * to make the GPU busy for a moment.
897 */
898 si_cp_dma_clear_buffer(sctx, cs[i], NULL, 0, alloc_size, 0,
899 SI_CPDMA_SKIP_BO_LIST_UPDATE |
900 SI_CPDMA_SKIP_CHECK_CS_SPACE |
901 SI_CPDMA_SKIP_GFX_SYNC, 0, 0);
902
903 ws->cs_add_buffer(cs[i], gds_bo[i], domain,
904 RADEON_USAGE_READWRITE, 0);
905 ws->cs_flush(cs[i], PIPE_FLUSH_ASYNC, NULL);
906 }
907 }
908 exit(0);
909 }
910
911 static void si_disk_cache_create(struct si_screen *sscreen)
912 {
913 /* Don't use the cache if shader dumping is enabled. */
914 if (sscreen->debug_flags & DBG_ALL_SHADERS)
915 return;
916
917 struct mesa_sha1 ctx;
918 unsigned char sha1[20];
919 char cache_id[20 * 2 + 1];
920
921 _mesa_sha1_init(&ctx);
922
923 if (!disk_cache_get_function_identifier(si_disk_cache_create, &ctx) ||
924 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo,
925 &ctx))
926 return;
927
928 _mesa_sha1_final(&ctx, sha1);
929 disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
930
931 /* These flags affect shader compilation. */
932 #define ALL_FLAGS (DBG(SI_SCHED) | DBG(GISEL))
933 uint64_t shader_debug_flags = sscreen->debug_flags & ALL_FLAGS;
934
935 /* Add the high bits of 32-bit addresses, which affects
936 * how 32-bit addresses are expanded to 64 bits.
937 */
938 STATIC_ASSERT(ALL_FLAGS <= UINT_MAX);
939 assert((int16_t)sscreen->info.address32_hi == (int32_t)sscreen->info.address32_hi);
940 shader_debug_flags |= (uint64_t)(sscreen->info.address32_hi & 0xffff) << 32;
941
942 sscreen->disk_shader_cache =
943 disk_cache_create(sscreen->info.name,
944 cache_id,
945 shader_debug_flags);
946 }
947
948 static void si_set_max_shader_compiler_threads(struct pipe_screen *screen,
949 unsigned max_threads)
950 {
951 struct si_screen *sscreen = (struct si_screen *)screen;
952
953 /* This function doesn't allow a greater number of threads than
954 * the queue had at its creation. */
955 util_queue_adjust_num_threads(&sscreen->shader_compiler_queue,
956 max_threads);
957 /* Don't change the number of threads on the low priority queue. */
958 }
959
960 static bool si_is_parallel_shader_compilation_finished(struct pipe_screen *screen,
961 void *shader,
962 enum pipe_shader_type shader_type)
963 {
964 struct si_shader_selector *sel = (struct si_shader_selector *)shader;
965
966 return util_queue_fence_is_signalled(&sel->ready);
967 }
968
969 static struct pipe_screen *
970 radeonsi_screen_create_impl(struct radeon_winsys *ws,
971 const struct pipe_screen_config *config)
972 {
973 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
974 unsigned hw_threads, num_comp_hi_threads, num_comp_lo_threads;
975 uint64_t test_flags;
976
977 if (!sscreen) {
978 return NULL;
979 }
980
981 sscreen->ws = ws;
982 ws->query_info(ws, &sscreen->info);
983
984 if (sscreen->info.chip_class == GFX10 && LLVM_VERSION_MAJOR < 9) {
985 fprintf(stderr, "radeonsi: Navi family support requires LLVM 9 or higher\n");
986 FREE(sscreen);
987 return NULL;
988 }
989
990 if (sscreen->info.chip_class >= GFX9) {
991 sscreen->se_tile_repeat = 32 * sscreen->info.max_se;
992 } else {
993 ac_get_raster_config(&sscreen->info,
994 &sscreen->pa_sc_raster_config,
995 &sscreen->pa_sc_raster_config_1,
996 &sscreen->se_tile_repeat);
997 }
998
999 sscreen->debug_flags = debug_get_flags_option("R600_DEBUG",
1000 debug_options, 0);
1001 sscreen->debug_flags |= debug_get_flags_option("AMD_DEBUG",
1002 debug_options, 0);
1003 test_flags = debug_get_flags_option("AMD_TEST",
1004 test_options, 0);
1005
1006 if (sscreen->debug_flags & DBG(NO_GFX))
1007 sscreen->info.has_graphics = false;
1008
1009 /* Set functions first. */
1010 sscreen->b.context_create = si_pipe_create_context;
1011 sscreen->b.destroy = si_destroy_screen;
1012 sscreen->b.set_max_shader_compiler_threads =
1013 si_set_max_shader_compiler_threads;
1014 sscreen->b.is_parallel_shader_compilation_finished =
1015 si_is_parallel_shader_compilation_finished;
1016 sscreen->b.finalize_nir = si_finalize_nir;
1017
1018 si_init_screen_get_functions(sscreen);
1019 si_init_screen_buffer_functions(sscreen);
1020 si_init_screen_fence_functions(sscreen);
1021 si_init_screen_state_functions(sscreen);
1022 si_init_screen_texture_functions(sscreen);
1023 si_init_screen_query_functions(sscreen);
1024 si_init_screen_live_shader_cache(sscreen);
1025
1026 /* Set these flags in debug_flags early, so that the shader cache takes
1027 * them into account.
1028 */
1029 if (driQueryOptionb(config->options,
1030 "glsl_correct_derivatives_after_discard"))
1031 sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
1032 if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
1033 sscreen->debug_flags |= DBG(SI_SCHED);
1034
1035 if (sscreen->debug_flags & DBG(INFO))
1036 ac_print_gpu_info(&sscreen->info);
1037
1038 slab_create_parent(&sscreen->pool_transfers,
1039 sizeof(struct si_transfer), 64);
1040
1041 sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1042 if (sscreen->force_aniso == -1) {
1043 sscreen->force_aniso = MIN2(16, debug_get_num_option("AMD_TEX_ANISO", -1));
1044 }
1045
1046 if (sscreen->force_aniso >= 0) {
1047 printf("radeonsi: Forcing anisotropy filter to %ix\n",
1048 /* round down to a power of two */
1049 1 << util_logbase2(sscreen->force_aniso));
1050 }
1051
1052 (void) simple_mtx_init(&sscreen->aux_context_lock, mtx_plain);
1053 (void) simple_mtx_init(&sscreen->gpu_load_mutex, mtx_plain);
1054
1055 si_init_gs_info(sscreen);
1056 if (!si_init_shader_cache(sscreen)) {
1057 FREE(sscreen);
1058 return NULL;
1059 }
1060
1061 {
1062 #define OPT_BOOL(name, dflt, description) \
1063 sscreen->options.name = \
1064 driQueryOptionb(config->options, "radeonsi_"#name);
1065 #include "si_debug_options.h"
1066 }
1067
1068 si_disk_cache_create(sscreen);
1069
1070 /* Determine the number of shader compiler threads. */
1071 hw_threads = sysconf(_SC_NPROCESSORS_ONLN);
1072
1073 if (hw_threads >= 12) {
1074 num_comp_hi_threads = hw_threads * 3 / 4;
1075 num_comp_lo_threads = hw_threads / 3;
1076 } else if (hw_threads >= 6) {
1077 num_comp_hi_threads = hw_threads - 2;
1078 num_comp_lo_threads = hw_threads / 2;
1079 } else if (hw_threads >= 2) {
1080 num_comp_hi_threads = hw_threads - 1;
1081 num_comp_lo_threads = hw_threads / 2;
1082 } else {
1083 num_comp_hi_threads = 1;
1084 num_comp_lo_threads = 1;
1085 }
1086
1087 num_comp_hi_threads = MIN2(num_comp_hi_threads,
1088 ARRAY_SIZE(sscreen->compiler));
1089 num_comp_lo_threads = MIN2(num_comp_lo_threads,
1090 ARRAY_SIZE(sscreen->compiler_lowp));
1091
1092 /* Take a reference on the glsl types for the compiler threads. */
1093 glsl_type_singleton_init_or_ref();
1094
1095 if (!util_queue_init(&sscreen->shader_compiler_queue, "sh",
1096 64, num_comp_hi_threads,
1097 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1098 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY)) {
1099 si_destroy_shader_cache(sscreen);
1100 FREE(sscreen);
1101 glsl_type_singleton_decref();
1102 return NULL;
1103 }
1104
1105 if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
1106 "shlo",
1107 64, num_comp_lo_threads,
1108 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1109 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY |
1110 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
1111 si_destroy_shader_cache(sscreen);
1112 FREE(sscreen);
1113 glsl_type_singleton_decref();
1114 return NULL;
1115 }
1116
1117 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1118 si_init_perfcounters(sscreen);
1119
1120 unsigned prim_discard_vertex_count_threshold, tmp;
1121 si_initialize_prim_discard_tunables(sscreen, false,
1122 &prim_discard_vertex_count_threshold,
1123 &tmp);
1124 /* Compute-shader-based culling doesn't support VBOs in user SGPRs. */
1125 if (prim_discard_vertex_count_threshold == UINT_MAX)
1126 sscreen->num_vbos_in_user_sgprs = sscreen->info.chip_class >= GFX9 ? 5 : 1;
1127
1128 /* Determine tessellation ring info. */
1129 bool double_offchip_buffers = sscreen->info.chip_class >= GFX7 &&
1130 sscreen->info.family != CHIP_CARRIZO &&
1131 sscreen->info.family != CHIP_STONEY;
1132 /* This must be one less than the maximum number due to a hw limitation.
1133 * Various hardware bugs need this.
1134 */
1135 unsigned max_offchip_buffers_per_se;
1136
1137 if (sscreen->info.chip_class >= GFX10)
1138 max_offchip_buffers_per_se = 256;
1139 /* Only certain chips can use the maximum value. */
1140 else if (sscreen->info.family == CHIP_VEGA12 ||
1141 sscreen->info.family == CHIP_VEGA20)
1142 max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1143 else
1144 max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
1145
1146 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1147 sscreen->info.max_se;
1148 unsigned offchip_granularity;
1149
1150 /* Hawaii has a bug with offchip buffers > 256 that can be worked
1151 * around by setting 4K granularity.
1152 */
1153 if (sscreen->info.family == CHIP_HAWAII) {
1154 sscreen->tess_offchip_block_dw_size = 4096;
1155 offchip_granularity = V_03093C_X_4K_DWORDS;
1156 } else {
1157 sscreen->tess_offchip_block_dw_size = 8192;
1158 offchip_granularity = V_03093C_X_8K_DWORDS;
1159 }
1160
1161 sscreen->tess_factor_ring_size = 32768 * sscreen->info.max_se;
1162 sscreen->tess_offchip_ring_size = max_offchip_buffers *
1163 sscreen->tess_offchip_block_dw_size * 4;
1164
1165 if (sscreen->info.chip_class >= GFX7) {
1166 if (sscreen->info.chip_class >= GFX8)
1167 --max_offchip_buffers;
1168 sscreen->vgt_hs_offchip_param =
1169 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1170 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1171 } else {
1172 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
1173 sscreen->vgt_hs_offchip_param =
1174 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1175 }
1176
1177 sscreen->has_draw_indirect_multi =
1178 (sscreen->info.family >= CHIP_POLARIS10) ||
1179 (sscreen->info.chip_class == GFX8 &&
1180 sscreen->info.pfp_fw_version >= 121 &&
1181 sscreen->info.me_fw_version >= 87) ||
1182 (sscreen->info.chip_class == GFX7 &&
1183 sscreen->info.pfp_fw_version >= 211 &&
1184 sscreen->info.me_fw_version >= 173) ||
1185 (sscreen->info.chip_class == GFX6 &&
1186 sscreen->info.pfp_fw_version >= 79 &&
1187 sscreen->info.me_fw_version >= 142);
1188
1189 sscreen->has_out_of_order_rast = sscreen->info.has_out_of_order_rast &&
1190 !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER));
1191 sscreen->assume_no_z_fights =
1192 driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
1193 sscreen->commutative_blend_add =
1194 driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
1195
1196 sscreen->use_ngg = sscreen->info.chip_class >= GFX10 &&
1197 sscreen->info.family != CHIP_NAVI14 &&
1198 !(sscreen->debug_flags & DBG(NO_NGG));
1199 sscreen->use_ngg_culling = sscreen->use_ngg &&
1200 !(sscreen->debug_flags & DBG(NO_NGG_CULLING));
1201 sscreen->always_use_ngg_culling = sscreen->use_ngg_culling &&
1202 sscreen->debug_flags & DBG(ALWAYS_NGG_CULLING);
1203 sscreen->use_ngg_streamout = false;
1204
1205 /* Only enable primitive binning on APUs by default. */
1206 if (sscreen->info.chip_class >= GFX10) {
1207 sscreen->dpbb_allowed = true;
1208 sscreen->dfsm_allowed = !sscreen->info.has_dedicated_vram;
1209 } else if (sscreen->info.chip_class == GFX9) {
1210 sscreen->dpbb_allowed = !sscreen->info.has_dedicated_vram;
1211 sscreen->dfsm_allowed = !sscreen->info.has_dedicated_vram;
1212 }
1213
1214 /* Process DPBB enable flags. */
1215 if (sscreen->debug_flags & DBG(DPBB)) {
1216 sscreen->dpbb_allowed = true;
1217 if (sscreen->debug_flags & DBG(DFSM))
1218 sscreen->dfsm_allowed = true;
1219 }
1220
1221 /* Process DPBB disable flags. */
1222 if (sscreen->debug_flags & DBG(NO_DPBB)) {
1223 sscreen->dpbb_allowed = false;
1224 sscreen->dfsm_allowed = false;
1225 } else if (sscreen->debug_flags & DBG(NO_DFSM)) {
1226 sscreen->dfsm_allowed = false;
1227 }
1228
1229 /* While it would be nice not to have this flag, we are constrained
1230 * by the reality that LLVM 9.0 has buggy VGPR indexing on GFX9.
1231 */
1232 sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class != GFX9;
1233
1234 sscreen->dcc_msaa_allowed =
1235 !(sscreen->debug_flags & DBG(NO_DCC_MSAA));
1236
1237 (void) simple_mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1238 sscreen->use_monolithic_shaders =
1239 (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
1240
1241 sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SCACHE |
1242 SI_CONTEXT_INV_VCACHE;
1243 if (sscreen->info.chip_class <= GFX8) {
1244 sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_L2;
1245 sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WB_L2;
1246 }
1247
1248 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1249 sscreen->debug_flags |= DBG_ALL_SHADERS;
1250
1251 /* Syntax:
1252 * EQAA=s,z,c
1253 * Example:
1254 * EQAA=8,4,2
1255
1256 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1257 * Constraints:
1258 * s >= z >= c (ignoring this only wastes memory)
1259 * s = [2..16]
1260 * z = [2..8]
1261 * c = [2..8]
1262 *
1263 * Only MSAA color and depth buffers are overriden.
1264 */
1265 if (sscreen->info.has_eqaa_surface_allocator) {
1266 const char *eqaa = debug_get_option("EQAA", NULL);
1267 unsigned s,z,f;
1268
1269 if (eqaa && sscanf(eqaa, "%u,%u,%u", &s, &z, &f) == 3 && s && z && f) {
1270 sscreen->eqaa_force_coverage_samples = s;
1271 sscreen->eqaa_force_z_samples = z;
1272 sscreen->eqaa_force_color_samples = f;
1273 }
1274 }
1275
1276 sscreen->ge_wave_size = 64;
1277 sscreen->ps_wave_size = 64;
1278 sscreen->compute_wave_size = 64;
1279
1280 if (sscreen->info.chip_class >= GFX10) {
1281 /* Pixels shaders: Wave64 is recommended.
1282 * Compute shaders: There are piglit failures with Wave32.
1283 */
1284 sscreen->ge_wave_size = 32;
1285
1286 if (sscreen->debug_flags & DBG(W32_GE))
1287 sscreen->ge_wave_size = 32;
1288 if (sscreen->debug_flags & DBG(W32_PS))
1289 sscreen->ps_wave_size = 32;
1290 if (sscreen->debug_flags & DBG(W32_CS))
1291 sscreen->compute_wave_size = 32;
1292
1293 if (sscreen->debug_flags & DBG(W64_GE))
1294 sscreen->ge_wave_size = 64;
1295 if (sscreen->debug_flags & DBG(W64_PS))
1296 sscreen->ps_wave_size = 64;
1297 if (sscreen->debug_flags & DBG(W64_CS))
1298 sscreen->compute_wave_size = 64;
1299 }
1300
1301 /* Create the auxiliary context. This must be done last. */
1302 sscreen->aux_context = si_create_context(&sscreen->b,
1303 (sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) |
1304 (sscreen->info.has_graphics ? 0 : PIPE_CONTEXT_COMPUTE_ONLY));
1305 if (sscreen->options.aux_debug) {
1306 struct u_log_context *log = CALLOC_STRUCT(u_log_context);
1307 u_log_context_init(log);
1308 sscreen->aux_context->set_log_context(sscreen->aux_context, log);
1309 }
1310
1311 if (test_flags & DBG(TEST_DMA))
1312 si_test_dma(sscreen);
1313
1314 if (test_flags & DBG(TEST_DMA_PERF)) {
1315 si_test_dma_perf(sscreen);
1316 }
1317
1318 if (test_flags & (DBG(TEST_VMFAULT_CP) |
1319 DBG(TEST_VMFAULT_SDMA) |
1320 DBG(TEST_VMFAULT_SHADER)))
1321 si_test_vmfault(sscreen, test_flags);
1322
1323 if (test_flags & DBG(TEST_GDS))
1324 si_test_gds((struct si_context*)sscreen->aux_context);
1325
1326 if (test_flags & DBG(TEST_GDS_MM)) {
1327 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1328 32 * 1024, 4, RADEON_DOMAIN_GDS);
1329 }
1330 if (test_flags & DBG(TEST_GDS_OA_MM)) {
1331 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1332 4, 1, RADEON_DOMAIN_OA);
1333 }
1334
1335 STATIC_ASSERT(sizeof(union si_vgt_stages_key) == 4);
1336 return &sscreen->b;
1337 }
1338
1339 struct pipe_screen *radeonsi_screen_create(int fd, const struct pipe_screen_config *config)
1340 {
1341 drmVersionPtr version = drmGetVersion(fd);
1342 struct radeon_winsys *rw = NULL;
1343
1344 switch (version->version_major) {
1345 case 2:
1346 rw = radeon_drm_winsys_create(fd, config, radeonsi_screen_create_impl);
1347 break;
1348 case 3:
1349 rw = amdgpu_winsys_create(fd, config, radeonsi_screen_create_impl);
1350 break;
1351 }
1352
1353 drmFreeVersion(version);
1354 return rw ? rw->screen : NULL;
1355 }