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radeonsi/gfx10: implement Wave32
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "si_pipe.h"
27 #include "si_public.h"
28 #include "si_shader_internal.h"
29 #include "si_compute.h"
30 #include "sid.h"
31
32 #include "ac_llvm_util.h"
33 #include "radeon/radeon_uvd.h"
34 #include "gallivm/lp_bld_misc.h"
35 #include "util/disk_cache.h"
36 #include "util/u_log.h"
37 #include "util/u_memory.h"
38 #include "util/u_suballoc.h"
39 #include "util/u_tests.h"
40 #include "util/u_upload_mgr.h"
41 #include "util/xmlconfig.h"
42 #include "vl/vl_decoder.h"
43 #include "driver_ddebug/dd_util.h"
44
45 #include "gallium/winsys/radeon/drm/radeon_drm_public.h"
46 #include "gallium/winsys/amdgpu/drm/amdgpu_public.h"
47 #include <xf86drm.h>
48
49 static const struct debug_named_value debug_options[] = {
50 /* Shader logging options: */
51 { "vs", DBG(VS), "Print vertex shaders" },
52 { "ps", DBG(PS), "Print pixel shaders" },
53 { "gs", DBG(GS), "Print geometry shaders" },
54 { "tcs", DBG(TCS), "Print tessellation control shaders" },
55 { "tes", DBG(TES), "Print tessellation evaluation shaders" },
56 { "cs", DBG(CS), "Print compute shaders" },
57 { "noir", DBG(NO_IR), "Don't print the LLVM IR"},
58 { "notgsi", DBG(NO_TGSI), "Don't print the TGSI"},
59 { "noasm", DBG(NO_ASM), "Don't print disassembled shaders"},
60 { "preoptir", DBG(PREOPT_IR), "Print the LLVM IR before initial optimizations" },
61
62 /* Shader compiler options the shader cache should be aware of: */
63 { "unsafemath", DBG(UNSAFE_MATH), "Enable unsafe math shader optimizations" },
64 { "sisched", DBG(SI_SCHED), "Enable LLVM SI Machine Instruction Scheduler." },
65 { "gisel", DBG(GISEL), "Enable LLVM global instruction selector." },
66
67 /* Shader compiler options (with no effect on the shader cache): */
68 { "checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR" },
69 { "mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand" },
70 { "nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants." },
71
72 /* Information logging options: */
73 { "info", DBG(INFO), "Print driver information" },
74 { "tex", DBG(TEX), "Print texture info" },
75 { "compute", DBG(COMPUTE), "Print compute info" },
76 { "vm", DBG(VM), "Print virtual addresses when creating resources" },
77
78 /* Driver options: */
79 { "forcedma", DBG(FORCE_DMA), "Use asynchronous DMA for all operations when possible." },
80 { "nodma", DBG(NO_ASYNC_DMA), "Disable asynchronous DMA" },
81 { "nowc", DBG(NO_WC), "Disable GTT write combining" },
82 { "check_vm", DBG(CHECK_VM), "Check VM faults and dump debug info." },
83 { "reserve_vmid", DBG(RESERVE_VMID), "Force VMID reservation per context." },
84 { "zerovram", DBG(ZERO_VRAM), "Clear VRAM allocations." },
85
86 /* 3D engine options: */
87 { "alwayspd", DBG(ALWAYS_PD), "Always enable the primitive discard compute shader." },
88 { "pd", DBG(PD), "Enable the primitive discard compute shader for large draw calls." },
89 { "nopd", DBG(NO_PD), "Disable the primitive discard compute shader." },
90 { "switch_on_eop", DBG(SWITCH_ON_EOP), "Program WD/IA to switch on end-of-packet." },
91 { "nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order rasterization" },
92 { "nodpbb", DBG(NO_DPBB), "Disable DPBB." },
93 { "nodfsm", DBG(NO_DFSM), "Disable DFSM." },
94 { "dpbb", DBG(DPBB), "Enable DPBB." },
95 { "dfsm", DBG(DFSM), "Enable DFSM." },
96 { "nohyperz", DBG(NO_HYPERZ), "Disable Hyper-Z" },
97 { "norbplus", DBG(NO_RB_PLUS), "Disable RB+." },
98 { "no2d", DBG(NO_2D_TILING), "Disable 2D tiling" },
99 { "notiling", DBG(NO_TILING), "Disable tiling" },
100 { "nodcc", DBG(NO_DCC), "Disable DCC." },
101 { "nodccclear", DBG(NO_DCC_CLEAR), "Disable DCC fast clear." },
102 { "nodccfb", DBG(NO_DCC_FB), "Disable separate DCC on the main framebuffer" },
103 { "nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA" },
104 { "nofmask", DBG(NO_FMASK), "Disable MSAA compression" },
105
106 /* Tests: */
107 { "testdma", DBG(TEST_DMA), "Invoke SDMA tests and exit." },
108 { "testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and exit." },
109 { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA), "Invoke a SDMA VM fault test and exit." },
110 { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM fault test and exit." },
111 { "testdmaperf", DBG(TEST_DMA_PERF), "Test DMA performance" },
112 { "testgds", DBG(TEST_GDS), "Test GDS." },
113 { "testgdsmm", DBG(TEST_GDS_MM), "Test GDS memory management." },
114 { "testgdsoamm", DBG(TEST_GDS_OA_MM), "Test GDS OA memory management." },
115
116 DEBUG_NAMED_VALUE_END /* must be last */
117 };
118
119 static void si_init_compiler(struct si_screen *sscreen,
120 struct ac_llvm_compiler *compiler)
121 {
122 /* Only create the less-optimizing version of the compiler on APUs
123 * predating Ryzen (Raven). */
124 bool create_low_opt_compiler = !sscreen->info.has_dedicated_vram &&
125 sscreen->info.chip_class <= GFX8;
126
127 enum ac_target_machine_options tm_options =
128 (sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
129 (sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL : 0) |
130 (sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
131 (sscreen->info.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
132 (!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0) |
133 (sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0) |
134 (create_low_opt_compiler ? AC_TM_CREATE_LOW_OPT : 0);
135
136 ac_init_llvm_once();
137 ac_init_llvm_compiler(compiler, sscreen->info.family, tm_options);
138 compiler->passes = ac_create_llvm_passes(compiler->tm);
139
140 if (compiler->tm_wave32)
141 compiler->passes_wave32 = ac_create_llvm_passes(compiler->tm_wave32);
142 if (compiler->low_opt_tm)
143 compiler->low_opt_passes = ac_create_llvm_passes(compiler->low_opt_tm);
144 }
145
146 static void si_destroy_compiler(struct ac_llvm_compiler *compiler)
147 {
148 ac_destroy_llvm_compiler(compiler);
149 }
150
151 /*
152 * pipe_context
153 */
154 static void si_destroy_context(struct pipe_context *context)
155 {
156 struct si_context *sctx = (struct si_context *)context;
157 int i;
158
159 util_queue_finish(&sctx->screen->shader_compiler_queue);
160 util_queue_finish(&sctx->screen->shader_compiler_queue_low_priority);
161
162 /* Unreference the framebuffer normally to disable related logic
163 * properly.
164 */
165 struct pipe_framebuffer_state fb = {};
166 if (context->set_framebuffer_state)
167 context->set_framebuffer_state(context, &fb);
168
169 si_release_all_descriptors(sctx);
170
171 if (sctx->chip_class >= GFX10)
172 gfx10_destroy_query(sctx);
173
174 pipe_resource_reference(&sctx->esgs_ring, NULL);
175 pipe_resource_reference(&sctx->gsvs_ring, NULL);
176 pipe_resource_reference(&sctx->tess_rings, NULL);
177 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
178 pipe_resource_reference(&sctx->sample_pos_buffer, NULL);
179 si_resource_reference(&sctx->border_color_buffer, NULL);
180 free(sctx->border_color_table);
181 si_resource_reference(&sctx->scratch_buffer, NULL);
182 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
183 si_resource_reference(&sctx->wait_mem_scratch, NULL);
184
185 si_pm4_free_state(sctx, sctx->init_config, ~0);
186 if (sctx->init_config_gs_rings)
187 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
188 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
189 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
190
191 if (sctx->fixed_func_tcs_shader.cso)
192 sctx->b.delete_tcs_state(&sctx->b, sctx->fixed_func_tcs_shader.cso);
193 if (sctx->custom_dsa_flush)
194 sctx->b.delete_depth_stencil_alpha_state(&sctx->b, sctx->custom_dsa_flush);
195 if (sctx->custom_blend_resolve)
196 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_resolve);
197 if (sctx->custom_blend_fmask_decompress)
198 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_fmask_decompress);
199 if (sctx->custom_blend_eliminate_fastclear)
200 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_eliminate_fastclear);
201 if (sctx->custom_blend_dcc_decompress)
202 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_dcc_decompress);
203 if (sctx->vs_blit_pos)
204 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos);
205 if (sctx->vs_blit_pos_layered)
206 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos_layered);
207 if (sctx->vs_blit_color)
208 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color);
209 if (sctx->vs_blit_color_layered)
210 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color_layered);
211 if (sctx->vs_blit_texcoord)
212 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_texcoord);
213 if (sctx->cs_clear_buffer)
214 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_buffer);
215 if (sctx->cs_copy_buffer)
216 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_buffer);
217 if (sctx->cs_copy_image)
218 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image);
219 if (sctx->cs_copy_image_1d_array)
220 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image_1d_array);
221 if (sctx->cs_clear_render_target)
222 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target);
223 if (sctx->cs_clear_render_target_1d_array)
224 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target_1d_array);
225 if (sctx->cs_dcc_retile)
226 sctx->b.delete_compute_state(&sctx->b, sctx->cs_dcc_retile);
227
228 if (sctx->blitter)
229 util_blitter_destroy(sctx->blitter);
230
231 /* Release DCC stats. */
232 for (int i = 0; i < ARRAY_SIZE(sctx->dcc_stats); i++) {
233 assert(!sctx->dcc_stats[i].query_active);
234
235 for (int j = 0; j < ARRAY_SIZE(sctx->dcc_stats[i].ps_stats); j++)
236 if (sctx->dcc_stats[i].ps_stats[j])
237 sctx->b.destroy_query(&sctx->b,
238 sctx->dcc_stats[i].ps_stats[j]);
239
240 si_texture_reference(&sctx->dcc_stats[i].tex, NULL);
241 }
242
243 if (sctx->query_result_shader)
244 sctx->b.delete_compute_state(&sctx->b, sctx->query_result_shader);
245 if (sctx->sh_query_result_shader)
246 sctx->b.delete_compute_state(&sctx->b, sctx->sh_query_result_shader);
247
248 if (sctx->gfx_cs)
249 sctx->ws->cs_destroy(sctx->gfx_cs);
250 if (sctx->dma_cs)
251 sctx->ws->cs_destroy(sctx->dma_cs);
252 if (sctx->ctx)
253 sctx->ws->ctx_destroy(sctx->ctx);
254
255 if (sctx->b.stream_uploader)
256 u_upload_destroy(sctx->b.stream_uploader);
257 if (sctx->b.const_uploader)
258 u_upload_destroy(sctx->b.const_uploader);
259 if (sctx->cached_gtt_allocator)
260 u_upload_destroy(sctx->cached_gtt_allocator);
261
262 slab_destroy_child(&sctx->pool_transfers);
263 slab_destroy_child(&sctx->pool_transfers_unsync);
264
265 if (sctx->allocator_zeroed_memory)
266 u_suballocator_destroy(sctx->allocator_zeroed_memory);
267
268 sctx->ws->fence_reference(&sctx->last_gfx_fence, NULL);
269 sctx->ws->fence_reference(&sctx->last_sdma_fence, NULL);
270 sctx->ws->fence_reference(&sctx->last_ib_barrier_fence, NULL);
271 si_resource_reference(&sctx->eop_bug_scratch, NULL);
272 si_resource_reference(&sctx->index_ring, NULL);
273 si_resource_reference(&sctx->barrier_buf, NULL);
274 si_resource_reference(&sctx->last_ib_barrier_buf, NULL);
275 pb_reference(&sctx->gds, NULL);
276 pb_reference(&sctx->gds_oa, NULL);
277
278 si_destroy_compiler(&sctx->compiler);
279
280 si_saved_cs_reference(&sctx->current_saved_cs, NULL);
281
282 _mesa_hash_table_destroy(sctx->tex_handles, NULL);
283 _mesa_hash_table_destroy(sctx->img_handles, NULL);
284
285 util_dynarray_fini(&sctx->resident_tex_handles);
286 util_dynarray_fini(&sctx->resident_img_handles);
287 util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
288 util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
289 util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
290 si_unref_sdma_uploads(sctx);
291 FREE(sctx);
292 }
293
294 static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx)
295 {
296 struct si_context *sctx = (struct si_context *)ctx;
297
298 return sctx->ws->ctx_query_reset_status(sctx->ctx);
299 }
300
301 static void si_set_device_reset_callback(struct pipe_context *ctx,
302 const struct pipe_device_reset_callback *cb)
303 {
304 struct si_context *sctx = (struct si_context *)ctx;
305
306 if (cb)
307 sctx->device_reset_callback = *cb;
308 else
309 memset(&sctx->device_reset_callback, 0,
310 sizeof(sctx->device_reset_callback));
311 }
312
313 bool si_check_device_reset(struct si_context *sctx)
314 {
315 enum pipe_reset_status status;
316
317 if (!sctx->device_reset_callback.reset)
318 return false;
319
320 status = sctx->ws->ctx_query_reset_status(sctx->ctx);
321 if (status == PIPE_NO_RESET)
322 return false;
323
324 sctx->device_reset_callback.reset(sctx->device_reset_callback.data, status);
325 return true;
326 }
327
328 /* Apitrace profiling:
329 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
330 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
331 * and remember its number.
332 * 3) In Mesa, enable queries and performance counters around that draw
333 * call and print the results.
334 * 4) glretrace --benchmark --markers ..
335 */
336 static void si_emit_string_marker(struct pipe_context *ctx,
337 const char *string, int len)
338 {
339 struct si_context *sctx = (struct si_context *)ctx;
340
341 dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
342
343 if (sctx->log)
344 u_log_printf(sctx->log, "\nString marker: %*s\n", len, string);
345 }
346
347 static void si_set_debug_callback(struct pipe_context *ctx,
348 const struct pipe_debug_callback *cb)
349 {
350 struct si_context *sctx = (struct si_context *)ctx;
351 struct si_screen *screen = sctx->screen;
352
353 util_queue_finish(&screen->shader_compiler_queue);
354 util_queue_finish(&screen->shader_compiler_queue_low_priority);
355
356 if (cb)
357 sctx->debug = *cb;
358 else
359 memset(&sctx->debug, 0, sizeof(sctx->debug));
360 }
361
362 static void si_set_log_context(struct pipe_context *ctx,
363 struct u_log_context *log)
364 {
365 struct si_context *sctx = (struct si_context *)ctx;
366 sctx->log = log;
367
368 if (log)
369 u_log_add_auto_logger(log, si_auto_log_cs, sctx);
370 }
371
372 static void si_set_context_param(struct pipe_context *ctx,
373 enum pipe_context_param param,
374 unsigned value)
375 {
376 struct radeon_winsys *ws = ((struct si_context *)ctx)->ws;
377
378 switch (param) {
379 case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE:
380 ws->pin_threads_to_L3_cache(ws, value);
381 break;
382 default:;
383 }
384 }
385
386 static struct pipe_context *si_create_context(struct pipe_screen *screen,
387 unsigned flags)
388 {
389 struct si_context *sctx = CALLOC_STRUCT(si_context);
390 struct si_screen* sscreen = (struct si_screen *)screen;
391 struct radeon_winsys *ws = sscreen->ws;
392 int shader, i;
393 bool stop_exec_on_failure = (flags & PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET) != 0;
394
395 if (!sctx)
396 return NULL;
397
398 sctx->has_graphics = sscreen->info.chip_class == GFX6 ||
399 !(flags & PIPE_CONTEXT_COMPUTE_ONLY);
400
401 if (flags & PIPE_CONTEXT_DEBUG)
402 sscreen->record_llvm_ir = true; /* racy but not critical */
403
404 sctx->b.screen = screen; /* this must be set first */
405 sctx->b.priv = NULL;
406 sctx->b.destroy = si_destroy_context;
407 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
408 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
409
410 slab_create_child(&sctx->pool_transfers, &sscreen->pool_transfers);
411 slab_create_child(&sctx->pool_transfers_unsync, &sscreen->pool_transfers);
412
413 sctx->ws = sscreen->ws;
414 sctx->family = sscreen->info.family;
415 sctx->chip_class = sscreen->info.chip_class;
416
417 if (sctx->chip_class == GFX7 ||
418 sctx->chip_class == GFX8 ||
419 sctx->chip_class == GFX9) {
420 sctx->eop_bug_scratch = si_resource(
421 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
422 16 * sscreen->info.num_render_backends));
423 if (!sctx->eop_bug_scratch)
424 goto fail;
425 }
426
427 /* Initialize context allocators. */
428 sctx->allocator_zeroed_memory =
429 u_suballocator_create(&sctx->b, 128 * 1024,
430 0, PIPE_USAGE_DEFAULT,
431 SI_RESOURCE_FLAG_UNMAPPABLE |
432 SI_RESOURCE_FLAG_CLEAR, false);
433 if (!sctx->allocator_zeroed_memory)
434 goto fail;
435
436 sctx->b.stream_uploader = u_upload_create(&sctx->b, 1024 * 1024,
437 0, PIPE_USAGE_STREAM,
438 SI_RESOURCE_FLAG_READ_ONLY);
439 if (!sctx->b.stream_uploader)
440 goto fail;
441
442 sctx->cached_gtt_allocator = u_upload_create(&sctx->b, 16 * 1024,
443 0, PIPE_USAGE_STAGING, 0);
444 if (!sctx->cached_gtt_allocator)
445 goto fail;
446
447 sctx->ctx = sctx->ws->ctx_create(sctx->ws);
448 if (!sctx->ctx)
449 goto fail;
450
451 if (sscreen->info.num_sdma_rings && !(sscreen->debug_flags & DBG(NO_ASYNC_DMA))) {
452 sctx->dma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA,
453 (void*)si_flush_dma_cs,
454 sctx, stop_exec_on_failure);
455 }
456
457 bool use_sdma_upload = sscreen->info.has_dedicated_vram && sctx->dma_cs;
458 sctx->b.const_uploader = u_upload_create(&sctx->b, 256 * 1024,
459 0, PIPE_USAGE_DEFAULT,
460 SI_RESOURCE_FLAG_32BIT |
461 (use_sdma_upload ?
462 SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA : 0));
463 if (!sctx->b.const_uploader)
464 goto fail;
465
466 if (use_sdma_upload)
467 u_upload_enable_flush_explicit(sctx->b.const_uploader);
468
469 sctx->gfx_cs = ws->cs_create(sctx->ctx,
470 sctx->has_graphics ? RING_GFX : RING_COMPUTE,
471 (void*)si_flush_gfx_cs, sctx, stop_exec_on_failure);
472
473 /* Border colors. */
474 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
475 sizeof(*sctx->border_color_table));
476 if (!sctx->border_color_table)
477 goto fail;
478
479 sctx->border_color_buffer = si_resource(
480 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
481 SI_MAX_BORDER_COLORS *
482 sizeof(*sctx->border_color_table)));
483 if (!sctx->border_color_buffer)
484 goto fail;
485
486 sctx->border_color_map =
487 ws->buffer_map(sctx->border_color_buffer->buf,
488 NULL, PIPE_TRANSFER_WRITE);
489 if (!sctx->border_color_map)
490 goto fail;
491
492 sctx->ngg = sctx->chip_class >= GFX10;
493
494 /* Initialize context functions used by graphics and compute. */
495 if (sctx->chip_class >= GFX10)
496 sctx->emit_cache_flush = gfx10_emit_cache_flush;
497 else
498 sctx->emit_cache_flush = si_emit_cache_flush;
499
500 sctx->b.emit_string_marker = si_emit_string_marker;
501 sctx->b.set_debug_callback = si_set_debug_callback;
502 sctx->b.set_log_context = si_set_log_context;
503 sctx->b.set_context_param = si_set_context_param;
504 sctx->b.get_device_reset_status = si_get_reset_status;
505 sctx->b.set_device_reset_callback = si_set_device_reset_callback;
506
507 si_init_all_descriptors(sctx);
508 si_init_buffer_functions(sctx);
509 si_init_clear_functions(sctx);
510 si_init_blit_functions(sctx);
511 si_init_compute_functions(sctx);
512 si_init_compute_blit_functions(sctx);
513 si_init_debug_functions(sctx);
514 si_init_fence_functions(sctx);
515 si_init_query_functions(sctx);
516 si_init_state_compute_functions(sctx);
517
518 /* Initialize graphics-only context functions. */
519 if (sctx->has_graphics) {
520 si_init_context_texture_functions(sctx);
521 if (sctx->chip_class >= GFX10)
522 gfx10_init_query(sctx);
523 si_init_msaa_functions(sctx);
524 si_init_shader_functions(sctx);
525 si_init_state_functions(sctx);
526 si_init_streamout_functions(sctx);
527 si_init_viewport_functions(sctx);
528
529 sctx->blitter = util_blitter_create(&sctx->b);
530 if (sctx->blitter == NULL)
531 goto fail;
532 sctx->blitter->skip_viewport_restore = true;
533
534 si_init_draw_functions(sctx);
535 si_initialize_prim_discard_tunables(sctx);
536 }
537
538 /* Initialize SDMA functions. */
539 if (sctx->chip_class >= GFX7)
540 cik_init_sdma_functions(sctx);
541 else
542 si_init_dma_functions(sctx);
543
544 if (sscreen->debug_flags & DBG(FORCE_DMA))
545 sctx->b.resource_copy_region = sctx->dma_copy;
546
547 sctx->sample_mask = 0xffff;
548
549 /* Initialize multimedia functions. */
550 if (sscreen->info.has_hw_decode) {
551 sctx->b.create_video_codec = si_uvd_create_decoder;
552 sctx->b.create_video_buffer = si_video_buffer_create;
553 } else {
554 sctx->b.create_video_codec = vl_create_decoder;
555 sctx->b.create_video_buffer = vl_video_buffer_create;
556 }
557
558 if (sctx->chip_class >= GFX9) {
559 sctx->wait_mem_scratch = si_resource(
560 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 8));
561 if (!sctx->wait_mem_scratch)
562 goto fail;
563
564 /* Initialize the memory. */
565 si_cp_write_data(sctx, sctx->wait_mem_scratch, 0, 4,
566 V_370_MEM, V_370_ME, &sctx->wait_mem_number);
567 }
568
569 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
570 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
571 if (sctx->chip_class == GFX7) {
572 sctx->null_const_buf.buffer =
573 pipe_aligned_buffer_create(screen,
574 SI_RESOURCE_FLAG_32BIT,
575 PIPE_USAGE_DEFAULT, 16,
576 sctx->screen->info.tcc_cache_line_size);
577 if (!sctx->null_const_buf.buffer)
578 goto fail;
579 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
580
581 unsigned start_shader = sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE;
582 for (shader = start_shader; shader < SI_NUM_SHADERS; shader++) {
583 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
584 sctx->b.set_constant_buffer(&sctx->b, shader, i,
585 &sctx->null_const_buf);
586 }
587 }
588
589 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
590 &sctx->null_const_buf);
591 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
592 &sctx->null_const_buf);
593 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
594 &sctx->null_const_buf);
595 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
596 &sctx->null_const_buf);
597 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
598 &sctx->null_const_buf);
599 }
600
601 uint64_t max_threads_per_block;
602 screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
603 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
604 &max_threads_per_block);
605
606 /* The maximum number of scratch waves. Scratch space isn't divided
607 * evenly between CUs. The number is only a function of the number of CUs.
608 * We can decrease the constant to decrease the scratch buffer size.
609 *
610 * sctx->scratch_waves must be >= the maximum posible size of
611 * 1 threadgroup, so that the hw doesn't hang from being unable
612 * to start any.
613 *
614 * The recommended value is 4 per CU at most. Higher numbers don't
615 * bring much benefit, but they still occupy chip resources (think
616 * async compute). I've seen ~2% performance difference between 4 and 32.
617 */
618 sctx->scratch_waves = MAX2(32 * sscreen->info.num_good_compute_units,
619 max_threads_per_block / 64);
620
621 si_init_compiler(sscreen, &sctx->compiler);
622
623 /* Bindless handles. */
624 sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
625 _mesa_key_pointer_equal);
626 sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
627 _mesa_key_pointer_equal);
628
629 util_dynarray_init(&sctx->resident_tex_handles, NULL);
630 util_dynarray_init(&sctx->resident_img_handles, NULL);
631 util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
632 util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
633 util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
634
635 sctx->sample_pos_buffer =
636 pipe_buffer_create(sctx->b.screen, 0, PIPE_USAGE_DEFAULT,
637 sizeof(sctx->sample_positions));
638 pipe_buffer_write(&sctx->b, sctx->sample_pos_buffer, 0,
639 sizeof(sctx->sample_positions), &sctx->sample_positions);
640
641 /* this must be last */
642 si_begin_new_gfx_cs(sctx);
643
644 if (sctx->chip_class == GFX7) {
645 /* Clear the NULL constant buffer, because loads should return zeros.
646 * Note that this forces CP DMA to be used, because clover deadlocks
647 * for some reason when the compute codepath is used.
648 */
649 uint32_t clear_value = 0;
650 si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0,
651 sctx->null_const_buf.buffer->width0,
652 &clear_value, 4, SI_COHERENCY_SHADER, true);
653 }
654 return &sctx->b;
655 fail:
656 fprintf(stderr, "radeonsi: Failed to create a context.\n");
657 si_destroy_context(&sctx->b);
658 return NULL;
659 }
660
661 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
662 void *priv, unsigned flags)
663 {
664 struct si_screen *sscreen = (struct si_screen *)screen;
665 struct pipe_context *ctx;
666
667 if (sscreen->debug_flags & DBG(CHECK_VM))
668 flags |= PIPE_CONTEXT_DEBUG;
669
670 ctx = si_create_context(screen, flags);
671
672 if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
673 return ctx;
674
675 /* Clover (compute-only) is unsupported. */
676 if (flags & PIPE_CONTEXT_COMPUTE_ONLY)
677 return ctx;
678
679 /* When shaders are logged to stderr, asynchronous compilation is
680 * disabled too. */
681 if (sscreen->debug_flags & DBG_ALL_SHADERS)
682 return ctx;
683
684 /* Use asynchronous flushes only on amdgpu, since the radeon
685 * implementation for fence_server_sync is incomplete. */
686 return threaded_context_create(ctx, &sscreen->pool_transfers,
687 si_replace_buffer_storage,
688 sscreen->info.is_amdgpu ? si_create_fence : NULL,
689 &((struct si_context*)ctx)->tc);
690 }
691
692 /*
693 * pipe_screen
694 */
695 static void si_destroy_screen(struct pipe_screen* pscreen)
696 {
697 struct si_screen *sscreen = (struct si_screen *)pscreen;
698 struct si_shader_part *parts[] = {
699 sscreen->vs_prologs,
700 sscreen->tcs_epilogs,
701 sscreen->gs_prologs,
702 sscreen->ps_prologs,
703 sscreen->ps_epilogs
704 };
705 unsigned i;
706
707 if (!sscreen->ws->unref(sscreen->ws))
708 return;
709
710 mtx_destroy(&sscreen->aux_context_lock);
711
712 struct u_log_context *aux_log = ((struct si_context *)sscreen->aux_context)->log;
713 if (aux_log) {
714 sscreen->aux_context->set_log_context(sscreen->aux_context, NULL);
715 u_log_context_destroy(aux_log);
716 FREE(aux_log);
717 }
718
719 sscreen->aux_context->destroy(sscreen->aux_context);
720
721 util_queue_destroy(&sscreen->shader_compiler_queue);
722 util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
723
724 for (i = 0; i < ARRAY_SIZE(sscreen->compiler); i++)
725 si_destroy_compiler(&sscreen->compiler[i]);
726
727 for (i = 0; i < ARRAY_SIZE(sscreen->compiler_lowp); i++)
728 si_destroy_compiler(&sscreen->compiler_lowp[i]);
729
730 /* Free shader parts. */
731 for (i = 0; i < ARRAY_SIZE(parts); i++) {
732 while (parts[i]) {
733 struct si_shader_part *part = parts[i];
734
735 parts[i] = part->next;
736 si_shader_binary_clean(&part->binary);
737 FREE(part);
738 }
739 }
740 mtx_destroy(&sscreen->shader_parts_mutex);
741 si_destroy_shader_cache(sscreen);
742
743 si_destroy_perfcounters(sscreen);
744 si_gpu_load_kill_thread(sscreen);
745
746 mtx_destroy(&sscreen->gpu_load_mutex);
747
748 slab_destroy_parent(&sscreen->pool_transfers);
749
750 disk_cache_destroy(sscreen->disk_shader_cache);
751 sscreen->ws->destroy(sscreen->ws);
752 FREE(sscreen);
753 }
754
755 static void si_init_gs_info(struct si_screen *sscreen)
756 {
757 sscreen->gs_table_depth = ac_get_gs_table_depth(sscreen->info.chip_class,
758 sscreen->info.family);
759 }
760
761 static void si_test_vmfault(struct si_screen *sscreen)
762 {
763 struct pipe_context *ctx = sscreen->aux_context;
764 struct si_context *sctx = (struct si_context *)ctx;
765 struct pipe_resource *buf =
766 pipe_buffer_create_const0(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 64);
767
768 if (!buf) {
769 puts("Buffer allocation failed.");
770 exit(1);
771 }
772
773 si_resource(buf)->gpu_address = 0; /* cause a VM fault */
774
775 if (sscreen->debug_flags & DBG(TEST_VMFAULT_CP)) {
776 si_cp_dma_copy_buffer(sctx, buf, buf, 0, 4, 4, 0,
777 SI_COHERENCY_NONE, L2_BYPASS);
778 ctx->flush(ctx, NULL, 0);
779 puts("VM fault test: CP - done.");
780 }
781 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SDMA)) {
782 si_sdma_clear_buffer(sctx, buf, 0, 4, 0);
783 ctx->flush(ctx, NULL, 0);
784 puts("VM fault test: SDMA - done.");
785 }
786 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SHADER)) {
787 util_test_constant_buffer(ctx, buf);
788 puts("VM fault test: Shader - done.");
789 }
790 exit(0);
791 }
792
793 static void si_test_gds_memory_management(struct si_context *sctx,
794 unsigned alloc_size, unsigned alignment,
795 enum radeon_bo_domain domain)
796 {
797 struct radeon_winsys *ws = sctx->ws;
798 struct radeon_cmdbuf *cs[8];
799 struct pb_buffer *gds_bo[ARRAY_SIZE(cs)];
800
801 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
802 cs[i] = ws->cs_create(sctx->ctx, RING_COMPUTE,
803 NULL, NULL, false);
804 gds_bo[i] = ws->buffer_create(ws, alloc_size, alignment, domain, 0);
805 assert(gds_bo[i]);
806 }
807
808 for (unsigned iterations = 0; iterations < 20000; iterations++) {
809 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
810 /* This clears GDS with CP DMA.
811 *
812 * We don't care if GDS is present. Just add some packet
813 * to make the GPU busy for a moment.
814 */
815 si_cp_dma_clear_buffer(sctx, cs[i], NULL, 0, alloc_size, 0,
816 SI_CPDMA_SKIP_BO_LIST_UPDATE |
817 SI_CPDMA_SKIP_CHECK_CS_SPACE |
818 SI_CPDMA_SKIP_GFX_SYNC, 0, 0);
819
820 ws->cs_add_buffer(cs[i], gds_bo[i], domain,
821 RADEON_USAGE_READWRITE, 0);
822 ws->cs_flush(cs[i], PIPE_FLUSH_ASYNC, NULL);
823 }
824 }
825 exit(0);
826 }
827
828 static void si_disk_cache_create(struct si_screen *sscreen)
829 {
830 /* Don't use the cache if shader dumping is enabled. */
831 if (sscreen->debug_flags & DBG_ALL_SHADERS)
832 return;
833
834 struct mesa_sha1 ctx;
835 unsigned char sha1[20];
836 char cache_id[20 * 2 + 1];
837
838 _mesa_sha1_init(&ctx);
839
840 if (!disk_cache_get_function_identifier(si_disk_cache_create, &ctx) ||
841 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo,
842 &ctx))
843 return;
844
845 _mesa_sha1_final(&ctx, sha1);
846 disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
847
848 /* These flags affect shader compilation. */
849 #define ALL_FLAGS (DBG(FS_CORRECT_DERIVS_AFTER_KILL) | \
850 DBG(SI_SCHED) | \
851 DBG(GISEL) | \
852 DBG(UNSAFE_MATH))
853 uint64_t shader_debug_flags = sscreen->debug_flags & ALL_FLAGS;
854
855 if (sscreen->options.enable_nir) {
856 STATIC_ASSERT((ALL_FLAGS & (1u << 31)) == 0);
857 shader_debug_flags |= 1u << 31;
858 }
859
860 /* Add the high bits of 32-bit addresses, which affects
861 * how 32-bit addresses are expanded to 64 bits.
862 */
863 STATIC_ASSERT(ALL_FLAGS <= UINT_MAX);
864 assert((int16_t)sscreen->info.address32_hi == (int32_t)sscreen->info.address32_hi);
865 shader_debug_flags |= (uint64_t)(sscreen->info.address32_hi & 0xffff) << 32;
866
867 sscreen->disk_shader_cache =
868 disk_cache_create(sscreen->info.name,
869 cache_id,
870 shader_debug_flags);
871 }
872
873 static void si_set_max_shader_compiler_threads(struct pipe_screen *screen,
874 unsigned max_threads)
875 {
876 struct si_screen *sscreen = (struct si_screen *)screen;
877
878 /* This function doesn't allow a greater number of threads than
879 * the queue had at its creation. */
880 util_queue_adjust_num_threads(&sscreen->shader_compiler_queue,
881 max_threads);
882 /* Don't change the number of threads on the low priority queue. */
883 }
884
885 static bool si_is_parallel_shader_compilation_finished(struct pipe_screen *screen,
886 void *shader,
887 enum pipe_shader_type shader_type)
888 {
889 struct si_shader_selector *sel = (struct si_shader_selector *)shader;
890
891 return util_queue_fence_is_signalled(&sel->ready);
892 }
893
894 static struct pipe_screen *
895 radeonsi_screen_create_impl(struct radeon_winsys *ws,
896 const struct pipe_screen_config *config)
897 {
898 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
899 unsigned hw_threads, num_comp_hi_threads, num_comp_lo_threads, i;
900
901 if (!sscreen) {
902 return NULL;
903 }
904
905 sscreen->ws = ws;
906 ws->query_info(ws, &sscreen->info);
907
908 if (sscreen->info.chip_class == GFX10 && HAVE_LLVM < 0x0900) {
909 fprintf(stderr, "radeonsi: Navi family support requires LLVM 9 or higher\n");
910 FREE(sscreen);
911 return NULL;
912 }
913
914 if (sscreen->info.chip_class >= GFX9) {
915 sscreen->se_tile_repeat = 32 * sscreen->info.max_se;
916 } else {
917 ac_get_raster_config(&sscreen->info,
918 &sscreen->pa_sc_raster_config,
919 &sscreen->pa_sc_raster_config_1,
920 &sscreen->se_tile_repeat);
921 }
922
923 sscreen->debug_flags = debug_get_flags_option("R600_DEBUG",
924 debug_options, 0);
925 sscreen->debug_flags |= debug_get_flags_option("AMD_DEBUG",
926 debug_options, 0);
927
928 /* Set functions first. */
929 sscreen->b.context_create = si_pipe_create_context;
930 sscreen->b.destroy = si_destroy_screen;
931 sscreen->b.set_max_shader_compiler_threads =
932 si_set_max_shader_compiler_threads;
933 sscreen->b.is_parallel_shader_compilation_finished =
934 si_is_parallel_shader_compilation_finished;
935
936 si_init_screen_get_functions(sscreen);
937 si_init_screen_buffer_functions(sscreen);
938 si_init_screen_fence_functions(sscreen);
939 si_init_screen_state_functions(sscreen);
940 si_init_screen_texture_functions(sscreen);
941 si_init_screen_query_functions(sscreen);
942
943 /* Set these flags in debug_flags early, so that the shader cache takes
944 * them into account.
945 */
946 if (driQueryOptionb(config->options,
947 "glsl_correct_derivatives_after_discard"))
948 sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
949 if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
950 sscreen->debug_flags |= DBG(SI_SCHED);
951
952 if (sscreen->debug_flags & DBG(INFO))
953 ac_print_gpu_info(&sscreen->info);
954
955 slab_create_parent(&sscreen->pool_transfers,
956 sizeof(struct si_transfer), 64);
957
958 sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
959 if (sscreen->force_aniso == -1) {
960 sscreen->force_aniso = MIN2(16, debug_get_num_option("AMD_TEX_ANISO", -1));
961 }
962
963 if (sscreen->force_aniso >= 0) {
964 printf("radeonsi: Forcing anisotropy filter to %ix\n",
965 /* round down to a power of two */
966 1 << util_logbase2(sscreen->force_aniso));
967 }
968
969 (void) mtx_init(&sscreen->aux_context_lock, mtx_plain);
970 (void) mtx_init(&sscreen->gpu_load_mutex, mtx_plain);
971
972 si_init_gs_info(sscreen);
973 if (!si_init_shader_cache(sscreen)) {
974 FREE(sscreen);
975 return NULL;
976 }
977
978 si_disk_cache_create(sscreen);
979
980 /* Determine the number of shader compiler threads. */
981 hw_threads = sysconf(_SC_NPROCESSORS_ONLN);
982
983 if (hw_threads >= 12) {
984 num_comp_hi_threads = hw_threads * 3 / 4;
985 num_comp_lo_threads = hw_threads / 3;
986 } else if (hw_threads >= 6) {
987 num_comp_hi_threads = hw_threads - 2;
988 num_comp_lo_threads = hw_threads / 2;
989 } else if (hw_threads >= 2) {
990 num_comp_hi_threads = hw_threads - 1;
991 num_comp_lo_threads = hw_threads / 2;
992 } else {
993 num_comp_hi_threads = 1;
994 num_comp_lo_threads = 1;
995 }
996
997 num_comp_hi_threads = MIN2(num_comp_hi_threads,
998 ARRAY_SIZE(sscreen->compiler));
999 num_comp_lo_threads = MIN2(num_comp_lo_threads,
1000 ARRAY_SIZE(sscreen->compiler_lowp));
1001
1002 if (!util_queue_init(&sscreen->shader_compiler_queue, "sh",
1003 64, num_comp_hi_threads,
1004 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1005 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY)) {
1006 si_destroy_shader_cache(sscreen);
1007 FREE(sscreen);
1008 return NULL;
1009 }
1010
1011 if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
1012 "shlo",
1013 64, num_comp_lo_threads,
1014 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1015 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY |
1016 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
1017 si_destroy_shader_cache(sscreen);
1018 FREE(sscreen);
1019 return NULL;
1020 }
1021
1022 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1023 si_init_perfcounters(sscreen);
1024
1025 /* Determine tessellation ring info. */
1026 bool double_offchip_buffers = sscreen->info.chip_class >= GFX7 &&
1027 sscreen->info.family != CHIP_CARRIZO &&
1028 sscreen->info.family != CHIP_STONEY;
1029 /* This must be one less than the maximum number due to a hw limitation.
1030 * Various hardware bugs need this.
1031 */
1032 unsigned max_offchip_buffers_per_se;
1033
1034 if (sscreen->info.chip_class >= GFX10)
1035 max_offchip_buffers_per_se = 256;
1036 /* Only certain chips can use the maximum value. */
1037 else if (sscreen->info.family == CHIP_VEGA12 ||
1038 sscreen->info.family == CHIP_VEGA20)
1039 max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1040 else
1041 max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
1042
1043 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1044 sscreen->info.max_se;
1045 unsigned offchip_granularity;
1046
1047 /* Hawaii has a bug with offchip buffers > 256 that can be worked
1048 * around by setting 4K granularity.
1049 */
1050 if (sscreen->info.family == CHIP_HAWAII) {
1051 sscreen->tess_offchip_block_dw_size = 4096;
1052 offchip_granularity = V_03093C_X_4K_DWORDS;
1053 } else {
1054 sscreen->tess_offchip_block_dw_size = 8192;
1055 offchip_granularity = V_03093C_X_8K_DWORDS;
1056 }
1057
1058 sscreen->tess_factor_ring_size = 32768 * sscreen->info.max_se;
1059 assert(((sscreen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
1060 sscreen->tess_offchip_ring_size = max_offchip_buffers *
1061 sscreen->tess_offchip_block_dw_size * 4;
1062
1063 if (sscreen->info.chip_class >= GFX7) {
1064 if (sscreen->info.chip_class >= GFX8)
1065 --max_offchip_buffers;
1066 sscreen->vgt_hs_offchip_param =
1067 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1068 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1069 } else {
1070 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
1071 sscreen->vgt_hs_offchip_param =
1072 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1073 }
1074
1075 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
1076 * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
1077 * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel. */
1078 sscreen->has_clear_state = sscreen->info.chip_class >= GFX7 &&
1079 sscreen->info.chip_class <= GFX9 &&
1080 sscreen->info.is_amdgpu;
1081
1082 sscreen->has_distributed_tess =
1083 sscreen->info.chip_class >= GFX8 &&
1084 sscreen->info.max_se >= 2;
1085
1086 sscreen->has_draw_indirect_multi =
1087 (sscreen->info.family >= CHIP_POLARIS10) ||
1088 (sscreen->info.chip_class == GFX8 &&
1089 sscreen->info.pfp_fw_version >= 121 &&
1090 sscreen->info.me_fw_version >= 87) ||
1091 (sscreen->info.chip_class == GFX7 &&
1092 sscreen->info.pfp_fw_version >= 211 &&
1093 sscreen->info.me_fw_version >= 173) ||
1094 (sscreen->info.chip_class == GFX6 &&
1095 sscreen->info.pfp_fw_version >= 79 &&
1096 sscreen->info.me_fw_version >= 142);
1097
1098 sscreen->has_out_of_order_rast = sscreen->info.chip_class >= GFX8 &&
1099 sscreen->info.max_se >= 2 &&
1100 !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER));
1101 sscreen->assume_no_z_fights =
1102 driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
1103 sscreen->commutative_blend_add =
1104 driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
1105
1106 {
1107 #define OPT_BOOL(name, dflt, description) \
1108 sscreen->options.name = \
1109 driQueryOptionb(config->options, "radeonsi_"#name);
1110 #include "si_debug_options.h"
1111 }
1112
1113 sscreen->has_gfx9_scissor_bug = sscreen->info.family == CHIP_VEGA10 ||
1114 sscreen->info.family == CHIP_RAVEN;
1115 sscreen->has_msaa_sample_loc_bug = (sscreen->info.family >= CHIP_POLARIS10 &&
1116 sscreen->info.family <= CHIP_POLARIS12) ||
1117 sscreen->info.family == CHIP_VEGA10 ||
1118 sscreen->info.family == CHIP_RAVEN;
1119 sscreen->has_ls_vgpr_init_bug = sscreen->info.family == CHIP_VEGA10 ||
1120 sscreen->info.family == CHIP_RAVEN;
1121 sscreen->has_dcc_constant_encode = sscreen->info.family == CHIP_RAVEN2 ||
1122 sscreen->info.chip_class >= GFX10;
1123
1124 /* Only enable primitive binning on APUs by default. */
1125 if (sscreen->info.chip_class >= GFX10) {
1126 sscreen->dpbb_allowed = true;
1127 sscreen->dfsm_allowed = !sscreen->info.has_dedicated_vram;
1128 } else if (sscreen->info.chip_class == GFX9) {
1129 sscreen->dpbb_allowed = !sscreen->info.has_dedicated_vram;
1130 sscreen->dfsm_allowed = !sscreen->info.has_dedicated_vram;
1131 }
1132
1133 /* Process DPBB enable flags. */
1134 if (sscreen->debug_flags & DBG(DPBB)) {
1135 sscreen->dpbb_allowed = true;
1136 if (sscreen->debug_flags & DBG(DFSM))
1137 sscreen->dfsm_allowed = true;
1138 }
1139
1140 /* Process DPBB disable flags. */
1141 if (sscreen->debug_flags & DBG(NO_DPBB)) {
1142 sscreen->dpbb_allowed = false;
1143 sscreen->dfsm_allowed = false;
1144 } else if (sscreen->debug_flags & DBG(NO_DFSM)) {
1145 sscreen->dfsm_allowed = false;
1146 }
1147
1148 /* While it would be nice not to have this flag, we are constrained
1149 * by the reality that LLVM 9.0 has buggy VGPR indexing on GFX9.
1150 */
1151 sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class != GFX9;
1152
1153 /* Some chips have RB+ registers, but don't support RB+. Those must
1154 * always disable it.
1155 */
1156 if (sscreen->info.family == CHIP_STONEY ||
1157 sscreen->info.chip_class >= GFX9) {
1158 sscreen->has_rbplus = true;
1159
1160 sscreen->rbplus_allowed =
1161 !(sscreen->debug_flags & DBG(NO_RB_PLUS)) &&
1162 (sscreen->info.family == CHIP_STONEY ||
1163 sscreen->info.family == CHIP_VEGA12 ||
1164 sscreen->info.family == CHIP_RAVEN ||
1165 sscreen->info.family == CHIP_RAVEN2);
1166 }
1167
1168 sscreen->dcc_msaa_allowed =
1169 !(sscreen->debug_flags & DBG(NO_DCC_MSAA));
1170
1171 sscreen->cpdma_prefetch_writes_memory = sscreen->info.chip_class <= GFX8;
1172
1173 (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1174 sscreen->use_monolithic_shaders =
1175 (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
1176
1177 sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SCACHE |
1178 SI_CONTEXT_INV_VCACHE;
1179 if (sscreen->info.chip_class <= GFX8) {
1180 sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_L2;
1181 sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WB_L2;
1182 }
1183
1184 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1185 sscreen->debug_flags |= DBG_ALL_SHADERS;
1186
1187 /* Syntax:
1188 * EQAA=s,z,c
1189 * Example:
1190 * EQAA=8,4,2
1191
1192 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1193 * Constraints:
1194 * s >= z >= c (ignoring this only wastes memory)
1195 * s = [2..16]
1196 * z = [2..8]
1197 * c = [2..8]
1198 *
1199 * Only MSAA color and depth buffers are overriden.
1200 */
1201 if (sscreen->info.has_eqaa_surface_allocator) {
1202 const char *eqaa = debug_get_option("EQAA", NULL);
1203 unsigned s,z,f;
1204
1205 if (eqaa && sscanf(eqaa, "%u,%u,%u", &s, &z, &f) == 3 && s && z && f) {
1206 sscreen->eqaa_force_coverage_samples = s;
1207 sscreen->eqaa_force_z_samples = z;
1208 sscreen->eqaa_force_color_samples = f;
1209 }
1210 }
1211
1212 for (i = 0; i < num_comp_hi_threads; i++)
1213 si_init_compiler(sscreen, &sscreen->compiler[i]);
1214 for (i = 0; i < num_comp_lo_threads; i++)
1215 si_init_compiler(sscreen, &sscreen->compiler_lowp[i]);
1216
1217 sscreen->ge_wave_size = 64;
1218 sscreen->ps_wave_size = 64;
1219 sscreen->compute_wave_size = 64;
1220
1221 /* Create the auxiliary context. This must be done last. */
1222 sscreen->aux_context = si_create_context(
1223 &sscreen->b, sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0);
1224 if (sscreen->options.aux_debug) {
1225 struct u_log_context *log = CALLOC_STRUCT(u_log_context);
1226 u_log_context_init(log);
1227 sscreen->aux_context->set_log_context(sscreen->aux_context, log);
1228 }
1229
1230 if (sscreen->debug_flags & DBG(TEST_DMA))
1231 si_test_dma(sscreen);
1232
1233 if (sscreen->debug_flags & DBG(TEST_DMA_PERF)) {
1234 si_test_dma_perf(sscreen);
1235 }
1236
1237 if (sscreen->debug_flags & (DBG(TEST_VMFAULT_CP) |
1238 DBG(TEST_VMFAULT_SDMA) |
1239 DBG(TEST_VMFAULT_SHADER)))
1240 si_test_vmfault(sscreen);
1241
1242 if (sscreen->debug_flags & DBG(TEST_GDS))
1243 si_test_gds((struct si_context*)sscreen->aux_context);
1244
1245 if (sscreen->debug_flags & DBG(TEST_GDS_MM)) {
1246 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1247 32 * 1024, 4, RADEON_DOMAIN_GDS);
1248 }
1249 if (sscreen->debug_flags & DBG(TEST_GDS_OA_MM)) {
1250 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1251 4, 1, RADEON_DOMAIN_OA);
1252 }
1253
1254 return &sscreen->b;
1255 }
1256
1257 struct pipe_screen *radeonsi_screen_create(int fd, const struct pipe_screen_config *config)
1258 {
1259 drmVersionPtr version = drmGetVersion(fd);
1260 struct radeon_winsys *rw = NULL;
1261
1262 switch (version->version_major) {
1263 case 2:
1264 rw = radeon_drm_winsys_create(fd, config, radeonsi_screen_create_impl);
1265 break;
1266 case 3:
1267 rw = amdgpu_winsys_create(fd, config, radeonsi_screen_create_impl);
1268 break;
1269 }
1270
1271 drmFreeVersion(version);
1272 return rw ? rw->screen : NULL;
1273 }