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radeonsi: make sure that blend state != NULL and remove all NULL checking
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "si_pipe.h"
27 #include "si_public.h"
28 #include "si_shader_internal.h"
29 #include "si_compute.h"
30 #include "sid.h"
31
32 #include "ac_llvm_util.h"
33 #include "radeon/radeon_uvd.h"
34 #include "util/disk_cache.h"
35 #include "util/u_log.h"
36 #include "util/u_memory.h"
37 #include "util/u_suballoc.h"
38 #include "util/u_tests.h"
39 #include "util/u_upload_mgr.h"
40 #include "util/xmlconfig.h"
41 #include "vl/vl_decoder.h"
42 #include "driver_ddebug/dd_util.h"
43
44 #include "gallium/winsys/radeon/drm/radeon_drm_public.h"
45 #include "gallium/winsys/amdgpu/drm/amdgpu_public.h"
46 #include <xf86drm.h>
47
48 static const struct debug_named_value debug_options[] = {
49 /* Shader logging options: */
50 { "vs", DBG(VS), "Print vertex shaders" },
51 { "ps", DBG(PS), "Print pixel shaders" },
52 { "gs", DBG(GS), "Print geometry shaders" },
53 { "tcs", DBG(TCS), "Print tessellation control shaders" },
54 { "tes", DBG(TES), "Print tessellation evaluation shaders" },
55 { "cs", DBG(CS), "Print compute shaders" },
56 { "noir", DBG(NO_IR), "Don't print the LLVM IR"},
57 { "notgsi", DBG(NO_TGSI), "Don't print the TGSI"},
58 { "noasm", DBG(NO_ASM), "Don't print disassembled shaders"},
59 { "preoptir", DBG(PREOPT_IR), "Print the LLVM IR before initial optimizations" },
60
61 /* Shader compiler options the shader cache should be aware of: */
62 { "unsafemath", DBG(UNSAFE_MATH), "Enable unsafe math shader optimizations" },
63 { "sisched", DBG(SI_SCHED), "Enable LLVM SI Machine Instruction Scheduler." },
64 { "gisel", DBG(GISEL), "Enable LLVM global instruction selector." },
65 { "w32ge", DBG(W32_GE), "Use Wave32 for vertex, tessellation, and geometry shaders." },
66 { "w32ps", DBG(W32_PS), "Use Wave32 for pixel shaders." },
67 { "w32cs", DBG(W32_CS), "Use Wave32 for computes shaders." },
68 { "w64ge", DBG(W64_GE), "Use Wave64 for vertex, tessellation, and geometry shaders." },
69 { "w64ps", DBG(W64_PS), "Use Wave64 for pixel shaders." },
70 { "w64cs", DBG(W64_CS), "Use Wave64 for computes shaders." },
71
72 /* Shader compiler options (with no effect on the shader cache): */
73 { "checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR" },
74 { "mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand" },
75 { "nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants." },
76
77 /* Information logging options: */
78 { "info", DBG(INFO), "Print driver information" },
79 { "tex", DBG(TEX), "Print texture info" },
80 { "compute", DBG(COMPUTE), "Print compute info" },
81 { "vm", DBG(VM), "Print virtual addresses when creating resources" },
82
83 /* Driver options: */
84 { "forcedma", DBG(FORCE_DMA), "Use asynchronous DMA for all operations when possible." },
85 { "nodma", DBG(NO_ASYNC_DMA), "Disable asynchronous DMA" },
86 { "nowc", DBG(NO_WC), "Disable GTT write combining" },
87 { "check_vm", DBG(CHECK_VM), "Check VM faults and dump debug info." },
88 { "reserve_vmid", DBG(RESERVE_VMID), "Force VMID reservation per context." },
89 { "zerovram", DBG(ZERO_VRAM), "Clear VRAM allocations." },
90
91 /* 3D engine options: */
92 { "nogfx", DBG(NO_GFX), "Disable graphics. Only multimedia compute paths can be used." },
93 { "alwayspd", DBG(ALWAYS_PD), "Always enable the primitive discard compute shader." },
94 { "pd", DBG(PD), "Enable the primitive discard compute shader for large draw calls." },
95 { "nopd", DBG(NO_PD), "Disable the primitive discard compute shader." },
96 { "switch_on_eop", DBG(SWITCH_ON_EOP), "Program WD/IA to switch on end-of-packet." },
97 { "nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order rasterization" },
98 { "nodpbb", DBG(NO_DPBB), "Disable DPBB." },
99 { "nodfsm", DBG(NO_DFSM), "Disable DFSM." },
100 { "dpbb", DBG(DPBB), "Enable DPBB." },
101 { "dfsm", DBG(DFSM), "Enable DFSM." },
102 { "nohyperz", DBG(NO_HYPERZ), "Disable Hyper-Z" },
103 { "norbplus", DBG(NO_RB_PLUS), "Disable RB+." },
104 { "no2d", DBG(NO_2D_TILING), "Disable 2D tiling" },
105 { "notiling", DBG(NO_TILING), "Disable tiling" },
106 { "nodcc", DBG(NO_DCC), "Disable DCC." },
107 { "nodccclear", DBG(NO_DCC_CLEAR), "Disable DCC fast clear." },
108 { "nodccfb", DBG(NO_DCC_FB), "Disable separate DCC on the main framebuffer" },
109 { "nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA" },
110 { "nofmask", DBG(NO_FMASK), "Disable MSAA compression" },
111
112 /* Tests: */
113 { "testdma", DBG(TEST_DMA), "Invoke SDMA tests and exit." },
114 { "testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and exit." },
115 { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA), "Invoke a SDMA VM fault test and exit." },
116 { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM fault test and exit." },
117 { "testdmaperf", DBG(TEST_DMA_PERF), "Test DMA performance" },
118 { "testgds", DBG(TEST_GDS), "Test GDS." },
119 { "testgdsmm", DBG(TEST_GDS_MM), "Test GDS memory management." },
120 { "testgdsoamm", DBG(TEST_GDS_OA_MM), "Test GDS OA memory management." },
121
122 DEBUG_NAMED_VALUE_END /* must be last */
123 };
124
125 static void si_init_compiler(struct si_screen *sscreen,
126 struct ac_llvm_compiler *compiler)
127 {
128 /* Only create the less-optimizing version of the compiler on APUs
129 * predating Ryzen (Raven). */
130 bool create_low_opt_compiler = !sscreen->info.has_dedicated_vram &&
131 sscreen->info.chip_class <= GFX8;
132
133 enum ac_target_machine_options tm_options =
134 (sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
135 (sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL : 0) |
136 (sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
137 (sscreen->info.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
138 (!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0) |
139 (sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0) |
140 (create_low_opt_compiler ? AC_TM_CREATE_LOW_OPT : 0);
141
142 ac_init_llvm_once();
143 ac_init_llvm_compiler(compiler, sscreen->info.family, tm_options);
144 compiler->passes = ac_create_llvm_passes(compiler->tm);
145
146 if (compiler->tm_wave32)
147 compiler->passes_wave32 = ac_create_llvm_passes(compiler->tm_wave32);
148 if (compiler->low_opt_tm)
149 compiler->low_opt_passes = ac_create_llvm_passes(compiler->low_opt_tm);
150 }
151
152 static void si_destroy_compiler(struct ac_llvm_compiler *compiler)
153 {
154 ac_destroy_llvm_compiler(compiler);
155 }
156
157 /*
158 * pipe_context
159 */
160 static void si_destroy_context(struct pipe_context *context)
161 {
162 struct si_context *sctx = (struct si_context *)context;
163 int i;
164
165 util_queue_finish(&sctx->screen->shader_compiler_queue);
166 util_queue_finish(&sctx->screen->shader_compiler_queue_low_priority);
167
168 /* Unreference the framebuffer normally to disable related logic
169 * properly.
170 */
171 struct pipe_framebuffer_state fb = {};
172 if (context->set_framebuffer_state)
173 context->set_framebuffer_state(context, &fb);
174
175 si_release_all_descriptors(sctx);
176
177 if (sctx->chip_class >= GFX10)
178 gfx10_destroy_query(sctx);
179
180 pipe_resource_reference(&sctx->esgs_ring, NULL);
181 pipe_resource_reference(&sctx->gsvs_ring, NULL);
182 pipe_resource_reference(&sctx->tess_rings, NULL);
183 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
184 pipe_resource_reference(&sctx->sample_pos_buffer, NULL);
185 si_resource_reference(&sctx->border_color_buffer, NULL);
186 free(sctx->border_color_table);
187 si_resource_reference(&sctx->scratch_buffer, NULL);
188 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
189 si_resource_reference(&sctx->wait_mem_scratch, NULL);
190
191 si_pm4_free_state(sctx, sctx->init_config, ~0);
192 if (sctx->init_config_gs_rings)
193 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
194 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
195 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
196
197 if (sctx->fixed_func_tcs_shader.cso)
198 sctx->b.delete_tcs_state(&sctx->b, sctx->fixed_func_tcs_shader.cso);
199 if (sctx->custom_dsa_flush)
200 sctx->b.delete_depth_stencil_alpha_state(&sctx->b, sctx->custom_dsa_flush);
201 if (sctx->custom_blend_resolve)
202 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_resolve);
203 if (sctx->custom_blend_fmask_decompress)
204 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_fmask_decompress);
205 if (sctx->custom_blend_eliminate_fastclear)
206 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_eliminate_fastclear);
207 if (sctx->custom_blend_dcc_decompress)
208 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_dcc_decompress);
209 if (sctx->vs_blit_pos)
210 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos);
211 if (sctx->vs_blit_pos_layered)
212 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos_layered);
213 if (sctx->vs_blit_color)
214 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color);
215 if (sctx->vs_blit_color_layered)
216 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color_layered);
217 if (sctx->vs_blit_texcoord)
218 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_texcoord);
219 if (sctx->cs_clear_buffer)
220 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_buffer);
221 if (sctx->cs_copy_buffer)
222 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_buffer);
223 if (sctx->cs_copy_image)
224 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image);
225 if (sctx->cs_copy_image_1d_array)
226 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image_1d_array);
227 if (sctx->cs_clear_render_target)
228 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target);
229 if (sctx->cs_clear_render_target_1d_array)
230 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target_1d_array);
231 if (sctx->cs_dcc_retile)
232 sctx->b.delete_compute_state(&sctx->b, sctx->cs_dcc_retile);
233
234 if (sctx->blitter)
235 util_blitter_destroy(sctx->blitter);
236
237 /* Release DCC stats. */
238 for (int i = 0; i < ARRAY_SIZE(sctx->dcc_stats); i++) {
239 assert(!sctx->dcc_stats[i].query_active);
240
241 for (int j = 0; j < ARRAY_SIZE(sctx->dcc_stats[i].ps_stats); j++)
242 if (sctx->dcc_stats[i].ps_stats[j])
243 sctx->b.destroy_query(&sctx->b,
244 sctx->dcc_stats[i].ps_stats[j]);
245
246 si_texture_reference(&sctx->dcc_stats[i].tex, NULL);
247 }
248
249 if (sctx->query_result_shader)
250 sctx->b.delete_compute_state(&sctx->b, sctx->query_result_shader);
251 if (sctx->sh_query_result_shader)
252 sctx->b.delete_compute_state(&sctx->b, sctx->sh_query_result_shader);
253
254 if (sctx->gfx_cs)
255 sctx->ws->cs_destroy(sctx->gfx_cs);
256 if (sctx->dma_cs)
257 sctx->ws->cs_destroy(sctx->dma_cs);
258 if (sctx->ctx)
259 sctx->ws->ctx_destroy(sctx->ctx);
260
261 if (sctx->b.stream_uploader)
262 u_upload_destroy(sctx->b.stream_uploader);
263 if (sctx->b.const_uploader)
264 u_upload_destroy(sctx->b.const_uploader);
265 if (sctx->cached_gtt_allocator)
266 u_upload_destroy(sctx->cached_gtt_allocator);
267
268 slab_destroy_child(&sctx->pool_transfers);
269 slab_destroy_child(&sctx->pool_transfers_unsync);
270
271 if (sctx->allocator_zeroed_memory)
272 u_suballocator_destroy(sctx->allocator_zeroed_memory);
273
274 sctx->ws->fence_reference(&sctx->last_gfx_fence, NULL);
275 sctx->ws->fence_reference(&sctx->last_sdma_fence, NULL);
276 sctx->ws->fence_reference(&sctx->last_ib_barrier_fence, NULL);
277 si_resource_reference(&sctx->eop_bug_scratch, NULL);
278 si_resource_reference(&sctx->index_ring, NULL);
279 si_resource_reference(&sctx->barrier_buf, NULL);
280 si_resource_reference(&sctx->last_ib_barrier_buf, NULL);
281 pb_reference(&sctx->gds, NULL);
282 pb_reference(&sctx->gds_oa, NULL);
283
284 si_destroy_compiler(&sctx->compiler);
285
286 si_saved_cs_reference(&sctx->current_saved_cs, NULL);
287
288 _mesa_hash_table_destroy(sctx->tex_handles, NULL);
289 _mesa_hash_table_destroy(sctx->img_handles, NULL);
290
291 util_dynarray_fini(&sctx->resident_tex_handles);
292 util_dynarray_fini(&sctx->resident_img_handles);
293 util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
294 util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
295 util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
296 si_unref_sdma_uploads(sctx);
297 FREE(sctx);
298 }
299
300 static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx)
301 {
302 struct si_context *sctx = (struct si_context *)ctx;
303
304 return sctx->ws->ctx_query_reset_status(sctx->ctx);
305 }
306
307 static void si_set_device_reset_callback(struct pipe_context *ctx,
308 const struct pipe_device_reset_callback *cb)
309 {
310 struct si_context *sctx = (struct si_context *)ctx;
311
312 if (cb)
313 sctx->device_reset_callback = *cb;
314 else
315 memset(&sctx->device_reset_callback, 0,
316 sizeof(sctx->device_reset_callback));
317 }
318
319 bool si_check_device_reset(struct si_context *sctx)
320 {
321 enum pipe_reset_status status;
322
323 if (!sctx->device_reset_callback.reset)
324 return false;
325
326 status = sctx->ws->ctx_query_reset_status(sctx->ctx);
327 if (status == PIPE_NO_RESET)
328 return false;
329
330 sctx->device_reset_callback.reset(sctx->device_reset_callback.data, status);
331 return true;
332 }
333
334 /* Apitrace profiling:
335 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
336 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
337 * and remember its number.
338 * 3) In Mesa, enable queries and performance counters around that draw
339 * call and print the results.
340 * 4) glretrace --benchmark --markers ..
341 */
342 static void si_emit_string_marker(struct pipe_context *ctx,
343 const char *string, int len)
344 {
345 struct si_context *sctx = (struct si_context *)ctx;
346
347 dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
348
349 if (sctx->log)
350 u_log_printf(sctx->log, "\nString marker: %*s\n", len, string);
351 }
352
353 static void si_set_debug_callback(struct pipe_context *ctx,
354 const struct pipe_debug_callback *cb)
355 {
356 struct si_context *sctx = (struct si_context *)ctx;
357 struct si_screen *screen = sctx->screen;
358
359 util_queue_finish(&screen->shader_compiler_queue);
360 util_queue_finish(&screen->shader_compiler_queue_low_priority);
361
362 if (cb)
363 sctx->debug = *cb;
364 else
365 memset(&sctx->debug, 0, sizeof(sctx->debug));
366 }
367
368 static void si_set_log_context(struct pipe_context *ctx,
369 struct u_log_context *log)
370 {
371 struct si_context *sctx = (struct si_context *)ctx;
372 sctx->log = log;
373
374 if (log)
375 u_log_add_auto_logger(log, si_auto_log_cs, sctx);
376 }
377
378 static void si_set_context_param(struct pipe_context *ctx,
379 enum pipe_context_param param,
380 unsigned value)
381 {
382 struct radeon_winsys *ws = ((struct si_context *)ctx)->ws;
383
384 switch (param) {
385 case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE:
386 ws->pin_threads_to_L3_cache(ws, value);
387 break;
388 default:;
389 }
390 }
391
392 static struct pipe_context *si_create_context(struct pipe_screen *screen,
393 unsigned flags)
394 {
395 struct si_screen* sscreen = (struct si_screen *)screen;
396
397 /* Don't create a context if it's not compute-only and hw is compute-only. */
398 if (!sscreen->info.has_graphics &&
399 !(flags & PIPE_CONTEXT_COMPUTE_ONLY))
400 return NULL;
401
402 struct si_context *sctx = CALLOC_STRUCT(si_context);
403 struct radeon_winsys *ws = sscreen->ws;
404 int shader, i;
405 bool stop_exec_on_failure = (flags & PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET) != 0;
406
407 if (!sctx)
408 return NULL;
409
410 sctx->has_graphics = sscreen->info.chip_class == GFX6 ||
411 !(flags & PIPE_CONTEXT_COMPUTE_ONLY);
412
413 if (flags & PIPE_CONTEXT_DEBUG)
414 sscreen->record_llvm_ir = true; /* racy but not critical */
415
416 sctx->b.screen = screen; /* this must be set first */
417 sctx->b.priv = NULL;
418 sctx->b.destroy = si_destroy_context;
419 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
420 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
421
422 slab_create_child(&sctx->pool_transfers, &sscreen->pool_transfers);
423 slab_create_child(&sctx->pool_transfers_unsync, &sscreen->pool_transfers);
424
425 sctx->ws = sscreen->ws;
426 sctx->family = sscreen->info.family;
427 sctx->chip_class = sscreen->info.chip_class;
428
429 if (sctx->chip_class == GFX7 ||
430 sctx->chip_class == GFX8 ||
431 sctx->chip_class == GFX9) {
432 sctx->eop_bug_scratch = si_resource(
433 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
434 16 * sscreen->info.num_render_backends));
435 if (!sctx->eop_bug_scratch)
436 goto fail;
437 }
438
439 /* Initialize context allocators. */
440 sctx->allocator_zeroed_memory =
441 u_suballocator_create(&sctx->b, 128 * 1024,
442 0, PIPE_USAGE_DEFAULT,
443 SI_RESOURCE_FLAG_UNMAPPABLE |
444 SI_RESOURCE_FLAG_CLEAR, false);
445 if (!sctx->allocator_zeroed_memory)
446 goto fail;
447
448 sctx->b.stream_uploader = u_upload_create(&sctx->b, 1024 * 1024,
449 0, PIPE_USAGE_STREAM,
450 SI_RESOURCE_FLAG_READ_ONLY);
451 if (!sctx->b.stream_uploader)
452 goto fail;
453
454 sctx->cached_gtt_allocator = u_upload_create(&sctx->b, 16 * 1024,
455 0, PIPE_USAGE_STAGING, 0);
456 if (!sctx->cached_gtt_allocator)
457 goto fail;
458
459 sctx->ctx = sctx->ws->ctx_create(sctx->ws);
460 if (!sctx->ctx)
461 goto fail;
462
463 if (sscreen->info.num_sdma_rings && !(sscreen->debug_flags & DBG(NO_ASYNC_DMA))) {
464 sctx->dma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA,
465 (void*)si_flush_dma_cs,
466 sctx, stop_exec_on_failure);
467 }
468
469 bool use_sdma_upload = sscreen->info.has_dedicated_vram && sctx->dma_cs;
470 sctx->b.const_uploader = u_upload_create(&sctx->b, 256 * 1024,
471 0, PIPE_USAGE_DEFAULT,
472 SI_RESOURCE_FLAG_32BIT |
473 (use_sdma_upload ?
474 SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA : 0));
475 if (!sctx->b.const_uploader)
476 goto fail;
477
478 if (use_sdma_upload)
479 u_upload_enable_flush_explicit(sctx->b.const_uploader);
480
481 sctx->gfx_cs = ws->cs_create(sctx->ctx,
482 sctx->has_graphics ? RING_GFX : RING_COMPUTE,
483 (void*)si_flush_gfx_cs, sctx, stop_exec_on_failure);
484
485 /* Border colors. */
486 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
487 sizeof(*sctx->border_color_table));
488 if (!sctx->border_color_table)
489 goto fail;
490
491 sctx->border_color_buffer = si_resource(
492 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
493 SI_MAX_BORDER_COLORS *
494 sizeof(*sctx->border_color_table)));
495 if (!sctx->border_color_buffer)
496 goto fail;
497
498 sctx->border_color_map =
499 ws->buffer_map(sctx->border_color_buffer->buf,
500 NULL, PIPE_TRANSFER_WRITE);
501 if (!sctx->border_color_map)
502 goto fail;
503
504 sctx->ngg = sctx->chip_class >= GFX10;
505
506 /* Initialize context functions used by graphics and compute. */
507 if (sctx->chip_class >= GFX10)
508 sctx->emit_cache_flush = gfx10_emit_cache_flush;
509 else
510 sctx->emit_cache_flush = si_emit_cache_flush;
511
512 sctx->b.emit_string_marker = si_emit_string_marker;
513 sctx->b.set_debug_callback = si_set_debug_callback;
514 sctx->b.set_log_context = si_set_log_context;
515 sctx->b.set_context_param = si_set_context_param;
516 sctx->b.get_device_reset_status = si_get_reset_status;
517 sctx->b.set_device_reset_callback = si_set_device_reset_callback;
518
519 si_init_all_descriptors(sctx);
520 si_init_buffer_functions(sctx);
521 si_init_clear_functions(sctx);
522 si_init_blit_functions(sctx);
523 si_init_compute_functions(sctx);
524 si_init_compute_blit_functions(sctx);
525 si_init_debug_functions(sctx);
526 si_init_fence_functions(sctx);
527 si_init_query_functions(sctx);
528 si_init_state_compute_functions(sctx);
529 si_init_context_texture_functions(sctx);
530
531 /* Initialize graphics-only context functions. */
532 if (sctx->has_graphics) {
533 if (sctx->chip_class >= GFX10)
534 gfx10_init_query(sctx);
535 si_init_msaa_functions(sctx);
536 si_init_shader_functions(sctx);
537 si_init_state_functions(sctx);
538 si_init_streamout_functions(sctx);
539 si_init_viewport_functions(sctx);
540
541 sctx->blitter = util_blitter_create(&sctx->b);
542 if (sctx->blitter == NULL)
543 goto fail;
544 sctx->blitter->skip_viewport_restore = true;
545
546 /* Some states are expected to be always non-NULL. */
547 sctx->noop_blend = util_blitter_get_noop_blend_state(sctx->blitter);
548 sctx->queued.named.blend = sctx->noop_blend;
549
550 si_init_draw_functions(sctx);
551 si_initialize_prim_discard_tunables(sctx);
552 }
553
554 /* Initialize SDMA functions. */
555 if (sctx->chip_class >= GFX7)
556 cik_init_sdma_functions(sctx);
557 else
558 si_init_dma_functions(sctx);
559
560 if (sscreen->debug_flags & DBG(FORCE_DMA))
561 sctx->b.resource_copy_region = sctx->dma_copy;
562
563 sctx->sample_mask = 0xffff;
564
565 /* Initialize multimedia functions. */
566 if (sscreen->info.has_hw_decode) {
567 sctx->b.create_video_codec = si_uvd_create_decoder;
568 sctx->b.create_video_buffer = si_video_buffer_create;
569 } else {
570 sctx->b.create_video_codec = vl_create_decoder;
571 sctx->b.create_video_buffer = vl_video_buffer_create;
572 }
573
574 if (sctx->chip_class >= GFX9) {
575 sctx->wait_mem_scratch = si_resource(
576 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 8));
577 if (!sctx->wait_mem_scratch)
578 goto fail;
579
580 /* Initialize the memory. */
581 si_cp_write_data(sctx, sctx->wait_mem_scratch, 0, 4,
582 V_370_MEM, V_370_ME, &sctx->wait_mem_number);
583 }
584
585 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
586 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
587 if (sctx->chip_class == GFX7) {
588 sctx->null_const_buf.buffer =
589 pipe_aligned_buffer_create(screen,
590 SI_RESOURCE_FLAG_32BIT,
591 PIPE_USAGE_DEFAULT, 16,
592 sctx->screen->info.tcc_cache_line_size);
593 if (!sctx->null_const_buf.buffer)
594 goto fail;
595 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
596
597 unsigned start_shader = sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE;
598 for (shader = start_shader; shader < SI_NUM_SHADERS; shader++) {
599 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
600 sctx->b.set_constant_buffer(&sctx->b, shader, i,
601 &sctx->null_const_buf);
602 }
603 }
604
605 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
606 &sctx->null_const_buf);
607 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
608 &sctx->null_const_buf);
609 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
610 &sctx->null_const_buf);
611 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
612 &sctx->null_const_buf);
613 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
614 &sctx->null_const_buf);
615 }
616
617 uint64_t max_threads_per_block;
618 screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
619 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
620 &max_threads_per_block);
621
622 /* The maximum number of scratch waves. Scratch space isn't divided
623 * evenly between CUs. The number is only a function of the number of CUs.
624 * We can decrease the constant to decrease the scratch buffer size.
625 *
626 * sctx->scratch_waves must be >= the maximum posible size of
627 * 1 threadgroup, so that the hw doesn't hang from being unable
628 * to start any.
629 *
630 * The recommended value is 4 per CU at most. Higher numbers don't
631 * bring much benefit, but they still occupy chip resources (think
632 * async compute). I've seen ~2% performance difference between 4 and 32.
633 */
634 sctx->scratch_waves = MAX2(32 * sscreen->info.num_good_compute_units,
635 max_threads_per_block / 64);
636
637 si_init_compiler(sscreen, &sctx->compiler);
638
639 /* Bindless handles. */
640 sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
641 _mesa_key_pointer_equal);
642 sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
643 _mesa_key_pointer_equal);
644
645 util_dynarray_init(&sctx->resident_tex_handles, NULL);
646 util_dynarray_init(&sctx->resident_img_handles, NULL);
647 util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
648 util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
649 util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
650
651 sctx->sample_pos_buffer =
652 pipe_buffer_create(sctx->b.screen, 0, PIPE_USAGE_DEFAULT,
653 sizeof(sctx->sample_positions));
654 pipe_buffer_write(&sctx->b, sctx->sample_pos_buffer, 0,
655 sizeof(sctx->sample_positions), &sctx->sample_positions);
656
657 /* this must be last */
658 si_begin_new_gfx_cs(sctx);
659
660 if (sctx->chip_class == GFX7) {
661 /* Clear the NULL constant buffer, because loads should return zeros.
662 * Note that this forces CP DMA to be used, because clover deadlocks
663 * for some reason when the compute codepath is used.
664 */
665 uint32_t clear_value = 0;
666 si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0,
667 sctx->null_const_buf.buffer->width0,
668 &clear_value, 4, SI_COHERENCY_SHADER, true);
669 }
670 return &sctx->b;
671 fail:
672 fprintf(stderr, "radeonsi: Failed to create a context.\n");
673 si_destroy_context(&sctx->b);
674 return NULL;
675 }
676
677 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
678 void *priv, unsigned flags)
679 {
680 struct si_screen *sscreen = (struct si_screen *)screen;
681 struct pipe_context *ctx;
682
683 if (sscreen->debug_flags & DBG(CHECK_VM))
684 flags |= PIPE_CONTEXT_DEBUG;
685
686 ctx = si_create_context(screen, flags);
687
688 if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
689 return ctx;
690
691 /* Clover (compute-only) is unsupported. */
692 if (flags & PIPE_CONTEXT_COMPUTE_ONLY)
693 return ctx;
694
695 /* When shaders are logged to stderr, asynchronous compilation is
696 * disabled too. */
697 if (sscreen->debug_flags & DBG_ALL_SHADERS)
698 return ctx;
699
700 /* Use asynchronous flushes only on amdgpu, since the radeon
701 * implementation for fence_server_sync is incomplete. */
702 return threaded_context_create(ctx, &sscreen->pool_transfers,
703 si_replace_buffer_storage,
704 sscreen->info.is_amdgpu ? si_create_fence : NULL,
705 &((struct si_context*)ctx)->tc);
706 }
707
708 /*
709 * pipe_screen
710 */
711 static void si_destroy_screen(struct pipe_screen* pscreen)
712 {
713 struct si_screen *sscreen = (struct si_screen *)pscreen;
714 struct si_shader_part *parts[] = {
715 sscreen->vs_prologs,
716 sscreen->tcs_epilogs,
717 sscreen->gs_prologs,
718 sscreen->ps_prologs,
719 sscreen->ps_epilogs
720 };
721 unsigned i;
722
723 if (!sscreen->ws->unref(sscreen->ws))
724 return;
725
726 mtx_destroy(&sscreen->aux_context_lock);
727
728 struct u_log_context *aux_log = ((struct si_context *)sscreen->aux_context)->log;
729 if (aux_log) {
730 sscreen->aux_context->set_log_context(sscreen->aux_context, NULL);
731 u_log_context_destroy(aux_log);
732 FREE(aux_log);
733 }
734
735 sscreen->aux_context->destroy(sscreen->aux_context);
736
737 util_queue_destroy(&sscreen->shader_compiler_queue);
738 util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
739
740 for (i = 0; i < ARRAY_SIZE(sscreen->compiler); i++)
741 si_destroy_compiler(&sscreen->compiler[i]);
742
743 for (i = 0; i < ARRAY_SIZE(sscreen->compiler_lowp); i++)
744 si_destroy_compiler(&sscreen->compiler_lowp[i]);
745
746 /* Free shader parts. */
747 for (i = 0; i < ARRAY_SIZE(parts); i++) {
748 while (parts[i]) {
749 struct si_shader_part *part = parts[i];
750
751 parts[i] = part->next;
752 si_shader_binary_clean(&part->binary);
753 FREE(part);
754 }
755 }
756 mtx_destroy(&sscreen->shader_parts_mutex);
757 si_destroy_shader_cache(sscreen);
758
759 si_destroy_perfcounters(sscreen);
760 si_gpu_load_kill_thread(sscreen);
761
762 mtx_destroy(&sscreen->gpu_load_mutex);
763
764 slab_destroy_parent(&sscreen->pool_transfers);
765
766 disk_cache_destroy(sscreen->disk_shader_cache);
767 sscreen->ws->destroy(sscreen->ws);
768 FREE(sscreen);
769 }
770
771 static void si_init_gs_info(struct si_screen *sscreen)
772 {
773 sscreen->gs_table_depth = ac_get_gs_table_depth(sscreen->info.chip_class,
774 sscreen->info.family);
775 }
776
777 static void si_test_vmfault(struct si_screen *sscreen)
778 {
779 struct pipe_context *ctx = sscreen->aux_context;
780 struct si_context *sctx = (struct si_context *)ctx;
781 struct pipe_resource *buf =
782 pipe_buffer_create_const0(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 64);
783
784 if (!buf) {
785 puts("Buffer allocation failed.");
786 exit(1);
787 }
788
789 si_resource(buf)->gpu_address = 0; /* cause a VM fault */
790
791 if (sscreen->debug_flags & DBG(TEST_VMFAULT_CP)) {
792 si_cp_dma_copy_buffer(sctx, buf, buf, 0, 4, 4, 0,
793 SI_COHERENCY_NONE, L2_BYPASS);
794 ctx->flush(ctx, NULL, 0);
795 puts("VM fault test: CP - done.");
796 }
797 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SDMA)) {
798 si_sdma_clear_buffer(sctx, buf, 0, 4, 0);
799 ctx->flush(ctx, NULL, 0);
800 puts("VM fault test: SDMA - done.");
801 }
802 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SHADER)) {
803 util_test_constant_buffer(ctx, buf);
804 puts("VM fault test: Shader - done.");
805 }
806 exit(0);
807 }
808
809 static void si_test_gds_memory_management(struct si_context *sctx,
810 unsigned alloc_size, unsigned alignment,
811 enum radeon_bo_domain domain)
812 {
813 struct radeon_winsys *ws = sctx->ws;
814 struct radeon_cmdbuf *cs[8];
815 struct pb_buffer *gds_bo[ARRAY_SIZE(cs)];
816
817 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
818 cs[i] = ws->cs_create(sctx->ctx, RING_COMPUTE,
819 NULL, NULL, false);
820 gds_bo[i] = ws->buffer_create(ws, alloc_size, alignment, domain, 0);
821 assert(gds_bo[i]);
822 }
823
824 for (unsigned iterations = 0; iterations < 20000; iterations++) {
825 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
826 /* This clears GDS with CP DMA.
827 *
828 * We don't care if GDS is present. Just add some packet
829 * to make the GPU busy for a moment.
830 */
831 si_cp_dma_clear_buffer(sctx, cs[i], NULL, 0, alloc_size, 0,
832 SI_CPDMA_SKIP_BO_LIST_UPDATE |
833 SI_CPDMA_SKIP_CHECK_CS_SPACE |
834 SI_CPDMA_SKIP_GFX_SYNC, 0, 0);
835
836 ws->cs_add_buffer(cs[i], gds_bo[i], domain,
837 RADEON_USAGE_READWRITE, 0);
838 ws->cs_flush(cs[i], PIPE_FLUSH_ASYNC, NULL);
839 }
840 }
841 exit(0);
842 }
843
844 static void si_disk_cache_create(struct si_screen *sscreen)
845 {
846 /* Don't use the cache if shader dumping is enabled. */
847 if (sscreen->debug_flags & DBG_ALL_SHADERS)
848 return;
849
850 struct mesa_sha1 ctx;
851 unsigned char sha1[20];
852 char cache_id[20 * 2 + 1];
853
854 _mesa_sha1_init(&ctx);
855
856 if (!disk_cache_get_function_identifier(si_disk_cache_create, &ctx) ||
857 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo,
858 &ctx))
859 return;
860
861 _mesa_sha1_final(&ctx, sha1);
862 disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
863
864 /* These flags affect shader compilation. */
865 #define ALL_FLAGS (DBG(FS_CORRECT_DERIVS_AFTER_KILL) | \
866 DBG(SI_SCHED) | \
867 DBG(GISEL) | \
868 DBG(UNSAFE_MATH) | \
869 DBG(W32_GE) | \
870 DBG(W32_PS) | \
871 DBG(W32_CS) | \
872 DBG(W64_GE) | \
873 DBG(W64_PS) | \
874 DBG(W64_CS))
875 uint64_t shader_debug_flags = sscreen->debug_flags & ALL_FLAGS;
876
877 if (sscreen->options.enable_nir) {
878 STATIC_ASSERT((ALL_FLAGS & (1u << 31)) == 0);
879 shader_debug_flags |= 1u << 31;
880 }
881
882 /* Add the high bits of 32-bit addresses, which affects
883 * how 32-bit addresses are expanded to 64 bits.
884 */
885 STATIC_ASSERT(ALL_FLAGS <= UINT_MAX);
886 assert((int16_t)sscreen->info.address32_hi == (int32_t)sscreen->info.address32_hi);
887 shader_debug_flags |= (uint64_t)(sscreen->info.address32_hi & 0xffff) << 32;
888
889 sscreen->disk_shader_cache =
890 disk_cache_create(sscreen->info.name,
891 cache_id,
892 shader_debug_flags);
893 }
894
895 static void si_set_max_shader_compiler_threads(struct pipe_screen *screen,
896 unsigned max_threads)
897 {
898 struct si_screen *sscreen = (struct si_screen *)screen;
899
900 /* This function doesn't allow a greater number of threads than
901 * the queue had at its creation. */
902 util_queue_adjust_num_threads(&sscreen->shader_compiler_queue,
903 max_threads);
904 /* Don't change the number of threads on the low priority queue. */
905 }
906
907 static bool si_is_parallel_shader_compilation_finished(struct pipe_screen *screen,
908 void *shader,
909 enum pipe_shader_type shader_type)
910 {
911 struct si_shader_selector *sel = (struct si_shader_selector *)shader;
912
913 return util_queue_fence_is_signalled(&sel->ready);
914 }
915
916 static struct pipe_screen *
917 radeonsi_screen_create_impl(struct radeon_winsys *ws,
918 const struct pipe_screen_config *config)
919 {
920 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
921 unsigned hw_threads, num_comp_hi_threads, num_comp_lo_threads, i;
922
923 if (!sscreen) {
924 return NULL;
925 }
926
927 sscreen->ws = ws;
928 ws->query_info(ws, &sscreen->info);
929
930 if (sscreen->info.chip_class == GFX10 && HAVE_LLVM < 0x0900) {
931 fprintf(stderr, "radeonsi: Navi family support requires LLVM 9 or higher\n");
932 FREE(sscreen);
933 return NULL;
934 }
935
936 if (sscreen->info.chip_class >= GFX9) {
937 sscreen->se_tile_repeat = 32 * sscreen->info.max_se;
938 } else {
939 ac_get_raster_config(&sscreen->info,
940 &sscreen->pa_sc_raster_config,
941 &sscreen->pa_sc_raster_config_1,
942 &sscreen->se_tile_repeat);
943 }
944
945 sscreen->debug_flags = debug_get_flags_option("R600_DEBUG",
946 debug_options, 0);
947 sscreen->debug_flags |= debug_get_flags_option("AMD_DEBUG",
948 debug_options, 0);
949
950 if (sscreen->debug_flags & DBG(NO_GFX))
951 sscreen->info.has_graphics = false;
952
953 /* Set functions first. */
954 sscreen->b.context_create = si_pipe_create_context;
955 sscreen->b.destroy = si_destroy_screen;
956 sscreen->b.set_max_shader_compiler_threads =
957 si_set_max_shader_compiler_threads;
958 sscreen->b.is_parallel_shader_compilation_finished =
959 si_is_parallel_shader_compilation_finished;
960
961 si_init_screen_get_functions(sscreen);
962 si_init_screen_buffer_functions(sscreen);
963 si_init_screen_fence_functions(sscreen);
964 si_init_screen_state_functions(sscreen);
965 si_init_screen_texture_functions(sscreen);
966 si_init_screen_query_functions(sscreen);
967
968 /* Set these flags in debug_flags early, so that the shader cache takes
969 * them into account.
970 */
971 if (driQueryOptionb(config->options,
972 "glsl_correct_derivatives_after_discard"))
973 sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
974 if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
975 sscreen->debug_flags |= DBG(SI_SCHED);
976
977 if (sscreen->debug_flags & DBG(INFO))
978 ac_print_gpu_info(&sscreen->info);
979
980 slab_create_parent(&sscreen->pool_transfers,
981 sizeof(struct si_transfer), 64);
982
983 sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
984 if (sscreen->force_aniso == -1) {
985 sscreen->force_aniso = MIN2(16, debug_get_num_option("AMD_TEX_ANISO", -1));
986 }
987
988 if (sscreen->force_aniso >= 0) {
989 printf("radeonsi: Forcing anisotropy filter to %ix\n",
990 /* round down to a power of two */
991 1 << util_logbase2(sscreen->force_aniso));
992 }
993
994 (void) mtx_init(&sscreen->aux_context_lock, mtx_plain);
995 (void) mtx_init(&sscreen->gpu_load_mutex, mtx_plain);
996
997 si_init_gs_info(sscreen);
998 if (!si_init_shader_cache(sscreen)) {
999 FREE(sscreen);
1000 return NULL;
1001 }
1002
1003 si_disk_cache_create(sscreen);
1004
1005 /* Determine the number of shader compiler threads. */
1006 hw_threads = sysconf(_SC_NPROCESSORS_ONLN);
1007
1008 if (hw_threads >= 12) {
1009 num_comp_hi_threads = hw_threads * 3 / 4;
1010 num_comp_lo_threads = hw_threads / 3;
1011 } else if (hw_threads >= 6) {
1012 num_comp_hi_threads = hw_threads - 2;
1013 num_comp_lo_threads = hw_threads / 2;
1014 } else if (hw_threads >= 2) {
1015 num_comp_hi_threads = hw_threads - 1;
1016 num_comp_lo_threads = hw_threads / 2;
1017 } else {
1018 num_comp_hi_threads = 1;
1019 num_comp_lo_threads = 1;
1020 }
1021
1022 num_comp_hi_threads = MIN2(num_comp_hi_threads,
1023 ARRAY_SIZE(sscreen->compiler));
1024 num_comp_lo_threads = MIN2(num_comp_lo_threads,
1025 ARRAY_SIZE(sscreen->compiler_lowp));
1026
1027 if (!util_queue_init(&sscreen->shader_compiler_queue, "sh",
1028 64, num_comp_hi_threads,
1029 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1030 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY)) {
1031 si_destroy_shader_cache(sscreen);
1032 FREE(sscreen);
1033 return NULL;
1034 }
1035
1036 if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
1037 "shlo",
1038 64, num_comp_lo_threads,
1039 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1040 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY |
1041 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
1042 si_destroy_shader_cache(sscreen);
1043 FREE(sscreen);
1044 return NULL;
1045 }
1046
1047 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1048 si_init_perfcounters(sscreen);
1049
1050 /* Determine tessellation ring info. */
1051 bool double_offchip_buffers = sscreen->info.chip_class >= GFX7 &&
1052 sscreen->info.family != CHIP_CARRIZO &&
1053 sscreen->info.family != CHIP_STONEY;
1054 /* This must be one less than the maximum number due to a hw limitation.
1055 * Various hardware bugs need this.
1056 */
1057 unsigned max_offchip_buffers_per_se;
1058
1059 if (sscreen->info.chip_class >= GFX10)
1060 max_offchip_buffers_per_se = 256;
1061 /* Only certain chips can use the maximum value. */
1062 else if (sscreen->info.family == CHIP_VEGA12 ||
1063 sscreen->info.family == CHIP_VEGA20)
1064 max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1065 else
1066 max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
1067
1068 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1069 sscreen->info.max_se;
1070 unsigned offchip_granularity;
1071
1072 /* Hawaii has a bug with offchip buffers > 256 that can be worked
1073 * around by setting 4K granularity.
1074 */
1075 if (sscreen->info.family == CHIP_HAWAII) {
1076 sscreen->tess_offchip_block_dw_size = 4096;
1077 offchip_granularity = V_03093C_X_4K_DWORDS;
1078 } else {
1079 sscreen->tess_offchip_block_dw_size = 8192;
1080 offchip_granularity = V_03093C_X_8K_DWORDS;
1081 }
1082
1083 sscreen->tess_factor_ring_size = 32768 * sscreen->info.max_se;
1084 assert(((sscreen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
1085 sscreen->tess_offchip_ring_size = max_offchip_buffers *
1086 sscreen->tess_offchip_block_dw_size * 4;
1087
1088 if (sscreen->info.chip_class >= GFX7) {
1089 if (sscreen->info.chip_class >= GFX8)
1090 --max_offchip_buffers;
1091 sscreen->vgt_hs_offchip_param =
1092 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1093 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1094 } else {
1095 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
1096 sscreen->vgt_hs_offchip_param =
1097 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1098 }
1099
1100 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
1101 * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
1102 * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel. */
1103 sscreen->has_clear_state = sscreen->info.chip_class >= GFX7 &&
1104 sscreen->info.is_amdgpu;
1105
1106 sscreen->has_distributed_tess =
1107 sscreen->info.chip_class >= GFX8 &&
1108 sscreen->info.max_se >= 2;
1109
1110 sscreen->has_draw_indirect_multi =
1111 (sscreen->info.family >= CHIP_POLARIS10) ||
1112 (sscreen->info.chip_class == GFX8 &&
1113 sscreen->info.pfp_fw_version >= 121 &&
1114 sscreen->info.me_fw_version >= 87) ||
1115 (sscreen->info.chip_class == GFX7 &&
1116 sscreen->info.pfp_fw_version >= 211 &&
1117 sscreen->info.me_fw_version >= 173) ||
1118 (sscreen->info.chip_class == GFX6 &&
1119 sscreen->info.pfp_fw_version >= 79 &&
1120 sscreen->info.me_fw_version >= 142);
1121
1122 sscreen->has_out_of_order_rast = sscreen->info.chip_class >= GFX8 &&
1123 sscreen->info.max_se >= 2 &&
1124 !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER));
1125 sscreen->assume_no_z_fights =
1126 driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
1127 sscreen->commutative_blend_add =
1128 driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
1129
1130 {
1131 #define OPT_BOOL(name, dflt, description) \
1132 sscreen->options.name = \
1133 driQueryOptionb(config->options, "radeonsi_"#name);
1134 #include "si_debug_options.h"
1135 }
1136
1137 if (sscreen->options.always_nir)
1138 sscreen->options.enable_nir = true;
1139
1140 sscreen->has_gfx9_scissor_bug = sscreen->info.family == CHIP_VEGA10 ||
1141 sscreen->info.family == CHIP_RAVEN;
1142 sscreen->has_msaa_sample_loc_bug = (sscreen->info.family >= CHIP_POLARIS10 &&
1143 sscreen->info.family <= CHIP_POLARIS12) ||
1144 sscreen->info.family == CHIP_VEGA10 ||
1145 sscreen->info.family == CHIP_RAVEN;
1146 sscreen->has_ls_vgpr_init_bug = sscreen->info.family == CHIP_VEGA10 ||
1147 sscreen->info.family == CHIP_RAVEN;
1148 sscreen->has_dcc_constant_encode = sscreen->info.family == CHIP_RAVEN2 ||
1149 sscreen->info.chip_class >= GFX10;
1150
1151 /* Only enable primitive binning on APUs by default. */
1152 if (sscreen->info.chip_class >= GFX10) {
1153 sscreen->dpbb_allowed = true;
1154 sscreen->dfsm_allowed = !sscreen->info.has_dedicated_vram;
1155 } else if (sscreen->info.chip_class == GFX9) {
1156 sscreen->dpbb_allowed = !sscreen->info.has_dedicated_vram;
1157 sscreen->dfsm_allowed = !sscreen->info.has_dedicated_vram;
1158 }
1159
1160 /* Process DPBB enable flags. */
1161 if (sscreen->debug_flags & DBG(DPBB)) {
1162 sscreen->dpbb_allowed = true;
1163 if (sscreen->debug_flags & DBG(DFSM))
1164 sscreen->dfsm_allowed = true;
1165 }
1166
1167 /* Process DPBB disable flags. */
1168 if (sscreen->debug_flags & DBG(NO_DPBB)) {
1169 sscreen->dpbb_allowed = false;
1170 sscreen->dfsm_allowed = false;
1171 } else if (sscreen->debug_flags & DBG(NO_DFSM)) {
1172 sscreen->dfsm_allowed = false;
1173 }
1174
1175 /* While it would be nice not to have this flag, we are constrained
1176 * by the reality that LLVM 9.0 has buggy VGPR indexing on GFX9.
1177 */
1178 sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class != GFX9;
1179
1180 /* Some chips have RB+ registers, but don't support RB+. Those must
1181 * always disable it.
1182 */
1183 if (sscreen->info.family == CHIP_STONEY ||
1184 sscreen->info.chip_class >= GFX9) {
1185 sscreen->has_rbplus = true;
1186
1187 sscreen->rbplus_allowed =
1188 !(sscreen->debug_flags & DBG(NO_RB_PLUS)) &&
1189 (sscreen->info.family == CHIP_STONEY ||
1190 sscreen->info.family == CHIP_VEGA12 ||
1191 sscreen->info.family == CHIP_RAVEN ||
1192 sscreen->info.family == CHIP_RAVEN2);
1193 }
1194
1195 sscreen->dcc_msaa_allowed =
1196 !(sscreen->debug_flags & DBG(NO_DCC_MSAA));
1197
1198 sscreen->cpdma_prefetch_writes_memory = sscreen->info.chip_class <= GFX8;
1199
1200 (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1201 sscreen->use_monolithic_shaders =
1202 (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
1203
1204 sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SCACHE |
1205 SI_CONTEXT_INV_VCACHE;
1206 if (sscreen->info.chip_class <= GFX8) {
1207 sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_L2;
1208 sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WB_L2;
1209 }
1210
1211 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1212 sscreen->debug_flags |= DBG_ALL_SHADERS;
1213
1214 /* Syntax:
1215 * EQAA=s,z,c
1216 * Example:
1217 * EQAA=8,4,2
1218
1219 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1220 * Constraints:
1221 * s >= z >= c (ignoring this only wastes memory)
1222 * s = [2..16]
1223 * z = [2..8]
1224 * c = [2..8]
1225 *
1226 * Only MSAA color and depth buffers are overriden.
1227 */
1228 if (sscreen->info.has_eqaa_surface_allocator) {
1229 const char *eqaa = debug_get_option("EQAA", NULL);
1230 unsigned s,z,f;
1231
1232 if (eqaa && sscanf(eqaa, "%u,%u,%u", &s, &z, &f) == 3 && s && z && f) {
1233 sscreen->eqaa_force_coverage_samples = s;
1234 sscreen->eqaa_force_z_samples = z;
1235 sscreen->eqaa_force_color_samples = f;
1236 }
1237 }
1238
1239 for (i = 0; i < num_comp_hi_threads; i++)
1240 si_init_compiler(sscreen, &sscreen->compiler[i]);
1241 for (i = 0; i < num_comp_lo_threads; i++)
1242 si_init_compiler(sscreen, &sscreen->compiler_lowp[i]);
1243
1244 sscreen->ge_wave_size = 64;
1245 sscreen->ps_wave_size = 64;
1246 sscreen->compute_wave_size = 64;
1247
1248 if (sscreen->info.chip_class >= GFX10) {
1249 /* Pixels shaders: Wave64 is recommended.
1250 * Compute shaders: There are piglit failures with Wave32.
1251 */
1252 sscreen->ge_wave_size = 32;
1253
1254 if (sscreen->debug_flags & DBG(W32_GE))
1255 sscreen->ge_wave_size = 32;
1256 if (sscreen->debug_flags & DBG(W32_PS))
1257 sscreen->ps_wave_size = 32;
1258 if (sscreen->debug_flags & DBG(W32_CS))
1259 sscreen->compute_wave_size = 32;
1260
1261 if (sscreen->debug_flags & DBG(W64_GE))
1262 sscreen->ge_wave_size = 64;
1263 if (sscreen->debug_flags & DBG(W64_PS))
1264 sscreen->ps_wave_size = 64;
1265 if (sscreen->debug_flags & DBG(W64_CS))
1266 sscreen->compute_wave_size = 64;
1267 }
1268
1269 /* Create the auxiliary context. This must be done last. */
1270 sscreen->aux_context = si_create_context(&sscreen->b,
1271 (sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) |
1272 (sscreen->info.has_graphics ? 0 : PIPE_CONTEXT_COMPUTE_ONLY));
1273 if (sscreen->options.aux_debug) {
1274 struct u_log_context *log = CALLOC_STRUCT(u_log_context);
1275 u_log_context_init(log);
1276 sscreen->aux_context->set_log_context(sscreen->aux_context, log);
1277 }
1278
1279 if (sscreen->debug_flags & DBG(TEST_DMA))
1280 si_test_dma(sscreen);
1281
1282 if (sscreen->debug_flags & DBG(TEST_DMA_PERF)) {
1283 si_test_dma_perf(sscreen);
1284 }
1285
1286 if (sscreen->debug_flags & (DBG(TEST_VMFAULT_CP) |
1287 DBG(TEST_VMFAULT_SDMA) |
1288 DBG(TEST_VMFAULT_SHADER)))
1289 si_test_vmfault(sscreen);
1290
1291 if (sscreen->debug_flags & DBG(TEST_GDS))
1292 si_test_gds((struct si_context*)sscreen->aux_context);
1293
1294 if (sscreen->debug_flags & DBG(TEST_GDS_MM)) {
1295 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1296 32 * 1024, 4, RADEON_DOMAIN_GDS);
1297 }
1298 if (sscreen->debug_flags & DBG(TEST_GDS_OA_MM)) {
1299 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1300 4, 1, RADEON_DOMAIN_OA);
1301 }
1302
1303 return &sscreen->b;
1304 }
1305
1306 struct pipe_screen *radeonsi_screen_create(int fd, const struct pipe_screen_config *config)
1307 {
1308 drmVersionPtr version = drmGetVersion(fd);
1309 struct radeon_winsys *rw = NULL;
1310
1311 switch (version->version_major) {
1312 case 2:
1313 rw = radeon_drm_winsys_create(fd, config, radeonsi_screen_create_impl);
1314 break;
1315 case 3:
1316 rw = amdgpu_winsys_create(fd, config, radeonsi_screen_create_impl);
1317 break;
1318 }
1319
1320 drmFreeVersion(version);
1321 return rw ? rw->screen : NULL;
1322 }