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radeonsi: add radeonsi_aux_debug option for aux context debug dumps
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "si_pipe.h"
27 #include "si_public.h"
28 #include "si_shader_internal.h"
29 #include "si_compute.h"
30 #include "sid.h"
31
32 #include "ac_llvm_util.h"
33 #include "radeon/radeon_uvd.h"
34 #include "gallivm/lp_bld_misc.h"
35 #include "util/disk_cache.h"
36 #include "util/u_log.h"
37 #include "util/u_memory.h"
38 #include "util/u_suballoc.h"
39 #include "util/u_tests.h"
40 #include "util/u_upload_mgr.h"
41 #include "util/xmlconfig.h"
42 #include "vl/vl_decoder.h"
43 #include "driver_ddebug/dd_util.h"
44
45 static const struct debug_named_value debug_options[] = {
46 /* Shader logging options: */
47 { "vs", DBG(VS), "Print vertex shaders" },
48 { "ps", DBG(PS), "Print pixel shaders" },
49 { "gs", DBG(GS), "Print geometry shaders" },
50 { "tcs", DBG(TCS), "Print tessellation control shaders" },
51 { "tes", DBG(TES), "Print tessellation evaluation shaders" },
52 { "cs", DBG(CS), "Print compute shaders" },
53 { "noir", DBG(NO_IR), "Don't print the LLVM IR"},
54 { "notgsi", DBG(NO_TGSI), "Don't print the TGSI"},
55 { "noasm", DBG(NO_ASM), "Don't print disassembled shaders"},
56 { "preoptir", DBG(PREOPT_IR), "Print the LLVM IR before initial optimizations" },
57
58 /* Shader compiler options the shader cache should be aware of: */
59 { "unsafemath", DBG(UNSAFE_MATH), "Enable unsafe math shader optimizations" },
60 { "sisched", DBG(SI_SCHED), "Enable LLVM SI Machine Instruction Scheduler." },
61 { "gisel", DBG(GISEL), "Enable LLVM global instruction selector." },
62
63 /* Shader compiler options (with no effect on the shader cache): */
64 { "checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR" },
65 { "mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand" },
66 { "nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants." },
67
68 /* Information logging options: */
69 { "info", DBG(INFO), "Print driver information" },
70 { "tex", DBG(TEX), "Print texture info" },
71 { "compute", DBG(COMPUTE), "Print compute info" },
72 { "vm", DBG(VM), "Print virtual addresses when creating resources" },
73
74 /* Driver options: */
75 { "forcedma", DBG(FORCE_DMA), "Use asynchronous DMA for all operations when possible." },
76 { "nodma", DBG(NO_ASYNC_DMA), "Disable asynchronous DMA" },
77 { "nowc", DBG(NO_WC), "Disable GTT write combining" },
78 { "check_vm", DBG(CHECK_VM), "Check VM faults and dump debug info." },
79 { "reserve_vmid", DBG(RESERVE_VMID), "Force VMID reservation per context." },
80 { "zerovram", DBG(ZERO_VRAM), "Clear VRAM allocations." },
81
82 /* 3D engine options: */
83 { "switch_on_eop", DBG(SWITCH_ON_EOP), "Program WD/IA to switch on end-of-packet." },
84 { "nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order rasterization" },
85 { "nodpbb", DBG(NO_DPBB), "Disable DPBB." },
86 { "nodfsm", DBG(NO_DFSM), "Disable DFSM." },
87 { "dpbb", DBG(DPBB), "Enable DPBB." },
88 { "dfsm", DBG(DFSM), "Enable DFSM." },
89 { "nohyperz", DBG(NO_HYPERZ), "Disable Hyper-Z" },
90 { "norbplus", DBG(NO_RB_PLUS), "Disable RB+." },
91 { "no2d", DBG(NO_2D_TILING), "Disable 2D tiling" },
92 { "notiling", DBG(NO_TILING), "Disable tiling" },
93 { "nodcc", DBG(NO_DCC), "Disable DCC." },
94 { "nodccclear", DBG(NO_DCC_CLEAR), "Disable DCC fast clear." },
95 { "nodccfb", DBG(NO_DCC_FB), "Disable separate DCC on the main framebuffer" },
96 { "nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA" },
97 { "nofmask", DBG(NO_FMASK), "Disable MSAA compression" },
98
99 /* Tests: */
100 { "testdma", DBG(TEST_DMA), "Invoke SDMA tests and exit." },
101 { "testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and exit." },
102 { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA), "Invoke a SDMA VM fault test and exit." },
103 { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM fault test and exit." },
104 { "testdmaperf", DBG(TEST_DMA_PERF), "Test DMA performance" },
105 { "testgds", DBG(TEST_GDS), "Test GDS." },
106 { "testgdsmm", DBG(TEST_GDS_MM), "Test GDS memory management." },
107 { "testgdsoamm", DBG(TEST_GDS_OA_MM), "Test GDS OA memory management." },
108
109 DEBUG_NAMED_VALUE_END /* must be last */
110 };
111
112 static void si_init_compiler(struct si_screen *sscreen,
113 struct ac_llvm_compiler *compiler)
114 {
115 /* Only create the less-optimizing version of the compiler on APUs
116 * predating Ryzen (Raven). */
117 bool create_low_opt_compiler = !sscreen->info.has_dedicated_vram &&
118 sscreen->info.chip_class <= VI;
119
120 enum ac_target_machine_options tm_options =
121 (sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
122 (sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL : 0) |
123 (sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
124 (sscreen->info.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
125 (!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0) |
126 (sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0) |
127 (create_low_opt_compiler ? AC_TM_CREATE_LOW_OPT : 0);
128
129 ac_init_llvm_once();
130 ac_init_llvm_compiler(compiler, sscreen->info.family, tm_options);
131 compiler->passes = ac_create_llvm_passes(compiler->tm);
132
133 if (compiler->low_opt_tm)
134 compiler->low_opt_passes = ac_create_llvm_passes(compiler->low_opt_tm);
135 }
136
137 static void si_destroy_compiler(struct ac_llvm_compiler *compiler)
138 {
139 ac_destroy_llvm_passes(compiler->passes);
140 ac_destroy_llvm_passes(compiler->low_opt_passes);
141 ac_destroy_llvm_compiler(compiler);
142 }
143
144 /*
145 * pipe_context
146 */
147 static void si_destroy_context(struct pipe_context *context)
148 {
149 struct si_context *sctx = (struct si_context *)context;
150 int i;
151
152 util_queue_finish(&sctx->screen->shader_compiler_queue);
153 util_queue_finish(&sctx->screen->shader_compiler_queue_low_priority);
154
155 /* Unreference the framebuffer normally to disable related logic
156 * properly.
157 */
158 struct pipe_framebuffer_state fb = {};
159 if (context->set_framebuffer_state)
160 context->set_framebuffer_state(context, &fb);
161
162 si_release_all_descriptors(sctx);
163
164 pipe_resource_reference(&sctx->esgs_ring, NULL);
165 pipe_resource_reference(&sctx->gsvs_ring, NULL);
166 pipe_resource_reference(&sctx->tess_rings, NULL);
167 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
168 pipe_resource_reference(&sctx->sample_pos_buffer, NULL);
169 si_resource_reference(&sctx->border_color_buffer, NULL);
170 free(sctx->border_color_table);
171 si_resource_reference(&sctx->scratch_buffer, NULL);
172 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
173 si_resource_reference(&sctx->wait_mem_scratch, NULL);
174
175 si_pm4_free_state(sctx, sctx->init_config, ~0);
176 if (sctx->init_config_gs_rings)
177 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
178 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
179 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
180
181 if (sctx->fixed_func_tcs_shader.cso)
182 sctx->b.delete_tcs_state(&sctx->b, sctx->fixed_func_tcs_shader.cso);
183 if (sctx->custom_dsa_flush)
184 sctx->b.delete_depth_stencil_alpha_state(&sctx->b, sctx->custom_dsa_flush);
185 if (sctx->custom_blend_resolve)
186 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_resolve);
187 if (sctx->custom_blend_fmask_decompress)
188 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_fmask_decompress);
189 if (sctx->custom_blend_eliminate_fastclear)
190 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_eliminate_fastclear);
191 if (sctx->custom_blend_dcc_decompress)
192 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_dcc_decompress);
193 if (sctx->vs_blit_pos)
194 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos);
195 if (sctx->vs_blit_pos_layered)
196 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos_layered);
197 if (sctx->vs_blit_color)
198 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color);
199 if (sctx->vs_blit_color_layered)
200 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color_layered);
201 if (sctx->vs_blit_texcoord)
202 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_texcoord);
203 if (sctx->cs_clear_buffer)
204 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_buffer);
205 if (sctx->cs_copy_buffer)
206 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_buffer);
207 if (sctx->cs_copy_image)
208 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image);
209 if (sctx->cs_copy_image_1d_array)
210 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image_1d_array);
211 if (sctx->cs_clear_render_target)
212 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target);
213 if (sctx->cs_clear_render_target_1d_array)
214 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target_1d_array);
215 if (sctx->cs_dcc_retile)
216 sctx->b.delete_compute_state(&sctx->b, sctx->cs_dcc_retile);
217
218 if (sctx->blitter)
219 util_blitter_destroy(sctx->blitter);
220
221 /* Release DCC stats. */
222 for (int i = 0; i < ARRAY_SIZE(sctx->dcc_stats); i++) {
223 assert(!sctx->dcc_stats[i].query_active);
224
225 for (int j = 0; j < ARRAY_SIZE(sctx->dcc_stats[i].ps_stats); j++)
226 if (sctx->dcc_stats[i].ps_stats[j])
227 sctx->b.destroy_query(&sctx->b,
228 sctx->dcc_stats[i].ps_stats[j]);
229
230 si_texture_reference(&sctx->dcc_stats[i].tex, NULL);
231 }
232
233 if (sctx->query_result_shader)
234 sctx->b.delete_compute_state(&sctx->b, sctx->query_result_shader);
235
236 if (sctx->gfx_cs)
237 sctx->ws->cs_destroy(sctx->gfx_cs);
238 if (sctx->dma_cs)
239 sctx->ws->cs_destroy(sctx->dma_cs);
240 if (sctx->ctx)
241 sctx->ws->ctx_destroy(sctx->ctx);
242
243 if (sctx->b.stream_uploader)
244 u_upload_destroy(sctx->b.stream_uploader);
245 if (sctx->b.const_uploader)
246 u_upload_destroy(sctx->b.const_uploader);
247 if (sctx->cached_gtt_allocator)
248 u_upload_destroy(sctx->cached_gtt_allocator);
249
250 slab_destroy_child(&sctx->pool_transfers);
251 slab_destroy_child(&sctx->pool_transfers_unsync);
252
253 if (sctx->allocator_zeroed_memory)
254 u_suballocator_destroy(sctx->allocator_zeroed_memory);
255
256 sctx->ws->fence_reference(&sctx->last_gfx_fence, NULL);
257 sctx->ws->fence_reference(&sctx->last_sdma_fence, NULL);
258 si_resource_reference(&sctx->eop_bug_scratch, NULL);
259
260 si_destroy_compiler(&sctx->compiler);
261
262 si_saved_cs_reference(&sctx->current_saved_cs, NULL);
263
264 _mesa_hash_table_destroy(sctx->tex_handles, NULL);
265 _mesa_hash_table_destroy(sctx->img_handles, NULL);
266
267 util_dynarray_fini(&sctx->resident_tex_handles);
268 util_dynarray_fini(&sctx->resident_img_handles);
269 util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
270 util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
271 util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
272 si_unref_sdma_uploads(sctx);
273 FREE(sctx);
274 }
275
276 static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx)
277 {
278 struct si_context *sctx = (struct si_context *)ctx;
279
280 if (sctx->screen->info.has_gpu_reset_status_query)
281 return sctx->ws->ctx_query_reset_status(sctx->ctx);
282
283 if (sctx->screen->info.has_gpu_reset_counter_query) {
284 unsigned latest = sctx->ws->query_value(sctx->ws,
285 RADEON_GPU_RESET_COUNTER);
286
287 if (sctx->gpu_reset_counter == latest)
288 return PIPE_NO_RESET;
289
290 sctx->gpu_reset_counter = latest;
291 return PIPE_UNKNOWN_CONTEXT_RESET;
292 }
293
294 return PIPE_NO_RESET;
295 }
296
297 static void si_set_device_reset_callback(struct pipe_context *ctx,
298 const struct pipe_device_reset_callback *cb)
299 {
300 struct si_context *sctx = (struct si_context *)ctx;
301
302 if (cb)
303 sctx->device_reset_callback = *cb;
304 else
305 memset(&sctx->device_reset_callback, 0,
306 sizeof(sctx->device_reset_callback));
307 }
308
309 bool si_check_device_reset(struct si_context *sctx)
310 {
311 enum pipe_reset_status status;
312
313 if (!sctx->device_reset_callback.reset)
314 return false;
315
316 if (!sctx->b.get_device_reset_status)
317 return false;
318
319 status = sctx->b.get_device_reset_status(&sctx->b);
320 if (status == PIPE_NO_RESET)
321 return false;
322
323 sctx->device_reset_callback.reset(sctx->device_reset_callback.data, status);
324 return true;
325 }
326
327 /* Apitrace profiling:
328 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
329 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
330 * and remember its number.
331 * 3) In Mesa, enable queries and performance counters around that draw
332 * call and print the results.
333 * 4) glretrace --benchmark --markers ..
334 */
335 static void si_emit_string_marker(struct pipe_context *ctx,
336 const char *string, int len)
337 {
338 struct si_context *sctx = (struct si_context *)ctx;
339
340 dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
341
342 if (sctx->log)
343 u_log_printf(sctx->log, "\nString marker: %*s\n", len, string);
344 }
345
346 static void si_set_debug_callback(struct pipe_context *ctx,
347 const struct pipe_debug_callback *cb)
348 {
349 struct si_context *sctx = (struct si_context *)ctx;
350 struct si_screen *screen = sctx->screen;
351
352 util_queue_finish(&screen->shader_compiler_queue);
353 util_queue_finish(&screen->shader_compiler_queue_low_priority);
354
355 if (cb)
356 sctx->debug = *cb;
357 else
358 memset(&sctx->debug, 0, sizeof(sctx->debug));
359 }
360
361 static void si_set_log_context(struct pipe_context *ctx,
362 struct u_log_context *log)
363 {
364 struct si_context *sctx = (struct si_context *)ctx;
365 sctx->log = log;
366
367 if (log)
368 u_log_add_auto_logger(log, si_auto_log_cs, sctx);
369 }
370
371 static void si_set_context_param(struct pipe_context *ctx,
372 enum pipe_context_param param,
373 unsigned value)
374 {
375 struct radeon_winsys *ws = ((struct si_context *)ctx)->ws;
376
377 switch (param) {
378 case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE:
379 ws->pin_threads_to_L3_cache(ws, value);
380 break;
381 default:;
382 }
383 }
384
385 static struct pipe_context *si_create_context(struct pipe_screen *screen,
386 unsigned flags)
387 {
388 struct si_context *sctx = CALLOC_STRUCT(si_context);
389 struct si_screen* sscreen = (struct si_screen *)screen;
390 struct radeon_winsys *ws = sscreen->ws;
391 int shader, i;
392 bool stop_exec_on_failure = (flags & PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET) != 0;
393
394 if (!sctx)
395 return NULL;
396
397 sctx->has_graphics = sscreen->info.chip_class == SI ||
398 !(flags & PIPE_CONTEXT_COMPUTE_ONLY);
399
400 if (flags & PIPE_CONTEXT_DEBUG)
401 sscreen->record_llvm_ir = true; /* racy but not critical */
402
403 sctx->b.screen = screen; /* this must be set first */
404 sctx->b.priv = NULL;
405 sctx->b.destroy = si_destroy_context;
406 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
407 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
408
409 slab_create_child(&sctx->pool_transfers, &sscreen->pool_transfers);
410 slab_create_child(&sctx->pool_transfers_unsync, &sscreen->pool_transfers);
411
412 sctx->ws = sscreen->ws;
413 sctx->family = sscreen->info.family;
414 sctx->chip_class = sscreen->info.chip_class;
415
416 if (sscreen->info.has_gpu_reset_counter_query) {
417 sctx->gpu_reset_counter =
418 sctx->ws->query_value(sctx->ws, RADEON_GPU_RESET_COUNTER);
419 }
420
421
422 if (sctx->chip_class == CIK ||
423 sctx->chip_class == VI ||
424 sctx->chip_class == GFX9) {
425 sctx->eop_bug_scratch = si_resource(
426 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
427 16 * sscreen->info.num_render_backends));
428 if (!sctx->eop_bug_scratch)
429 goto fail;
430 }
431
432 /* Initialize context allocators. */
433 sctx->allocator_zeroed_memory =
434 u_suballocator_create(&sctx->b, 128 * 1024,
435 0, PIPE_USAGE_DEFAULT,
436 SI_RESOURCE_FLAG_UNMAPPABLE |
437 SI_RESOURCE_FLAG_CLEAR, false);
438 if (!sctx->allocator_zeroed_memory)
439 goto fail;
440
441 sctx->b.stream_uploader = u_upload_create(&sctx->b, 1024 * 1024,
442 0, PIPE_USAGE_STREAM,
443 SI_RESOURCE_FLAG_READ_ONLY);
444 if (!sctx->b.stream_uploader)
445 goto fail;
446
447 sctx->cached_gtt_allocator = u_upload_create(&sctx->b, 16 * 1024,
448 0, PIPE_USAGE_STAGING, 0);
449 if (!sctx->cached_gtt_allocator)
450 goto fail;
451
452 sctx->ctx = sctx->ws->ctx_create(sctx->ws);
453 if (!sctx->ctx)
454 goto fail;
455
456 if (sscreen->info.num_sdma_rings && !(sscreen->debug_flags & DBG(NO_ASYNC_DMA))) {
457 sctx->dma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA,
458 (void*)si_flush_dma_cs,
459 sctx, stop_exec_on_failure);
460 }
461
462 bool use_sdma_upload = sscreen->info.has_dedicated_vram && sctx->dma_cs;
463 sctx->b.const_uploader = u_upload_create(&sctx->b, 256 * 1024,
464 0, PIPE_USAGE_DEFAULT,
465 SI_RESOURCE_FLAG_32BIT |
466 (use_sdma_upload ?
467 SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA :
468 (sscreen->cpdma_prefetch_writes_memory ?
469 0 : SI_RESOURCE_FLAG_READ_ONLY)));
470 if (!sctx->b.const_uploader)
471 goto fail;
472
473 if (use_sdma_upload)
474 u_upload_enable_flush_explicit(sctx->b.const_uploader);
475
476 sctx->gfx_cs = ws->cs_create(sctx->ctx,
477 sctx->has_graphics ? RING_GFX : RING_COMPUTE,
478 (void*)si_flush_gfx_cs, sctx, stop_exec_on_failure);
479
480 /* Border colors. */
481 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
482 sizeof(*sctx->border_color_table));
483 if (!sctx->border_color_table)
484 goto fail;
485
486 sctx->border_color_buffer = si_resource(
487 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
488 SI_MAX_BORDER_COLORS *
489 sizeof(*sctx->border_color_table)));
490 if (!sctx->border_color_buffer)
491 goto fail;
492
493 sctx->border_color_map =
494 ws->buffer_map(sctx->border_color_buffer->buf,
495 NULL, PIPE_TRANSFER_WRITE);
496 if (!sctx->border_color_map)
497 goto fail;
498
499 /* Initialize context functions used by graphics and compute. */
500 sctx->b.emit_string_marker = si_emit_string_marker;
501 sctx->b.set_debug_callback = si_set_debug_callback;
502 sctx->b.set_log_context = si_set_log_context;
503 sctx->b.set_context_param = si_set_context_param;
504 sctx->b.get_device_reset_status = si_get_reset_status;
505 sctx->b.set_device_reset_callback = si_set_device_reset_callback;
506 sctx->b.memory_barrier = si_memory_barrier;
507
508 si_init_all_descriptors(sctx);
509 si_init_buffer_functions(sctx);
510 si_init_clear_functions(sctx);
511 si_init_blit_functions(sctx);
512 si_init_compute_functions(sctx);
513 si_init_compute_blit_functions(sctx);
514 si_init_debug_functions(sctx);
515 si_init_fence_functions(sctx);
516
517 if (sscreen->debug_flags & DBG(FORCE_DMA))
518 sctx->b.resource_copy_region = sctx->dma_copy;
519
520 /* Initialize graphics-only context functions. */
521 if (sctx->has_graphics) {
522 si_init_context_texture_functions(sctx);
523 si_init_query_functions(sctx);
524 si_init_msaa_functions(sctx);
525 si_init_shader_functions(sctx);
526 si_init_state_functions(sctx);
527 si_init_streamout_functions(sctx);
528 si_init_viewport_functions(sctx);
529
530 sctx->blitter = util_blitter_create(&sctx->b);
531 if (sctx->blitter == NULL)
532 goto fail;
533 sctx->blitter->skip_viewport_restore = true;
534
535 si_init_draw_functions(sctx);
536 }
537
538 /* Initialize SDMA functions. */
539 if (sctx->chip_class >= CIK)
540 cik_init_sdma_functions(sctx);
541 else
542 si_init_dma_functions(sctx);
543
544 sctx->sample_mask = 0xffff;
545
546 /* Initialize multimedia functions. */
547 if (sscreen->info.has_hw_decode) {
548 sctx->b.create_video_codec = si_uvd_create_decoder;
549 sctx->b.create_video_buffer = si_video_buffer_create;
550 } else {
551 sctx->b.create_video_codec = vl_create_decoder;
552 sctx->b.create_video_buffer = vl_video_buffer_create;
553 }
554
555 if (sctx->chip_class >= GFX9) {
556 sctx->wait_mem_scratch = si_resource(
557 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 4));
558 if (!sctx->wait_mem_scratch)
559 goto fail;
560
561 /* Initialize the memory. */
562 si_cp_write_data(sctx, sctx->wait_mem_scratch, 0, 4,
563 V_370_MEM, V_370_ME, &sctx->wait_mem_number);
564 }
565
566 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
567 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
568 if (sctx->chip_class == CIK) {
569 sctx->null_const_buf.buffer =
570 pipe_aligned_buffer_create(screen,
571 SI_RESOURCE_FLAG_32BIT,
572 PIPE_USAGE_DEFAULT, 16,
573 sctx->screen->info.tcc_cache_line_size);
574 if (!sctx->null_const_buf.buffer)
575 goto fail;
576 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
577
578 unsigned start_shader = sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE;
579 for (shader = start_shader; shader < SI_NUM_SHADERS; shader++) {
580 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
581 sctx->b.set_constant_buffer(&sctx->b, shader, i,
582 &sctx->null_const_buf);
583 }
584 }
585
586 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
587 &sctx->null_const_buf);
588 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
589 &sctx->null_const_buf);
590 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
591 &sctx->null_const_buf);
592 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
593 &sctx->null_const_buf);
594 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
595 &sctx->null_const_buf);
596 }
597
598 uint64_t max_threads_per_block;
599 screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
600 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
601 &max_threads_per_block);
602
603 /* The maximum number of scratch waves. Scratch space isn't divided
604 * evenly between CUs. The number is only a function of the number of CUs.
605 * We can decrease the constant to decrease the scratch buffer size.
606 *
607 * sctx->scratch_waves must be >= the maximum posible size of
608 * 1 threadgroup, so that the hw doesn't hang from being unable
609 * to start any.
610 *
611 * The recommended value is 4 per CU at most. Higher numbers don't
612 * bring much benefit, but they still occupy chip resources (think
613 * async compute). I've seen ~2% performance difference between 4 and 32.
614 */
615 sctx->scratch_waves = MAX2(32 * sscreen->info.num_good_compute_units,
616 max_threads_per_block / 64);
617
618 si_init_compiler(sscreen, &sctx->compiler);
619
620 /* Bindless handles. */
621 sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
622 _mesa_key_pointer_equal);
623 sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
624 _mesa_key_pointer_equal);
625
626 util_dynarray_init(&sctx->resident_tex_handles, NULL);
627 util_dynarray_init(&sctx->resident_img_handles, NULL);
628 util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
629 util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
630 util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
631
632 sctx->sample_pos_buffer =
633 pipe_buffer_create(sctx->b.screen, 0, PIPE_USAGE_DEFAULT,
634 sizeof(sctx->sample_positions));
635 pipe_buffer_write(&sctx->b, sctx->sample_pos_buffer, 0,
636 sizeof(sctx->sample_positions), &sctx->sample_positions);
637
638 /* this must be last */
639 si_begin_new_gfx_cs(sctx);
640
641 if (sctx->chip_class == CIK) {
642 /* Clear the NULL constant buffer, because loads should return zeros.
643 * Note that this forces CP DMA to be used, because clover deadlocks
644 * for some reason when the compute codepath is used.
645 */
646 uint32_t clear_value = 0;
647 si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0,
648 sctx->null_const_buf.buffer->width0,
649 &clear_value, 4, SI_COHERENCY_SHADER, true);
650 }
651 return &sctx->b;
652 fail:
653 fprintf(stderr, "radeonsi: Failed to create a context.\n");
654 si_destroy_context(&sctx->b);
655 return NULL;
656 }
657
658 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
659 void *priv, unsigned flags)
660 {
661 struct si_screen *sscreen = (struct si_screen *)screen;
662 struct pipe_context *ctx;
663
664 if (sscreen->debug_flags & DBG(CHECK_VM))
665 flags |= PIPE_CONTEXT_DEBUG;
666
667 ctx = si_create_context(screen, flags);
668
669 if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
670 return ctx;
671
672 /* Clover (compute-only) is unsupported. */
673 if (flags & PIPE_CONTEXT_COMPUTE_ONLY)
674 return ctx;
675
676 /* When shaders are logged to stderr, asynchronous compilation is
677 * disabled too. */
678 if (sscreen->debug_flags & DBG_ALL_SHADERS)
679 return ctx;
680
681 /* Use asynchronous flushes only on amdgpu, since the radeon
682 * implementation for fence_server_sync is incomplete. */
683 return threaded_context_create(ctx, &sscreen->pool_transfers,
684 si_replace_buffer_storage,
685 sscreen->info.drm_major >= 3 ? si_create_fence : NULL,
686 &((struct si_context*)ctx)->tc);
687 }
688
689 /*
690 * pipe_screen
691 */
692 static void si_destroy_screen(struct pipe_screen* pscreen)
693 {
694 struct si_screen *sscreen = (struct si_screen *)pscreen;
695 struct si_shader_part *parts[] = {
696 sscreen->vs_prologs,
697 sscreen->tcs_epilogs,
698 sscreen->gs_prologs,
699 sscreen->ps_prologs,
700 sscreen->ps_epilogs
701 };
702 unsigned i;
703
704 if (!sscreen->ws->unref(sscreen->ws))
705 return;
706
707 mtx_destroy(&sscreen->aux_context_lock);
708
709 struct u_log_context *aux_log = ((struct si_context *)sscreen->aux_context)->log;
710 if (aux_log) {
711 sscreen->aux_context->set_log_context(sscreen->aux_context, NULL);
712 u_log_context_destroy(aux_log);
713 FREE(aux_log);
714 }
715
716 sscreen->aux_context->destroy(sscreen->aux_context);
717
718 util_queue_destroy(&sscreen->shader_compiler_queue);
719 util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
720
721 for (i = 0; i < ARRAY_SIZE(sscreen->compiler); i++)
722 si_destroy_compiler(&sscreen->compiler[i]);
723
724 for (i = 0; i < ARRAY_SIZE(sscreen->compiler_lowp); i++)
725 si_destroy_compiler(&sscreen->compiler_lowp[i]);
726
727 /* Free shader parts. */
728 for (i = 0; i < ARRAY_SIZE(parts); i++) {
729 while (parts[i]) {
730 struct si_shader_part *part = parts[i];
731
732 parts[i] = part->next;
733 ac_shader_binary_clean(&part->binary);
734 FREE(part);
735 }
736 }
737 mtx_destroy(&sscreen->shader_parts_mutex);
738 si_destroy_shader_cache(sscreen);
739
740 si_destroy_perfcounters(sscreen);
741 si_gpu_load_kill_thread(sscreen);
742
743 mtx_destroy(&sscreen->gpu_load_mutex);
744
745 slab_destroy_parent(&sscreen->pool_transfers);
746
747 disk_cache_destroy(sscreen->disk_shader_cache);
748 sscreen->ws->destroy(sscreen->ws);
749 FREE(sscreen);
750 }
751
752 static void si_init_gs_info(struct si_screen *sscreen)
753 {
754 sscreen->gs_table_depth = ac_get_gs_table_depth(sscreen->info.chip_class,
755 sscreen->info.family);
756 }
757
758 static void si_test_vmfault(struct si_screen *sscreen)
759 {
760 struct pipe_context *ctx = sscreen->aux_context;
761 struct si_context *sctx = (struct si_context *)ctx;
762 struct pipe_resource *buf =
763 pipe_buffer_create_const0(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 64);
764
765 if (!buf) {
766 puts("Buffer allocation failed.");
767 exit(1);
768 }
769
770 si_resource(buf)->gpu_address = 0; /* cause a VM fault */
771
772 if (sscreen->debug_flags & DBG(TEST_VMFAULT_CP)) {
773 si_cp_dma_copy_buffer(sctx, buf, buf, 0, 4, 4, 0,
774 SI_COHERENCY_NONE, L2_BYPASS);
775 ctx->flush(ctx, NULL, 0);
776 puts("VM fault test: CP - done.");
777 }
778 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SDMA)) {
779 si_sdma_clear_buffer(sctx, buf, 0, 4, 0);
780 ctx->flush(ctx, NULL, 0);
781 puts("VM fault test: SDMA - done.");
782 }
783 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SHADER)) {
784 util_test_constant_buffer(ctx, buf);
785 puts("VM fault test: Shader - done.");
786 }
787 exit(0);
788 }
789
790 static void si_test_gds_memory_management(struct si_context *sctx,
791 unsigned alloc_size, unsigned alignment,
792 enum radeon_bo_domain domain)
793 {
794 struct radeon_winsys *ws = sctx->ws;
795 struct radeon_cmdbuf *cs[8];
796 struct pb_buffer *gds_bo[ARRAY_SIZE(cs)];
797
798 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
799 cs[i] = ws->cs_create(sctx->ctx, RING_COMPUTE,
800 NULL, NULL, false);
801 gds_bo[i] = ws->buffer_create(ws, alloc_size, alignment, domain, 0);
802 assert(gds_bo[i]);
803 }
804
805 for (unsigned iterations = 0; iterations < 20000; iterations++) {
806 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
807 /* This clears GDS with CP DMA.
808 *
809 * We don't care if GDS is present. Just add some packet
810 * to make the GPU busy for a moment.
811 */
812 si_cp_dma_clear_buffer(sctx, cs[i], NULL, 0, alloc_size, 0,
813 SI_CPDMA_SKIP_BO_LIST_UPDATE |
814 SI_CPDMA_SKIP_CHECK_CS_SPACE |
815 SI_CPDMA_SKIP_GFX_SYNC, 0, 0);
816
817 ws->cs_add_buffer(cs[i], gds_bo[i], domain,
818 RADEON_USAGE_READWRITE, 0);
819 ws->cs_flush(cs[i], PIPE_FLUSH_ASYNC, NULL);
820 }
821 }
822 exit(0);
823 }
824
825 static void si_disk_cache_create(struct si_screen *sscreen)
826 {
827 /* Don't use the cache if shader dumping is enabled. */
828 if (sscreen->debug_flags & DBG_ALL_SHADERS)
829 return;
830
831 struct mesa_sha1 ctx;
832 unsigned char sha1[20];
833 char cache_id[20 * 2 + 1];
834
835 _mesa_sha1_init(&ctx);
836
837 if (!disk_cache_get_function_identifier(si_disk_cache_create, &ctx) ||
838 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo,
839 &ctx))
840 return;
841
842 _mesa_sha1_final(&ctx, sha1);
843 disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
844
845 /* These flags affect shader compilation. */
846 #define ALL_FLAGS (DBG(FS_CORRECT_DERIVS_AFTER_KILL) | \
847 DBG(SI_SCHED) | \
848 DBG(GISEL) | \
849 DBG(UNSAFE_MATH))
850 uint64_t shader_debug_flags = sscreen->debug_flags &
851 ALL_FLAGS;
852
853 /* Add the high bits of 32-bit addresses, which affects
854 * how 32-bit addresses are expanded to 64 bits.
855 */
856 STATIC_ASSERT(ALL_FLAGS <= UINT_MAX);
857 assert((int16_t)sscreen->info.address32_hi == (int32_t)sscreen->info.address32_hi);
858 shader_debug_flags |= (uint64_t)(sscreen->info.address32_hi & 0xffff) << 32;
859
860 if (sscreen->options.enable_nir)
861 shader_debug_flags |= 1ull << 48;
862
863 sscreen->disk_shader_cache =
864 disk_cache_create(sscreen->info.name,
865 cache_id,
866 shader_debug_flags);
867 }
868
869 static void si_set_max_shader_compiler_threads(struct pipe_screen *screen,
870 unsigned max_threads)
871 {
872 struct si_screen *sscreen = (struct si_screen *)screen;
873
874 /* This function doesn't allow a greater number of threads than
875 * the queue had at its creation. */
876 util_queue_adjust_num_threads(&sscreen->shader_compiler_queue,
877 max_threads);
878 /* Don't change the number of threads on the low priority queue. */
879 }
880
881 static bool si_is_parallel_shader_compilation_finished(struct pipe_screen *screen,
882 void *shader,
883 unsigned shader_type)
884 {
885 if (shader_type == PIPE_SHADER_COMPUTE) {
886 struct si_compute *cs = (struct si_compute*)shader;
887
888 return util_queue_fence_is_signalled(&cs->ready);
889 }
890 struct si_shader_selector *sel = (struct si_shader_selector *)shader;
891
892 return util_queue_fence_is_signalled(&sel->ready);
893 }
894
895 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
896 const struct pipe_screen_config *config)
897 {
898 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
899 unsigned hw_threads, num_comp_hi_threads, num_comp_lo_threads, i;
900
901 if (!sscreen) {
902 return NULL;
903 }
904
905 sscreen->ws = ws;
906 ws->query_info(ws, &sscreen->info);
907
908 if (sscreen->info.chip_class >= GFX9) {
909 sscreen->se_tile_repeat = 32 * sscreen->info.max_se;
910 } else {
911 ac_get_raster_config(&sscreen->info,
912 &sscreen->pa_sc_raster_config,
913 &sscreen->pa_sc_raster_config_1,
914 &sscreen->se_tile_repeat);
915 }
916
917 sscreen->debug_flags = debug_get_flags_option("R600_DEBUG",
918 debug_options, 0);
919 sscreen->debug_flags |= debug_get_flags_option("AMD_DEBUG",
920 debug_options, 0);
921
922 /* Set functions first. */
923 sscreen->b.context_create = si_pipe_create_context;
924 sscreen->b.destroy = si_destroy_screen;
925 sscreen->b.set_max_shader_compiler_threads =
926 si_set_max_shader_compiler_threads;
927 sscreen->b.is_parallel_shader_compilation_finished =
928 si_is_parallel_shader_compilation_finished;
929
930 si_init_screen_get_functions(sscreen);
931 si_init_screen_buffer_functions(sscreen);
932 si_init_screen_fence_functions(sscreen);
933 si_init_screen_state_functions(sscreen);
934 si_init_screen_texture_functions(sscreen);
935 si_init_screen_query_functions(sscreen);
936
937 /* Set these flags in debug_flags early, so that the shader cache takes
938 * them into account.
939 */
940 if (driQueryOptionb(config->options,
941 "glsl_correct_derivatives_after_discard"))
942 sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
943 if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
944 sscreen->debug_flags |= DBG(SI_SCHED);
945
946 if (sscreen->debug_flags & DBG(INFO))
947 ac_print_gpu_info(&sscreen->info);
948
949 slab_create_parent(&sscreen->pool_transfers,
950 sizeof(struct si_transfer), 64);
951
952 sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
953 if (sscreen->force_aniso >= 0) {
954 printf("radeonsi: Forcing anisotropy filter to %ix\n",
955 /* round down to a power of two */
956 1 << util_logbase2(sscreen->force_aniso));
957 }
958
959 (void) mtx_init(&sscreen->aux_context_lock, mtx_plain);
960 (void) mtx_init(&sscreen->gpu_load_mutex, mtx_plain);
961
962 si_init_gs_info(sscreen);
963 if (!si_init_shader_cache(sscreen)) {
964 FREE(sscreen);
965 return NULL;
966 }
967
968 si_disk_cache_create(sscreen);
969
970 /* Determine the number of shader compiler threads. */
971 hw_threads = sysconf(_SC_NPROCESSORS_ONLN);
972
973 if (hw_threads >= 12) {
974 num_comp_hi_threads = hw_threads * 3 / 4;
975 num_comp_lo_threads = hw_threads / 3;
976 } else if (hw_threads >= 6) {
977 num_comp_hi_threads = hw_threads - 2;
978 num_comp_lo_threads = hw_threads / 2;
979 } else if (hw_threads >= 2) {
980 num_comp_hi_threads = hw_threads - 1;
981 num_comp_lo_threads = hw_threads / 2;
982 } else {
983 num_comp_hi_threads = 1;
984 num_comp_lo_threads = 1;
985 }
986
987 num_comp_hi_threads = MIN2(num_comp_hi_threads,
988 ARRAY_SIZE(sscreen->compiler));
989 num_comp_lo_threads = MIN2(num_comp_lo_threads,
990 ARRAY_SIZE(sscreen->compiler_lowp));
991
992 if (!util_queue_init(&sscreen->shader_compiler_queue, "sh",
993 64, num_comp_hi_threads,
994 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
995 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY)) {
996 si_destroy_shader_cache(sscreen);
997 FREE(sscreen);
998 return NULL;
999 }
1000
1001 if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
1002 "shlo",
1003 64, num_comp_lo_threads,
1004 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1005 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY |
1006 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
1007 si_destroy_shader_cache(sscreen);
1008 FREE(sscreen);
1009 return NULL;
1010 }
1011
1012 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1013 si_init_perfcounters(sscreen);
1014
1015 /* Determine tessellation ring info. */
1016 bool double_offchip_buffers = sscreen->info.chip_class >= CIK &&
1017 sscreen->info.family != CHIP_CARRIZO &&
1018 sscreen->info.family != CHIP_STONEY;
1019 /* This must be one less than the maximum number due to a hw limitation.
1020 * Various hardware bugs in SI, CIK, and GFX9 need this.
1021 */
1022 unsigned max_offchip_buffers_per_se;
1023
1024 /* Only certain chips can use the maximum value. */
1025 if (sscreen->info.family == CHIP_VEGA12 ||
1026 sscreen->info.family == CHIP_VEGA20)
1027 max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1028 else
1029 max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
1030
1031 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1032 sscreen->info.max_se;
1033 unsigned offchip_granularity;
1034
1035 /* Hawaii has a bug with offchip buffers > 256 that can be worked
1036 * around by setting 4K granularity.
1037 */
1038 if (sscreen->info.family == CHIP_HAWAII) {
1039 sscreen->tess_offchip_block_dw_size = 4096;
1040 offchip_granularity = V_03093C_X_4K_DWORDS;
1041 } else {
1042 sscreen->tess_offchip_block_dw_size = 8192;
1043 offchip_granularity = V_03093C_X_8K_DWORDS;
1044 }
1045
1046 sscreen->tess_factor_ring_size = 32768 * sscreen->info.max_se;
1047 assert(((sscreen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
1048 sscreen->tess_offchip_ring_size = max_offchip_buffers *
1049 sscreen->tess_offchip_block_dw_size * 4;
1050
1051 if (sscreen->info.chip_class >= CIK) {
1052 if (sscreen->info.chip_class >= VI)
1053 --max_offchip_buffers;
1054 sscreen->vgt_hs_offchip_param =
1055 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1056 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1057 } else {
1058 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
1059 sscreen->vgt_hs_offchip_param =
1060 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1061 }
1062
1063 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
1064 * on SI. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
1065 * SPI_VS_OUT_CONFIG. So only enable CI CLEAR_STATE on amdgpu kernel.*/
1066 sscreen->has_clear_state = sscreen->info.chip_class >= CIK &&
1067 sscreen->info.drm_major == 3;
1068
1069 sscreen->has_distributed_tess =
1070 sscreen->info.chip_class >= VI &&
1071 sscreen->info.max_se >= 2;
1072
1073 sscreen->has_draw_indirect_multi =
1074 (sscreen->info.family >= CHIP_POLARIS10) ||
1075 (sscreen->info.chip_class == VI &&
1076 sscreen->info.pfp_fw_version >= 121 &&
1077 sscreen->info.me_fw_version >= 87) ||
1078 (sscreen->info.chip_class == CIK &&
1079 sscreen->info.pfp_fw_version >= 211 &&
1080 sscreen->info.me_fw_version >= 173) ||
1081 (sscreen->info.chip_class == SI &&
1082 sscreen->info.pfp_fw_version >= 79 &&
1083 sscreen->info.me_fw_version >= 142);
1084
1085 sscreen->has_out_of_order_rast = sscreen->info.chip_class >= VI &&
1086 sscreen->info.max_se >= 2 &&
1087 !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER));
1088 sscreen->assume_no_z_fights =
1089 driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
1090 sscreen->commutative_blend_add =
1091 driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
1092
1093 {
1094 #define OPT_BOOL(name, dflt, description) \
1095 sscreen->options.name = \
1096 driQueryOptionb(config->options, "radeonsi_"#name);
1097 #include "si_debug_options.h"
1098 }
1099
1100 sscreen->has_msaa_sample_loc_bug = (sscreen->info.family >= CHIP_POLARIS10 &&
1101 sscreen->info.family <= CHIP_POLARIS12) ||
1102 sscreen->info.family == CHIP_VEGA10 ||
1103 sscreen->info.family == CHIP_RAVEN;
1104 sscreen->has_ls_vgpr_init_bug = sscreen->info.family == CHIP_VEGA10 ||
1105 sscreen->info.family == CHIP_RAVEN;
1106 sscreen->has_dcc_constant_encode = sscreen->info.family == CHIP_RAVEN2;
1107
1108 /* Only enable primitive binning on APUs by default. */
1109 sscreen->dpbb_allowed = sscreen->info.family == CHIP_RAVEN ||
1110 sscreen->info.family == CHIP_RAVEN2;
1111
1112 sscreen->dfsm_allowed = sscreen->info.family == CHIP_RAVEN ||
1113 sscreen->info.family == CHIP_RAVEN2;
1114
1115 /* Process DPBB enable flags. */
1116 if (sscreen->debug_flags & DBG(DPBB)) {
1117 sscreen->dpbb_allowed = true;
1118 if (sscreen->debug_flags & DBG(DFSM))
1119 sscreen->dfsm_allowed = true;
1120 }
1121
1122 /* Process DPBB disable flags. */
1123 if (sscreen->debug_flags & DBG(NO_DPBB)) {
1124 sscreen->dpbb_allowed = false;
1125 sscreen->dfsm_allowed = false;
1126 } else if (sscreen->debug_flags & DBG(NO_DFSM)) {
1127 sscreen->dfsm_allowed = false;
1128 }
1129
1130 /* While it would be nice not to have this flag, we are constrained
1131 * by the reality that LLVM 5.0 doesn't have working VGPR indexing
1132 * on GFX9.
1133 */
1134 sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class <= VI;
1135
1136 /* Some chips have RB+ registers, but don't support RB+. Those must
1137 * always disable it.
1138 */
1139 if (sscreen->info.family == CHIP_STONEY ||
1140 sscreen->info.chip_class >= GFX9) {
1141 sscreen->has_rbplus = true;
1142
1143 sscreen->rbplus_allowed =
1144 !(sscreen->debug_flags & DBG(NO_RB_PLUS)) &&
1145 (sscreen->info.family == CHIP_STONEY ||
1146 sscreen->info.family == CHIP_VEGA12 ||
1147 sscreen->info.family == CHIP_RAVEN ||
1148 sscreen->info.family == CHIP_RAVEN2);
1149 }
1150
1151 sscreen->dcc_msaa_allowed =
1152 !(sscreen->debug_flags & DBG(NO_DCC_MSAA));
1153
1154 sscreen->cpdma_prefetch_writes_memory = sscreen->info.chip_class <= VI;
1155
1156 (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1157 sscreen->use_monolithic_shaders =
1158 (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
1159
1160 sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
1161 SI_CONTEXT_INV_VMEM_L1;
1162 if (sscreen->info.chip_class <= VI) {
1163 sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_GLOBAL_L2;
1164 sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1165 }
1166
1167 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1168 sscreen->debug_flags |= DBG_ALL_SHADERS;
1169
1170 /* Syntax:
1171 * EQAA=s,z,c
1172 * Example:
1173 * EQAA=8,4,2
1174
1175 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1176 * Constraints:
1177 * s >= z >= c (ignoring this only wastes memory)
1178 * s = [2..16]
1179 * z = [2..8]
1180 * c = [2..8]
1181 *
1182 * Only MSAA color and depth buffers are overriden.
1183 */
1184 if (sscreen->info.has_eqaa_surface_allocator) {
1185 const char *eqaa = debug_get_option("EQAA", NULL);
1186 unsigned s,z,f;
1187
1188 if (eqaa && sscanf(eqaa, "%u,%u,%u", &s, &z, &f) == 3 && s && z && f) {
1189 sscreen->eqaa_force_coverage_samples = s;
1190 sscreen->eqaa_force_z_samples = z;
1191 sscreen->eqaa_force_color_samples = f;
1192 }
1193 }
1194
1195 for (i = 0; i < num_comp_hi_threads; i++)
1196 si_init_compiler(sscreen, &sscreen->compiler[i]);
1197 for (i = 0; i < num_comp_lo_threads; i++)
1198 si_init_compiler(sscreen, &sscreen->compiler_lowp[i]);
1199
1200 /* Create the auxiliary context. This must be done last. */
1201 sscreen->aux_context = si_create_context(
1202 &sscreen->b, sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0);
1203 if (sscreen->options.aux_debug) {
1204 struct u_log_context *log = CALLOC_STRUCT(u_log_context);
1205 u_log_context_init(log);
1206 sscreen->aux_context->set_log_context(sscreen->aux_context, log);
1207 }
1208
1209 if (sscreen->debug_flags & DBG(TEST_DMA))
1210 si_test_dma(sscreen);
1211
1212 if (sscreen->debug_flags & DBG(TEST_DMA_PERF)) {
1213 si_test_dma_perf(sscreen);
1214 }
1215
1216 if (sscreen->debug_flags & (DBG(TEST_VMFAULT_CP) |
1217 DBG(TEST_VMFAULT_SDMA) |
1218 DBG(TEST_VMFAULT_SHADER)))
1219 si_test_vmfault(sscreen);
1220
1221 if (sscreen->debug_flags & DBG(TEST_GDS))
1222 si_test_gds((struct si_context*)sscreen->aux_context);
1223
1224 if (sscreen->debug_flags & DBG(TEST_GDS_MM)) {
1225 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1226 32 * 1024, 4, RADEON_DOMAIN_GDS);
1227 }
1228 if (sscreen->debug_flags & DBG(TEST_GDS_OA_MM)) {
1229 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1230 4, 1, RADEON_DOMAIN_OA);
1231 }
1232
1233 return &sscreen->b;
1234 }