2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "driver_ddebug/dd_util.h"
29 #include "gallium/winsys/amdgpu/drm/amdgpu_public.h"
30 #include "gallium/winsys/radeon/drm/radeon_drm_public.h"
31 #include "radeon/radeon_uvd.h"
32 #include "si_compute.h"
33 #include "si_public.h"
34 #include "si_shader_internal.h"
36 #include "util/disk_cache.h"
37 #include "util/u_log.h"
38 #include "util/u_memory.h"
39 #include "util/u_suballoc.h"
40 #include "util/u_tests.h"
41 #include "util/u_upload_mgr.h"
42 #include "util/xmlconfig.h"
43 #include "vl/vl_decoder.h"
47 static struct pipe_context
*si_create_context(struct pipe_screen
*screen
, unsigned flags
);
49 static const struct debug_named_value debug_options
[] = {
50 /* Shader logging options: */
51 {"vs", DBG(VS
), "Print vertex shaders"},
52 {"ps", DBG(PS
), "Print pixel shaders"},
53 {"gs", DBG(GS
), "Print geometry shaders"},
54 {"tcs", DBG(TCS
), "Print tessellation control shaders"},
55 {"tes", DBG(TES
), "Print tessellation evaluation shaders"},
56 {"cs", DBG(CS
), "Print compute shaders"},
57 {"noir", DBG(NO_IR
), "Don't print the LLVM IR"},
58 {"nonir", DBG(NO_NIR
), "Don't print NIR when printing shaders"},
59 {"noasm", DBG(NO_ASM
), "Don't print disassembled shaders"},
60 {"preoptir", DBG(PREOPT_IR
), "Print the LLVM IR before initial optimizations"},
62 /* Shader compiler options the shader cache should be aware of: */
63 {"gisel", DBG(GISEL
), "Enable LLVM global instruction selector."},
64 {"w32ge", DBG(W32_GE
), "Use Wave32 for vertex, tessellation, and geometry shaders."},
65 {"w32ps", DBG(W32_PS
), "Use Wave32 for pixel shaders."},
66 {"w32cs", DBG(W32_CS
), "Use Wave32 for computes shaders."},
67 {"w64ge", DBG(W64_GE
), "Use Wave64 for vertex, tessellation, and geometry shaders."},
68 {"w64ps", DBG(W64_PS
), "Use Wave64 for pixel shaders."},
69 {"w64cs", DBG(W64_CS
), "Use Wave64 for computes shaders."},
71 /* Shader compiler options (with no effect on the shader cache): */
72 {"checkir", DBG(CHECK_IR
), "Enable additional sanity checks on shader IR"},
73 {"mono", DBG(MONOLITHIC_SHADERS
), "Use old-style monolithic shaders compiled on demand"},
74 {"nooptvariant", DBG(NO_OPT_VARIANT
), "Disable compiling optimized shader variants."},
76 /* Information logging options: */
77 {"info", DBG(INFO
), "Print driver information"},
78 {"tex", DBG(TEX
), "Print texture info"},
79 {"compute", DBG(COMPUTE
), "Print compute info"},
80 {"vm", DBG(VM
), "Print virtual addresses when creating resources"},
81 {"cache_stats", DBG(CACHE_STATS
), "Print shader cache statistics."},
84 {"forcedma", DBG(FORCE_SDMA
), "Use SDMA for all operations when possible."},
85 {"nodma", DBG(NO_SDMA
), "Disable SDMA"},
86 {"nodmaclear", DBG(NO_SDMA_CLEARS
), "Disable SDMA clears"},
87 {"nodmacopyimage", DBG(NO_SDMA_COPY_IMAGE
), "Disable SDMA image copies"},
88 {"nowc", DBG(NO_WC
), "Disable GTT write combining"},
89 {"check_vm", DBG(CHECK_VM
), "Check VM faults and dump debug info."},
90 {"reserve_vmid", DBG(RESERVE_VMID
), "Force VMID reservation per context."},
91 {"zerovram", DBG(ZERO_VRAM
), "Clear VRAM allocations."},
93 /* 3D engine options: */
94 {"nogfx", DBG(NO_GFX
), "Disable graphics. Only multimedia compute paths can be used."},
95 {"nongg", DBG(NO_NGG
), "Disable NGG and use the legacy pipeline."},
96 {"nggc", DBG(ALWAYS_NGG_CULLING
), "Always use NGG culling even when it can hurt."},
97 {"nonggc", DBG(NO_NGG_CULLING
), "Disable NGG culling."},
98 {"alwayspd", DBG(ALWAYS_PD
), "Always enable the primitive discard compute shader."},
99 {"pd", DBG(PD
), "Enable the primitive discard compute shader for large draw calls."},
100 {"nopd", DBG(NO_PD
), "Disable the primitive discard compute shader."},
101 {"switch_on_eop", DBG(SWITCH_ON_EOP
), "Program WD/IA to switch on end-of-packet."},
102 {"nooutoforder", DBG(NO_OUT_OF_ORDER
), "Disable out-of-order rasterization"},
103 {"nodpbb", DBG(NO_DPBB
), "Disable DPBB."},
104 {"nodfsm", DBG(NO_DFSM
), "Disable DFSM."},
105 {"dpbb", DBG(DPBB
), "Enable DPBB."},
106 {"dfsm", DBG(DFSM
), "Enable DFSM."},
107 {"nohyperz", DBG(NO_HYPERZ
), "Disable Hyper-Z"},
108 {"norbplus", DBG(NO_RB_PLUS
), "Disable RB+."},
109 {"no2d", DBG(NO_2D_TILING
), "Disable 2D tiling"},
110 {"notiling", DBG(NO_TILING
), "Disable tiling"},
111 {"nodcc", DBG(NO_DCC
), "Disable DCC."},
112 {"nodccclear", DBG(NO_DCC_CLEAR
), "Disable DCC fast clear."},
113 {"nodccfb", DBG(NO_DCC_FB
), "Disable separate DCC on the main framebuffer"},
114 {"nodccmsaa", DBG(NO_DCC_MSAA
), "Disable DCC for MSAA"},
115 {"nofmask", DBG(NO_FMASK
), "Disable MSAA compression"},
117 DEBUG_NAMED_VALUE_END
/* must be last */
120 static const struct debug_named_value test_options
[] = {
122 {"testdma", DBG(TEST_DMA
), "Invoke SDMA tests and exit."},
123 {"testvmfaultcp", DBG(TEST_VMFAULT_CP
), "Invoke a CP VM fault test and exit."},
124 {"testvmfaultsdma", DBG(TEST_VMFAULT_SDMA
), "Invoke a SDMA VM fault test and exit."},
125 {"testvmfaultshader", DBG(TEST_VMFAULT_SHADER
), "Invoke a shader VM fault test and exit."},
126 {"testdmaperf", DBG(TEST_DMA_PERF
), "Test DMA performance"},
127 {"testgds", DBG(TEST_GDS
), "Test GDS."},
128 {"testgdsmm", DBG(TEST_GDS_MM
), "Test GDS memory management."},
129 {"testgdsoamm", DBG(TEST_GDS_OA_MM
), "Test GDS OA memory management."},
131 DEBUG_NAMED_VALUE_END
/* must be last */
134 void si_init_compiler(struct si_screen
*sscreen
, struct ac_llvm_compiler
*compiler
)
136 /* Only create the less-optimizing version of the compiler on APUs
137 * predating Ryzen (Raven). */
138 bool create_low_opt_compiler
=
139 !sscreen
->info
.has_dedicated_vram
&& sscreen
->info
.chip_class
<= GFX8
;
141 enum ac_target_machine_options tm_options
=
142 (sscreen
->debug_flags
& DBG(GISEL
) ? AC_TM_ENABLE_GLOBAL_ISEL
: 0) |
143 (sscreen
->info
.chip_class
>= GFX9
? AC_TM_FORCE_ENABLE_XNACK
: 0) |
144 (sscreen
->info
.chip_class
< GFX9
? AC_TM_FORCE_DISABLE_XNACK
: 0) |
145 (!sscreen
->llvm_has_working_vgpr_indexing
? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH
: 0) |
146 (sscreen
->debug_flags
& DBG(CHECK_IR
) ? AC_TM_CHECK_IR
: 0) |
147 (create_low_opt_compiler
? AC_TM_CREATE_LOW_OPT
: 0);
150 ac_init_llvm_compiler(compiler
, sscreen
->info
.family
, tm_options
);
151 compiler
->passes
= ac_create_llvm_passes(compiler
->tm
);
153 if (compiler
->tm_wave32
)
154 compiler
->passes_wave32
= ac_create_llvm_passes(compiler
->tm_wave32
);
155 if (compiler
->low_opt_tm
)
156 compiler
->low_opt_passes
= ac_create_llvm_passes(compiler
->low_opt_tm
);
159 static void si_destroy_compiler(struct ac_llvm_compiler
*compiler
)
161 ac_destroy_llvm_compiler(compiler
);
167 static void si_destroy_context(struct pipe_context
*context
)
169 struct si_context
*sctx
= (struct si_context
*)context
;
172 /* Unreference the framebuffer normally to disable related logic
175 struct pipe_framebuffer_state fb
= {};
176 if (context
->set_framebuffer_state
)
177 context
->set_framebuffer_state(context
, &fb
);
179 si_release_all_descriptors(sctx
);
181 if (sctx
->chip_class
>= GFX10
&& sctx
->has_graphics
)
182 gfx10_destroy_query(sctx
);
184 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
185 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
186 pipe_resource_reference(&sctx
->tess_rings
, NULL
);
187 pipe_resource_reference(&sctx
->null_const_buf
.buffer
, NULL
);
188 pipe_resource_reference(&sctx
->sample_pos_buffer
, NULL
);
189 si_resource_reference(&sctx
->border_color_buffer
, NULL
);
190 free(sctx
->border_color_table
);
191 si_resource_reference(&sctx
->scratch_buffer
, NULL
);
192 si_resource_reference(&sctx
->compute_scratch_buffer
, NULL
);
193 si_resource_reference(&sctx
->wait_mem_scratch
, NULL
);
194 si_resource_reference(&sctx
->small_prim_cull_info_buf
, NULL
);
196 si_pm4_free_state(sctx
, sctx
->init_config
, ~0);
197 if (sctx
->init_config_gs_rings
)
198 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
199 for (i
= 0; i
< ARRAY_SIZE(sctx
->vgt_shader_config
); i
++)
200 si_pm4_delete_state(sctx
, vgt_shader_config
, sctx
->vgt_shader_config
[i
]);
202 if (sctx
->fixed_func_tcs_shader
.cso
)
203 sctx
->b
.delete_tcs_state(&sctx
->b
, sctx
->fixed_func_tcs_shader
.cso
);
204 if (sctx
->custom_dsa_flush
)
205 sctx
->b
.delete_depth_stencil_alpha_state(&sctx
->b
, sctx
->custom_dsa_flush
);
206 if (sctx
->custom_blend_resolve
)
207 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_resolve
);
208 if (sctx
->custom_blend_fmask_decompress
)
209 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_fmask_decompress
);
210 if (sctx
->custom_blend_eliminate_fastclear
)
211 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_eliminate_fastclear
);
212 if (sctx
->custom_blend_dcc_decompress
)
213 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_dcc_decompress
);
214 if (sctx
->vs_blit_pos
)
215 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_pos
);
216 if (sctx
->vs_blit_pos_layered
)
217 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_pos_layered
);
218 if (sctx
->vs_blit_color
)
219 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_color
);
220 if (sctx
->vs_blit_color_layered
)
221 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_color_layered
);
222 if (sctx
->vs_blit_texcoord
)
223 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_texcoord
);
224 if (sctx
->cs_clear_buffer
)
225 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_clear_buffer
);
226 if (sctx
->cs_copy_buffer
)
227 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_copy_buffer
);
228 if (sctx
->cs_copy_image
)
229 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_copy_image
);
230 if (sctx
->cs_copy_image_1d_array
)
231 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_copy_image_1d_array
);
232 if (sctx
->cs_clear_render_target
)
233 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_clear_render_target
);
234 if (sctx
->cs_clear_render_target_1d_array
)
235 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_clear_render_target_1d_array
);
236 if (sctx
->cs_clear_12bytes_buffer
)
237 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_clear_12bytes_buffer
);
238 if (sctx
->cs_dcc_retile
)
239 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_dcc_retile
);
241 for (unsigned i
= 0; i
< ARRAY_SIZE(sctx
->cs_fmask_expand
); i
++) {
242 for (unsigned j
= 0; j
< ARRAY_SIZE(sctx
->cs_fmask_expand
[i
]); j
++) {
243 if (sctx
->cs_fmask_expand
[i
][j
]) {
244 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_fmask_expand
[i
][j
]);
250 util_blitter_destroy(sctx
->blitter
);
252 /* Release DCC stats. */
253 for (int i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++) {
254 assert(!sctx
->dcc_stats
[i
].query_active
);
256 for (int j
= 0; j
< ARRAY_SIZE(sctx
->dcc_stats
[i
].ps_stats
); j
++)
257 if (sctx
->dcc_stats
[i
].ps_stats
[j
])
258 sctx
->b
.destroy_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[j
]);
260 si_texture_reference(&sctx
->dcc_stats
[i
].tex
, NULL
);
263 if (sctx
->query_result_shader
)
264 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->query_result_shader
);
265 if (sctx
->sh_query_result_shader
)
266 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->sh_query_result_shader
);
269 sctx
->ws
->cs_destroy(sctx
->gfx_cs
);
271 sctx
->ws
->cs_destroy(sctx
->sdma_cs
);
273 sctx
->ws
->ctx_destroy(sctx
->ctx
);
275 if (sctx
->b
.stream_uploader
)
276 u_upload_destroy(sctx
->b
.stream_uploader
);
277 if (sctx
->b
.const_uploader
)
278 u_upload_destroy(sctx
->b
.const_uploader
);
279 if (sctx
->cached_gtt_allocator
)
280 u_upload_destroy(sctx
->cached_gtt_allocator
);
282 slab_destroy_child(&sctx
->pool_transfers
);
283 slab_destroy_child(&sctx
->pool_transfers_unsync
);
285 if (sctx
->allocator_zeroed_memory
)
286 u_suballocator_destroy(sctx
->allocator_zeroed_memory
);
288 sctx
->ws
->fence_reference(&sctx
->last_gfx_fence
, NULL
);
289 sctx
->ws
->fence_reference(&sctx
->last_sdma_fence
, NULL
);
290 sctx
->ws
->fence_reference(&sctx
->last_ib_barrier_fence
, NULL
);
291 si_resource_reference(&sctx
->eop_bug_scratch
, NULL
);
292 si_resource_reference(&sctx
->index_ring
, NULL
);
293 si_resource_reference(&sctx
->barrier_buf
, NULL
);
294 si_resource_reference(&sctx
->last_ib_barrier_buf
, NULL
);
295 pb_reference(&sctx
->gds
, NULL
);
296 pb_reference(&sctx
->gds_oa
, NULL
);
298 si_destroy_compiler(&sctx
->compiler
);
300 si_saved_cs_reference(&sctx
->current_saved_cs
, NULL
);
302 _mesa_hash_table_destroy(sctx
->tex_handles
, NULL
);
303 _mesa_hash_table_destroy(sctx
->img_handles
, NULL
);
305 util_dynarray_fini(&sctx
->resident_tex_handles
);
306 util_dynarray_fini(&sctx
->resident_img_handles
);
307 util_dynarray_fini(&sctx
->resident_tex_needs_color_decompress
);
308 util_dynarray_fini(&sctx
->resident_img_needs_color_decompress
);
309 util_dynarray_fini(&sctx
->resident_tex_needs_depth_decompress
);
310 si_unref_sdma_uploads(sctx
);
311 free(sctx
->sdma_uploads
);
315 static enum pipe_reset_status
si_get_reset_status(struct pipe_context
*ctx
)
317 struct si_context
*sctx
= (struct si_context
*)ctx
;
318 struct si_screen
*sscreen
= sctx
->screen
;
319 enum pipe_reset_status status
= sctx
->ws
->ctx_query_reset_status(sctx
->ctx
);
321 if (status
!= PIPE_NO_RESET
) {
322 /* Call the state tracker to set a no-op API dispatch. */
323 if (sctx
->device_reset_callback
.reset
) {
324 sctx
->device_reset_callback
.reset(sctx
->device_reset_callback
.data
, status
);
327 /* Re-create the auxiliary context, because it won't submit
328 * any new IBs due to a GPU reset.
330 simple_mtx_lock(&sscreen
->aux_context_lock
);
332 struct u_log_context
*aux_log
= ((struct si_context
*)sscreen
->aux_context
)->log
;
333 sscreen
->aux_context
->set_log_context(sscreen
->aux_context
, NULL
);
334 sscreen
->aux_context
->destroy(sscreen
->aux_context
);
336 sscreen
->aux_context
= si_create_context(
337 &sscreen
->b
, (sscreen
->options
.aux_debug
? PIPE_CONTEXT_DEBUG
: 0) |
338 (sscreen
->info
.has_graphics
? 0 : PIPE_CONTEXT_COMPUTE_ONLY
));
339 sscreen
->aux_context
->set_log_context(sscreen
->aux_context
, aux_log
);
340 simple_mtx_unlock(&sscreen
->aux_context_lock
);
345 static void si_set_device_reset_callback(struct pipe_context
*ctx
,
346 const struct pipe_device_reset_callback
*cb
)
348 struct si_context
*sctx
= (struct si_context
*)ctx
;
351 sctx
->device_reset_callback
= *cb
;
353 memset(&sctx
->device_reset_callback
, 0, sizeof(sctx
->device_reset_callback
));
356 /* Apitrace profiling:
357 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
358 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
359 * and remember its number.
360 * 3) In Mesa, enable queries and performance counters around that draw
361 * call and print the results.
362 * 4) glretrace --benchmark --markers ..
364 static void si_emit_string_marker(struct pipe_context
*ctx
, const char *string
, int len
)
366 struct si_context
*sctx
= (struct si_context
*)ctx
;
368 dd_parse_apitrace_marker(string
, len
, &sctx
->apitrace_call_number
);
371 u_log_printf(sctx
->log
, "\nString marker: %*s\n", len
, string
);
374 static void si_set_debug_callback(struct pipe_context
*ctx
, const struct pipe_debug_callback
*cb
)
376 struct si_context
*sctx
= (struct si_context
*)ctx
;
377 struct si_screen
*screen
= sctx
->screen
;
379 util_queue_finish(&screen
->shader_compiler_queue
);
380 util_queue_finish(&screen
->shader_compiler_queue_low_priority
);
385 memset(&sctx
->debug
, 0, sizeof(sctx
->debug
));
388 static void si_set_log_context(struct pipe_context
*ctx
, struct u_log_context
*log
)
390 struct si_context
*sctx
= (struct si_context
*)ctx
;
394 u_log_add_auto_logger(log
, si_auto_log_cs
, sctx
);
397 static void si_set_context_param(struct pipe_context
*ctx
, enum pipe_context_param param
,
400 struct radeon_winsys
*ws
= ((struct si_context
*)ctx
)->ws
;
403 case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE
:
404 ws
->pin_threads_to_L3_cache(ws
, value
);
410 static struct pipe_context
*si_create_context(struct pipe_screen
*screen
, unsigned flags
)
412 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
413 STATIC_ASSERT(DBG_COUNT
<= 64);
415 /* Don't create a context if it's not compute-only and hw is compute-only. */
416 if (!sscreen
->info
.has_graphics
&& !(flags
& PIPE_CONTEXT_COMPUTE_ONLY
))
419 struct si_context
*sctx
= CALLOC_STRUCT(si_context
);
420 struct radeon_winsys
*ws
= sscreen
->ws
;
422 bool stop_exec_on_failure
= (flags
& PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET
) != 0;
427 sctx
->has_graphics
= sscreen
->info
.chip_class
== GFX6
|| !(flags
& PIPE_CONTEXT_COMPUTE_ONLY
);
429 if (flags
& PIPE_CONTEXT_DEBUG
)
430 sscreen
->record_llvm_ir
= true; /* racy but not critical */
432 sctx
->b
.screen
= screen
; /* this must be set first */
434 sctx
->b
.destroy
= si_destroy_context
;
435 sctx
->screen
= sscreen
; /* Easy accessing of screen/winsys. */
436 sctx
->is_debug
= (flags
& PIPE_CONTEXT_DEBUG
) != 0;
438 slab_create_child(&sctx
->pool_transfers
, &sscreen
->pool_transfers
);
439 slab_create_child(&sctx
->pool_transfers_unsync
, &sscreen
->pool_transfers
);
441 sctx
->ws
= sscreen
->ws
;
442 sctx
->family
= sscreen
->info
.family
;
443 sctx
->chip_class
= sscreen
->info
.chip_class
;
445 if (sctx
->chip_class
== GFX7
|| sctx
->chip_class
== GFX8
|| sctx
->chip_class
== GFX9
) {
446 sctx
->eop_bug_scratch
= si_resource(pipe_buffer_create(
447 &sscreen
->b
, 0, PIPE_USAGE_DEFAULT
, 16 * sscreen
->info
.num_render_backends
));
448 if (!sctx
->eop_bug_scratch
)
452 /* Initialize context allocators. */
453 sctx
->allocator_zeroed_memory
=
454 u_suballocator_create(&sctx
->b
, 128 * 1024, 0, PIPE_USAGE_DEFAULT
,
455 SI_RESOURCE_FLAG_UNMAPPABLE
| SI_RESOURCE_FLAG_CLEAR
, false);
456 if (!sctx
->allocator_zeroed_memory
)
459 sctx
->b
.stream_uploader
=
460 u_upload_create(&sctx
->b
, 1024 * 1024, 0, PIPE_USAGE_STREAM
, SI_RESOURCE_FLAG_READ_ONLY
);
461 if (!sctx
->b
.stream_uploader
)
464 sctx
->cached_gtt_allocator
= u_upload_create(&sctx
->b
, 16 * 1024, 0, PIPE_USAGE_STAGING
, 0);
465 if (!sctx
->cached_gtt_allocator
)
468 sctx
->ctx
= sctx
->ws
->ctx_create(sctx
->ws
);
472 if (sscreen
->info
.num_rings
[RING_DMA
] && !(sscreen
->debug_flags
& DBG(NO_SDMA
)) &&
473 /* SDMA causes corruption on RX 580:
474 * https://gitlab.freedesktop.org/mesa/mesa/issues/1399
475 * https://gitlab.freedesktop.org/mesa/mesa/issues/1889
477 (sctx
->chip_class
!= GFX8
|| sscreen
->debug_flags
& DBG(FORCE_SDMA
)) &&
478 /* SDMA timeouts sometimes on gfx10 so disable it for now. See:
479 * https://bugs.freedesktop.org/show_bug.cgi?id=111481
480 * https://gitlab.freedesktop.org/mesa/mesa/issues/1907
482 (sctx
->chip_class
!= GFX10
|| sscreen
->debug_flags
& DBG(FORCE_SDMA
))) {
483 sctx
->sdma_cs
= sctx
->ws
->cs_create(sctx
->ctx
, RING_DMA
, (void *)si_flush_dma_cs
, sctx
,
484 stop_exec_on_failure
);
487 bool use_sdma_upload
= sscreen
->info
.has_dedicated_vram
&& sctx
->sdma_cs
;
488 sctx
->b
.const_uploader
=
489 u_upload_create(&sctx
->b
, 256 * 1024, 0, PIPE_USAGE_DEFAULT
,
490 SI_RESOURCE_FLAG_32BIT
|
491 (use_sdma_upload
? SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA
: 0));
492 if (!sctx
->b
.const_uploader
)
496 u_upload_enable_flush_explicit(sctx
->b
.const_uploader
);
498 sctx
->gfx_cs
= ws
->cs_create(sctx
->ctx
, sctx
->has_graphics
? RING_GFX
: RING_COMPUTE
,
499 (void *)si_flush_gfx_cs
, sctx
, stop_exec_on_failure
);
502 sctx
->border_color_table
= malloc(SI_MAX_BORDER_COLORS
* sizeof(*sctx
->border_color_table
));
503 if (!sctx
->border_color_table
)
506 sctx
->border_color_buffer
= si_resource(pipe_buffer_create(
507 screen
, 0, PIPE_USAGE_DEFAULT
, SI_MAX_BORDER_COLORS
* sizeof(*sctx
->border_color_table
)));
508 if (!sctx
->border_color_buffer
)
511 sctx
->border_color_map
=
512 ws
->buffer_map(sctx
->border_color_buffer
->buf
, NULL
, PIPE_TRANSFER_WRITE
);
513 if (!sctx
->border_color_map
)
516 sctx
->ngg
= sscreen
->use_ngg
;
518 /* Initialize context functions used by graphics and compute. */
519 if (sctx
->chip_class
>= GFX10
)
520 sctx
->emit_cache_flush
= gfx10_emit_cache_flush
;
522 sctx
->emit_cache_flush
= si_emit_cache_flush
;
524 sctx
->b
.emit_string_marker
= si_emit_string_marker
;
525 sctx
->b
.set_debug_callback
= si_set_debug_callback
;
526 sctx
->b
.set_log_context
= si_set_log_context
;
527 sctx
->b
.set_context_param
= si_set_context_param
;
528 sctx
->b
.get_device_reset_status
= si_get_reset_status
;
529 sctx
->b
.set_device_reset_callback
= si_set_device_reset_callback
;
531 si_init_all_descriptors(sctx
);
532 si_init_buffer_functions(sctx
);
533 si_init_clear_functions(sctx
);
534 si_init_blit_functions(sctx
);
535 si_init_compute_functions(sctx
);
536 si_init_compute_blit_functions(sctx
);
537 si_init_debug_functions(sctx
);
538 si_init_fence_functions(sctx
);
539 si_init_query_functions(sctx
);
540 si_init_state_compute_functions(sctx
);
541 si_init_context_texture_functions(sctx
);
543 /* Initialize graphics-only context functions. */
544 if (sctx
->has_graphics
) {
545 if (sctx
->chip_class
>= GFX10
)
546 gfx10_init_query(sctx
);
547 si_init_msaa_functions(sctx
);
548 si_init_shader_functions(sctx
);
549 si_init_state_functions(sctx
);
550 si_init_streamout_functions(sctx
);
551 si_init_viewport_functions(sctx
);
553 sctx
->blitter
= util_blitter_create(&sctx
->b
);
554 if (sctx
->blitter
== NULL
)
556 sctx
->blitter
->skip_viewport_restore
= true;
558 /* Some states are expected to be always non-NULL. */
559 sctx
->noop_blend
= util_blitter_get_noop_blend_state(sctx
->blitter
);
560 sctx
->queued
.named
.blend
= sctx
->noop_blend
;
562 sctx
->noop_dsa
= util_blitter_get_noop_dsa_state(sctx
->blitter
);
563 sctx
->queued
.named
.dsa
= sctx
->noop_dsa
;
565 sctx
->discard_rasterizer_state
= util_blitter_get_discard_rasterizer_state(sctx
->blitter
);
566 sctx
->queued
.named
.rasterizer
= sctx
->discard_rasterizer_state
;
568 si_init_draw_functions(sctx
);
570 /* If aux_context == NULL, we are initializing aux_context right now. */
571 bool is_aux_context
= !sscreen
->aux_context
;
572 si_initialize_prim_discard_tunables(sscreen
, is_aux_context
,
573 &sctx
->prim_discard_vertex_count_threshold
,
574 &sctx
->index_ring_size_per_ib
);
577 /* Initialize SDMA functions. */
578 if (sctx
->chip_class
>= GFX7
)
579 cik_init_sdma_functions(sctx
);
581 sctx
->dma_copy
= si_resource_copy_region
;
583 if (sscreen
->debug_flags
& DBG(FORCE_SDMA
))
584 sctx
->b
.resource_copy_region
= sctx
->dma_copy
;
586 sctx
->sample_mask
= 0xffff;
588 /* Initialize multimedia functions. */
589 if (sscreen
->info
.has_hw_decode
) {
590 sctx
->b
.create_video_codec
= si_uvd_create_decoder
;
591 sctx
->b
.create_video_buffer
= si_video_buffer_create
;
593 sctx
->b
.create_video_codec
= vl_create_decoder
;
594 sctx
->b
.create_video_buffer
= vl_video_buffer_create
;
597 if (sctx
->chip_class
>= GFX9
|| si_compute_prim_discard_enabled(sctx
)) {
598 sctx
->wait_mem_scratch
= si_resource(pipe_buffer_create(screen
, 0, PIPE_USAGE_DEFAULT
, 8));
599 if (!sctx
->wait_mem_scratch
)
602 /* Initialize the memory. */
603 si_cp_write_data(sctx
, sctx
->wait_mem_scratch
, 0, 4, V_370_MEM
, V_370_ME
,
604 &sctx
->wait_mem_number
);
607 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
608 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
609 if (sctx
->chip_class
== GFX7
) {
610 sctx
->null_const_buf
.buffer
=
611 pipe_aligned_buffer_create(screen
, SI_RESOURCE_FLAG_32BIT
, PIPE_USAGE_DEFAULT
, 16,
612 sctx
->screen
->info
.tcc_cache_line_size
);
613 if (!sctx
->null_const_buf
.buffer
)
615 sctx
->null_const_buf
.buffer_size
= sctx
->null_const_buf
.buffer
->width0
;
617 unsigned start_shader
= sctx
->has_graphics
? 0 : PIPE_SHADER_COMPUTE
;
618 for (shader
= start_shader
; shader
< SI_NUM_SHADERS
; shader
++) {
619 for (i
= 0; i
< SI_NUM_CONST_BUFFERS
; i
++) {
620 sctx
->b
.set_constant_buffer(&sctx
->b
, shader
, i
, &sctx
->null_const_buf
);
624 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
, &sctx
->null_const_buf
);
625 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
, &sctx
->null_const_buf
);
626 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
, &sctx
->null_const_buf
);
627 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
, &sctx
->null_const_buf
);
628 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
, &sctx
->null_const_buf
);
631 uint64_t max_threads_per_block
;
632 screen
->get_compute_param(screen
, PIPE_SHADER_IR_NIR
, PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
,
633 &max_threads_per_block
);
635 /* The maximum number of scratch waves. Scratch space isn't divided
636 * evenly between CUs. The number is only a function of the number of CUs.
637 * We can decrease the constant to decrease the scratch buffer size.
639 * sctx->scratch_waves must be >= the maximum posible size of
640 * 1 threadgroup, so that the hw doesn't hang from being unable
643 * The recommended value is 4 per CU at most. Higher numbers don't
644 * bring much benefit, but they still occupy chip resources (think
645 * async compute). I've seen ~2% performance difference between 4 and 32.
647 sctx
->scratch_waves
=
648 MAX2(32 * sscreen
->info
.num_good_compute_units
, max_threads_per_block
/ 64);
650 /* Bindless handles. */
651 sctx
->tex_handles
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
652 sctx
->img_handles
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
654 util_dynarray_init(&sctx
->resident_tex_handles
, NULL
);
655 util_dynarray_init(&sctx
->resident_img_handles
, NULL
);
656 util_dynarray_init(&sctx
->resident_tex_needs_color_decompress
, NULL
);
657 util_dynarray_init(&sctx
->resident_img_needs_color_decompress
, NULL
);
658 util_dynarray_init(&sctx
->resident_tex_needs_depth_decompress
, NULL
);
660 sctx
->sample_pos_buffer
=
661 pipe_buffer_create(sctx
->b
.screen
, 0, PIPE_USAGE_DEFAULT
, sizeof(sctx
->sample_positions
));
662 pipe_buffer_write(&sctx
->b
, sctx
->sample_pos_buffer
, 0, sizeof(sctx
->sample_positions
),
663 &sctx
->sample_positions
);
665 /* this must be last */
666 si_begin_new_gfx_cs(sctx
);
668 if (sctx
->chip_class
== GFX7
) {
669 /* Clear the NULL constant buffer, because loads should return zeros.
670 * Note that this forces CP DMA to be used, because clover deadlocks
671 * for some reason when the compute codepath is used.
673 uint32_t clear_value
= 0;
674 si_clear_buffer(sctx
, sctx
->null_const_buf
.buffer
, 0, sctx
->null_const_buf
.buffer
->width0
,
675 &clear_value
, 4, SI_COHERENCY_SHADER
, true);
679 fprintf(stderr
, "radeonsi: Failed to create a context.\n");
680 si_destroy_context(&sctx
->b
);
684 static struct pipe_context
*si_pipe_create_context(struct pipe_screen
*screen
, void *priv
,
687 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
688 struct pipe_context
*ctx
;
690 if (sscreen
->debug_flags
& DBG(CHECK_VM
))
691 flags
|= PIPE_CONTEXT_DEBUG
;
693 ctx
= si_create_context(screen
, flags
);
695 if (!(flags
& PIPE_CONTEXT_PREFER_THREADED
))
698 /* Clover (compute-only) is unsupported. */
699 if (flags
& PIPE_CONTEXT_COMPUTE_ONLY
)
702 /* When shaders are logged to stderr, asynchronous compilation is
704 if (sscreen
->debug_flags
& DBG_ALL_SHADERS
)
707 /* Use asynchronous flushes only on amdgpu, since the radeon
708 * implementation for fence_server_sync is incomplete. */
709 return threaded_context_create(ctx
, &sscreen
->pool_transfers
, si_replace_buffer_storage
,
710 sscreen
->info
.is_amdgpu
? si_create_fence
: NULL
,
711 &((struct si_context
*)ctx
)->tc
);
717 static void si_destroy_screen(struct pipe_screen
*pscreen
)
719 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
720 struct si_shader_part
*parts
[] = {sscreen
->vs_prologs
, sscreen
->tcs_epilogs
, sscreen
->gs_prologs
,
721 sscreen
->ps_prologs
, sscreen
->ps_epilogs
};
724 if (!sscreen
->ws
->unref(sscreen
->ws
))
727 if (sscreen
->debug_flags
& DBG(CACHE_STATS
)) {
728 printf("live shader cache: hits = %u, misses = %u\n", sscreen
->live_shader_cache
.hits
,
729 sscreen
->live_shader_cache
.misses
);
730 printf("memory shader cache: hits = %u, misses = %u\n", sscreen
->num_memory_shader_cache_hits
,
731 sscreen
->num_memory_shader_cache_misses
);
732 printf("disk shader cache: hits = %u, misses = %u\n", sscreen
->num_disk_shader_cache_hits
,
733 sscreen
->num_disk_shader_cache_misses
);
736 simple_mtx_destroy(&sscreen
->aux_context_lock
);
738 struct u_log_context
*aux_log
= ((struct si_context
*)sscreen
->aux_context
)->log
;
740 sscreen
->aux_context
->set_log_context(sscreen
->aux_context
, NULL
);
741 u_log_context_destroy(aux_log
);
745 sscreen
->aux_context
->destroy(sscreen
->aux_context
);
747 util_queue_destroy(&sscreen
->shader_compiler_queue
);
748 util_queue_destroy(&sscreen
->shader_compiler_queue_low_priority
);
750 /* Release the reference on glsl types of the compiler threads. */
751 glsl_type_singleton_decref();
753 for (i
= 0; i
< ARRAY_SIZE(sscreen
->compiler
); i
++)
754 si_destroy_compiler(&sscreen
->compiler
[i
]);
756 for (i
= 0; i
< ARRAY_SIZE(sscreen
->compiler_lowp
); i
++)
757 si_destroy_compiler(&sscreen
->compiler_lowp
[i
]);
759 /* Free shader parts. */
760 for (i
= 0; i
< ARRAY_SIZE(parts
); i
++) {
762 struct si_shader_part
*part
= parts
[i
];
764 parts
[i
] = part
->next
;
765 si_shader_binary_clean(&part
->binary
);
769 simple_mtx_destroy(&sscreen
->shader_parts_mutex
);
770 si_destroy_shader_cache(sscreen
);
772 si_destroy_perfcounters(sscreen
);
773 si_gpu_load_kill_thread(sscreen
);
775 simple_mtx_destroy(&sscreen
->gpu_load_mutex
);
777 slab_destroy_parent(&sscreen
->pool_transfers
);
779 disk_cache_destroy(sscreen
->disk_shader_cache
);
780 util_live_shader_cache_deinit(&sscreen
->live_shader_cache
);
781 sscreen
->ws
->destroy(sscreen
->ws
);
785 static void si_init_gs_info(struct si_screen
*sscreen
)
787 sscreen
->gs_table_depth
= ac_get_gs_table_depth(sscreen
->info
.chip_class
, sscreen
->info
.family
);
790 static void si_test_vmfault(struct si_screen
*sscreen
, uint64_t test_flags
)
792 struct pipe_context
*ctx
= sscreen
->aux_context
;
793 struct si_context
*sctx
= (struct si_context
*)ctx
;
794 struct pipe_resource
*buf
= pipe_buffer_create_const0(&sscreen
->b
, 0, PIPE_USAGE_DEFAULT
, 64);
797 puts("Buffer allocation failed.");
801 si_resource(buf
)->gpu_address
= 0; /* cause a VM fault */
803 if (test_flags
& DBG(TEST_VMFAULT_CP
)) {
804 si_cp_dma_copy_buffer(sctx
, buf
, buf
, 0, 4, 4, 0, SI_COHERENCY_NONE
, L2_BYPASS
);
805 ctx
->flush(ctx
, NULL
, 0);
806 puts("VM fault test: CP - done.");
808 if (test_flags
& DBG(TEST_VMFAULT_SDMA
)) {
809 si_sdma_clear_buffer(sctx
, buf
, 0, 4, 0);
810 ctx
->flush(ctx
, NULL
, 0);
811 puts("VM fault test: SDMA - done.");
813 if (test_flags
& DBG(TEST_VMFAULT_SHADER
)) {
814 util_test_constant_buffer(ctx
, buf
);
815 puts("VM fault test: Shader - done.");
820 static void si_test_gds_memory_management(struct si_context
*sctx
, unsigned alloc_size
,
821 unsigned alignment
, enum radeon_bo_domain domain
)
823 struct radeon_winsys
*ws
= sctx
->ws
;
824 struct radeon_cmdbuf
*cs
[8];
825 struct pb_buffer
*gds_bo
[ARRAY_SIZE(cs
)];
827 for (unsigned i
= 0; i
< ARRAY_SIZE(cs
); i
++) {
828 cs
[i
] = ws
->cs_create(sctx
->ctx
, RING_COMPUTE
, NULL
, NULL
, false);
829 gds_bo
[i
] = ws
->buffer_create(ws
, alloc_size
, alignment
, domain
, 0);
833 for (unsigned iterations
= 0; iterations
< 20000; iterations
++) {
834 for (unsigned i
= 0; i
< ARRAY_SIZE(cs
); i
++) {
835 /* This clears GDS with CP DMA.
837 * We don't care if GDS is present. Just add some packet
838 * to make the GPU busy for a moment.
840 si_cp_dma_clear_buffer(
841 sctx
, cs
[i
], NULL
, 0, alloc_size
, 0,
842 SI_CPDMA_SKIP_BO_LIST_UPDATE
| SI_CPDMA_SKIP_CHECK_CS_SPACE
| SI_CPDMA_SKIP_GFX_SYNC
, 0,
845 ws
->cs_add_buffer(cs
[i
], gds_bo
[i
], domain
, RADEON_USAGE_READWRITE
, 0);
846 ws
->cs_flush(cs
[i
], PIPE_FLUSH_ASYNC
, NULL
);
852 static void si_disk_cache_create(struct si_screen
*sscreen
)
854 /* Don't use the cache if shader dumping is enabled. */
855 if (sscreen
->debug_flags
& DBG_ALL_SHADERS
)
858 struct mesa_sha1 ctx
;
859 unsigned char sha1
[20];
860 char cache_id
[20 * 2 + 1];
862 _mesa_sha1_init(&ctx
);
864 if (!disk_cache_get_function_identifier(si_disk_cache_create
, &ctx
) ||
865 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo
, &ctx
))
868 _mesa_sha1_final(&ctx
, sha1
);
869 disk_cache_format_hex_id(cache_id
, sha1
, 20 * 2);
871 /* These flags affect shader compilation. */
872 #define ALL_FLAGS (DBG(GISEL))
873 uint64_t shader_debug_flags
= sscreen
->debug_flags
& ALL_FLAGS
;
875 /* Add the high bits of 32-bit addresses, which affects
876 * how 32-bit addresses are expanded to 64 bits.
878 STATIC_ASSERT(ALL_FLAGS
<= UINT_MAX
);
879 assert((int16_t)sscreen
->info
.address32_hi
== (int32_t)sscreen
->info
.address32_hi
);
880 shader_debug_flags
|= (uint64_t)(sscreen
->info
.address32_hi
& 0xffff) << 32;
882 sscreen
->disk_shader_cache
= disk_cache_create(sscreen
->info
.name
, cache_id
, shader_debug_flags
);
885 static void si_set_max_shader_compiler_threads(struct pipe_screen
*screen
, unsigned max_threads
)
887 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
889 /* This function doesn't allow a greater number of threads than
890 * the queue had at its creation. */
891 util_queue_adjust_num_threads(&sscreen
->shader_compiler_queue
, max_threads
);
892 /* Don't change the number of threads on the low priority queue. */
895 static bool si_is_parallel_shader_compilation_finished(struct pipe_screen
*screen
, void *shader
,
896 enum pipe_shader_type shader_type
)
898 struct si_shader_selector
*sel
= (struct si_shader_selector
*)shader
;
900 return util_queue_fence_is_signalled(&sel
->ready
);
903 static struct pipe_screen
*radeonsi_screen_create_impl(struct radeon_winsys
*ws
,
904 const struct pipe_screen_config
*config
)
906 struct si_screen
*sscreen
= CALLOC_STRUCT(si_screen
);
907 unsigned hw_threads
, num_comp_hi_threads
, num_comp_lo_threads
;
915 ws
->query_info(ws
, &sscreen
->info
);
917 if (sscreen
->info
.chip_class
== GFX10
&& LLVM_VERSION_MAJOR
< 9) {
918 fprintf(stderr
, "radeonsi: Navi family support requires LLVM 9 or higher\n");
923 if (sscreen
->info
.chip_class
>= GFX9
) {
924 sscreen
->se_tile_repeat
= 32 * sscreen
->info
.max_se
;
926 ac_get_raster_config(&sscreen
->info
, &sscreen
->pa_sc_raster_config
,
927 &sscreen
->pa_sc_raster_config_1
, &sscreen
->se_tile_repeat
);
930 sscreen
->debug_flags
= debug_get_flags_option("R600_DEBUG", debug_options
, 0);
931 sscreen
->debug_flags
|= debug_get_flags_option("AMD_DEBUG", debug_options
, 0);
932 test_flags
= debug_get_flags_option("AMD_TEST", test_options
, 0);
934 if (sscreen
->debug_flags
& DBG(NO_GFX
))
935 sscreen
->info
.has_graphics
= false;
937 /* Set functions first. */
938 sscreen
->b
.context_create
= si_pipe_create_context
;
939 sscreen
->b
.destroy
= si_destroy_screen
;
940 sscreen
->b
.set_max_shader_compiler_threads
= si_set_max_shader_compiler_threads
;
941 sscreen
->b
.is_parallel_shader_compilation_finished
= si_is_parallel_shader_compilation_finished
;
942 sscreen
->b
.finalize_nir
= si_finalize_nir
;
944 si_init_screen_get_functions(sscreen
);
945 si_init_screen_buffer_functions(sscreen
);
946 si_init_screen_fence_functions(sscreen
);
947 si_init_screen_state_functions(sscreen
);
948 si_init_screen_texture_functions(sscreen
);
949 si_init_screen_query_functions(sscreen
);
950 si_init_screen_live_shader_cache(sscreen
);
952 /* Set these flags in debug_flags early, so that the shader cache takes
955 if (driQueryOptionb(config
->options
, "glsl_correct_derivatives_after_discard"))
956 sscreen
->debug_flags
|= DBG(FS_CORRECT_DERIVS_AFTER_KILL
);
958 if (sscreen
->debug_flags
& DBG(INFO
))
959 ac_print_gpu_info(&sscreen
->info
);
961 slab_create_parent(&sscreen
->pool_transfers
, sizeof(struct si_transfer
), 64);
963 sscreen
->force_aniso
= MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
964 if (sscreen
->force_aniso
== -1) {
965 sscreen
->force_aniso
= MIN2(16, debug_get_num_option("AMD_TEX_ANISO", -1));
968 if (sscreen
->force_aniso
>= 0) {
969 printf("radeonsi: Forcing anisotropy filter to %ix\n",
970 /* round down to a power of two */
971 1 << util_logbase2(sscreen
->force_aniso
));
974 (void)simple_mtx_init(&sscreen
->aux_context_lock
, mtx_plain
);
975 (void)simple_mtx_init(&sscreen
->gpu_load_mutex
, mtx_plain
);
977 si_init_gs_info(sscreen
);
978 if (!si_init_shader_cache(sscreen
)) {
984 #define OPT_BOOL(name, dflt, description) \
985 sscreen->options.name = driQueryOptionb(config->options, "radeonsi_" #name);
986 #include "si_debug_options.h"
989 si_disk_cache_create(sscreen
);
991 /* Determine the number of shader compiler threads. */
992 hw_threads
= sysconf(_SC_NPROCESSORS_ONLN
);
994 if (hw_threads
>= 12) {
995 num_comp_hi_threads
= hw_threads
* 3 / 4;
996 num_comp_lo_threads
= hw_threads
/ 3;
997 } else if (hw_threads
>= 6) {
998 num_comp_hi_threads
= hw_threads
- 2;
999 num_comp_lo_threads
= hw_threads
/ 2;
1000 } else if (hw_threads
>= 2) {
1001 num_comp_hi_threads
= hw_threads
- 1;
1002 num_comp_lo_threads
= hw_threads
/ 2;
1004 num_comp_hi_threads
= 1;
1005 num_comp_lo_threads
= 1;
1008 num_comp_hi_threads
= MIN2(num_comp_hi_threads
, ARRAY_SIZE(sscreen
->compiler
));
1009 num_comp_lo_threads
= MIN2(num_comp_lo_threads
, ARRAY_SIZE(sscreen
->compiler_lowp
));
1011 /* Take a reference on the glsl types for the compiler threads. */
1012 glsl_type_singleton_init_or_ref();
1014 if (!util_queue_init(
1015 &sscreen
->shader_compiler_queue
, "sh", 64, num_comp_hi_threads
,
1016 UTIL_QUEUE_INIT_RESIZE_IF_FULL
| UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY
)) {
1017 si_destroy_shader_cache(sscreen
);
1019 glsl_type_singleton_decref();
1023 if (!util_queue_init(&sscreen
->shader_compiler_queue_low_priority
, "shlo", 64,
1024 num_comp_lo_threads
,
1025 UTIL_QUEUE_INIT_RESIZE_IF_FULL
| UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY
|
1026 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY
)) {
1027 si_destroy_shader_cache(sscreen
);
1029 glsl_type_singleton_decref();
1033 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1034 si_init_perfcounters(sscreen
);
1036 unsigned prim_discard_vertex_count_threshold
, tmp
;
1037 si_initialize_prim_discard_tunables(sscreen
, false, &prim_discard_vertex_count_threshold
, &tmp
);
1038 /* Compute-shader-based culling doesn't support VBOs in user SGPRs. */
1039 if (prim_discard_vertex_count_threshold
== UINT_MAX
)
1040 sscreen
->num_vbos_in_user_sgprs
= sscreen
->info
.chip_class
>= GFX9
? 5 : 1;
1042 /* Determine tessellation ring info. */
1043 bool double_offchip_buffers
= sscreen
->info
.chip_class
>= GFX7
&&
1044 sscreen
->info
.family
!= CHIP_CARRIZO
&&
1045 sscreen
->info
.family
!= CHIP_STONEY
;
1046 /* This must be one less than the maximum number due to a hw limitation.
1047 * Various hardware bugs need this.
1049 unsigned max_offchip_buffers_per_se
;
1051 if (sscreen
->info
.chip_class
>= GFX10
)
1052 max_offchip_buffers_per_se
= 256;
1053 /* Only certain chips can use the maximum value. */
1054 else if (sscreen
->info
.family
== CHIP_VEGA12
|| sscreen
->info
.family
== CHIP_VEGA20
)
1055 max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
1057 max_offchip_buffers_per_se
= double_offchip_buffers
? 127 : 63;
1059 unsigned max_offchip_buffers
= max_offchip_buffers_per_se
* sscreen
->info
.max_se
;
1060 unsigned offchip_granularity
;
1062 /* Hawaii has a bug with offchip buffers > 256 that can be worked
1063 * around by setting 4K granularity.
1065 if (sscreen
->info
.family
== CHIP_HAWAII
) {
1066 sscreen
->tess_offchip_block_dw_size
= 4096;
1067 offchip_granularity
= V_03093C_X_4K_DWORDS
;
1069 sscreen
->tess_offchip_block_dw_size
= 8192;
1070 offchip_granularity
= V_03093C_X_8K_DWORDS
;
1073 sscreen
->tess_factor_ring_size
= 32768 * sscreen
->info
.max_se
;
1074 sscreen
->tess_offchip_ring_size
= max_offchip_buffers
* sscreen
->tess_offchip_block_dw_size
* 4;
1076 if (sscreen
->info
.chip_class
>= GFX7
) {
1077 if (sscreen
->info
.chip_class
>= GFX8
)
1078 --max_offchip_buffers
;
1079 sscreen
->vgt_hs_offchip_param
= S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
1080 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
1082 assert(offchip_granularity
== V_03093C_X_8K_DWORDS
);
1083 sscreen
->vgt_hs_offchip_param
= S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
1086 sscreen
->has_draw_indirect_multi
=
1087 (sscreen
->info
.family
>= CHIP_POLARIS10
) ||
1088 (sscreen
->info
.chip_class
== GFX8
&& sscreen
->info
.pfp_fw_version
>= 121 &&
1089 sscreen
->info
.me_fw_version
>= 87) ||
1090 (sscreen
->info
.chip_class
== GFX7
&& sscreen
->info
.pfp_fw_version
>= 211 &&
1091 sscreen
->info
.me_fw_version
>= 173) ||
1092 (sscreen
->info
.chip_class
== GFX6
&& sscreen
->info
.pfp_fw_version
>= 79 &&
1093 sscreen
->info
.me_fw_version
>= 142);
1095 sscreen
->has_out_of_order_rast
=
1096 sscreen
->info
.has_out_of_order_rast
&& !(sscreen
->debug_flags
& DBG(NO_OUT_OF_ORDER
));
1097 sscreen
->assume_no_z_fights
= driQueryOptionb(config
->options
, "radeonsi_assume_no_z_fights") ||
1098 driQueryOptionb(config
->options
, "allow_draw_out_of_order");
1099 sscreen
->commutative_blend_add
=
1100 driQueryOptionb(config
->options
, "radeonsi_commutative_blend_add") ||
1101 driQueryOptionb(config
->options
, "allow_draw_out_of_order");
1103 sscreen
->use_ngg
= sscreen
->info
.chip_class
>= GFX10
&& sscreen
->info
.family
!= CHIP_NAVI14
&&
1104 !(sscreen
->debug_flags
& DBG(NO_NGG
));
1105 sscreen
->use_ngg_culling
= sscreen
->use_ngg
&& !(sscreen
->debug_flags
& DBG(NO_NGG_CULLING
));
1106 sscreen
->always_use_ngg_culling
=
1107 sscreen
->use_ngg_culling
&& sscreen
->debug_flags
& DBG(ALWAYS_NGG_CULLING
);
1108 sscreen
->use_ngg_streamout
= false;
1110 /* Only enable primitive binning on APUs by default. */
1111 if (sscreen
->info
.chip_class
>= GFX10
) {
1112 sscreen
->dpbb_allowed
= true;
1113 sscreen
->dfsm_allowed
= !sscreen
->info
.has_dedicated_vram
;
1114 } else if (sscreen
->info
.chip_class
== GFX9
) {
1115 sscreen
->dpbb_allowed
= !sscreen
->info
.has_dedicated_vram
;
1116 sscreen
->dfsm_allowed
= !sscreen
->info
.has_dedicated_vram
;
1119 /* Process DPBB enable flags. */
1120 if (sscreen
->debug_flags
& DBG(DPBB
)) {
1121 sscreen
->dpbb_allowed
= true;
1122 if (sscreen
->debug_flags
& DBG(DFSM
))
1123 sscreen
->dfsm_allowed
= true;
1126 /* Process DPBB disable flags. */
1127 if (sscreen
->debug_flags
& DBG(NO_DPBB
)) {
1128 sscreen
->dpbb_allowed
= false;
1129 sscreen
->dfsm_allowed
= false;
1130 } else if (sscreen
->debug_flags
& DBG(NO_DFSM
)) {
1131 sscreen
->dfsm_allowed
= false;
1134 /* While it would be nice not to have this flag, we are constrained
1135 * by the reality that LLVM 9.0 has buggy VGPR indexing on GFX9.
1137 sscreen
->llvm_has_working_vgpr_indexing
= sscreen
->info
.chip_class
!= GFX9
;
1139 sscreen
->dcc_msaa_allowed
= !(sscreen
->debug_flags
& DBG(NO_DCC_MSAA
));
1141 (void)simple_mtx_init(&sscreen
->shader_parts_mutex
, mtx_plain
);
1142 sscreen
->use_monolithic_shaders
= (sscreen
->debug_flags
& DBG(MONOLITHIC_SHADERS
)) != 0;
1144 sscreen
->barrier_flags
.cp_to_L2
= SI_CONTEXT_INV_SCACHE
| SI_CONTEXT_INV_VCACHE
;
1145 if (sscreen
->info
.chip_class
<= GFX8
) {
1146 sscreen
->barrier_flags
.cp_to_L2
|= SI_CONTEXT_INV_L2
;
1147 sscreen
->barrier_flags
.L2_to_cp
|= SI_CONTEXT_WB_L2
;
1150 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1151 sscreen
->debug_flags
|= DBG_ALL_SHADERS
;
1158 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1160 * s >= z >= c (ignoring this only wastes memory)
1165 * Only MSAA color and depth buffers are overriden.
1167 if (sscreen
->info
.has_eqaa_surface_allocator
) {
1168 const char *eqaa
= debug_get_option("EQAA", NULL
);
1171 if (eqaa
&& sscanf(eqaa
, "%u,%u,%u", &s
, &z
, &f
) == 3 && s
&& z
&& f
) {
1172 sscreen
->eqaa_force_coverage_samples
= s
;
1173 sscreen
->eqaa_force_z_samples
= z
;
1174 sscreen
->eqaa_force_color_samples
= f
;
1178 sscreen
->ge_wave_size
= 64;
1179 sscreen
->ps_wave_size
= 64;
1180 sscreen
->compute_wave_size
= 64;
1182 if (sscreen
->info
.chip_class
>= GFX10
) {
1183 /* Pixels shaders: Wave64 is recommended.
1184 * Compute shaders: There are piglit failures with Wave32.
1186 sscreen
->ge_wave_size
= 32;
1188 if (sscreen
->debug_flags
& DBG(W32_GE
))
1189 sscreen
->ge_wave_size
= 32;
1190 if (sscreen
->debug_flags
& DBG(W32_PS
))
1191 sscreen
->ps_wave_size
= 32;
1192 if (sscreen
->debug_flags
& DBG(W32_CS
))
1193 sscreen
->compute_wave_size
= 32;
1195 if (sscreen
->debug_flags
& DBG(W64_GE
))
1196 sscreen
->ge_wave_size
= 64;
1197 if (sscreen
->debug_flags
& DBG(W64_PS
))
1198 sscreen
->ps_wave_size
= 64;
1199 if (sscreen
->debug_flags
& DBG(W64_CS
))
1200 sscreen
->compute_wave_size
= 64;
1203 /* Create the auxiliary context. This must be done last. */
1204 sscreen
->aux_context
= si_create_context(
1205 &sscreen
->b
, (sscreen
->options
.aux_debug
? PIPE_CONTEXT_DEBUG
: 0) |
1206 (sscreen
->info
.has_graphics
? 0 : PIPE_CONTEXT_COMPUTE_ONLY
));
1207 if (sscreen
->options
.aux_debug
) {
1208 struct u_log_context
*log
= CALLOC_STRUCT(u_log_context
);
1209 u_log_context_init(log
);
1210 sscreen
->aux_context
->set_log_context(sscreen
->aux_context
, log
);
1213 if (test_flags
& DBG(TEST_DMA
))
1214 si_test_dma(sscreen
);
1216 if (test_flags
& DBG(TEST_DMA_PERF
)) {
1217 si_test_dma_perf(sscreen
);
1220 if (test_flags
& (DBG(TEST_VMFAULT_CP
) | DBG(TEST_VMFAULT_SDMA
) | DBG(TEST_VMFAULT_SHADER
)))
1221 si_test_vmfault(sscreen
, test_flags
);
1223 if (test_flags
& DBG(TEST_GDS
))
1224 si_test_gds((struct si_context
*)sscreen
->aux_context
);
1226 if (test_flags
& DBG(TEST_GDS_MM
)) {
1227 si_test_gds_memory_management((struct si_context
*)sscreen
->aux_context
, 32 * 1024, 4,
1230 if (test_flags
& DBG(TEST_GDS_OA_MM
)) {
1231 si_test_gds_memory_management((struct si_context
*)sscreen
->aux_context
, 4, 1,
1235 STATIC_ASSERT(sizeof(union si_vgt_stages_key
) == 4);
1239 struct pipe_screen
*radeonsi_screen_create(int fd
, const struct pipe_screen_config
*config
)
1241 drmVersionPtr version
= drmGetVersion(fd
);
1242 struct radeon_winsys
*rw
= NULL
;
1244 switch (version
->version_major
) {
1246 rw
= radeon_drm_winsys_create(fd
, config
, radeonsi_screen_create_impl
);
1249 rw
= amdgpu_winsys_create(fd
, config
, radeonsi_screen_create_impl
);
1253 drmFreeVersion(version
);
1254 return rw
? rw
->screen
: NULL
;