2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "si_public.h"
28 #include "si_shader_internal.h"
29 #include "si_compute.h"
32 #include "ac_llvm_util.h"
33 #include "radeon/radeon_uvd.h"
34 #include "gallivm/lp_bld_misc.h"
35 #include "util/disk_cache.h"
36 #include "util/u_log.h"
37 #include "util/u_memory.h"
38 #include "util/u_suballoc.h"
39 #include "util/u_tests.h"
40 #include "util/u_upload_mgr.h"
41 #include "util/xmlconfig.h"
42 #include "vl/vl_decoder.h"
43 #include "driver_ddebug/dd_util.h"
45 #include "gallium/winsys/radeon/drm/radeon_drm_public.h"
46 #include "gallium/winsys/amdgpu/drm/amdgpu_public.h"
49 static const struct debug_named_value debug_options
[] = {
50 /* Shader logging options: */
51 { "vs", DBG(VS
), "Print vertex shaders" },
52 { "ps", DBG(PS
), "Print pixel shaders" },
53 { "gs", DBG(GS
), "Print geometry shaders" },
54 { "tcs", DBG(TCS
), "Print tessellation control shaders" },
55 { "tes", DBG(TES
), "Print tessellation evaluation shaders" },
56 { "cs", DBG(CS
), "Print compute shaders" },
57 { "noir", DBG(NO_IR
), "Don't print the LLVM IR"},
58 { "notgsi", DBG(NO_TGSI
), "Don't print the TGSI"},
59 { "noasm", DBG(NO_ASM
), "Don't print disassembled shaders"},
60 { "preoptir", DBG(PREOPT_IR
), "Print the LLVM IR before initial optimizations" },
62 /* Shader compiler options the shader cache should be aware of: */
63 { "unsafemath", DBG(UNSAFE_MATH
), "Enable unsafe math shader optimizations" },
64 { "sisched", DBG(SI_SCHED
), "Enable LLVM SI Machine Instruction Scheduler." },
65 { "gisel", DBG(GISEL
), "Enable LLVM global instruction selector." },
67 /* Shader compiler options (with no effect on the shader cache): */
68 { "checkir", DBG(CHECK_IR
), "Enable additional sanity checks on shader IR" },
69 { "mono", DBG(MONOLITHIC_SHADERS
), "Use old-style monolithic shaders compiled on demand" },
70 { "nooptvariant", DBG(NO_OPT_VARIANT
), "Disable compiling optimized shader variants." },
72 /* Information logging options: */
73 { "info", DBG(INFO
), "Print driver information" },
74 { "tex", DBG(TEX
), "Print texture info" },
75 { "compute", DBG(COMPUTE
), "Print compute info" },
76 { "vm", DBG(VM
), "Print virtual addresses when creating resources" },
79 { "forcedma", DBG(FORCE_DMA
), "Use asynchronous DMA for all operations when possible." },
80 { "nodma", DBG(NO_ASYNC_DMA
), "Disable asynchronous DMA" },
81 { "nowc", DBG(NO_WC
), "Disable GTT write combining" },
82 { "check_vm", DBG(CHECK_VM
), "Check VM faults and dump debug info." },
83 { "reserve_vmid", DBG(RESERVE_VMID
), "Force VMID reservation per context." },
84 { "zerovram", DBG(ZERO_VRAM
), "Clear VRAM allocations." },
86 /* 3D engine options: */
87 { "alwayspd", DBG(ALWAYS_PD
), "Always enable the primitive discard compute shader." },
88 { "pd", DBG(PD
), "Enable the primitive discard compute shader for large draw calls." },
89 { "nopd", DBG(NO_PD
), "Disable the primitive discard compute shader." },
90 { "switch_on_eop", DBG(SWITCH_ON_EOP
), "Program WD/IA to switch on end-of-packet." },
91 { "nooutoforder", DBG(NO_OUT_OF_ORDER
), "Disable out-of-order rasterization" },
92 { "nodpbb", DBG(NO_DPBB
), "Disable DPBB." },
93 { "nodfsm", DBG(NO_DFSM
), "Disable DFSM." },
94 { "dpbb", DBG(DPBB
), "Enable DPBB." },
95 { "dfsm", DBG(DFSM
), "Enable DFSM." },
96 { "nohyperz", DBG(NO_HYPERZ
), "Disable Hyper-Z" },
97 { "norbplus", DBG(NO_RB_PLUS
), "Disable RB+." },
98 { "no2d", DBG(NO_2D_TILING
), "Disable 2D tiling" },
99 { "notiling", DBG(NO_TILING
), "Disable tiling" },
100 { "nodcc", DBG(NO_DCC
), "Disable DCC." },
101 { "nodccclear", DBG(NO_DCC_CLEAR
), "Disable DCC fast clear." },
102 { "nodccfb", DBG(NO_DCC_FB
), "Disable separate DCC on the main framebuffer" },
103 { "nodccmsaa", DBG(NO_DCC_MSAA
), "Disable DCC for MSAA" },
104 { "nofmask", DBG(NO_FMASK
), "Disable MSAA compression" },
107 { "testdma", DBG(TEST_DMA
), "Invoke SDMA tests and exit." },
108 { "testvmfaultcp", DBG(TEST_VMFAULT_CP
), "Invoke a CP VM fault test and exit." },
109 { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA
), "Invoke a SDMA VM fault test and exit." },
110 { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER
), "Invoke a shader VM fault test and exit." },
111 { "testdmaperf", DBG(TEST_DMA_PERF
), "Test DMA performance" },
112 { "testgds", DBG(TEST_GDS
), "Test GDS." },
113 { "testgdsmm", DBG(TEST_GDS_MM
), "Test GDS memory management." },
114 { "testgdsoamm", DBG(TEST_GDS_OA_MM
), "Test GDS OA memory management." },
116 DEBUG_NAMED_VALUE_END
/* must be last */
119 static void si_init_compiler(struct si_screen
*sscreen
,
120 struct ac_llvm_compiler
*compiler
)
122 /* Only create the less-optimizing version of the compiler on APUs
123 * predating Ryzen (Raven). */
124 bool create_low_opt_compiler
= !sscreen
->info
.has_dedicated_vram
&&
125 sscreen
->info
.chip_class
<= GFX8
;
127 enum ac_target_machine_options tm_options
=
128 (sscreen
->debug_flags
& DBG(SI_SCHED
) ? AC_TM_SISCHED
: 0) |
129 (sscreen
->debug_flags
& DBG(GISEL
) ? AC_TM_ENABLE_GLOBAL_ISEL
: 0) |
130 (sscreen
->info
.chip_class
>= GFX9
? AC_TM_FORCE_ENABLE_XNACK
: 0) |
131 (sscreen
->info
.chip_class
< GFX9
? AC_TM_FORCE_DISABLE_XNACK
: 0) |
132 (!sscreen
->llvm_has_working_vgpr_indexing
? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH
: 0) |
133 (sscreen
->debug_flags
& DBG(CHECK_IR
) ? AC_TM_CHECK_IR
: 0) |
134 (create_low_opt_compiler
? AC_TM_CREATE_LOW_OPT
: 0);
137 ac_init_llvm_compiler(compiler
, sscreen
->info
.family
, tm_options
);
138 compiler
->passes
= ac_create_llvm_passes(compiler
->tm
);
140 if (compiler
->low_opt_tm
)
141 compiler
->low_opt_passes
= ac_create_llvm_passes(compiler
->low_opt_tm
);
144 static void si_destroy_compiler(struct ac_llvm_compiler
*compiler
)
146 ac_destroy_llvm_passes(compiler
->passes
);
147 ac_destroy_llvm_passes(compiler
->low_opt_passes
);
148 ac_destroy_llvm_compiler(compiler
);
154 static void si_destroy_context(struct pipe_context
*context
)
156 struct si_context
*sctx
= (struct si_context
*)context
;
159 util_queue_finish(&sctx
->screen
->shader_compiler_queue
);
160 util_queue_finish(&sctx
->screen
->shader_compiler_queue_low_priority
);
162 /* Unreference the framebuffer normally to disable related logic
165 struct pipe_framebuffer_state fb
= {};
166 if (context
->set_framebuffer_state
)
167 context
->set_framebuffer_state(context
, &fb
);
169 si_release_all_descriptors(sctx
);
171 if (sctx
->chip_class
>= GFX10
)
172 gfx10_destroy_query(sctx
);
174 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
175 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
176 pipe_resource_reference(&sctx
->tess_rings
, NULL
);
177 pipe_resource_reference(&sctx
->null_const_buf
.buffer
, NULL
);
178 pipe_resource_reference(&sctx
->sample_pos_buffer
, NULL
);
179 si_resource_reference(&sctx
->border_color_buffer
, NULL
);
180 free(sctx
->border_color_table
);
181 si_resource_reference(&sctx
->scratch_buffer
, NULL
);
182 si_resource_reference(&sctx
->compute_scratch_buffer
, NULL
);
183 si_resource_reference(&sctx
->wait_mem_scratch
, NULL
);
185 si_pm4_free_state(sctx
, sctx
->init_config
, ~0);
186 if (sctx
->init_config_gs_rings
)
187 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
188 for (i
= 0; i
< ARRAY_SIZE(sctx
->vgt_shader_config
); i
++)
189 si_pm4_delete_state(sctx
, vgt_shader_config
, sctx
->vgt_shader_config
[i
]);
191 if (sctx
->fixed_func_tcs_shader
.cso
)
192 sctx
->b
.delete_tcs_state(&sctx
->b
, sctx
->fixed_func_tcs_shader
.cso
);
193 if (sctx
->custom_dsa_flush
)
194 sctx
->b
.delete_depth_stencil_alpha_state(&sctx
->b
, sctx
->custom_dsa_flush
);
195 if (sctx
->custom_blend_resolve
)
196 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_resolve
);
197 if (sctx
->custom_blend_fmask_decompress
)
198 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_fmask_decompress
);
199 if (sctx
->custom_blend_eliminate_fastclear
)
200 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_eliminate_fastclear
);
201 if (sctx
->custom_blend_dcc_decompress
)
202 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_dcc_decompress
);
203 if (sctx
->vs_blit_pos
)
204 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_pos
);
205 if (sctx
->vs_blit_pos_layered
)
206 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_pos_layered
);
207 if (sctx
->vs_blit_color
)
208 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_color
);
209 if (sctx
->vs_blit_color_layered
)
210 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_color_layered
);
211 if (sctx
->vs_blit_texcoord
)
212 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_texcoord
);
213 if (sctx
->cs_clear_buffer
)
214 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_clear_buffer
);
215 if (sctx
->cs_copy_buffer
)
216 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_copy_buffer
);
217 if (sctx
->cs_copy_image
)
218 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_copy_image
);
219 if (sctx
->cs_copy_image_1d_array
)
220 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_copy_image_1d_array
);
221 if (sctx
->cs_clear_render_target
)
222 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_clear_render_target
);
223 if (sctx
->cs_clear_render_target_1d_array
)
224 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_clear_render_target_1d_array
);
225 if (sctx
->cs_dcc_retile
)
226 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_dcc_retile
);
229 util_blitter_destroy(sctx
->blitter
);
231 /* Release DCC stats. */
232 for (int i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++) {
233 assert(!sctx
->dcc_stats
[i
].query_active
);
235 for (int j
= 0; j
< ARRAY_SIZE(sctx
->dcc_stats
[i
].ps_stats
); j
++)
236 if (sctx
->dcc_stats
[i
].ps_stats
[j
])
237 sctx
->b
.destroy_query(&sctx
->b
,
238 sctx
->dcc_stats
[i
].ps_stats
[j
]);
240 si_texture_reference(&sctx
->dcc_stats
[i
].tex
, NULL
);
243 if (sctx
->query_result_shader
)
244 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->query_result_shader
);
245 if (sctx
->sh_query_result_shader
)
246 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->sh_query_result_shader
);
249 sctx
->ws
->cs_destroy(sctx
->gfx_cs
);
251 sctx
->ws
->cs_destroy(sctx
->dma_cs
);
253 sctx
->ws
->ctx_destroy(sctx
->ctx
);
255 if (sctx
->b
.stream_uploader
)
256 u_upload_destroy(sctx
->b
.stream_uploader
);
257 if (sctx
->b
.const_uploader
)
258 u_upload_destroy(sctx
->b
.const_uploader
);
259 if (sctx
->cached_gtt_allocator
)
260 u_upload_destroy(sctx
->cached_gtt_allocator
);
262 slab_destroy_child(&sctx
->pool_transfers
);
263 slab_destroy_child(&sctx
->pool_transfers_unsync
);
265 if (sctx
->allocator_zeroed_memory
)
266 u_suballocator_destroy(sctx
->allocator_zeroed_memory
);
268 sctx
->ws
->fence_reference(&sctx
->last_gfx_fence
, NULL
);
269 sctx
->ws
->fence_reference(&sctx
->last_sdma_fence
, NULL
);
270 sctx
->ws
->fence_reference(&sctx
->last_ib_barrier_fence
, NULL
);
271 si_resource_reference(&sctx
->eop_bug_scratch
, NULL
);
272 si_resource_reference(&sctx
->index_ring
, NULL
);
273 si_resource_reference(&sctx
->barrier_buf
, NULL
);
274 si_resource_reference(&sctx
->last_ib_barrier_buf
, NULL
);
275 pb_reference(&sctx
->gds
, NULL
);
276 pb_reference(&sctx
->gds_oa
, NULL
);
278 si_destroy_compiler(&sctx
->compiler
);
280 si_saved_cs_reference(&sctx
->current_saved_cs
, NULL
);
282 _mesa_hash_table_destroy(sctx
->tex_handles
, NULL
);
283 _mesa_hash_table_destroy(sctx
->img_handles
, NULL
);
285 util_dynarray_fini(&sctx
->resident_tex_handles
);
286 util_dynarray_fini(&sctx
->resident_img_handles
);
287 util_dynarray_fini(&sctx
->resident_tex_needs_color_decompress
);
288 util_dynarray_fini(&sctx
->resident_img_needs_color_decompress
);
289 util_dynarray_fini(&sctx
->resident_tex_needs_depth_decompress
);
290 si_unref_sdma_uploads(sctx
);
294 static enum pipe_reset_status
si_get_reset_status(struct pipe_context
*ctx
)
296 struct si_context
*sctx
= (struct si_context
*)ctx
;
298 return sctx
->ws
->ctx_query_reset_status(sctx
->ctx
);
301 static void si_set_device_reset_callback(struct pipe_context
*ctx
,
302 const struct pipe_device_reset_callback
*cb
)
304 struct si_context
*sctx
= (struct si_context
*)ctx
;
307 sctx
->device_reset_callback
= *cb
;
309 memset(&sctx
->device_reset_callback
, 0,
310 sizeof(sctx
->device_reset_callback
));
313 bool si_check_device_reset(struct si_context
*sctx
)
315 enum pipe_reset_status status
;
317 if (!sctx
->device_reset_callback
.reset
)
320 status
= sctx
->ws
->ctx_query_reset_status(sctx
->ctx
);
321 if (status
== PIPE_NO_RESET
)
324 sctx
->device_reset_callback
.reset(sctx
->device_reset_callback
.data
, status
);
328 /* Apitrace profiling:
329 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
330 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
331 * and remember its number.
332 * 3) In Mesa, enable queries and performance counters around that draw
333 * call and print the results.
334 * 4) glretrace --benchmark --markers ..
336 static void si_emit_string_marker(struct pipe_context
*ctx
,
337 const char *string
, int len
)
339 struct si_context
*sctx
= (struct si_context
*)ctx
;
341 dd_parse_apitrace_marker(string
, len
, &sctx
->apitrace_call_number
);
344 u_log_printf(sctx
->log
, "\nString marker: %*s\n", len
, string
);
347 static void si_set_debug_callback(struct pipe_context
*ctx
,
348 const struct pipe_debug_callback
*cb
)
350 struct si_context
*sctx
= (struct si_context
*)ctx
;
351 struct si_screen
*screen
= sctx
->screen
;
353 util_queue_finish(&screen
->shader_compiler_queue
);
354 util_queue_finish(&screen
->shader_compiler_queue_low_priority
);
359 memset(&sctx
->debug
, 0, sizeof(sctx
->debug
));
362 static void si_set_log_context(struct pipe_context
*ctx
,
363 struct u_log_context
*log
)
365 struct si_context
*sctx
= (struct si_context
*)ctx
;
369 u_log_add_auto_logger(log
, si_auto_log_cs
, sctx
);
372 static void si_set_context_param(struct pipe_context
*ctx
,
373 enum pipe_context_param param
,
376 struct radeon_winsys
*ws
= ((struct si_context
*)ctx
)->ws
;
379 case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE
:
380 ws
->pin_threads_to_L3_cache(ws
, value
);
386 static struct pipe_context
*si_create_context(struct pipe_screen
*screen
,
389 struct si_context
*sctx
= CALLOC_STRUCT(si_context
);
390 struct si_screen
* sscreen
= (struct si_screen
*)screen
;
391 struct radeon_winsys
*ws
= sscreen
->ws
;
393 bool stop_exec_on_failure
= (flags
& PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET
) != 0;
398 sctx
->has_graphics
= sscreen
->info
.chip_class
== GFX6
||
399 !(flags
& PIPE_CONTEXT_COMPUTE_ONLY
);
401 if (flags
& PIPE_CONTEXT_DEBUG
)
402 sscreen
->record_llvm_ir
= true; /* racy but not critical */
404 sctx
->b
.screen
= screen
; /* this must be set first */
406 sctx
->b
.destroy
= si_destroy_context
;
407 sctx
->screen
= sscreen
; /* Easy accessing of screen/winsys. */
408 sctx
->is_debug
= (flags
& PIPE_CONTEXT_DEBUG
) != 0;
410 slab_create_child(&sctx
->pool_transfers
, &sscreen
->pool_transfers
);
411 slab_create_child(&sctx
->pool_transfers_unsync
, &sscreen
->pool_transfers
);
413 sctx
->ws
= sscreen
->ws
;
414 sctx
->family
= sscreen
->info
.family
;
415 sctx
->chip_class
= sscreen
->info
.chip_class
;
417 if (sctx
->chip_class
== GFX7
||
418 sctx
->chip_class
== GFX8
||
419 sctx
->chip_class
== GFX9
) {
420 sctx
->eop_bug_scratch
= si_resource(
421 pipe_buffer_create(&sscreen
->b
, 0, PIPE_USAGE_DEFAULT
,
422 16 * sscreen
->info
.num_render_backends
));
423 if (!sctx
->eop_bug_scratch
)
427 /* Initialize context allocators. */
428 sctx
->allocator_zeroed_memory
=
429 u_suballocator_create(&sctx
->b
, 128 * 1024,
430 0, PIPE_USAGE_DEFAULT
,
431 SI_RESOURCE_FLAG_UNMAPPABLE
|
432 SI_RESOURCE_FLAG_CLEAR
, false);
433 if (!sctx
->allocator_zeroed_memory
)
436 sctx
->b
.stream_uploader
= u_upload_create(&sctx
->b
, 1024 * 1024,
437 0, PIPE_USAGE_STREAM
,
438 SI_RESOURCE_FLAG_READ_ONLY
);
439 if (!sctx
->b
.stream_uploader
)
442 sctx
->cached_gtt_allocator
= u_upload_create(&sctx
->b
, 16 * 1024,
443 0, PIPE_USAGE_STAGING
, 0);
444 if (!sctx
->cached_gtt_allocator
)
447 sctx
->ctx
= sctx
->ws
->ctx_create(sctx
->ws
);
451 if (sscreen
->info
.chip_class
== GFX10
)
452 sscreen
->debug_flags
|= DBG(NO_ASYNC_DMA
); /* TODO-GFX10: implement this */
453 if (sscreen
->info
.num_sdma_rings
&& !(sscreen
->debug_flags
& DBG(NO_ASYNC_DMA
))) {
454 sctx
->dma_cs
= sctx
->ws
->cs_create(sctx
->ctx
, RING_DMA
,
455 (void*)si_flush_dma_cs
,
456 sctx
, stop_exec_on_failure
);
459 bool use_sdma_upload
= sscreen
->info
.has_dedicated_vram
&& sctx
->dma_cs
;
460 sctx
->b
.const_uploader
= u_upload_create(&sctx
->b
, 256 * 1024,
461 0, PIPE_USAGE_DEFAULT
,
462 SI_RESOURCE_FLAG_32BIT
|
464 SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA
:
465 (sscreen
->cpdma_prefetch_writes_memory
?
466 0 : SI_RESOURCE_FLAG_READ_ONLY
)));
467 if (!sctx
->b
.const_uploader
)
471 u_upload_enable_flush_explicit(sctx
->b
.const_uploader
);
473 sctx
->gfx_cs
= ws
->cs_create(sctx
->ctx
,
474 sctx
->has_graphics
? RING_GFX
: RING_COMPUTE
,
475 (void*)si_flush_gfx_cs
, sctx
, stop_exec_on_failure
);
478 sctx
->border_color_table
= malloc(SI_MAX_BORDER_COLORS
*
479 sizeof(*sctx
->border_color_table
));
480 if (!sctx
->border_color_table
)
483 sctx
->border_color_buffer
= si_resource(
484 pipe_buffer_create(screen
, 0, PIPE_USAGE_DEFAULT
,
485 SI_MAX_BORDER_COLORS
*
486 sizeof(*sctx
->border_color_table
)));
487 if (!sctx
->border_color_buffer
)
490 sctx
->border_color_map
=
491 ws
->buffer_map(sctx
->border_color_buffer
->buf
,
492 NULL
, PIPE_TRANSFER_WRITE
);
493 if (!sctx
->border_color_map
)
496 if (sctx
->chip_class
>= GFX10
)
497 sctx
->ngg
= !sscreen
->options
.disable_ngg
;
499 /* Initialize context functions used by graphics and compute. */
500 if (sctx
->chip_class
>= GFX10
)
501 sctx
->emit_cache_flush
= gfx10_emit_cache_flush
;
503 sctx
->emit_cache_flush
= si_emit_cache_flush
;
505 sctx
->b
.emit_string_marker
= si_emit_string_marker
;
506 sctx
->b
.set_debug_callback
= si_set_debug_callback
;
507 sctx
->b
.set_log_context
= si_set_log_context
;
508 sctx
->b
.set_context_param
= si_set_context_param
;
509 sctx
->b
.get_device_reset_status
= si_get_reset_status
;
510 sctx
->b
.set_device_reset_callback
= si_set_device_reset_callback
;
512 si_init_all_descriptors(sctx
);
513 si_init_buffer_functions(sctx
);
514 si_init_clear_functions(sctx
);
515 si_init_blit_functions(sctx
);
516 si_init_compute_functions(sctx
);
517 si_init_compute_blit_functions(sctx
);
518 si_init_debug_functions(sctx
);
519 si_init_fence_functions(sctx
);
520 si_init_query_functions(sctx
);
521 si_init_state_compute_functions(sctx
);
523 /* Initialize graphics-only context functions. */
524 if (sctx
->has_graphics
) {
525 si_init_context_texture_functions(sctx
);
526 if (sctx
->chip_class
>= GFX10
)
527 gfx10_init_query(sctx
);
528 si_init_msaa_functions(sctx
);
529 si_init_shader_functions(sctx
);
530 si_init_state_functions(sctx
);
531 si_init_streamout_functions(sctx
);
532 si_init_viewport_functions(sctx
);
534 sctx
->blitter
= util_blitter_create(&sctx
->b
);
535 if (sctx
->blitter
== NULL
)
537 sctx
->blitter
->skip_viewport_restore
= true;
539 si_init_draw_functions(sctx
);
540 si_initialize_prim_discard_tunables(sctx
);
543 /* Initialize SDMA functions. */
544 if (sctx
->chip_class
>= GFX7
)
545 cik_init_sdma_functions(sctx
);
547 si_init_dma_functions(sctx
);
549 if (sscreen
->debug_flags
& DBG(FORCE_DMA
))
550 sctx
->b
.resource_copy_region
= sctx
->dma_copy
;
552 sctx
->sample_mask
= 0xffff;
554 /* Initialize multimedia functions. */
555 if (sscreen
->info
.has_hw_decode
) {
556 sctx
->b
.create_video_codec
= si_uvd_create_decoder
;
557 sctx
->b
.create_video_buffer
= si_video_buffer_create
;
559 sctx
->b
.create_video_codec
= vl_create_decoder
;
560 sctx
->b
.create_video_buffer
= vl_video_buffer_create
;
563 if (sctx
->chip_class
>= GFX9
) {
564 sctx
->wait_mem_scratch
= si_resource(
565 pipe_buffer_create(screen
, 0, PIPE_USAGE_DEFAULT
, 8));
566 if (!sctx
->wait_mem_scratch
)
569 /* Initialize the memory. */
570 si_cp_write_data(sctx
, sctx
->wait_mem_scratch
, 0, 4,
571 V_370_MEM
, V_370_ME
, &sctx
->wait_mem_number
);
574 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
575 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
576 if (sctx
->chip_class
== GFX7
) {
577 sctx
->null_const_buf
.buffer
=
578 pipe_aligned_buffer_create(screen
,
579 SI_RESOURCE_FLAG_32BIT
,
580 PIPE_USAGE_DEFAULT
, 16,
581 sctx
->screen
->info
.tcc_cache_line_size
);
582 if (!sctx
->null_const_buf
.buffer
)
584 sctx
->null_const_buf
.buffer_size
= sctx
->null_const_buf
.buffer
->width0
;
586 unsigned start_shader
= sctx
->has_graphics
? 0 : PIPE_SHADER_COMPUTE
;
587 for (shader
= start_shader
; shader
< SI_NUM_SHADERS
; shader
++) {
588 for (i
= 0; i
< SI_NUM_CONST_BUFFERS
; i
++) {
589 sctx
->b
.set_constant_buffer(&sctx
->b
, shader
, i
,
590 &sctx
->null_const_buf
);
594 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
,
595 &sctx
->null_const_buf
);
596 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
,
597 &sctx
->null_const_buf
);
598 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
,
599 &sctx
->null_const_buf
);
600 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
,
601 &sctx
->null_const_buf
);
602 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
,
603 &sctx
->null_const_buf
);
606 uint64_t max_threads_per_block
;
607 screen
->get_compute_param(screen
, PIPE_SHADER_IR_TGSI
,
608 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
,
609 &max_threads_per_block
);
611 /* The maximum number of scratch waves. Scratch space isn't divided
612 * evenly between CUs. The number is only a function of the number of CUs.
613 * We can decrease the constant to decrease the scratch buffer size.
615 * sctx->scratch_waves must be >= the maximum posible size of
616 * 1 threadgroup, so that the hw doesn't hang from being unable
619 * The recommended value is 4 per CU at most. Higher numbers don't
620 * bring much benefit, but they still occupy chip resources (think
621 * async compute). I've seen ~2% performance difference between 4 and 32.
623 sctx
->scratch_waves
= MAX2(32 * sscreen
->info
.num_good_compute_units
,
624 max_threads_per_block
/ 64);
626 si_init_compiler(sscreen
, &sctx
->compiler
);
628 /* Bindless handles. */
629 sctx
->tex_handles
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
630 _mesa_key_pointer_equal
);
631 sctx
->img_handles
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
632 _mesa_key_pointer_equal
);
634 util_dynarray_init(&sctx
->resident_tex_handles
, NULL
);
635 util_dynarray_init(&sctx
->resident_img_handles
, NULL
);
636 util_dynarray_init(&sctx
->resident_tex_needs_color_decompress
, NULL
);
637 util_dynarray_init(&sctx
->resident_img_needs_color_decompress
, NULL
);
638 util_dynarray_init(&sctx
->resident_tex_needs_depth_decompress
, NULL
);
640 sctx
->sample_pos_buffer
=
641 pipe_buffer_create(sctx
->b
.screen
, 0, PIPE_USAGE_DEFAULT
,
642 sizeof(sctx
->sample_positions
));
643 pipe_buffer_write(&sctx
->b
, sctx
->sample_pos_buffer
, 0,
644 sizeof(sctx
->sample_positions
), &sctx
->sample_positions
);
646 /* this must be last */
647 si_begin_new_gfx_cs(sctx
);
649 if (sctx
->chip_class
== GFX7
) {
650 /* Clear the NULL constant buffer, because loads should return zeros.
651 * Note that this forces CP DMA to be used, because clover deadlocks
652 * for some reason when the compute codepath is used.
654 uint32_t clear_value
= 0;
655 si_clear_buffer(sctx
, sctx
->null_const_buf
.buffer
, 0,
656 sctx
->null_const_buf
.buffer
->width0
,
657 &clear_value
, 4, SI_COHERENCY_SHADER
, true);
661 fprintf(stderr
, "radeonsi: Failed to create a context.\n");
662 si_destroy_context(&sctx
->b
);
666 static struct pipe_context
*si_pipe_create_context(struct pipe_screen
*screen
,
667 void *priv
, unsigned flags
)
669 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
670 struct pipe_context
*ctx
;
672 if (sscreen
->debug_flags
& DBG(CHECK_VM
))
673 flags
|= PIPE_CONTEXT_DEBUG
;
675 ctx
= si_create_context(screen
, flags
);
677 if (!(flags
& PIPE_CONTEXT_PREFER_THREADED
))
680 /* Clover (compute-only) is unsupported. */
681 if (flags
& PIPE_CONTEXT_COMPUTE_ONLY
)
684 /* When shaders are logged to stderr, asynchronous compilation is
686 if (sscreen
->debug_flags
& DBG_ALL_SHADERS
)
689 /* Use asynchronous flushes only on amdgpu, since the radeon
690 * implementation for fence_server_sync is incomplete. */
691 return threaded_context_create(ctx
, &sscreen
->pool_transfers
,
692 si_replace_buffer_storage
,
693 sscreen
->info
.is_amdgpu
? si_create_fence
: NULL
,
694 &((struct si_context
*)ctx
)->tc
);
700 static void si_destroy_screen(struct pipe_screen
* pscreen
)
702 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
703 struct si_shader_part
*parts
[] = {
705 sscreen
->tcs_epilogs
,
712 if (!sscreen
->ws
->unref(sscreen
->ws
))
715 mtx_destroy(&sscreen
->aux_context_lock
);
717 struct u_log_context
*aux_log
= ((struct si_context
*)sscreen
->aux_context
)->log
;
719 sscreen
->aux_context
->set_log_context(sscreen
->aux_context
, NULL
);
720 u_log_context_destroy(aux_log
);
724 sscreen
->aux_context
->destroy(sscreen
->aux_context
);
726 util_queue_destroy(&sscreen
->shader_compiler_queue
);
727 util_queue_destroy(&sscreen
->shader_compiler_queue_low_priority
);
729 for (i
= 0; i
< ARRAY_SIZE(sscreen
->compiler
); i
++)
730 si_destroy_compiler(&sscreen
->compiler
[i
]);
732 for (i
= 0; i
< ARRAY_SIZE(sscreen
->compiler_lowp
); i
++)
733 si_destroy_compiler(&sscreen
->compiler_lowp
[i
]);
735 /* Free shader parts. */
736 for (i
= 0; i
< ARRAY_SIZE(parts
); i
++) {
738 struct si_shader_part
*part
= parts
[i
];
740 parts
[i
] = part
->next
;
741 si_shader_binary_clean(&part
->binary
);
745 mtx_destroy(&sscreen
->shader_parts_mutex
);
746 si_destroy_shader_cache(sscreen
);
748 si_destroy_perfcounters(sscreen
);
749 si_gpu_load_kill_thread(sscreen
);
751 mtx_destroy(&sscreen
->gpu_load_mutex
);
753 slab_destroy_parent(&sscreen
->pool_transfers
);
755 disk_cache_destroy(sscreen
->disk_shader_cache
);
756 sscreen
->ws
->destroy(sscreen
->ws
);
760 static void si_init_gs_info(struct si_screen
*sscreen
)
762 sscreen
->gs_table_depth
= ac_get_gs_table_depth(sscreen
->info
.chip_class
,
763 sscreen
->info
.family
);
766 static void si_test_vmfault(struct si_screen
*sscreen
)
768 struct pipe_context
*ctx
= sscreen
->aux_context
;
769 struct si_context
*sctx
= (struct si_context
*)ctx
;
770 struct pipe_resource
*buf
=
771 pipe_buffer_create_const0(&sscreen
->b
, 0, PIPE_USAGE_DEFAULT
, 64);
774 puts("Buffer allocation failed.");
778 si_resource(buf
)->gpu_address
= 0; /* cause a VM fault */
780 if (sscreen
->debug_flags
& DBG(TEST_VMFAULT_CP
)) {
781 si_cp_dma_copy_buffer(sctx
, buf
, buf
, 0, 4, 4, 0,
782 SI_COHERENCY_NONE
, L2_BYPASS
);
783 ctx
->flush(ctx
, NULL
, 0);
784 puts("VM fault test: CP - done.");
786 if (sscreen
->debug_flags
& DBG(TEST_VMFAULT_SDMA
)) {
787 si_sdma_clear_buffer(sctx
, buf
, 0, 4, 0);
788 ctx
->flush(ctx
, NULL
, 0);
789 puts("VM fault test: SDMA - done.");
791 if (sscreen
->debug_flags
& DBG(TEST_VMFAULT_SHADER
)) {
792 util_test_constant_buffer(ctx
, buf
);
793 puts("VM fault test: Shader - done.");
798 static void si_test_gds_memory_management(struct si_context
*sctx
,
799 unsigned alloc_size
, unsigned alignment
,
800 enum radeon_bo_domain domain
)
802 struct radeon_winsys
*ws
= sctx
->ws
;
803 struct radeon_cmdbuf
*cs
[8];
804 struct pb_buffer
*gds_bo
[ARRAY_SIZE(cs
)];
806 for (unsigned i
= 0; i
< ARRAY_SIZE(cs
); i
++) {
807 cs
[i
] = ws
->cs_create(sctx
->ctx
, RING_COMPUTE
,
809 gds_bo
[i
] = ws
->buffer_create(ws
, alloc_size
, alignment
, domain
, 0);
813 for (unsigned iterations
= 0; iterations
< 20000; iterations
++) {
814 for (unsigned i
= 0; i
< ARRAY_SIZE(cs
); i
++) {
815 /* This clears GDS with CP DMA.
817 * We don't care if GDS is present. Just add some packet
818 * to make the GPU busy for a moment.
820 si_cp_dma_clear_buffer(sctx
, cs
[i
], NULL
, 0, alloc_size
, 0,
821 SI_CPDMA_SKIP_BO_LIST_UPDATE
|
822 SI_CPDMA_SKIP_CHECK_CS_SPACE
|
823 SI_CPDMA_SKIP_GFX_SYNC
, 0, 0);
825 ws
->cs_add_buffer(cs
[i
], gds_bo
[i
], domain
,
826 RADEON_USAGE_READWRITE
, 0);
827 ws
->cs_flush(cs
[i
], PIPE_FLUSH_ASYNC
, NULL
);
833 static void si_disk_cache_create(struct si_screen
*sscreen
)
835 /* Don't use the cache if shader dumping is enabled. */
836 if (sscreen
->debug_flags
& DBG_ALL_SHADERS
)
839 struct mesa_sha1 ctx
;
840 unsigned char sha1
[20];
841 char cache_id
[20 * 2 + 1];
843 _mesa_sha1_init(&ctx
);
845 if (!disk_cache_get_function_identifier(si_disk_cache_create
, &ctx
) ||
846 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo
,
850 _mesa_sha1_final(&ctx
, sha1
);
851 disk_cache_format_hex_id(cache_id
, sha1
, 20 * 2);
853 /* These flags affect shader compilation. */
854 #define ALL_FLAGS (DBG(FS_CORRECT_DERIVS_AFTER_KILL) | \
858 uint64_t shader_debug_flags
= sscreen
->debug_flags
&
861 /* Add the high bits of 32-bit addresses, which affects
862 * how 32-bit addresses are expanded to 64 bits.
864 STATIC_ASSERT(ALL_FLAGS
<= UINT_MAX
);
865 assert((int16_t)sscreen
->info
.address32_hi
== (int32_t)sscreen
->info
.address32_hi
);
866 shader_debug_flags
|= (uint64_t)(sscreen
->info
.address32_hi
& 0xffff) << 32;
868 if (sscreen
->options
.enable_nir
)
869 shader_debug_flags
|= 1ull << 48;
871 sscreen
->disk_shader_cache
=
872 disk_cache_create(sscreen
->info
.name
,
877 static void si_set_max_shader_compiler_threads(struct pipe_screen
*screen
,
878 unsigned max_threads
)
880 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
882 /* This function doesn't allow a greater number of threads than
883 * the queue had at its creation. */
884 util_queue_adjust_num_threads(&sscreen
->shader_compiler_queue
,
886 /* Don't change the number of threads on the low priority queue. */
889 static bool si_is_parallel_shader_compilation_finished(struct pipe_screen
*screen
,
891 unsigned shader_type
)
893 if (shader_type
== PIPE_SHADER_COMPUTE
) {
894 struct si_compute
*cs
= (struct si_compute
*)shader
;
896 return util_queue_fence_is_signalled(&cs
->ready
);
898 struct si_shader_selector
*sel
= (struct si_shader_selector
*)shader
;
900 return util_queue_fence_is_signalled(&sel
->ready
);
903 static struct pipe_screen
*
904 radeonsi_screen_create_impl(struct radeon_winsys
*ws
,
905 const struct pipe_screen_config
*config
)
907 struct si_screen
*sscreen
= CALLOC_STRUCT(si_screen
);
908 unsigned hw_threads
, num_comp_hi_threads
, num_comp_lo_threads
, i
;
915 ws
->query_info(ws
, &sscreen
->info
);
917 if (sscreen
->info
.chip_class
== GFX10
&& HAVE_LLVM
< 0x0900) {
918 fprintf(stderr
, "radeonsi: Navi family support requires LLVM 9 or higher\n");
923 if (sscreen
->info
.chip_class
>= GFX9
) {
924 sscreen
->se_tile_repeat
= 32 * sscreen
->info
.max_se
;
926 ac_get_raster_config(&sscreen
->info
,
927 &sscreen
->pa_sc_raster_config
,
928 &sscreen
->pa_sc_raster_config_1
,
929 &sscreen
->se_tile_repeat
);
932 sscreen
->debug_flags
= debug_get_flags_option("R600_DEBUG",
934 sscreen
->debug_flags
|= debug_get_flags_option("AMD_DEBUG",
937 /* Set functions first. */
938 sscreen
->b
.context_create
= si_pipe_create_context
;
939 sscreen
->b
.destroy
= si_destroy_screen
;
940 sscreen
->b
.set_max_shader_compiler_threads
=
941 si_set_max_shader_compiler_threads
;
942 sscreen
->b
.is_parallel_shader_compilation_finished
=
943 si_is_parallel_shader_compilation_finished
;
945 si_init_screen_get_functions(sscreen
);
946 si_init_screen_buffer_functions(sscreen
);
947 si_init_screen_fence_functions(sscreen
);
948 si_init_screen_state_functions(sscreen
);
949 si_init_screen_texture_functions(sscreen
);
950 si_init_screen_query_functions(sscreen
);
952 /* Set these flags in debug_flags early, so that the shader cache takes
955 if (driQueryOptionb(config
->options
,
956 "glsl_correct_derivatives_after_discard"))
957 sscreen
->debug_flags
|= DBG(FS_CORRECT_DERIVS_AFTER_KILL
);
958 if (driQueryOptionb(config
->options
, "radeonsi_enable_sisched"))
959 sscreen
->debug_flags
|= DBG(SI_SCHED
);
961 if (sscreen
->debug_flags
& DBG(INFO
))
962 ac_print_gpu_info(&sscreen
->info
);
964 slab_create_parent(&sscreen
->pool_transfers
,
965 sizeof(struct si_transfer
), 64);
967 sscreen
->force_aniso
= MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
968 if (sscreen
->force_aniso
== -1) {
969 sscreen
->force_aniso
= MIN2(16, debug_get_num_option("AMD_TEX_ANISO", -1));
972 if (sscreen
->force_aniso
>= 0) {
973 printf("radeonsi: Forcing anisotropy filter to %ix\n",
974 /* round down to a power of two */
975 1 << util_logbase2(sscreen
->force_aniso
));
978 (void) mtx_init(&sscreen
->aux_context_lock
, mtx_plain
);
979 (void) mtx_init(&sscreen
->gpu_load_mutex
, mtx_plain
);
981 si_init_gs_info(sscreen
);
982 if (!si_init_shader_cache(sscreen
)) {
987 si_disk_cache_create(sscreen
);
989 /* Determine the number of shader compiler threads. */
990 hw_threads
= sysconf(_SC_NPROCESSORS_ONLN
);
992 if (hw_threads
>= 12) {
993 num_comp_hi_threads
= hw_threads
* 3 / 4;
994 num_comp_lo_threads
= hw_threads
/ 3;
995 } else if (hw_threads
>= 6) {
996 num_comp_hi_threads
= hw_threads
- 2;
997 num_comp_lo_threads
= hw_threads
/ 2;
998 } else if (hw_threads
>= 2) {
999 num_comp_hi_threads
= hw_threads
- 1;
1000 num_comp_lo_threads
= hw_threads
/ 2;
1002 num_comp_hi_threads
= 1;
1003 num_comp_lo_threads
= 1;
1006 num_comp_hi_threads
= MIN2(num_comp_hi_threads
,
1007 ARRAY_SIZE(sscreen
->compiler
));
1008 num_comp_lo_threads
= MIN2(num_comp_lo_threads
,
1009 ARRAY_SIZE(sscreen
->compiler_lowp
));
1011 if (!util_queue_init(&sscreen
->shader_compiler_queue
, "sh",
1012 64, num_comp_hi_threads
,
1013 UTIL_QUEUE_INIT_RESIZE_IF_FULL
|
1014 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY
)) {
1015 si_destroy_shader_cache(sscreen
);
1020 if (!util_queue_init(&sscreen
->shader_compiler_queue_low_priority
,
1022 64, num_comp_lo_threads
,
1023 UTIL_QUEUE_INIT_RESIZE_IF_FULL
|
1024 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY
|
1025 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY
)) {
1026 si_destroy_shader_cache(sscreen
);
1031 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1032 si_init_perfcounters(sscreen
);
1034 /* Determine tessellation ring info. */
1035 bool double_offchip_buffers
= sscreen
->info
.chip_class
>= GFX7
&&
1036 sscreen
->info
.family
!= CHIP_CARRIZO
&&
1037 sscreen
->info
.family
!= CHIP_STONEY
;
1038 /* This must be one less than the maximum number due to a hw limitation.
1039 * Various hardware bugs need this.
1041 unsigned max_offchip_buffers_per_se
;
1043 if (sscreen
->info
.chip_class
>= GFX10
)
1044 max_offchip_buffers_per_se
= 256;
1045 /* Only certain chips can use the maximum value. */
1046 else if (sscreen
->info
.family
== CHIP_VEGA12
||
1047 sscreen
->info
.family
== CHIP_VEGA20
)
1048 max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
1050 max_offchip_buffers_per_se
= double_offchip_buffers
? 127 : 63;
1052 unsigned max_offchip_buffers
= max_offchip_buffers_per_se
*
1053 sscreen
->info
.max_se
;
1054 unsigned offchip_granularity
;
1056 /* Hawaii has a bug with offchip buffers > 256 that can be worked
1057 * around by setting 4K granularity.
1059 if (sscreen
->info
.family
== CHIP_HAWAII
) {
1060 sscreen
->tess_offchip_block_dw_size
= 4096;
1061 offchip_granularity
= V_03093C_X_4K_DWORDS
;
1063 sscreen
->tess_offchip_block_dw_size
= 8192;
1064 offchip_granularity
= V_03093C_X_8K_DWORDS
;
1067 sscreen
->tess_factor_ring_size
= 32768 * sscreen
->info
.max_se
;
1068 assert(((sscreen
->tess_factor_ring_size
/ 4) & C_030938_SIZE
) == 0);
1069 sscreen
->tess_offchip_ring_size
= max_offchip_buffers
*
1070 sscreen
->tess_offchip_block_dw_size
* 4;
1072 if (sscreen
->info
.chip_class
>= GFX7
) {
1073 if (sscreen
->info
.chip_class
>= GFX8
)
1074 --max_offchip_buffers
;
1075 sscreen
->vgt_hs_offchip_param
=
1076 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
1077 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
1079 assert(offchip_granularity
== V_03093C_X_8K_DWORDS
);
1080 sscreen
->vgt_hs_offchip_param
=
1081 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
1084 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
1085 * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
1086 * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel. */
1087 sscreen
->has_clear_state
= sscreen
->info
.chip_class
>= GFX7
&&
1088 sscreen
->info
.chip_class
<= GFX9
&&
1089 sscreen
->info
.is_amdgpu
;
1091 sscreen
->has_distributed_tess
=
1092 sscreen
->info
.chip_class
>= GFX8
&&
1093 sscreen
->info
.max_se
>= 2;
1095 sscreen
->has_draw_indirect_multi
=
1096 (sscreen
->info
.family
>= CHIP_POLARIS10
) ||
1097 (sscreen
->info
.chip_class
== GFX8
&&
1098 sscreen
->info
.pfp_fw_version
>= 121 &&
1099 sscreen
->info
.me_fw_version
>= 87) ||
1100 (sscreen
->info
.chip_class
== GFX7
&&
1101 sscreen
->info
.pfp_fw_version
>= 211 &&
1102 sscreen
->info
.me_fw_version
>= 173) ||
1103 (sscreen
->info
.chip_class
== GFX6
&&
1104 sscreen
->info
.pfp_fw_version
>= 79 &&
1105 sscreen
->info
.me_fw_version
>= 142);
1107 sscreen
->has_out_of_order_rast
= sscreen
->info
.chip_class
>= GFX8
&&
1108 sscreen
->info
.max_se
>= 2 &&
1109 !(sscreen
->debug_flags
& DBG(NO_OUT_OF_ORDER
));
1110 sscreen
->assume_no_z_fights
=
1111 driQueryOptionb(config
->options
, "radeonsi_assume_no_z_fights");
1112 sscreen
->commutative_blend_add
=
1113 driQueryOptionb(config
->options
, "radeonsi_commutative_blend_add");
1116 #define OPT_BOOL(name, dflt, description) \
1117 sscreen->options.name = \
1118 driQueryOptionb(config->options, "radeonsi_"#name);
1119 #include "si_debug_options.h"
1122 sscreen
->has_gfx9_scissor_bug
= sscreen
->info
.family
== CHIP_VEGA10
||
1123 sscreen
->info
.family
== CHIP_RAVEN
;
1124 sscreen
->has_msaa_sample_loc_bug
= (sscreen
->info
.family
>= CHIP_POLARIS10
&&
1125 sscreen
->info
.family
<= CHIP_POLARIS12
) ||
1126 sscreen
->info
.family
== CHIP_VEGA10
||
1127 sscreen
->info
.family
== CHIP_RAVEN
;
1128 sscreen
->has_ls_vgpr_init_bug
= sscreen
->info
.family
== CHIP_VEGA10
||
1129 sscreen
->info
.family
== CHIP_RAVEN
;
1130 sscreen
->has_dcc_constant_encode
= sscreen
->info
.family
== CHIP_RAVEN2
||
1131 sscreen
->info
.chip_class
>= GFX10
;
1133 /* Only enable primitive binning on APUs by default. */
1134 sscreen
->dpbb_allowed
= sscreen
->info
.family
== CHIP_RAVEN
||
1135 sscreen
->info
.family
== CHIP_RAVEN2
;
1137 sscreen
->dfsm_allowed
= sscreen
->info
.family
== CHIP_RAVEN
||
1138 sscreen
->info
.family
== CHIP_RAVEN2
;
1140 /* Process DPBB enable flags. */
1141 if (sscreen
->debug_flags
& DBG(DPBB
)) {
1142 sscreen
->dpbb_allowed
= true;
1143 if (sscreen
->debug_flags
& DBG(DFSM
))
1144 sscreen
->dfsm_allowed
= true;
1147 /* Process DPBB disable flags. */
1148 if (sscreen
->debug_flags
& DBG(NO_DPBB
)) {
1149 sscreen
->dpbb_allowed
= false;
1150 sscreen
->dfsm_allowed
= false;
1151 } else if (sscreen
->debug_flags
& DBG(NO_DFSM
)) {
1152 sscreen
->dfsm_allowed
= false;
1155 if (sscreen
->info
.chip_class
== GFX10
) {
1156 sscreen
->dpbb_allowed
= false; /* TODO-GFX10: implement this */
1157 sscreen
->dfsm_allowed
= false;
1160 /* While it would be nice not to have this flag, we are constrained
1161 * by the reality that LLVM 9.0 has buggy VGPR indexing on GFX9.
1163 sscreen
->llvm_has_working_vgpr_indexing
= sscreen
->info
.chip_class
!= GFX9
;
1165 /* Some chips have RB+ registers, but don't support RB+. Those must
1166 * always disable it.
1168 if (sscreen
->info
.family
== CHIP_STONEY
||
1169 sscreen
->info
.chip_class
>= GFX9
) {
1170 sscreen
->has_rbplus
= true;
1172 sscreen
->rbplus_allowed
=
1173 !(sscreen
->debug_flags
& DBG(NO_RB_PLUS
)) &&
1174 (sscreen
->info
.family
== CHIP_STONEY
||
1175 sscreen
->info
.family
== CHIP_VEGA12
||
1176 sscreen
->info
.family
== CHIP_RAVEN
||
1177 sscreen
->info
.family
== CHIP_RAVEN2
);
1180 sscreen
->dcc_msaa_allowed
=
1181 !(sscreen
->debug_flags
& DBG(NO_DCC_MSAA
));
1183 sscreen
->cpdma_prefetch_writes_memory
= sscreen
->info
.chip_class
<= GFX8
;
1185 (void) mtx_init(&sscreen
->shader_parts_mutex
, mtx_plain
);
1186 sscreen
->use_monolithic_shaders
=
1187 (sscreen
->debug_flags
& DBG(MONOLITHIC_SHADERS
)) != 0;
1189 sscreen
->barrier_flags
.cp_to_L2
= SI_CONTEXT_INV_SCACHE
|
1190 SI_CONTEXT_INV_VCACHE
;
1191 if (sscreen
->info
.chip_class
<= GFX8
) {
1192 sscreen
->barrier_flags
.cp_to_L2
|= SI_CONTEXT_INV_L2
;
1193 sscreen
->barrier_flags
.L2_to_cp
|= SI_CONTEXT_WB_L2
;
1196 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1197 sscreen
->debug_flags
|= DBG_ALL_SHADERS
;
1204 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1206 * s >= z >= c (ignoring this only wastes memory)
1211 * Only MSAA color and depth buffers are overriden.
1213 if (sscreen
->info
.has_eqaa_surface_allocator
) {
1214 const char *eqaa
= debug_get_option("EQAA", NULL
);
1217 if (eqaa
&& sscanf(eqaa
, "%u,%u,%u", &s
, &z
, &f
) == 3 && s
&& z
&& f
) {
1218 sscreen
->eqaa_force_coverage_samples
= s
;
1219 sscreen
->eqaa_force_z_samples
= z
;
1220 sscreen
->eqaa_force_color_samples
= f
;
1224 for (i
= 0; i
< num_comp_hi_threads
; i
++)
1225 si_init_compiler(sscreen
, &sscreen
->compiler
[i
]);
1226 for (i
= 0; i
< num_comp_lo_threads
; i
++)
1227 si_init_compiler(sscreen
, &sscreen
->compiler_lowp
[i
]);
1229 /* Create the auxiliary context. This must be done last. */
1230 sscreen
->aux_context
= si_create_context(
1231 &sscreen
->b
, sscreen
->options
.aux_debug
? PIPE_CONTEXT_DEBUG
: 0);
1232 if (sscreen
->options
.aux_debug
) {
1233 struct u_log_context
*log
= CALLOC_STRUCT(u_log_context
);
1234 u_log_context_init(log
);
1235 sscreen
->aux_context
->set_log_context(sscreen
->aux_context
, log
);
1238 if (sscreen
->debug_flags
& DBG(TEST_DMA
))
1239 si_test_dma(sscreen
);
1241 if (sscreen
->debug_flags
& DBG(TEST_DMA_PERF
)) {
1242 si_test_dma_perf(sscreen
);
1245 if (sscreen
->debug_flags
& (DBG(TEST_VMFAULT_CP
) |
1246 DBG(TEST_VMFAULT_SDMA
) |
1247 DBG(TEST_VMFAULT_SHADER
)))
1248 si_test_vmfault(sscreen
);
1250 if (sscreen
->debug_flags
& DBG(TEST_GDS
))
1251 si_test_gds((struct si_context
*)sscreen
->aux_context
);
1253 if (sscreen
->debug_flags
& DBG(TEST_GDS_MM
)) {
1254 si_test_gds_memory_management((struct si_context
*)sscreen
->aux_context
,
1255 32 * 1024, 4, RADEON_DOMAIN_GDS
);
1257 if (sscreen
->debug_flags
& DBG(TEST_GDS_OA_MM
)) {
1258 si_test_gds_memory_management((struct si_context
*)sscreen
->aux_context
,
1259 4, 1, RADEON_DOMAIN_OA
);
1265 struct pipe_screen
*radeonsi_screen_create(int fd
, const struct pipe_screen_config
*config
)
1267 drmVersionPtr version
= drmGetVersion(fd
);
1268 struct radeon_winsys
*rw
= NULL
;
1270 switch (version
->version_major
) {
1272 rw
= radeon_drm_winsys_create(fd
, config
, radeonsi_screen_create_impl
);
1275 rw
= amdgpu_winsys_create(fd
, config
, radeonsi_screen_create_impl
);
1279 drmFreeVersion(version
);
1280 return rw
? rw
->screen
: NULL
;