2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "si_shader.h"
30 #include "util/u_dynarray.h"
31 #include "util/u_idalloc.h"
32 #include "util/u_threaded_context.h"
34 #if UTIL_ARCH_BIG_ENDIAN
35 #define SI_BIG_ENDIAN 1
37 #define SI_BIG_ENDIAN 0
40 #define ATI_VENDOR_ID 0x1002
41 #define SI_PRIM_DISCARD_DEBUG 0
42 #define SI_NOT_QUERY 0xffffffff
44 /* The base vertex and primitive restart can be any number, but we must pick
45 * one which will mean "unknown" for the purpose of state tracking and
46 * the number shouldn't be a commonly-used one. */
47 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
48 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
49 #define SI_INSTANCE_COUNT_UNKNOWN INT_MIN
50 #define SI_NUM_SMOOTH_AA_SAMPLES 8
51 #define SI_MAX_POINT_SIZE 2048
52 #define SI_GS_PER_ES 128
53 /* Alignment for optimal CP DMA performance. */
54 #define SI_CPDMA_ALIGNMENT 32
56 /* Tunables for compute-based clear_buffer and copy_buffer: */
57 #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
58 #define SI_COMPUTE_COPY_DW_PER_THREAD 4
59 #define SI_COMPUTE_DST_CACHE_POLICY L2_STREAM
61 /* Pipeline & streamout query controls. */
62 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
63 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
64 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
65 /* Instruction cache. */
66 #define SI_CONTEXT_INV_ICACHE (1 << 3)
67 /* Scalar cache. (GFX6-9: scalar L1; GFX10: scalar L0)
68 * GFX10: This also invalidates the L1 shader array cache. */
69 #define SI_CONTEXT_INV_SCACHE (1 << 4)
70 /* Vector cache. (GFX6-9: vector L1; GFX10: vector L0)
71 * GFX10: This also invalidates the L1 shader array cache. */
72 #define SI_CONTEXT_INV_VCACHE (1 << 5)
73 /* L2 cache + L2 metadata cache writeback & invalidate.
74 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
75 #define SI_CONTEXT_INV_L2 (1 << 6)
76 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
77 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
78 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
79 #define SI_CONTEXT_WB_L2 (1 << 7)
80 /* Writeback & invalidate the L2 metadata cache only. It can only be coupled with
81 * a CB or DB flush. */
82 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
83 /* Framebuffer caches. */
84 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
85 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
86 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
87 /* Engine synchronization. */
88 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
89 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
90 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
91 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
92 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
94 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
95 #define SI_PREFETCH_LS (1 << 1)
96 #define SI_PREFETCH_HS (1 << 2)
97 #define SI_PREFETCH_ES (1 << 3)
98 #define SI_PREFETCH_GS (1 << 4)
99 #define SI_PREFETCH_VS (1 << 5)
100 #define SI_PREFETCH_PS (1 << 6)
102 #define SI_MAX_BORDER_COLORS 4096
103 #define SI_MAX_VIEWPORTS 16
104 #define SIX_BITS 0x3F
105 #define SI_MAP_BUFFER_ALIGNMENT 64
106 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
108 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
109 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
110 #define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
111 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
112 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
113 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
114 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
115 #define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
116 /* For const_uploader, upload data via GTT and copy to VRAM on context flush via SDMA. */
117 #define SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA (PIPE_RESOURCE_FLAG_DRV_PRIV << 8)
118 /* Set a micro tile mode: */
119 #define SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE (PIPE_RESOURCE_FLAG_DRV_PRIV << 9)
120 #define SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT (util_logbase2(PIPE_RESOURCE_FLAG_DRV_PRIV) + 10)
121 #define SI_RESOURCE_FLAG_MICRO_TILE_MODE_SET(x) \
122 (((x)&0x3) << SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT)
123 #define SI_RESOURCE_FLAG_MICRO_TILE_MODE_GET(x) \
124 (((x) >> SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT) & 0x3)
128 DCC_CLEAR_COLOR_0000
= 0x00000000,
129 DCC_CLEAR_COLOR_0001
= 0x40404040,
130 DCC_CLEAR_COLOR_1110
= 0x80808080,
131 DCC_CLEAR_COLOR_1111
= 0xC0C0C0C0,
132 DCC_CLEAR_COLOR_REG
= 0x20202020,
133 DCC_UNCOMPRESSED
= 0xFFFFFFFF,
136 #define SI_IMAGE_ACCESS_AS_BUFFER (1 << 7)
141 /* Shader logging options: */
142 DBG_VS
= PIPE_SHADER_VERTEX
,
143 DBG_PS
= PIPE_SHADER_FRAGMENT
,
144 DBG_GS
= PIPE_SHADER_GEOMETRY
,
145 DBG_TCS
= PIPE_SHADER_TESS_CTRL
,
146 DBG_TES
= PIPE_SHADER_TESS_EVAL
,
147 DBG_CS
= PIPE_SHADER_COMPUTE
,
153 /* Shader compiler options the shader cache should be aware of: */
154 DBG_FS_CORRECT_DERIVS_AFTER_KILL
,
163 /* Shader compiler options (with no effect on the shader cache): */
165 DBG_MONOLITHIC_SHADERS
,
168 /* Information logging options: */
175 /* Driver options: */
179 DBG_NO_SDMA_COPY_IMAGE
,
185 /* 3D engine options: */
188 DBG_ALWAYS_NGG_CULLING
,
217 DBG_TEST_VMFAULT_SDMA
,
218 DBG_TEST_VMFAULT_SHADER
,
225 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
226 #define DBG(name) (1ull << DBG_##name)
231 L2_STREAM
, /* same as SLC=1 */
232 L2_LRU
, /* same as SLC=0 */
237 SI_COHERENCY_NONE
, /* no cache flushes needed */
239 SI_COHERENCY_CB_META
,
244 struct si_shader_context
;
246 struct u_suballocator
;
248 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
252 struct threaded_resource b
;
254 /* Winsys objects. */
255 struct pb_buffer
*buf
;
256 uint64_t gpu_address
;
257 /* Memory usage if the buffer placement is optimal. */
261 /* Resource properties. */
263 unsigned bo_alignment
;
264 enum radeon_bo_domain domains
;
265 enum radeon_bo_flag flags
;
266 unsigned bind_history
;
267 int max_forced_staging_uploads
;
269 /* The buffer range which is initialized (with a write transfer,
270 * streamout, DMA, or as a random access target). The rest of
271 * the buffer is considered invalid and can be mapped unsynchronized.
273 * This allows unsychronized mapping of a buffer range which hasn't
274 * been used yet. It's for applications which forget to use
275 * the unsynchronized map flag and expect the driver to figure it out.
277 struct util_range valid_buffer_range
;
279 /* For buffers only. This indicates that a write operation has been
280 * performed by TC L2, but the cache hasn't been flushed.
281 * Any hw block which doesn't use or bypasses TC L2 should check this
282 * flag and flush the cache before using the buffer.
284 * For example, TC L2 must be flushed if a buffer which has been
285 * modified by a shader store instruction is about to be used as
286 * an index buffer. The reason is that VGT DMA index fetching doesn't
291 /* Whether this resource is referenced by bindless handles. */
292 bool texture_handle_allocated
;
293 bool image_handle_allocated
;
295 /* Whether the resource has been exported via resource_get_handle. */
296 unsigned external_usage
; /* PIPE_HANDLE_USAGE_* */
300 struct threaded_transfer b
;
301 struct si_resource
*staging
;
306 struct si_resource buffer
;
308 struct radeon_surf surface
;
309 struct si_texture
*flushed_depth_texture
;
311 /* One texture allocation can contain these buffers:
312 * - image (pixel data)
313 * - FMASK buffer (MSAA compression)
314 * - CMASK buffer (MSAA compression and/or legacy fast color clear)
315 * - HTILE buffer (Z/S compression and fast Z/S clear)
316 * - DCC buffer (color compression and new fast color clear)
317 * - displayable DCC buffer (if the DCC buffer is not displayable)
318 * - DCC retile mapping buffer (if the DCC buffer is not displayable)
320 uint64_t cmask_base_address_reg
;
321 struct si_resource
*cmask_buffer
;
322 unsigned cb_color_info
; /* fast clear enable bit */
323 unsigned color_clear_value
[2];
324 unsigned last_msaa_resolve_target_micro_mode
;
325 unsigned num_level0_transfers
;
326 unsigned plane_index
; /* other planes are different pipe_resources */
329 /* Depth buffer compression and fast clear. */
330 float depth_clear_value
;
331 uint16_t dirty_level_mask
; /* each bit says if that mipmap is compressed */
332 uint16_t stencil_dirty_level_mask
; /* each bit says if that mipmap is compressed */
333 enum pipe_format db_render_format
: 16;
334 uint8_t stencil_clear_value
;
335 bool fmask_is_identity
: 1;
336 bool tc_compatible_htile
: 1;
337 bool htile_stencil_disabled
: 1;
338 bool depth_cleared
: 1; /* if it was cleared at least once */
339 bool stencil_cleared
: 1; /* if it was cleared at least once */
340 bool upgraded_depth
: 1; /* upgraded from unorm to Z32_FLOAT */
342 bool db_compatible
: 1;
343 bool can_sample_z
: 1;
344 bool can_sample_s
: 1;
346 /* We need to track DCC dirtiness, because st/dri usually calls
347 * flush_resource twice per frame (not a bug) and we don't wanna
348 * decompress DCC twice. Also, the dirty tracking must be done even
349 * if DCC isn't used, because it's required by the DCC usage analysis
350 * for a possible future enablement.
352 bool separate_dcc_dirty
: 1;
353 bool displayable_dcc_dirty
: 1;
355 /* Statistics gathering for the DCC enablement heuristic. */
356 bool dcc_gather_statistics
: 1;
357 /* Counter that should be non-zero if the texture is bound to a
360 unsigned framebuffers_bound
;
361 /* Whether the texture is a displayable back buffer and needs DCC
362 * decompression, which is expensive. Therefore, it's enabled only
363 * if statistics suggest that it will pay off and it's allocated
364 * separately. It can't be bound as a sampler by apps. Limited to
365 * target == 2D and last_level == 0. If enabled, dcc_offset contains
366 * the absolute GPUVM address, not the relative one.
368 struct si_resource
*dcc_separate_buffer
;
369 /* When DCC is temporarily disabled, the separate buffer is here. */
370 struct si_resource
*last_dcc_separate_buffer
;
371 /* Estimate of how much this color buffer is written to in units of
372 * full-screen draws: ps_invocations / (width * height)
373 * Shader kills, late Z, and blending with trivial discards make it
374 * inaccurate (we need to count CB updates, not PS invocations).
376 unsigned ps_draw_ratio
;
377 /* The number of clears since the last DCC usage analysis. */
378 unsigned num_slow_clears
;
382 struct pipe_surface base
;
384 /* These can vary with block-compressed textures. */
388 bool color_initialized
: 1;
389 bool depth_initialized
: 1;
391 /* Misc. color flags. */
392 bool color_is_int8
: 1;
393 bool color_is_int10
: 1;
394 bool dcc_incompatible
: 1;
396 /* Color registers. */
397 unsigned cb_color_info
;
398 unsigned cb_color_view
;
399 unsigned cb_color_attrib
;
400 unsigned cb_color_attrib2
; /* GFX9 and later */
401 unsigned cb_color_attrib3
; /* GFX10 and later */
402 unsigned cb_dcc_control
; /* GFX8 and later */
403 unsigned spi_shader_col_format
: 8; /* no blending, no alpha-to-coverage. */
404 unsigned spi_shader_col_format_alpha
: 8; /* alpha-to-coverage */
405 unsigned spi_shader_col_format_blend
: 8; /* blending without alpha. */
406 unsigned spi_shader_col_format_blend_alpha
: 8; /* blending with alpha. */
409 uint64_t db_depth_base
; /* DB_Z_READ/WRITE_BASE */
410 uint64_t db_stencil_base
;
411 uint64_t db_htile_data_base
;
412 unsigned db_depth_info
;
414 unsigned db_z_info2
; /* GFX9 only */
415 unsigned db_depth_view
;
416 unsigned db_depth_size
;
417 unsigned db_depth_slice
;
418 unsigned db_stencil_info
;
419 unsigned db_stencil_info2
; /* GFX9 only */
420 unsigned db_htile_surface
;
423 struct si_mmio_counter
{
428 union si_mmio_counters
{
430 /* For global GPU load including SDMA. */
431 struct si_mmio_counter gpu
;
434 struct si_mmio_counter spi
;
435 struct si_mmio_counter gui
;
436 struct si_mmio_counter ta
;
437 struct si_mmio_counter gds
;
438 struct si_mmio_counter vgt
;
439 struct si_mmio_counter ia
;
440 struct si_mmio_counter sx
;
441 struct si_mmio_counter wd
;
442 struct si_mmio_counter bci
;
443 struct si_mmio_counter sc
;
444 struct si_mmio_counter pa
;
445 struct si_mmio_counter db
;
446 struct si_mmio_counter cp
;
447 struct si_mmio_counter cb
;
450 struct si_mmio_counter sdma
;
453 struct si_mmio_counter pfp
;
454 struct si_mmio_counter meq
;
455 struct si_mmio_counter me
;
456 struct si_mmio_counter surf_sync
;
457 struct si_mmio_counter cp_dma
;
458 struct si_mmio_counter scratch_ram
;
463 struct si_memory_object
{
464 struct pipe_memory_object b
;
465 struct pb_buffer
*buf
;
469 /* Saved CS data for debugging features. */
470 struct radeon_saved_cs
{
474 struct radeon_bo_list_item
*bo_list
;
479 struct pipe_screen b
;
480 struct radeon_winsys
*ws
;
481 struct disk_cache
*disk_shader_cache
;
483 struct radeon_info info
;
484 uint64_t debug_flags
;
485 char renderer_string
[183];
487 void (*make_texture_descriptor
)(struct si_screen
*screen
, struct si_texture
*tex
, bool sampler
,
488 enum pipe_texture_target target
, enum pipe_format pipe_format
,
489 const unsigned char state_swizzle
[4], unsigned first_level
,
490 unsigned last_level
, unsigned first_layer
, unsigned last_layer
,
491 unsigned width
, unsigned height
, unsigned depth
, uint32_t *state
,
492 uint32_t *fmask_state
);
494 unsigned num_vbos_in_user_sgprs
;
495 unsigned pa_sc_raster_config
;
496 unsigned pa_sc_raster_config_1
;
497 unsigned se_tile_repeat
;
498 unsigned gs_table_depth
;
499 unsigned tess_offchip_block_dw_size
;
500 unsigned tess_offchip_ring_size
;
501 unsigned tess_factor_ring_size
;
502 unsigned vgt_hs_offchip_param
;
503 unsigned eqaa_force_coverage_samples
;
504 unsigned eqaa_force_z_samples
;
505 unsigned eqaa_force_color_samples
;
506 bool has_draw_indirect_multi
;
507 bool has_out_of_order_rast
;
508 bool assume_no_z_fights
;
509 bool commutative_blend_add
;
512 bool llvm_has_working_vgpr_indexing
;
514 bool use_ngg_culling
;
515 bool always_use_ngg_culling
;
516 bool use_ngg_streamout
;
519 #define OPT_BOOL(name, dflt, description) bool name : 1;
520 #include "si_debug_options.h"
523 /* Whether shaders are monolithic (1-part) or separate (3-part). */
524 bool use_monolithic_shaders
;
526 bool dcc_msaa_allowed
;
528 struct slab_parent_pool pool_transfers
;
530 /* Texture filter settings. */
531 int force_aniso
; /* -1 = disabled */
533 /* Auxiliary context. Mainly used to initialize resources.
534 * It must be locked prior to using and flushed before unlocking. */
535 struct pipe_context
*aux_context
;
536 simple_mtx_t aux_context_lock
;
538 /* This must be in the screen, because UE4 uses one context for
539 * compilation and another one for rendering.
541 unsigned num_compilations
;
542 /* Along with ST_DEBUG=precompile, this should show if applications
543 * are loading shaders on demand. This is a monotonic counter.
545 unsigned num_shaders_created
;
546 unsigned num_memory_shader_cache_hits
;
547 unsigned num_memory_shader_cache_misses
;
548 unsigned num_disk_shader_cache_hits
;
549 unsigned num_disk_shader_cache_misses
;
551 /* GPU load thread. */
552 simple_mtx_t gpu_load_mutex
;
553 thrd_t gpu_load_thread
;
554 union si_mmio_counters mmio_counters
;
555 volatile unsigned gpu_load_stop_thread
; /* bool */
557 /* Performance counters. */
558 struct si_perfcounters
*perfcounters
;
560 /* If pipe_screen wants to recompute and re-emit the framebuffer,
561 * sampler, and image states of all contexts, it should atomically
564 * Each context will compare this with its own last known value of
565 * the counter before drawing and re-emit the states accordingly.
567 unsigned dirty_tex_counter
;
568 unsigned dirty_buf_counter
;
570 /* Atomically increment this counter when an existing texture's
571 * metadata is enabled or disabled in a way that requires changing
572 * contexts' compressed texture binding masks.
574 unsigned compressed_colortex_counter
;
577 /* Context flags to set so that all writes from earlier jobs
578 * in the CP are seen by L2 clients.
582 /* Context flags to set so that all writes from earlier jobs
583 * that end in L2 are seen by CP.
588 simple_mtx_t shader_parts_mutex
;
589 struct si_shader_part
*vs_prologs
;
590 struct si_shader_part
*tcs_epilogs
;
591 struct si_shader_part
*gs_prologs
;
592 struct si_shader_part
*ps_prologs
;
593 struct si_shader_part
*ps_epilogs
;
595 /* Shader cache in memory.
597 * Design & limitations:
598 * - The shader cache is per screen (= per process), never saved to
599 * disk, and skips redundant shader compilations from NIR to bytecode.
600 * - It can only be used with one-variant-per-shader support, in which
601 * case only the main (typically middle) part of shaders is cached.
602 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
603 * variants of VS and TES are cached, so LS and ES aren't.
604 * - GS and CS aren't cached, but it's certainly possible to cache
607 simple_mtx_t shader_cache_mutex
;
608 struct hash_table
*shader_cache
;
610 /* Shader cache of live shaders. */
611 struct util_live_shader_cache live_shader_cache
;
613 /* Shader compiler queue for multithreaded compilation. */
614 struct util_queue shader_compiler_queue
;
615 /* Use at most 3 normal compiler threads on quadcore and better.
616 * Hyperthreaded CPUs report the number of threads, but we want
617 * the number of cores. We only need this many threads for shader-db. */
618 struct ac_llvm_compiler compiler
[24]; /* used by the queue only */
620 struct util_queue shader_compiler_queue_low_priority
;
621 /* Use at most 2 low priority threads on quadcore and better.
622 * We want to minimize the impact on multithreaded Mesa. */
623 struct ac_llvm_compiler compiler_lowp
[10];
625 unsigned compute_wave_size
;
626 unsigned ps_wave_size
;
627 unsigned ge_wave_size
;
630 struct si_blend_color
{
631 struct pipe_blend_color state
;
635 struct si_sampler_view
{
636 struct pipe_sampler_view base
;
637 /* [0..7] = image descriptor
638 * [4..7] = buffer descriptor */
640 uint32_t fmask_state
[8];
641 const struct legacy_surf_level
*base_level_info
;
644 bool is_stencil_sampler
;
646 bool dcc_incompatible
;
649 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
651 struct si_sampler_state
{
656 uint32_t integer_val
[4];
657 uint32_t upgraded_depth_val
[4];
660 struct si_cs_shader_state
{
661 struct si_compute
*program
;
662 struct si_compute
*emitted_program
;
669 struct pipe_sampler_view
*views
[SI_NUM_SAMPLERS
];
670 struct si_sampler_state
*sampler_states
[SI_NUM_SAMPLERS
];
672 /* The i-th bit is set if that element is enabled (non-NULL resource). */
673 unsigned enabled_mask
;
674 uint32_t needs_depth_decompress_mask
;
675 uint32_t needs_color_decompress_mask
;
679 struct pipe_image_view views
[SI_NUM_IMAGES
];
680 uint32_t needs_color_decompress_mask
;
681 unsigned enabled_mask
;
684 struct si_framebuffer
{
685 struct pipe_framebuffer_state state
;
686 unsigned colorbuf_enabled_4bit
;
687 unsigned spi_shader_col_format
;
688 unsigned spi_shader_col_format_alpha
;
689 unsigned spi_shader_col_format_blend
;
690 unsigned spi_shader_col_format_blend_alpha
;
691 ubyte nr_samples
: 5; /* at most 16xAA */
692 ubyte log_samples
: 3; /* at most 4 = 16xAA */
693 ubyte nr_color_samples
; /* at most 8xAA */
694 ubyte compressed_cb_mask
;
695 ubyte uncompressed_cb_mask
;
696 ubyte displayable_dcc_cb_mask
;
698 ubyte color_is_int10
;
700 ubyte dcc_overwrite_combiner_watermark
;
701 ubyte min_bytes_per_pixel
;
704 bool CB_has_shader_readable_metadata
;
705 bool DB_has_shader_readable_metadata
;
706 bool all_DCC_pipe_aligned
;
711 /* This is the list we want to support. */
712 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH
,
713 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH
,
714 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH
,
717 struct si_signed_scissor
{
722 enum si_quant_mode quant_mode
;
725 struct si_viewports
{
726 struct pipe_viewport_state states
[SI_MAX_VIEWPORTS
];
727 struct si_signed_scissor as_scissor
[SI_MAX_VIEWPORTS
];
731 struct si_clip_state
{
732 struct pipe_clip_state state
;
736 struct si_streamout_target
{
737 struct pipe_stream_output_target b
;
739 /* The buffer where BUFFER_FILLED_SIZE is stored. */
740 struct si_resource
*buf_filled_size
;
741 unsigned buf_filled_size_offset
;
742 bool buf_filled_size_valid
;
744 unsigned stride_in_dw
;
747 struct si_streamout
{
750 unsigned enabled_mask
;
751 unsigned num_targets
;
752 struct si_streamout_target
*targets
[PIPE_MAX_SO_BUFFERS
];
754 unsigned append_bitmask
;
757 /* External state which comes from the vertex shader,
758 * it must be set explicitly when binding a shader. */
759 uint16_t *stride_in_dw
;
760 unsigned enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
762 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
763 unsigned hw_enabled_mask
;
765 /* The state of VGT_STRMOUT_(CONFIG|EN). */
766 bool streamout_enabled
;
767 bool prims_gen_query_enabled
;
768 int num_prims_gen_queries
;
771 /* A shader state consists of the shader selector, which is a constant state
772 * object shared by multiple contexts and shouldn't be modified, and
773 * the current shader variant selected for this context.
775 struct si_shader_ctx_state
{
776 struct si_shader_selector
*cso
;
777 struct si_shader
*current
;
780 #define SI_NUM_VGT_PARAM_KEY_BITS 12
781 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
783 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
784 * Some fields are set by state-change calls, most are set by draw_vbo.
786 union si_vgt_param_key
{
788 #if UTIL_ARCH_LITTLE_ENDIAN
790 unsigned uses_instancing
: 1;
791 unsigned multi_instances_smaller_than_primgroup
: 1;
792 unsigned primitive_restart
: 1;
793 unsigned count_from_stream_output
: 1;
794 unsigned line_stipple_enabled
: 1;
795 unsigned uses_tess
: 1;
796 unsigned tess_uses_prim_id
: 1;
797 unsigned uses_gs
: 1;
798 unsigned _pad
: 32 - SI_NUM_VGT_PARAM_KEY_BITS
;
799 #else /* UTIL_ARCH_BIG_ENDIAN */
800 unsigned _pad
: 32 - SI_NUM_VGT_PARAM_KEY_BITS
;
801 unsigned uses_gs
: 1;
802 unsigned tess_uses_prim_id
: 1;
803 unsigned uses_tess
: 1;
804 unsigned line_stipple_enabled
: 1;
805 unsigned count_from_stream_output
: 1;
806 unsigned primitive_restart
: 1;
807 unsigned multi_instances_smaller_than_primgroup
: 1;
808 unsigned uses_instancing
: 1;
815 #define SI_NUM_VGT_STAGES_KEY_BITS 6
816 #define SI_NUM_VGT_STAGES_STATES (1 << SI_NUM_VGT_STAGES_KEY_BITS)
818 /* The VGT_SHADER_STAGES key used to index the table of precomputed values.
819 * Some fields are set by state-change calls, most are set by draw_vbo.
821 union si_vgt_stages_key
{
823 #if UTIL_ARCH_LITTLE_ENDIAN
826 unsigned ngg_gs_fast_launch
: 1;
827 unsigned ngg_passthrough
: 1;
828 unsigned ngg
: 1; /* gfx10+ */
829 unsigned streamout
: 1; /* only used with NGG */
830 unsigned _pad
: 32 - SI_NUM_VGT_STAGES_KEY_BITS
;
831 #else /* UTIL_ARCH_BIG_ENDIAN */
832 unsigned _pad
: 32 - SI_NUM_VGT_STAGES_KEY_BITS
;
833 unsigned streamout
: 1;
835 unsigned ngg_passthrough
: 1;
836 unsigned ngg_gs_fast_launch
: 1;
844 struct si_texture_handle
{
847 struct pipe_sampler_view
*view
;
848 struct si_sampler_state sstate
;
851 struct si_image_handle
{
854 struct pipe_image_view view
;
858 struct pipe_reference reference
;
859 struct si_context
*ctx
;
860 struct radeon_saved_cs gfx
;
861 struct radeon_saved_cs compute
;
862 struct si_resource
*trace_buf
;
865 unsigned gfx_last_dw
;
866 unsigned compute_last_dw
;
871 struct si_sdma_upload
{
872 struct si_resource
*dst
;
873 struct si_resource
*src
;
879 struct si_small_prim_cull_info
{
880 float scale
[2], translate
[2];
884 struct pipe_context b
; /* base class */
886 enum radeon_family family
;
887 enum chip_class chip_class
;
889 struct radeon_winsys
*ws
;
890 struct radeon_winsys_ctx
*ctx
;
891 struct radeon_cmdbuf
*gfx_cs
; /* compute IB if graphics is disabled */
892 struct radeon_cmdbuf
*sdma_cs
;
893 struct pipe_fence_handle
*last_gfx_fence
;
894 struct pipe_fence_handle
*last_sdma_fence
;
895 struct si_resource
*eop_bug_scratch
;
896 struct u_upload_mgr
*cached_gtt_allocator
;
897 struct threaded_context
*tc
;
898 struct u_suballocator
*allocator_zeroed_memory
;
899 struct slab_child_pool pool_transfers
;
900 struct slab_child_pool pool_transfers_unsync
; /* for threaded_context */
901 struct pipe_device_reset_callback device_reset_callback
;
902 struct u_log_context
*log
;
903 void *query_result_shader
;
904 void *sh_query_result_shader
;
906 void (*emit_cache_flush
)(struct si_context
*ctx
);
908 struct blitter_context
*blitter
;
911 void *discard_rasterizer_state
;
912 void *custom_dsa_flush
;
913 void *custom_blend_resolve
;
914 void *custom_blend_fmask_decompress
;
915 void *custom_blend_eliminate_fastclear
;
916 void *custom_blend_dcc_decompress
;
918 void *vs_blit_pos_layered
;
920 void *vs_blit_color_layered
;
921 void *vs_blit_texcoord
;
922 void *cs_clear_buffer
;
923 void *cs_copy_buffer
;
925 void *cs_copy_image_1d_array
;
926 void *cs_clear_render_target
;
927 void *cs_clear_render_target_1d_array
;
928 void *cs_clear_12bytes_buffer
;
930 void *cs_fmask_expand
[3][2]; /* [log2(samples)-1][is_array] */
931 struct si_screen
*screen
;
932 struct pipe_debug_callback debug
;
933 struct ac_llvm_compiler compiler
; /* only non-threaded compilation */
934 struct si_shader_ctx_state fixed_func_tcs_shader
;
935 /* Offset 0: EOP flush number; Offset 4: GDS prim restart counter */
936 struct si_resource
*wait_mem_scratch
;
937 unsigned wait_mem_number
;
938 uint16_t prefetch_L2_mask
;
941 bool gfx_flush_in_progress
: 1;
942 bool gfx_last_ib_is_busy
: 1;
943 bool compute_is_busy
: 1;
945 unsigned num_gfx_cs_flushes
;
946 unsigned initial_gfx_cs_size
;
947 unsigned last_dirty_tex_counter
;
948 unsigned last_dirty_buf_counter
;
949 unsigned last_compressed_colortex_counter
;
950 unsigned last_num_draw_calls
;
951 unsigned flags
; /* flush flags */
952 /* Current unaccounted memory usage. */
956 /* Compute-based primitive discard. */
957 unsigned prim_discard_vertex_count_threshold
;
958 struct pb_buffer
*gds
;
959 struct pb_buffer
*gds_oa
;
960 struct radeon_cmdbuf
*prim_discard_compute_cs
;
961 unsigned compute_gds_offset
;
962 struct si_shader
*compute_ib_last_shader
;
963 uint32_t compute_rewind_va
;
964 unsigned compute_num_prims_in_batch
;
965 bool preserve_prim_restart_gds_at_flush
;
966 /* index_ring is divided into 2 halves for doublebuffering. */
967 struct si_resource
*index_ring
;
968 unsigned index_ring_base
; /* offset of a per-IB portion */
969 unsigned index_ring_offset
; /* offset within a per-IB portion */
970 unsigned index_ring_size_per_ib
; /* max available size per IB */
971 bool prim_discard_compute_ib_initialized
;
972 /* For tracking the last execution barrier - it can be either
973 * a WRITE_DATA packet or a fence. */
974 uint32_t *last_pkt3_write_data
;
975 struct si_resource
*barrier_buf
;
976 unsigned barrier_buf_offset
;
977 struct pipe_fence_handle
*last_ib_barrier_fence
;
978 struct si_resource
*last_ib_barrier_buf
;
979 unsigned last_ib_barrier_buf_offset
;
981 /* Atoms (direct states). */
982 union si_state_atoms atoms
;
983 unsigned dirty_atoms
; /* mask */
984 /* PM4 states (precomputed immutable states) */
985 unsigned dirty_states
;
986 union si_state queued
;
987 union si_state emitted
;
989 /* Atom declarations. */
990 struct si_framebuffer framebuffer
;
991 unsigned sample_locs_num_samples
;
992 uint16_t sample_mask
;
993 unsigned last_cb_target_mask
;
994 struct si_blend_color blend_color
;
995 struct si_clip_state clip_state
;
996 struct si_shader_data shader_pointers
;
997 struct si_stencil_ref stencil_ref
;
998 struct pipe_scissor_state scissors
[SI_MAX_VIEWPORTS
];
999 struct si_streamout streamout
;
1000 struct si_viewports viewports
;
1001 unsigned num_window_rectangles
;
1002 bool window_rectangles_include
;
1003 struct pipe_scissor_state window_rectangles
[4];
1005 /* Precomputed states. */
1006 struct si_pm4_state
*init_config
;
1007 struct si_pm4_state
*init_config_gs_rings
;
1008 bool init_config_has_vgt_flush
;
1009 struct si_pm4_state
*vgt_shader_config
[SI_NUM_VGT_STAGES_STATES
];
1012 struct si_shader_ctx_state ps_shader
;
1013 struct si_shader_ctx_state gs_shader
;
1014 struct si_shader_ctx_state vs_shader
;
1015 struct si_shader_ctx_state tcs_shader
;
1016 struct si_shader_ctx_state tes_shader
;
1017 struct si_shader_ctx_state cs_prim_discard_state
;
1018 struct si_cs_shader_state cs_shader_state
;
1020 /* shader information */
1021 struct si_vertex_elements
*vertex_elements
;
1022 unsigned num_vertex_elements
;
1023 unsigned sprite_coord_enable
;
1024 unsigned cs_max_waves_per_sh
;
1026 bool do_update_shaders
;
1028 /* shader descriptors */
1029 struct si_descriptors descriptors
[SI_NUM_DESCS
];
1030 unsigned descriptors_dirty
;
1031 unsigned shader_pointers_dirty
;
1032 unsigned shader_needs_decompress_mask
;
1033 struct si_buffer_resources rw_buffers
;
1034 struct si_buffer_resources const_and_shader_buffers
[SI_NUM_SHADERS
];
1035 struct si_samplers samplers
[SI_NUM_SHADERS
];
1036 struct si_images images
[SI_NUM_SHADERS
];
1037 bool bo_list_add_all_resident_resources
;
1038 bool bo_list_add_all_gfx_resources
;
1039 bool bo_list_add_all_compute_resources
;
1041 /* other shader resources */
1042 struct pipe_constant_buffer null_const_buf
; /* used for set_constant_buffer(NULL) on GFX7 */
1043 struct pipe_resource
*esgs_ring
;
1044 struct pipe_resource
*gsvs_ring
;
1045 struct pipe_resource
*tess_rings
;
1046 union pipe_color_union
*border_color_table
; /* in CPU memory, any endian */
1047 struct si_resource
*border_color_buffer
;
1048 union pipe_color_union
*border_color_map
; /* in VRAM (slow access), little endian */
1049 unsigned border_color_count
;
1050 unsigned num_vs_blit_sgprs
;
1051 uint32_t vs_blit_sh_data
[SI_VS_BLIT_SGPRS_POS_TEXCOORD
];
1052 uint32_t cs_user_data
[4];
1054 /* Vertex buffers. */
1055 bool vertex_buffers_dirty
;
1056 bool vertex_buffer_pointer_dirty
;
1057 bool vertex_buffer_user_sgprs_dirty
;
1058 struct pipe_vertex_buffer vertex_buffer
[SI_NUM_VERTEX_BUFFERS
];
1059 uint16_t vertex_buffer_unaligned
; /* bitmask of not dword-aligned buffers */
1060 uint32_t *vb_descriptors_gpu_list
;
1061 struct si_resource
*vb_descriptors_buffer
;
1062 unsigned vb_descriptors_offset
;
1063 unsigned vb_descriptor_user_sgprs
[5 * 4];
1065 /* MSAA config state. */
1066 int ps_iter_samples
;
1067 bool ps_uses_fbfetch
;
1068 bool smoothing_enabled
;
1070 /* DB render state. */
1071 unsigned ps_db_shader_control
;
1072 unsigned dbcb_copy_sample
;
1073 bool dbcb_depth_copy_enabled
: 1;
1074 bool dbcb_stencil_copy_enabled
: 1;
1075 bool db_flush_depth_inplace
: 1;
1076 bool db_flush_stencil_inplace
: 1;
1077 bool db_depth_clear
: 1;
1078 bool db_depth_disable_expclear
: 1;
1079 bool db_stencil_clear
: 1;
1080 bool db_stencil_disable_expclear
: 1;
1081 bool occlusion_queries_disabled
: 1;
1082 bool generate_mipmap_for_depth
: 1;
1084 /* Emitted draw state. */
1085 bool gs_tri_strip_adj_fix
: 1;
1086 bool ls_vgpr_fix
: 1;
1087 bool prim_discard_cs_instancing
: 1;
1089 uint8_t ngg_culling
;
1090 int last_index_size
;
1091 int last_base_vertex
;
1092 int last_start_instance
;
1093 int last_instance_count
;
1095 int last_sh_base_reg
;
1096 int last_primitive_restart_en
;
1097 int last_restart_index
;
1099 int last_multi_vgt_param
;
1100 int last_gs_out_prim
;
1101 int last_binning_enabled
;
1102 unsigned current_vs_state
;
1103 unsigned last_vs_state
;
1104 enum pipe_prim_type current_rast_prim
; /* primitive type after TES, GS */
1106 struct si_small_prim_cull_info last_small_prim_cull_info
;
1107 struct si_resource
*small_prim_cull_info_buf
;
1108 uint64_t small_prim_cull_info_address
;
1109 bool small_prim_cull_info_dirty
;
1111 /* Scratch buffer */
1112 struct si_resource
*scratch_buffer
;
1113 unsigned scratch_waves
;
1114 unsigned spi_tmpring_size
;
1115 unsigned max_seen_scratch_bytes_per_wave
;
1116 unsigned max_seen_compute_scratch_bytes_per_wave
;
1118 struct si_resource
*compute_scratch_buffer
;
1120 /* Emitted derived tessellation state. */
1121 /* Local shader (VS), or HS if LS-HS are merged. */
1122 struct si_shader
*last_ls
;
1123 struct si_shader_selector
*last_tcs
;
1124 int last_num_tcs_input_cp
;
1125 int last_tes_sh_base
;
1126 bool last_tess_uses_primid
;
1127 unsigned last_num_patches
;
1128 int last_ls_hs_config
;
1132 struct si_saved_cs
*current_saved_cs
;
1133 uint64_t dmesg_timestamp
;
1134 unsigned apitrace_call_number
;
1137 bool need_check_render_feedback
;
1138 bool decompression_enabled
;
1139 bool dpbb_force_off
;
1140 bool vs_writes_viewport_index
;
1141 bool vs_disables_clipping_viewport
;
1143 /* Precomputed IA_MULTI_VGT_PARAM */
1144 union si_vgt_param_key ia_multi_vgt_param_key
;
1145 unsigned ia_multi_vgt_param
[SI_NUM_VGT_PARAM_STATES
];
1147 /* Bindless descriptors. */
1148 struct si_descriptors bindless_descriptors
;
1149 struct util_idalloc bindless_used_slots
;
1150 unsigned num_bindless_descriptors
;
1151 bool bindless_descriptors_dirty
;
1152 bool graphics_bindless_pointer_dirty
;
1153 bool compute_bindless_pointer_dirty
;
1155 /* Allocated bindless handles */
1156 struct hash_table
*tex_handles
;
1157 struct hash_table
*img_handles
;
1159 /* Resident bindless handles */
1160 struct util_dynarray resident_tex_handles
;
1161 struct util_dynarray resident_img_handles
;
1163 /* Resident bindless handles which need decompression */
1164 struct util_dynarray resident_tex_needs_color_decompress
;
1165 struct util_dynarray resident_img_needs_color_decompress
;
1166 struct util_dynarray resident_tex_needs_depth_decompress
;
1168 /* Bindless state */
1169 bool uses_bindless_samplers
;
1170 bool uses_bindless_images
;
1172 /* MSAA sample locations.
1173 * The first index is the sample index.
1174 * The second index is the coordinate: X, Y. */
1182 struct pipe_resource
*sample_pos_buffer
;
1185 unsigned num_draw_calls
;
1186 unsigned num_decompress_calls
;
1187 unsigned num_mrt_draw_calls
;
1188 unsigned num_prim_restart_calls
;
1189 unsigned num_spill_draw_calls
;
1190 unsigned num_compute_calls
;
1191 unsigned num_spill_compute_calls
;
1192 unsigned num_dma_calls
;
1193 unsigned num_cp_dma_calls
;
1194 unsigned num_vs_flushes
;
1195 unsigned num_ps_flushes
;
1196 unsigned num_cs_flushes
;
1197 unsigned num_cb_cache_flushes
;
1198 unsigned num_db_cache_flushes
;
1199 unsigned num_L2_invalidates
;
1200 unsigned num_L2_writebacks
;
1201 unsigned num_resident_handles
;
1202 uint64_t num_alloc_tex_transfer_bytes
;
1203 unsigned last_tex_ps_draw_ratio
; /* for query */
1204 unsigned compute_num_verts_accepted
;
1205 unsigned compute_num_verts_rejected
;
1206 unsigned compute_num_verts_ineligible
; /* due to low vertex count */
1207 unsigned context_roll
;
1210 /* Maintain the list of active queries for pausing between IBs. */
1211 int num_occlusion_queries
;
1212 int num_perfect_occlusion_queries
;
1213 int num_pipeline_stat_queries
;
1214 struct list_head active_queries
;
1215 unsigned num_cs_dw_queries_suspend
;
1217 /* Render condition. */
1218 struct pipe_query
*render_cond
;
1219 unsigned render_cond_mode
;
1220 bool render_cond_invert
;
1221 bool render_cond_force_off
; /* for u_blitter */
1223 /* For uploading data via GTT and copy to VRAM on context flush via SDMA. */
1224 bool sdma_uploads_in_progress
;
1225 struct si_sdma_upload
*sdma_uploads
;
1226 unsigned num_sdma_uploads
;
1227 unsigned max_sdma_uploads
;
1229 /* Shader-based queries. */
1230 struct list_head shader_query_buffers
;
1231 unsigned num_active_shader_queries
;
1233 /* Statistics gathering for the DCC enablement heuristic. It can't be
1234 * in si_texture because si_texture can be shared by multiple
1235 * contexts. This is for back buffers only. We shouldn't get too many
1238 * X11 DRI3 rotates among a finite set of back buffers. They should
1239 * all fit in this array. If they don't, separate DCC might never be
1240 * enabled by DCC stat gathering.
1243 struct si_texture
*tex
;
1244 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1245 struct pipe_query
*ps_stats
[3];
1246 /* If all slots are used and another slot is needed,
1247 * the least recently used slot is evicted based on this. */
1248 int64_t last_use_timestamp
;
1252 /* Copy one resource to another using async DMA. */
1253 void (*dma_copy
)(struct pipe_context
*ctx
, struct pipe_resource
*dst
, unsigned dst_level
,
1254 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
, struct pipe_resource
*src
,
1255 unsigned src_level
, const struct pipe_box
*src_box
);
1257 struct si_tracked_regs tracked_regs
;
1261 void cik_init_sdma_functions(struct si_context
*sctx
);
1264 enum si_blitter_op
/* bitmask */
1266 SI_SAVE_TEXTURES
= 1,
1267 SI_SAVE_FRAMEBUFFER
= 2,
1268 SI_SAVE_FRAGMENT_STATE
= 4,
1269 SI_DISABLE_RENDER_COND
= 8,
1272 void si_blitter_begin(struct si_context
*sctx
, enum si_blitter_op op
);
1273 void si_blitter_end(struct si_context
*sctx
);
1274 void si_init_blit_functions(struct si_context
*sctx
);
1275 void si_decompress_textures(struct si_context
*sctx
, unsigned shader_mask
);
1276 void si_decompress_subresource(struct pipe_context
*ctx
, struct pipe_resource
*tex
, unsigned planes
,
1277 unsigned level
, unsigned first_layer
, unsigned last_layer
);
1278 void si_resource_copy_region(struct pipe_context
*ctx
, struct pipe_resource
*dst
,
1279 unsigned dst_level
, unsigned dstx
, unsigned dsty
, unsigned dstz
,
1280 struct pipe_resource
*src
, unsigned src_level
,
1281 const struct pipe_box
*src_box
);
1282 void si_decompress_dcc(struct si_context
*sctx
, struct si_texture
*tex
);
1285 bool si_rings_is_buffer_referenced(struct si_context
*sctx
, struct pb_buffer
*buf
,
1286 enum radeon_bo_usage usage
);
1287 void *si_buffer_map_sync_with_rings(struct si_context
*sctx
, struct si_resource
*resource
,
1289 void si_init_resource_fields(struct si_screen
*sscreen
, struct si_resource
*res
, uint64_t size
,
1290 unsigned alignment
);
1291 bool si_alloc_resource(struct si_screen
*sscreen
, struct si_resource
*res
);
1292 struct pipe_resource
*pipe_aligned_buffer_create(struct pipe_screen
*screen
, unsigned flags
,
1293 unsigned usage
, unsigned size
, unsigned alignment
);
1294 struct si_resource
*si_aligned_buffer_create(struct pipe_screen
*screen
, unsigned flags
,
1295 unsigned usage
, unsigned size
, unsigned alignment
);
1296 void si_replace_buffer_storage(struct pipe_context
*ctx
, struct pipe_resource
*dst
,
1297 struct pipe_resource
*src
);
1298 void si_init_screen_buffer_functions(struct si_screen
*sscreen
);
1299 void si_init_buffer_functions(struct si_context
*sctx
);
1302 enum pipe_format
si_simplify_cb_format(enum pipe_format format
);
1303 bool vi_alpha_is_on_msb(struct si_screen
*sscreen
, enum pipe_format format
);
1304 bool vi_dcc_clear_level(struct si_context
*sctx
, struct si_texture
*tex
, unsigned level
,
1305 unsigned clear_value
);
1306 void si_init_clear_functions(struct si_context
*sctx
);
1308 /* si_compute_blit.c */
1309 unsigned si_get_flush_flags(struct si_context
*sctx
, enum si_coherency coher
,
1310 enum si_cache_policy cache_policy
);
1311 void si_clear_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
, uint64_t offset
,
1312 uint64_t size
, uint32_t *clear_value
, uint32_t clear_value_size
,
1313 enum si_coherency coher
, bool force_cpdma
);
1314 void si_copy_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
, struct pipe_resource
*src
,
1315 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
);
1316 void si_compute_copy_image(struct si_context
*sctx
, struct pipe_resource
*dst
, unsigned dst_level
,
1317 struct pipe_resource
*src
, unsigned src_level
, unsigned dstx
,
1318 unsigned dsty
, unsigned dstz
, const struct pipe_box
*src_box
);
1319 void si_compute_clear_render_target(struct pipe_context
*ctx
, struct pipe_surface
*dstsurf
,
1320 const union pipe_color_union
*color
, unsigned dstx
,
1321 unsigned dsty
, unsigned width
, unsigned height
,
1322 bool render_condition_enabled
);
1323 void si_retile_dcc(struct si_context
*sctx
, struct si_texture
*tex
);
1324 void si_compute_expand_fmask(struct pipe_context
*ctx
, struct pipe_resource
*tex
);
1325 void si_init_compute_blit_functions(struct si_context
*sctx
);
1328 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1329 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1330 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1331 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1332 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1333 #define SI_CPDMA_SKIP_ALL \
1334 (SI_CPDMA_SKIP_CHECK_CS_SPACE | SI_CPDMA_SKIP_SYNC_AFTER | SI_CPDMA_SKIP_SYNC_BEFORE | \
1335 SI_CPDMA_SKIP_GFX_SYNC | SI_CPDMA_SKIP_BO_LIST_UPDATE)
1337 void si_cp_dma_wait_for_idle(struct si_context
*sctx
);
1338 void si_cp_dma_clear_buffer(struct si_context
*sctx
, struct radeon_cmdbuf
*cs
,
1339 struct pipe_resource
*dst
, uint64_t offset
, uint64_t size
,
1340 unsigned value
, unsigned user_flags
, enum si_coherency coher
,
1341 enum si_cache_policy cache_policy
);
1342 void si_cp_dma_copy_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
,
1343 struct pipe_resource
*src
, uint64_t dst_offset
, uint64_t src_offset
,
1344 unsigned size
, unsigned user_flags
, enum si_coherency coher
,
1345 enum si_cache_policy cache_policy
);
1346 void cik_prefetch_TC_L2_async(struct si_context
*sctx
, struct pipe_resource
*buf
, uint64_t offset
,
1348 void cik_emit_prefetch_L2(struct si_context
*sctx
, bool vertex_stage_only
);
1349 void si_test_gds(struct si_context
*sctx
);
1350 void si_cp_write_data(struct si_context
*sctx
, struct si_resource
*buf
, unsigned offset
,
1351 unsigned size
, unsigned dst_sel
, unsigned engine
, const void *data
);
1352 void si_cp_copy_data(struct si_context
*sctx
, struct radeon_cmdbuf
*cs
, unsigned dst_sel
,
1353 struct si_resource
*dst
, unsigned dst_offset
, unsigned src_sel
,
1354 struct si_resource
*src
, unsigned src_offset
);
1357 void si_save_cs(struct radeon_winsys
*ws
, struct radeon_cmdbuf
*cs
, struct radeon_saved_cs
*saved
,
1358 bool get_buffer_list
);
1359 void si_clear_saved_cs(struct radeon_saved_cs
*saved
);
1360 void si_destroy_saved_cs(struct si_saved_cs
*scs
);
1361 void si_auto_log_cs(void *data
, struct u_log_context
*log
);
1362 void si_log_hw_flush(struct si_context
*sctx
);
1363 void si_log_draw_state(struct si_context
*sctx
, struct u_log_context
*log
);
1364 void si_log_compute_state(struct si_context
*sctx
, struct u_log_context
*log
);
1365 void si_init_debug_functions(struct si_context
*sctx
);
1366 void si_check_vm_faults(struct si_context
*sctx
, struct radeon_saved_cs
*saved
,
1367 enum ring_type ring
);
1368 bool si_replace_shader(unsigned num
, struct si_shader_binary
*binary
);
1371 void si_dma_emit_timestamp(struct si_context
*sctx
, struct si_resource
*dst
, uint64_t offset
);
1372 void si_sdma_clear_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
, uint64_t offset
,
1373 uint64_t size
, unsigned clear_value
);
1374 void si_sdma_copy_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
,
1375 struct pipe_resource
*src
, uint64_t dst_offset
, uint64_t src_offset
,
1377 void si_need_dma_space(struct si_context
*ctx
, unsigned num_dw
, struct si_resource
*dst
,
1378 struct si_resource
*src
);
1379 void si_flush_dma_cs(struct si_context
*ctx
, unsigned flags
, struct pipe_fence_handle
**fence
);
1380 void si_screen_clear_buffer(struct si_screen
*sscreen
, struct pipe_resource
*dst
, uint64_t offset
,
1381 uint64_t size
, unsigned value
);
1384 void si_cp_release_mem(struct si_context
*ctx
, struct radeon_cmdbuf
*cs
, unsigned event
,
1385 unsigned event_flags
, unsigned dst_sel
, unsigned int_sel
, unsigned data_sel
,
1386 struct si_resource
*buf
, uint64_t va
, uint32_t new_fence
,
1387 unsigned query_type
);
1388 unsigned si_cp_write_fence_dwords(struct si_screen
*screen
);
1389 void si_cp_wait_mem(struct si_context
*ctx
, struct radeon_cmdbuf
*cs
, uint64_t va
, uint32_t ref
,
1390 uint32_t mask
, unsigned flags
);
1391 void si_init_fence_functions(struct si_context
*ctx
);
1392 void si_init_screen_fence_functions(struct si_screen
*screen
);
1393 struct pipe_fence_handle
*si_create_fence(struct pipe_context
*ctx
,
1394 struct tc_unflushed_batch_token
*tc_token
);
1397 void si_init_screen_get_functions(struct si_screen
*sscreen
);
1400 void si_flush_gfx_cs(struct si_context
*ctx
, unsigned flags
, struct pipe_fence_handle
**fence
);
1401 void si_allocate_gds(struct si_context
*ctx
);
1402 void si_begin_new_gfx_cs(struct si_context
*ctx
);
1403 void si_need_gfx_cs_space(struct si_context
*ctx
);
1404 void si_unref_sdma_uploads(struct si_context
*sctx
);
1407 void si_gpu_load_kill_thread(struct si_screen
*sscreen
);
1408 uint64_t si_begin_counter(struct si_screen
*sscreen
, unsigned type
);
1409 unsigned si_end_counter(struct si_screen
*sscreen
, unsigned type
, uint64_t begin
);
1412 void si_emit_initial_compute_regs(struct si_context
*sctx
, struct radeon_cmdbuf
*cs
);
1413 void si_init_compute_functions(struct si_context
*sctx
);
1415 /* si_compute_prim_discard.c */
1416 enum si_prim_discard_outcome
1418 SI_PRIM_DISCARD_ENABLED
,
1419 SI_PRIM_DISCARD_DISABLED
,
1420 SI_PRIM_DISCARD_DRAW_SPLIT
,
1423 void si_build_prim_discard_compute_shader(struct si_shader_context
*ctx
);
1424 enum si_prim_discard_outcome
1425 si_prepare_prim_discard_or_split_draw(struct si_context
*sctx
, const struct pipe_draw_info
*info
,
1426 bool primitive_restart
);
1427 void si_compute_signal_gfx(struct si_context
*sctx
);
1428 void si_dispatch_prim_discard_cs_and_draw(struct si_context
*sctx
,
1429 const struct pipe_draw_info
*info
, unsigned index_size
,
1430 unsigned base_vertex
, uint64_t input_indexbuf_va
,
1431 unsigned input_indexbuf_max_elements
);
1432 void si_initialize_prim_discard_tunables(struct si_screen
*sscreen
, bool is_aux_context
,
1433 unsigned *prim_discard_vertex_count_threshold
,
1434 unsigned *index_ring_size_per_ib
);
1437 void si_init_compiler(struct si_screen
*sscreen
, struct ac_llvm_compiler
*compiler
);
1439 /* si_perfcounters.c */
1440 void si_init_perfcounters(struct si_screen
*screen
);
1441 void si_destroy_perfcounters(struct si_screen
*screen
);
1444 void si_init_screen_query_functions(struct si_screen
*sscreen
);
1445 void si_init_query_functions(struct si_context
*sctx
);
1446 void si_suspend_queries(struct si_context
*sctx
);
1447 void si_resume_queries(struct si_context
*sctx
);
1449 /* si_shaderlib_tgsi.c */
1450 void *si_get_blitter_vs(struct si_context
*sctx
, enum blitter_attrib_type type
,
1451 unsigned num_layers
);
1452 void *si_create_fixed_func_tcs(struct si_context
*sctx
);
1453 void *si_create_dma_compute_shader(struct pipe_context
*ctx
, unsigned num_dwords_per_thread
,
1454 bool dst_stream_cache_policy
, bool is_copy
);
1455 void *si_create_copy_image_compute_shader(struct pipe_context
*ctx
);
1456 void *si_create_copy_image_compute_shader_1d_array(struct pipe_context
*ctx
);
1457 void *si_clear_render_target_shader(struct pipe_context
*ctx
);
1458 void *si_clear_render_target_shader_1d_array(struct pipe_context
*ctx
);
1459 void *si_clear_12bytes_buffer_shader(struct pipe_context
*ctx
);
1460 void *si_create_dcc_retile_cs(struct pipe_context
*ctx
);
1461 void *si_create_fmask_expand_cs(struct pipe_context
*ctx
, unsigned num_samples
, bool is_array
);
1462 void *si_create_query_result_cs(struct si_context
*sctx
);
1463 void *gfx10_create_sh_query_result_cs(struct si_context
*sctx
);
1466 void gfx10_init_query(struct si_context
*sctx
);
1467 void gfx10_destroy_query(struct si_context
*sctx
);
1470 void si_test_dma(struct si_screen
*sscreen
);
1472 /* si_test_clearbuffer.c */
1473 void si_test_dma_perf(struct si_screen
*sscreen
);
1476 struct pipe_video_codec
*si_uvd_create_decoder(struct pipe_context
*context
,
1477 const struct pipe_video_codec
*templ
);
1479 struct pipe_video_buffer
*si_video_buffer_create(struct pipe_context
*pipe
,
1480 const struct pipe_video_buffer
*tmpl
);
1483 void si_update_ngg_small_prim_precision(struct si_context
*ctx
);
1484 void si_get_small_prim_cull_info(struct si_context
*sctx
, struct si_small_prim_cull_info
*out
);
1485 void si_update_vs_viewport_state(struct si_context
*ctx
);
1486 void si_init_viewport_functions(struct si_context
*ctx
);
1489 bool si_prepare_for_dma_blit(struct si_context
*sctx
, struct si_texture
*dst
, unsigned dst_level
,
1490 unsigned dstx
, unsigned dsty
, unsigned dstz
, struct si_texture
*src
,
1491 unsigned src_level
, const struct pipe_box
*src_box
);
1492 void si_eliminate_fast_color_clear(struct si_context
*sctx
, struct si_texture
*tex
);
1493 void si_texture_discard_cmask(struct si_screen
*sscreen
, struct si_texture
*tex
);
1494 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
, struct pipe_resource
*texture
);
1495 void si_print_texture_info(struct si_screen
*sscreen
, struct si_texture
*tex
,
1496 struct u_log_context
*log
);
1497 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1498 const struct pipe_resource
*templ
);
1499 bool vi_dcc_formats_compatible(struct si_screen
*sscreen
, enum pipe_format format1
,
1500 enum pipe_format format2
);
1501 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
, unsigned level
,
1502 enum pipe_format view_format
);
1503 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
, struct pipe_resource
*tex
,
1504 unsigned level
, enum pipe_format view_format
);
1505 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
1506 struct pipe_resource
*texture
,
1507 const struct pipe_surface
*templ
, unsigned width0
,
1508 unsigned height0
, unsigned width
, unsigned height
);
1509 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
);
1510 void vi_separate_dcc_try_enable(struct si_context
*sctx
, struct si_texture
*tex
);
1511 void vi_separate_dcc_start_query(struct si_context
*sctx
, struct si_texture
*tex
);
1512 void vi_separate_dcc_stop_query(struct si_context
*sctx
, struct si_texture
*tex
);
1513 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
, struct si_texture
*tex
);
1514 bool si_texture_disable_dcc(struct si_context
*sctx
, struct si_texture
*tex
);
1515 void si_init_screen_texture_functions(struct si_screen
*sscreen
);
1516 void si_init_context_texture_functions(struct si_context
*sctx
);
1522 static inline struct si_resource
*si_resource(struct pipe_resource
*r
)
1524 return (struct si_resource
*)r
;
1527 static inline void si_resource_reference(struct si_resource
**ptr
, struct si_resource
*res
)
1529 pipe_resource_reference((struct pipe_resource
**)ptr
, (struct pipe_resource
*)res
);
1532 static inline void si_texture_reference(struct si_texture
**ptr
, struct si_texture
*res
)
1534 pipe_resource_reference((struct pipe_resource
**)ptr
, &res
->buffer
.b
.b
);
1538 si_shader_selector_reference(struct si_context
*sctx
, /* sctx can optionally be NULL */
1539 struct si_shader_selector
**dst
, struct si_shader_selector
*src
)
1544 struct si_screen
*sscreen
= src
? src
->screen
: (*dst
)->screen
;
1545 util_shader_reference(&sctx
->b
, &sscreen
->live_shader_cache
, (void **)dst
, src
);
1548 static inline bool vi_dcc_enabled(struct si_texture
*tex
, unsigned level
)
1550 return tex
->surface
.dcc_offset
&& level
< tex
->surface
.num_dcc_levels
;
1553 static inline unsigned si_tile_mode_index(struct si_texture
*tex
, unsigned level
, bool stencil
)
1556 return tex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
1558 return tex
->surface
.u
.legacy
.tiling_index
[level
];
1561 static inline unsigned si_get_minimum_num_gfx_cs_dwords(struct si_context
*sctx
)
1563 /* Don't count the needed CS space exactly and just use an upper bound.
1565 * Also reserve space for stopping queries at the end of IB, because
1566 * the number of active queries is unlimited in theory.
1568 return 2048 + sctx
->num_cs_dw_queries_suspend
;
1571 static inline void si_context_add_resource_size(struct si_context
*sctx
, struct pipe_resource
*r
)
1574 /* Add memory usage for need_gfx_cs_space */
1575 sctx
->vram
+= si_resource(r
)->vram_usage
;
1576 sctx
->gtt
+= si_resource(r
)->gart_usage
;
1580 static inline void si_invalidate_draw_sh_constants(struct si_context
*sctx
)
1582 sctx
->last_base_vertex
= SI_BASE_VERTEX_UNKNOWN
;
1583 sctx
->last_instance_count
= SI_INSTANCE_COUNT_UNKNOWN
;
1586 static inline unsigned si_get_atom_bit(struct si_context
*sctx
, struct si_atom
*atom
)
1588 return 1 << (atom
- sctx
->atoms
.array
);
1591 static inline void si_set_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
, bool dirty
)
1593 unsigned bit
= si_get_atom_bit(sctx
, atom
);
1596 sctx
->dirty_atoms
|= bit
;
1598 sctx
->dirty_atoms
&= ~bit
;
1601 static inline bool si_is_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
)
1603 return (sctx
->dirty_atoms
& si_get_atom_bit(sctx
, atom
)) != 0;
1606 static inline void si_mark_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
)
1608 si_set_atom_dirty(sctx
, atom
, true);
1611 static inline struct si_shader_ctx_state
*si_get_vs(struct si_context
*sctx
)
1613 if (sctx
->gs_shader
.cso
)
1614 return &sctx
->gs_shader
;
1615 if (sctx
->tes_shader
.cso
)
1616 return &sctx
->tes_shader
;
1618 return &sctx
->vs_shader
;
1621 static inline struct si_shader_info
*si_get_vs_info(struct si_context
*sctx
)
1623 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
1625 return vs
->cso
? &vs
->cso
->info
: NULL
;
1628 static inline struct si_shader
*si_get_vs_state(struct si_context
*sctx
)
1630 if (sctx
->gs_shader
.cso
&& sctx
->gs_shader
.current
&& !sctx
->gs_shader
.current
->key
.as_ngg
)
1631 return sctx
->gs_shader
.cso
->gs_copy_shader
;
1633 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
1634 return vs
->current
? vs
->current
: NULL
;
1637 static inline bool si_can_dump_shader(struct si_screen
*sscreen
, unsigned processor
)
1639 return sscreen
->debug_flags
& (1 << processor
);
1642 static inline bool si_get_strmout_en(struct si_context
*sctx
)
1644 return sctx
->streamout
.streamout_enabled
|| sctx
->streamout
.prims_gen_query_enabled
;
1647 static inline unsigned si_optimal_tcc_alignment(struct si_context
*sctx
, unsigned upload_size
)
1649 unsigned alignment
, tcc_cache_line_size
;
1651 /* If the upload size is less than the cache line size (e.g. 16, 32),
1652 * the whole thing will fit into a cache line if we align it to its size.
1653 * The idea is that multiple small uploads can share a cache line.
1654 * If the upload size is greater, align it to the cache line size.
1656 alignment
= util_next_power_of_two(upload_size
);
1657 tcc_cache_line_size
= sctx
->screen
->info
.tcc_cache_line_size
;
1658 return MIN2(alignment
, tcc_cache_line_size
);
1661 static inline void si_saved_cs_reference(struct si_saved_cs
**dst
, struct si_saved_cs
*src
)
1663 if (pipe_reference(&(*dst
)->reference
, &src
->reference
))
1664 si_destroy_saved_cs(*dst
);
1669 static inline void si_make_CB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
1670 bool shaders_read_metadata
, bool dcc_pipe_aligned
)
1672 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
| SI_CONTEXT_INV_VCACHE
;
1674 if (sctx
->chip_class
>= GFX10
) {
1675 if (sctx
->screen
->info
.tcc_harvested
)
1676 sctx
->flags
|= SI_CONTEXT_INV_L2
;
1677 else if (shaders_read_metadata
)
1678 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1679 } else if (sctx
->chip_class
== GFX9
) {
1680 /* Single-sample color is coherent with shaders on GFX9, but
1681 * L2 metadata must be flushed if shaders read metadata.
1684 if (num_samples
>= 2 || (shaders_read_metadata
&& !dcc_pipe_aligned
))
1685 sctx
->flags
|= SI_CONTEXT_INV_L2
;
1686 else if (shaders_read_metadata
)
1687 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1690 sctx
->flags
|= SI_CONTEXT_INV_L2
;
1694 static inline void si_make_DB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
1695 bool include_stencil
, bool shaders_read_metadata
)
1697 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_DB
| SI_CONTEXT_INV_VCACHE
;
1699 if (sctx
->chip_class
>= GFX10
) {
1700 if (sctx
->screen
->info
.tcc_harvested
)
1701 sctx
->flags
|= SI_CONTEXT_INV_L2
;
1702 else if (shaders_read_metadata
)
1703 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1704 } else if (sctx
->chip_class
== GFX9
) {
1705 /* Single-sample depth (not stencil) is coherent with shaders
1706 * on GFX9, but L2 metadata must be flushed if shaders read
1709 if (num_samples
>= 2 || include_stencil
)
1710 sctx
->flags
|= SI_CONTEXT_INV_L2
;
1711 else if (shaders_read_metadata
)
1712 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1715 sctx
->flags
|= SI_CONTEXT_INV_L2
;
1719 static inline bool si_can_sample_zs(struct si_texture
*tex
, bool stencil_sampler
)
1721 return (stencil_sampler
&& tex
->can_sample_s
) || (!stencil_sampler
&& tex
->can_sample_z
);
1724 static inline bool si_htile_enabled(struct si_texture
*tex
, unsigned level
, unsigned zs_mask
)
1726 if (zs_mask
== PIPE_MASK_S
&& tex
->htile_stencil_disabled
)
1729 return tex
->surface
.htile_offset
&& level
== 0;
1732 static inline bool vi_tc_compat_htile_enabled(struct si_texture
*tex
, unsigned level
,
1735 assert(!tex
->tc_compatible_htile
|| tex
->surface
.htile_offset
);
1736 return tex
->tc_compatible_htile
&& si_htile_enabled(tex
, level
, zs_mask
);
1739 static inline unsigned si_get_ps_iter_samples(struct si_context
*sctx
)
1741 if (sctx
->ps_uses_fbfetch
)
1742 return sctx
->framebuffer
.nr_color_samples
;
1744 return MIN2(sctx
->ps_iter_samples
, sctx
->framebuffer
.nr_color_samples
);
1747 static inline unsigned si_get_total_colormask(struct si_context
*sctx
)
1749 if (sctx
->queued
.named
.rasterizer
->rasterizer_discard
)
1752 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1756 unsigned colormask
=
1757 sctx
->framebuffer
.colorbuf_enabled_4bit
& sctx
->queued
.named
.blend
->cb_target_mask
;
1759 if (!ps
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
])
1760 colormask
&= ps
->colors_written_4bit
;
1761 else if (!ps
->colors_written_4bit
)
1762 colormask
= 0; /* color0 writes all cbufs, but it's not written */
1767 #define UTIL_ALL_PRIM_LINE_MODES \
1768 ((1 << PIPE_PRIM_LINES) | (1 << PIPE_PRIM_LINE_LOOP) | (1 << PIPE_PRIM_LINE_STRIP) | \
1769 (1 << PIPE_PRIM_LINES_ADJACENCY) | (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1771 static inline bool util_prim_is_lines(unsigned prim
)
1773 return ((1 << prim
) & UTIL_ALL_PRIM_LINE_MODES
) != 0;
1776 static inline bool util_prim_is_points_or_lines(unsigned prim
)
1778 return ((1 << prim
) & (UTIL_ALL_PRIM_LINE_MODES
| (1 << PIPE_PRIM_POINTS
))) != 0;
1781 static inline bool util_rast_prim_is_triangles(unsigned prim
)
1783 return ((1 << prim
) &
1784 ((1 << PIPE_PRIM_TRIANGLES
) | (1 << PIPE_PRIM_TRIANGLE_STRIP
) |
1785 (1 << PIPE_PRIM_TRIANGLE_FAN
) | (1 << PIPE_PRIM_QUADS
) | (1 << PIPE_PRIM_QUAD_STRIP
) |
1786 (1 << PIPE_PRIM_POLYGON
) | (1 << PIPE_PRIM_TRIANGLES_ADJACENCY
) |
1787 (1 << PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
)));
1791 * Return true if there is enough memory in VRAM and GTT for the buffers
1794 * \param vram VRAM memory size not added to the buffer list yet
1795 * \param gtt GTT memory size not added to the buffer list yet
1797 static inline bool radeon_cs_memory_below_limit(struct si_screen
*screen
, struct radeon_cmdbuf
*cs
,
1798 uint64_t vram
, uint64_t gtt
)
1800 vram
+= cs
->used_vram
;
1801 gtt
+= cs
->used_gart
;
1803 /* Anything that goes above the VRAM size should go to GTT. */
1804 if (vram
> screen
->info
.vram_size
)
1805 gtt
+= vram
- screen
->info
.vram_size
;
1807 /* Now we just need to check if we have enough GTT. */
1808 return gtt
< screen
->info
.gart_size
* 0.7;
1812 * Add a buffer to the buffer list for the given command stream (CS).
1814 * All buffers used by a CS must be added to the list. This tells the kernel
1815 * driver which buffers are used by GPU commands. Other buffers can
1816 * be swapped out (not accessible) during execution.
1818 * The buffer list becomes empty after every context flush and must be
1821 static inline void radeon_add_to_buffer_list(struct si_context
*sctx
, struct radeon_cmdbuf
*cs
,
1822 struct si_resource
*bo
, enum radeon_bo_usage usage
,
1823 enum radeon_bo_priority priority
)
1826 sctx
->ws
->cs_add_buffer(cs
, bo
->buf
, (enum radeon_bo_usage
)(usage
| RADEON_USAGE_SYNCHRONIZED
),
1827 bo
->domains
, priority
);
1831 * Same as above, but also checks memory usage and flushes the context
1834 * When this SHOULD NOT be used:
1836 * - if si_context_add_resource_size has been called for the buffer
1837 * followed by *_need_cs_space for checking the memory usage
1839 * - if si_need_dma_space has been called for the buffer
1841 * - when emitting state packets and draw packets (because preceding packets
1842 * can't be re-emitted at that point)
1844 * - if shader resource "enabled_mask" is not up-to-date or there is
1845 * a different constraint disallowing a context flush
1847 static inline void radeon_add_to_gfx_buffer_list_check_mem(struct si_context
*sctx
,
1848 struct si_resource
*bo
,
1849 enum radeon_bo_usage usage
,
1850 enum radeon_bo_priority priority
,
1854 !radeon_cs_memory_below_limit(sctx
->screen
, sctx
->gfx_cs
, sctx
->vram
+ bo
->vram_usage
,
1855 sctx
->gtt
+ bo
->gart_usage
))
1856 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
1858 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, bo
, usage
, priority
);
1861 static inline bool si_compute_prim_discard_enabled(struct si_context
*sctx
)
1863 return sctx
->prim_discard_vertex_count_threshold
!= UINT_MAX
;
1866 static inline unsigned si_get_wave_size(struct si_screen
*sscreen
,
1867 enum pipe_shader_type shader_type
, bool ngg
, bool es
,
1868 bool prim_discard_cs
)
1870 if (shader_type
== PIPE_SHADER_COMPUTE
)
1871 return sscreen
->compute_wave_size
;
1872 else if (shader_type
== PIPE_SHADER_FRAGMENT
)
1873 return sscreen
->ps_wave_size
;
1874 else if ((shader_type
== PIPE_SHADER_VERTEX
&& prim_discard_cs
) || /* only Wave64 implemented */
1875 (shader_type
== PIPE_SHADER_VERTEX
&& es
&& !ngg
) ||
1876 (shader_type
== PIPE_SHADER_TESS_EVAL
&& es
&& !ngg
) ||
1877 (shader_type
== PIPE_SHADER_GEOMETRY
&& !ngg
)) /* legacy GS only supports Wave64 */
1880 return sscreen
->ge_wave_size
;
1883 static inline unsigned si_get_shader_wave_size(struct si_shader
*shader
)
1885 return si_get_wave_size(shader
->selector
->screen
, shader
->selector
->type
, shader
->key
.as_ngg
,
1886 shader
->key
.as_es
, shader
->key
.opt
.vs_as_prim_discard_cs
);
1889 #define PRINT_ERR(fmt, args...) \
1890 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)