9e5a8e87df4b02c7cc5802985e438262f9d007fe
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25 #ifndef SI_PIPE_H
26 #define SI_PIPE_H
27
28 #include "si_shader.h"
29 #include "si_state.h"
30 #include "util/u_dynarray.h"
31 #include "util/u_idalloc.h"
32 #include "util/u_threaded_context.h"
33
34 #if UTIL_ARCH_BIG_ENDIAN
35 #define SI_BIG_ENDIAN 1
36 #else
37 #define SI_BIG_ENDIAN 0
38 #endif
39
40 #define ATI_VENDOR_ID 0x1002
41 #define SI_PRIM_DISCARD_DEBUG 0
42 #define SI_NOT_QUERY 0xffffffff
43
44 /* The base vertex and primitive restart can be any number, but we must pick
45 * one which will mean "unknown" for the purpose of state tracking and
46 * the number shouldn't be a commonly-used one. */
47 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
48 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
49 #define SI_INSTANCE_COUNT_UNKNOWN INT_MIN
50 #define SI_NUM_SMOOTH_AA_SAMPLES 8
51 #define SI_MAX_POINT_SIZE 2048
52 #define SI_GS_PER_ES 128
53 /* Alignment for optimal CP DMA performance. */
54 #define SI_CPDMA_ALIGNMENT 32
55
56 /* Tunables for compute-based clear_buffer and copy_buffer: */
57 #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
58 #define SI_COMPUTE_COPY_DW_PER_THREAD 4
59 #define SI_COMPUTE_DST_CACHE_POLICY L2_STREAM
60
61 /* Pipeline & streamout query controls. */
62 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
63 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
64 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
65 /* Instruction cache. */
66 #define SI_CONTEXT_INV_ICACHE (1 << 3)
67 /* Scalar cache. (GFX6-9: scalar L1; GFX10: scalar L0)
68 * GFX10: This also invalidates the L1 shader array cache. */
69 #define SI_CONTEXT_INV_SCACHE (1 << 4)
70 /* Vector cache. (GFX6-9: vector L1; GFX10: vector L0)
71 * GFX10: This also invalidates the L1 shader array cache. */
72 #define SI_CONTEXT_INV_VCACHE (1 << 5)
73 /* L2 cache + L2 metadata cache writeback & invalidate.
74 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
75 #define SI_CONTEXT_INV_L2 (1 << 6)
76 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
77 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
78 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
79 #define SI_CONTEXT_WB_L2 (1 << 7)
80 /* Writeback & invalidate the L2 metadata cache only. It can only be coupled with
81 * a CB or DB flush. */
82 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
83 /* Framebuffer caches. */
84 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
85 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
86 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
87 /* Engine synchronization. */
88 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
89 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
90 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
91 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
92 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
93
94 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
95 #define SI_PREFETCH_LS (1 << 1)
96 #define SI_PREFETCH_HS (1 << 2)
97 #define SI_PREFETCH_ES (1 << 3)
98 #define SI_PREFETCH_GS (1 << 4)
99 #define SI_PREFETCH_VS (1 << 5)
100 #define SI_PREFETCH_PS (1 << 6)
101
102 #define SI_MAX_BORDER_COLORS 4096
103 #define SI_MAX_VIEWPORTS 16
104 #define SIX_BITS 0x3F
105 #define SI_MAP_BUFFER_ALIGNMENT 64
106 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
107
108 #define SI_RESOURCE_FLAG_FORCE_LINEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
109 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
110 #define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
111 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
112 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
113 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
114 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
115 #define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
116 /* For const_uploader, upload data via GTT and copy to VRAM on context flush via SDMA. */
117 #define SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA (PIPE_RESOURCE_FLAG_DRV_PRIV << 8)
118 /* Set a micro tile mode: */
119 #define SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE (PIPE_RESOURCE_FLAG_DRV_PRIV << 9)
120 #define SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT (util_logbase2(PIPE_RESOURCE_FLAG_DRV_PRIV) + 10)
121 #define SI_RESOURCE_FLAG_MICRO_TILE_MODE_SET(x) \
122 (((x)&0x3) << SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT)
123 #define SI_RESOURCE_FLAG_MICRO_TILE_MODE_GET(x) \
124 (((x) >> SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT) & 0x3)
125 #define SI_RESOURCE_FLAG_UNCACHED (PIPE_RESOURCE_FLAG_DRV_PRIV << 12)
126
127 enum si_clear_code
128 {
129 DCC_CLEAR_COLOR_0000 = 0x00000000,
130 DCC_CLEAR_COLOR_0001 = 0x40404040,
131 DCC_CLEAR_COLOR_1110 = 0x80808080,
132 DCC_CLEAR_COLOR_1111 = 0xC0C0C0C0,
133 DCC_CLEAR_COLOR_REG = 0x20202020,
134 DCC_UNCOMPRESSED = 0xFFFFFFFF,
135 };
136
137 #define SI_IMAGE_ACCESS_AS_BUFFER (1 << 7)
138 #define SI_IMAGE_ACCESS_DCC_OFF (1 << 8)
139
140 /* Debug flags. */
141 enum
142 {
143 /* Shader logging options: */
144 DBG_VS = PIPE_SHADER_VERTEX,
145 DBG_PS = PIPE_SHADER_FRAGMENT,
146 DBG_GS = PIPE_SHADER_GEOMETRY,
147 DBG_TCS = PIPE_SHADER_TESS_CTRL,
148 DBG_TES = PIPE_SHADER_TESS_EVAL,
149 DBG_CS = PIPE_SHADER_COMPUTE,
150 DBG_NO_IR,
151 DBG_NO_NIR,
152 DBG_NO_ASM,
153 DBG_PREOPT_IR,
154
155 /* Shader compiler options the shader cache should be aware of: */
156 DBG_FS_CORRECT_DERIVS_AFTER_KILL,
157 DBG_GISEL,
158 DBG_W32_GE,
159 DBG_W32_PS,
160 DBG_W32_CS,
161 DBG_W64_GE,
162 DBG_W64_PS,
163 DBG_W64_CS,
164 DBG_KILL_PS_INF_INTERP,
165
166 /* Shader compiler options (with no effect on the shader cache): */
167 DBG_CHECK_IR,
168 DBG_MONOLITHIC_SHADERS,
169 DBG_NO_OPT_VARIANT,
170
171 /* Information logging options: */
172 DBG_INFO,
173 DBG_TEX,
174 DBG_COMPUTE,
175 DBG_VM,
176 DBG_CACHE_STATS,
177
178 /* Driver options: */
179 DBG_FORCE_SDMA,
180 DBG_NO_SDMA,
181 DBG_NO_SDMA_CLEARS,
182 DBG_NO_SDMA_COPY_IMAGE,
183 DBG_NO_WC,
184 DBG_CHECK_VM,
185 DBG_RESERVE_VMID,
186 DBG_ZERO_VRAM,
187
188 /* 3D engine options: */
189 DBG_NO_GFX,
190 DBG_NO_NGG,
191 DBG_ALWAYS_NGG_CULLING,
192 DBG_NO_NGG_CULLING,
193 DBG_ALWAYS_PD,
194 DBG_PD,
195 DBG_NO_PD,
196 DBG_SWITCH_ON_EOP,
197 DBG_NO_OUT_OF_ORDER,
198 DBG_NO_DPBB,
199 DBG_NO_DFSM,
200 DBG_DPBB,
201 DBG_DFSM,
202 DBG_NO_HYPERZ,
203 DBG_NO_RB_PLUS,
204 DBG_NO_2D_TILING,
205 DBG_NO_TILING,
206 DBG_NO_DCC,
207 DBG_NO_DCC_CLEAR,
208 DBG_NO_DCC_FB,
209 DBG_NO_DCC_MSAA,
210 DBG_NO_FMASK,
211
212 DBG_COUNT
213 };
214
215 enum
216 {
217 /* Tests: */
218 DBG_TEST_DMA,
219 DBG_TEST_VMFAULT_CP,
220 DBG_TEST_VMFAULT_SDMA,
221 DBG_TEST_VMFAULT_SHADER,
222 DBG_TEST_DMA_PERF,
223 DBG_TEST_GDS,
224 DBG_TEST_GDS_MM,
225 DBG_TEST_GDS_OA_MM,
226 };
227
228 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
229 #define DBG(name) (1ull << DBG_##name)
230
231 enum si_cache_policy
232 {
233 L2_BYPASS,
234 L2_STREAM, /* same as SLC=1 */
235 L2_LRU, /* same as SLC=0 */
236 };
237
238 enum si_coherency
239 {
240 SI_COHERENCY_NONE, /* no cache flushes needed */
241 SI_COHERENCY_SHADER,
242 SI_COHERENCY_CB_META,
243 SI_COHERENCY_DB_META,
244 SI_COHERENCY_CP,
245 };
246
247 struct si_compute;
248 struct si_shader_context;
249 struct hash_table;
250 struct u_suballocator;
251
252 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
253 * at the moment.
254 */
255 struct si_resource {
256 struct threaded_resource b;
257
258 /* Winsys objects. */
259 struct pb_buffer *buf;
260 uint64_t gpu_address;
261 /* Memory usage if the buffer placement is optimal. */
262 uint64_t vram_usage;
263 uint64_t gart_usage;
264
265 /* Resource properties. */
266 uint64_t bo_size;
267 unsigned bo_alignment;
268 enum radeon_bo_domain domains;
269 enum radeon_bo_flag flags;
270 unsigned bind_history;
271 int max_forced_staging_uploads;
272
273 /* The buffer range which is initialized (with a write transfer,
274 * streamout, DMA, or as a random access target). The rest of
275 * the buffer is considered invalid and can be mapped unsynchronized.
276 *
277 * This allows unsychronized mapping of a buffer range which hasn't
278 * been used yet. It's for applications which forget to use
279 * the unsynchronized map flag and expect the driver to figure it out.
280 */
281 struct util_range valid_buffer_range;
282
283 /* For buffers only. This indicates that a write operation has been
284 * performed by TC L2, but the cache hasn't been flushed.
285 * Any hw block which doesn't use or bypasses TC L2 should check this
286 * flag and flush the cache before using the buffer.
287 *
288 * For example, TC L2 must be flushed if a buffer which has been
289 * modified by a shader store instruction is about to be used as
290 * an index buffer. The reason is that VGT DMA index fetching doesn't
291 * use TC L2.
292 */
293 bool TC_L2_dirty;
294
295 /* Whether this resource is referenced by bindless handles. */
296 bool texture_handle_allocated;
297 bool image_handle_allocated;
298
299 /* Whether the resource has been exported via resource_get_handle. */
300 unsigned external_usage; /* PIPE_HANDLE_USAGE_* */
301 };
302
303 struct si_transfer {
304 struct threaded_transfer b;
305 struct si_resource *staging;
306 unsigned offset;
307 };
308
309 struct si_texture {
310 struct si_resource buffer;
311
312 struct radeon_surf surface;
313 struct si_texture *flushed_depth_texture;
314
315 /* One texture allocation can contain these buffers:
316 * - image (pixel data)
317 * - FMASK buffer (MSAA compression)
318 * - CMASK buffer (MSAA compression and/or legacy fast color clear)
319 * - HTILE buffer (Z/S compression and fast Z/S clear)
320 * - DCC buffer (color compression and new fast color clear)
321 * - displayable DCC buffer (if the DCC buffer is not displayable)
322 * - DCC retile mapping buffer (if the DCC buffer is not displayable)
323 */
324 uint64_t cmask_base_address_reg;
325 struct si_resource *cmask_buffer;
326 unsigned cb_color_info; /* fast clear enable bit */
327 unsigned color_clear_value[2];
328 unsigned last_msaa_resolve_target_micro_mode;
329 unsigned num_level0_transfers;
330 unsigned plane_index; /* other planes are different pipe_resources */
331 unsigned num_planes;
332
333 /* Depth buffer compression and fast clear. */
334 float depth_clear_value;
335 uint16_t dirty_level_mask; /* each bit says if that mipmap is compressed */
336 uint16_t stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
337 enum pipe_format db_render_format : 16;
338 uint8_t stencil_clear_value;
339 bool fmask_is_identity : 1;
340 bool tc_compatible_htile : 1;
341 bool enable_tc_compatible_htile_next_clear : 1;
342 bool htile_stencil_disabled : 1;
343 bool depth_cleared : 1; /* if it was cleared at least once */
344 bool stencil_cleared : 1; /* if it was cleared at least once */
345 bool upgraded_depth : 1; /* upgraded from unorm to Z32_FLOAT */
346 bool is_depth : 1;
347 bool db_compatible : 1;
348 bool can_sample_z : 1;
349 bool can_sample_s : 1;
350
351 /* We need to track DCC dirtiness, because st/dri usually calls
352 * flush_resource twice per frame (not a bug) and we don't wanna
353 * decompress DCC twice. Also, the dirty tracking must be done even
354 * if DCC isn't used, because it's required by the DCC usage analysis
355 * for a possible future enablement.
356 */
357 bool separate_dcc_dirty : 1;
358 bool displayable_dcc_dirty : 1;
359
360 /* Statistics gathering for the DCC enablement heuristic. */
361 bool dcc_gather_statistics : 1;
362 /* Counter that should be non-zero if the texture is bound to a
363 * framebuffer.
364 */
365 unsigned framebuffers_bound;
366 /* Whether the texture is a displayable back buffer and needs DCC
367 * decompression, which is expensive. Therefore, it's enabled only
368 * if statistics suggest that it will pay off and it's allocated
369 * separately. It can't be bound as a sampler by apps. Limited to
370 * target == 2D and last_level == 0. If enabled, dcc_offset contains
371 * the absolute GPUVM address, not the relative one.
372 */
373 struct si_resource *dcc_separate_buffer;
374 /* When DCC is temporarily disabled, the separate buffer is here. */
375 struct si_resource *last_dcc_separate_buffer;
376 /* Estimate of how much this color buffer is written to in units of
377 * full-screen draws: ps_invocations / (width * height)
378 * Shader kills, late Z, and blending with trivial discards make it
379 * inaccurate (we need to count CB updates, not PS invocations).
380 */
381 unsigned ps_draw_ratio;
382 /* The number of clears since the last DCC usage analysis. */
383 unsigned num_slow_clears;
384 };
385
386 struct si_surface {
387 struct pipe_surface base;
388
389 /* These can vary with block-compressed textures. */
390 uint16_t width0;
391 uint16_t height0;
392
393 bool color_initialized : 1;
394 bool depth_initialized : 1;
395
396 /* Misc. color flags. */
397 bool color_is_int8 : 1;
398 bool color_is_int10 : 1;
399 bool dcc_incompatible : 1;
400
401 /* Color registers. */
402 unsigned cb_color_info;
403 unsigned cb_color_view;
404 unsigned cb_color_attrib;
405 unsigned cb_color_attrib2; /* GFX9 and later */
406 unsigned cb_color_attrib3; /* GFX10 and later */
407 unsigned cb_dcc_control; /* GFX8 and later */
408 unsigned spi_shader_col_format : 8; /* no blending, no alpha-to-coverage. */
409 unsigned spi_shader_col_format_alpha : 8; /* alpha-to-coverage */
410 unsigned spi_shader_col_format_blend : 8; /* blending without alpha. */
411 unsigned spi_shader_col_format_blend_alpha : 8; /* blending with alpha. */
412
413 /* DB registers. */
414 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE */
415 uint64_t db_stencil_base;
416 uint64_t db_htile_data_base;
417 unsigned db_depth_info;
418 unsigned db_z_info;
419 unsigned db_z_info2; /* GFX9 only */
420 unsigned db_depth_view;
421 unsigned db_depth_size;
422 unsigned db_depth_slice;
423 unsigned db_stencil_info;
424 unsigned db_stencil_info2; /* GFX9 only */
425 unsigned db_htile_surface;
426 };
427
428 struct si_mmio_counter {
429 unsigned busy;
430 unsigned idle;
431 };
432
433 union si_mmio_counters {
434 struct {
435 /* For global GPU load including SDMA. */
436 struct si_mmio_counter gpu;
437
438 /* GRBM_STATUS */
439 struct si_mmio_counter spi;
440 struct si_mmio_counter gui;
441 struct si_mmio_counter ta;
442 struct si_mmio_counter gds;
443 struct si_mmio_counter vgt;
444 struct si_mmio_counter ia;
445 struct si_mmio_counter sx;
446 struct si_mmio_counter wd;
447 struct si_mmio_counter bci;
448 struct si_mmio_counter sc;
449 struct si_mmio_counter pa;
450 struct si_mmio_counter db;
451 struct si_mmio_counter cp;
452 struct si_mmio_counter cb;
453
454 /* SRBM_STATUS2 */
455 struct si_mmio_counter sdma;
456
457 /* CP_STAT */
458 struct si_mmio_counter pfp;
459 struct si_mmio_counter meq;
460 struct si_mmio_counter me;
461 struct si_mmio_counter surf_sync;
462 struct si_mmio_counter cp_dma;
463 struct si_mmio_counter scratch_ram;
464 } named;
465 unsigned array[0];
466 };
467
468 struct si_memory_object {
469 struct pipe_memory_object b;
470 struct pb_buffer *buf;
471 uint32_t stride;
472 };
473
474 /* Saved CS data for debugging features. */
475 struct radeon_saved_cs {
476 uint32_t *ib;
477 unsigned num_dw;
478
479 struct radeon_bo_list_item *bo_list;
480 unsigned bo_count;
481 };
482
483 struct si_screen {
484 struct pipe_screen b;
485 struct radeon_winsys *ws;
486 struct disk_cache *disk_shader_cache;
487
488 struct radeon_info info;
489 uint64_t debug_flags;
490 char renderer_string[183];
491
492 void (*make_texture_descriptor)(struct si_screen *screen, struct si_texture *tex, bool sampler,
493 enum pipe_texture_target target, enum pipe_format pipe_format,
494 const unsigned char state_swizzle[4], unsigned first_level,
495 unsigned last_level, unsigned first_layer, unsigned last_layer,
496 unsigned width, unsigned height, unsigned depth, uint32_t *state,
497 uint32_t *fmask_state);
498
499 unsigned num_vbos_in_user_sgprs;
500 unsigned pa_sc_raster_config;
501 unsigned pa_sc_raster_config_1;
502 unsigned se_tile_repeat;
503 unsigned gs_table_depth;
504 unsigned tess_offchip_block_dw_size;
505 unsigned tess_offchip_ring_size;
506 unsigned tess_factor_ring_size;
507 unsigned vgt_hs_offchip_param;
508 unsigned eqaa_force_coverage_samples;
509 unsigned eqaa_force_z_samples;
510 unsigned eqaa_force_color_samples;
511 bool has_draw_indirect_multi;
512 bool has_out_of_order_rast;
513 bool assume_no_z_fights;
514 bool commutative_blend_add;
515 bool dpbb_allowed;
516 bool dfsm_allowed;
517 bool llvm_has_working_vgpr_indexing;
518 bool use_ngg;
519 bool use_ngg_culling;
520 bool always_use_ngg_culling;
521 bool use_ngg_streamout;
522
523 struct {
524 #define OPT_BOOL(name, dflt, description) bool name : 1;
525 #include "si_debug_options.h"
526 } options;
527
528 /* Whether shaders are monolithic (1-part) or separate (3-part). */
529 bool use_monolithic_shaders;
530 bool record_llvm_ir;
531 bool dcc_msaa_allowed;
532
533 struct slab_parent_pool pool_transfers;
534
535 /* Texture filter settings. */
536 int force_aniso; /* -1 = disabled */
537
538 /* Auxiliary context. Mainly used to initialize resources.
539 * It must be locked prior to using and flushed before unlocking. */
540 struct pipe_context *aux_context;
541 simple_mtx_t aux_context_lock;
542
543 /* This must be in the screen, because UE4 uses one context for
544 * compilation and another one for rendering.
545 */
546 unsigned num_compilations;
547 /* Along with ST_DEBUG=precompile, this should show if applications
548 * are loading shaders on demand. This is a monotonic counter.
549 */
550 unsigned num_shaders_created;
551 unsigned num_memory_shader_cache_hits;
552 unsigned num_memory_shader_cache_misses;
553 unsigned num_disk_shader_cache_hits;
554 unsigned num_disk_shader_cache_misses;
555
556 /* GPU load thread. */
557 simple_mtx_t gpu_load_mutex;
558 thrd_t gpu_load_thread;
559 union si_mmio_counters mmio_counters;
560 volatile unsigned gpu_load_stop_thread; /* bool */
561
562 /* Performance counters. */
563 struct si_perfcounters *perfcounters;
564
565 /* If pipe_screen wants to recompute and re-emit the framebuffer,
566 * sampler, and image states of all contexts, it should atomically
567 * increment this.
568 *
569 * Each context will compare this with its own last known value of
570 * the counter before drawing and re-emit the states accordingly.
571 */
572 unsigned dirty_tex_counter;
573 unsigned dirty_buf_counter;
574
575 /* Atomically increment this counter when an existing texture's
576 * metadata is enabled or disabled in a way that requires changing
577 * contexts' compressed texture binding masks.
578 */
579 unsigned compressed_colortex_counter;
580
581 struct {
582 /* Context flags to set so that all writes from earlier jobs
583 * in the CP are seen by L2 clients.
584 */
585 unsigned cp_to_L2;
586
587 /* Context flags to set so that all writes from earlier jobs
588 * that end in L2 are seen by CP.
589 */
590 unsigned L2_to_cp;
591 } barrier_flags;
592
593 simple_mtx_t shader_parts_mutex;
594 struct si_shader_part *vs_prologs;
595 struct si_shader_part *tcs_epilogs;
596 struct si_shader_part *gs_prologs;
597 struct si_shader_part *ps_prologs;
598 struct si_shader_part *ps_epilogs;
599
600 /* Shader cache in memory.
601 *
602 * Design & limitations:
603 * - The shader cache is per screen (= per process), never saved to
604 * disk, and skips redundant shader compilations from NIR to bytecode.
605 * - It can only be used with one-variant-per-shader support, in which
606 * case only the main (typically middle) part of shaders is cached.
607 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
608 * variants of VS and TES are cached, so LS and ES aren't.
609 * - GS and CS aren't cached, but it's certainly possible to cache
610 * those as well.
611 */
612 simple_mtx_t shader_cache_mutex;
613 struct hash_table *shader_cache;
614
615 /* Shader cache of live shaders. */
616 struct util_live_shader_cache live_shader_cache;
617
618 /* Shader compiler queue for multithreaded compilation. */
619 struct util_queue shader_compiler_queue;
620 /* Use at most 3 normal compiler threads on quadcore and better.
621 * Hyperthreaded CPUs report the number of threads, but we want
622 * the number of cores. We only need this many threads for shader-db. */
623 struct ac_llvm_compiler compiler[24]; /* used by the queue only */
624
625 struct util_queue shader_compiler_queue_low_priority;
626 /* Use at most 2 low priority threads on quadcore and better.
627 * We want to minimize the impact on multithreaded Mesa. */
628 struct ac_llvm_compiler compiler_lowp[10];
629
630 unsigned compute_wave_size;
631 unsigned ps_wave_size;
632 unsigned ge_wave_size;
633 };
634
635 struct si_blend_color {
636 struct pipe_blend_color state;
637 bool any_nonzeros;
638 };
639
640 struct si_sampler_view {
641 struct pipe_sampler_view base;
642 /* [0..7] = image descriptor
643 * [4..7] = buffer descriptor */
644 uint32_t state[8];
645 uint32_t fmask_state[8];
646 const struct legacy_surf_level *base_level_info;
647 ubyte base_level;
648 ubyte block_width;
649 bool is_stencil_sampler;
650 bool is_integer;
651 bool dcc_incompatible;
652 };
653
654 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
655
656 struct si_sampler_state {
657 #ifndef NDEBUG
658 unsigned magic;
659 #endif
660 uint32_t val[4];
661 uint32_t integer_val[4];
662 uint32_t upgraded_depth_val[4];
663 };
664
665 struct si_cs_shader_state {
666 struct si_compute *program;
667 struct si_compute *emitted_program;
668 unsigned offset;
669 bool initialized;
670 bool uses_scratch;
671 };
672
673 struct si_samplers {
674 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
675 struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS];
676
677 /* The i-th bit is set if that element is enabled (non-NULL resource). */
678 unsigned enabled_mask;
679 uint32_t needs_depth_decompress_mask;
680 uint32_t needs_color_decompress_mask;
681 };
682
683 struct si_images {
684 struct pipe_image_view views[SI_NUM_IMAGES];
685 uint32_t needs_color_decompress_mask;
686 unsigned enabled_mask;
687 };
688
689 struct si_framebuffer {
690 struct pipe_framebuffer_state state;
691 unsigned colorbuf_enabled_4bit;
692 unsigned spi_shader_col_format;
693 unsigned spi_shader_col_format_alpha;
694 unsigned spi_shader_col_format_blend;
695 unsigned spi_shader_col_format_blend_alpha;
696 ubyte nr_samples : 5; /* at most 16xAA */
697 ubyte log_samples : 3; /* at most 4 = 16xAA */
698 ubyte nr_color_samples; /* at most 8xAA */
699 ubyte compressed_cb_mask;
700 ubyte uncompressed_cb_mask;
701 ubyte displayable_dcc_cb_mask;
702 ubyte color_is_int8;
703 ubyte color_is_int10;
704 ubyte dirty_cbufs;
705 ubyte dcc_overwrite_combiner_watermark;
706 ubyte min_bytes_per_pixel;
707 bool dirty_zsbuf;
708 bool any_dst_linear;
709 bool CB_has_shader_readable_metadata;
710 bool DB_has_shader_readable_metadata;
711 bool all_DCC_pipe_aligned;
712 };
713
714 enum si_quant_mode
715 {
716 /* This is the list we want to support. */
717 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH,
718 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH,
719 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH,
720 };
721
722 struct si_signed_scissor {
723 int minx;
724 int miny;
725 int maxx;
726 int maxy;
727 enum si_quant_mode quant_mode;
728 };
729
730 struct si_viewports {
731 struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
732 struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS];
733 bool y_inverted;
734 };
735
736 struct si_clip_state {
737 struct pipe_clip_state state;
738 bool any_nonzeros;
739 };
740
741 struct si_streamout_target {
742 struct pipe_stream_output_target b;
743
744 /* The buffer where BUFFER_FILLED_SIZE is stored. */
745 struct si_resource *buf_filled_size;
746 unsigned buf_filled_size_offset;
747 bool buf_filled_size_valid;
748
749 unsigned stride_in_dw;
750 };
751
752 struct si_streamout {
753 bool begin_emitted;
754
755 unsigned enabled_mask;
756 unsigned num_targets;
757 struct si_streamout_target *targets[PIPE_MAX_SO_BUFFERS];
758
759 unsigned append_bitmask;
760 bool suspended;
761
762 /* External state which comes from the vertex shader,
763 * it must be set explicitly when binding a shader. */
764 uint16_t *stride_in_dw;
765 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
766
767 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
768 unsigned hw_enabled_mask;
769
770 /* The state of VGT_STRMOUT_(CONFIG|EN). */
771 bool streamout_enabled;
772 bool prims_gen_query_enabled;
773 int num_prims_gen_queries;
774 };
775
776 /* A shader state consists of the shader selector, which is a constant state
777 * object shared by multiple contexts and shouldn't be modified, and
778 * the current shader variant selected for this context.
779 */
780 struct si_shader_ctx_state {
781 struct si_shader_selector *cso;
782 struct si_shader *current;
783 };
784
785 #define SI_NUM_VGT_PARAM_KEY_BITS 12
786 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
787
788 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
789 * Some fields are set by state-change calls, most are set by draw_vbo.
790 */
791 union si_vgt_param_key {
792 struct {
793 #if UTIL_ARCH_LITTLE_ENDIAN
794 unsigned prim : 4;
795 unsigned uses_instancing : 1;
796 unsigned multi_instances_smaller_than_primgroup : 1;
797 unsigned primitive_restart : 1;
798 unsigned count_from_stream_output : 1;
799 unsigned line_stipple_enabled : 1;
800 unsigned uses_tess : 1;
801 unsigned tess_uses_prim_id : 1;
802 unsigned uses_gs : 1;
803 unsigned _pad : 32 - SI_NUM_VGT_PARAM_KEY_BITS;
804 #else /* UTIL_ARCH_BIG_ENDIAN */
805 unsigned _pad : 32 - SI_NUM_VGT_PARAM_KEY_BITS;
806 unsigned uses_gs : 1;
807 unsigned tess_uses_prim_id : 1;
808 unsigned uses_tess : 1;
809 unsigned line_stipple_enabled : 1;
810 unsigned count_from_stream_output : 1;
811 unsigned primitive_restart : 1;
812 unsigned multi_instances_smaller_than_primgroup : 1;
813 unsigned uses_instancing : 1;
814 unsigned prim : 4;
815 #endif
816 } u;
817 uint32_t index;
818 };
819
820 #define SI_NUM_VGT_STAGES_KEY_BITS 6
821 #define SI_NUM_VGT_STAGES_STATES (1 << SI_NUM_VGT_STAGES_KEY_BITS)
822
823 /* The VGT_SHADER_STAGES key used to index the table of precomputed values.
824 * Some fields are set by state-change calls, most are set by draw_vbo.
825 */
826 union si_vgt_stages_key {
827 struct {
828 #if UTIL_ARCH_LITTLE_ENDIAN
829 unsigned tess : 1;
830 unsigned gs : 1;
831 unsigned ngg_gs_fast_launch : 1;
832 unsigned ngg_passthrough : 1;
833 unsigned ngg : 1; /* gfx10+ */
834 unsigned streamout : 1; /* only used with NGG */
835 unsigned _pad : 32 - SI_NUM_VGT_STAGES_KEY_BITS;
836 #else /* UTIL_ARCH_BIG_ENDIAN */
837 unsigned _pad : 32 - SI_NUM_VGT_STAGES_KEY_BITS;
838 unsigned streamout : 1;
839 unsigned ngg : 1;
840 unsigned ngg_passthrough : 1;
841 unsigned ngg_gs_fast_launch : 1;
842 unsigned gs : 1;
843 unsigned tess : 1;
844 #endif
845 } u;
846 uint32_t index;
847 };
848
849 struct si_texture_handle {
850 unsigned desc_slot;
851 bool desc_dirty;
852 struct pipe_sampler_view *view;
853 struct si_sampler_state sstate;
854 };
855
856 struct si_image_handle {
857 unsigned desc_slot;
858 bool desc_dirty;
859 struct pipe_image_view view;
860 };
861
862 struct si_saved_cs {
863 struct pipe_reference reference;
864 struct si_context *ctx;
865 struct radeon_saved_cs gfx;
866 struct radeon_saved_cs compute;
867 struct si_resource *trace_buf;
868 unsigned trace_id;
869
870 unsigned gfx_last_dw;
871 unsigned compute_last_dw;
872 bool flushed;
873 int64_t time_flush;
874 };
875
876 struct si_sdma_upload {
877 struct si_resource *dst;
878 struct si_resource *src;
879 unsigned src_offset;
880 unsigned dst_offset;
881 unsigned size;
882 };
883
884 struct si_small_prim_cull_info {
885 float scale[2], translate[2];
886 };
887
888 struct si_context {
889 struct pipe_context b; /* base class */
890
891 enum radeon_family family;
892 enum chip_class chip_class;
893
894 struct radeon_winsys *ws;
895 struct radeon_winsys_ctx *ctx;
896 struct radeon_cmdbuf *gfx_cs; /* compute IB if graphics is disabled */
897 struct radeon_cmdbuf *sdma_cs;
898 struct pipe_fence_handle *last_gfx_fence;
899 struct pipe_fence_handle *last_sdma_fence;
900 struct si_resource *eop_bug_scratch;
901 struct u_upload_mgr *cached_gtt_allocator;
902 struct threaded_context *tc;
903 struct u_suballocator *allocator_zeroed_memory;
904 struct slab_child_pool pool_transfers;
905 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
906 struct pipe_device_reset_callback device_reset_callback;
907 struct u_log_context *log;
908 void *query_result_shader;
909 void *sh_query_result_shader;
910
911 void (*emit_cache_flush)(struct si_context *ctx);
912
913 struct blitter_context *blitter;
914 void *noop_blend;
915 void *noop_dsa;
916 void *discard_rasterizer_state;
917 void *custom_dsa_flush;
918 void *custom_blend_resolve;
919 void *custom_blend_fmask_decompress;
920 void *custom_blend_eliminate_fastclear;
921 void *custom_blend_dcc_decompress;
922 void *vs_blit_pos;
923 void *vs_blit_pos_layered;
924 void *vs_blit_color;
925 void *vs_blit_color_layered;
926 void *vs_blit_texcoord;
927 void *cs_clear_buffer;
928 void *cs_copy_buffer;
929 void *cs_copy_image;
930 void *cs_copy_image_1d_array;
931 void *cs_clear_render_target;
932 void *cs_clear_render_target_1d_array;
933 void *cs_clear_12bytes_buffer;
934 void *cs_dcc_decompress;
935 void *cs_dcc_retile;
936 void *cs_fmask_expand[3][2]; /* [log2(samples)-1][is_array] */
937 struct si_screen *screen;
938 struct pipe_debug_callback debug;
939 struct ac_llvm_compiler compiler; /* only non-threaded compilation */
940 struct si_shader_ctx_state fixed_func_tcs_shader;
941 /* Offset 0: EOP flush number; Offset 4: GDS prim restart counter */
942 struct si_resource *wait_mem_scratch;
943 unsigned wait_mem_number;
944 uint16_t prefetch_L2_mask;
945
946 bool has_graphics;
947 bool gfx_flush_in_progress : 1;
948 bool gfx_last_ib_is_busy : 1;
949 bool compute_is_busy : 1;
950
951 unsigned num_gfx_cs_flushes;
952 unsigned initial_gfx_cs_size;
953 unsigned last_dirty_tex_counter;
954 unsigned last_dirty_buf_counter;
955 unsigned last_compressed_colortex_counter;
956 unsigned last_num_draw_calls;
957 unsigned flags; /* flush flags */
958 /* Current unaccounted memory usage. */
959 uint64_t vram;
960 uint64_t gtt;
961
962 /* Compute-based primitive discard. */
963 unsigned prim_discard_vertex_count_threshold;
964 struct pb_buffer *gds;
965 struct pb_buffer *gds_oa;
966 struct radeon_cmdbuf *prim_discard_compute_cs;
967 unsigned compute_gds_offset;
968 struct si_shader *compute_ib_last_shader;
969 uint32_t compute_rewind_va;
970 unsigned compute_num_prims_in_batch;
971 bool preserve_prim_restart_gds_at_flush;
972 /* index_ring is divided into 2 halves for doublebuffering. */
973 struct si_resource *index_ring;
974 unsigned index_ring_base; /* offset of a per-IB portion */
975 unsigned index_ring_offset; /* offset within a per-IB portion */
976 unsigned index_ring_size_per_ib; /* max available size per IB */
977 bool prim_discard_compute_ib_initialized;
978 /* For tracking the last execution barrier - it can be either
979 * a WRITE_DATA packet or a fence. */
980 uint32_t *last_pkt3_write_data;
981 struct si_resource *barrier_buf;
982 unsigned barrier_buf_offset;
983 struct pipe_fence_handle *last_ib_barrier_fence;
984 struct si_resource *last_ib_barrier_buf;
985 unsigned last_ib_barrier_buf_offset;
986
987 /* Atoms (direct states). */
988 union si_state_atoms atoms;
989 unsigned dirty_atoms; /* mask */
990 /* PM4 states (precomputed immutable states) */
991 unsigned dirty_states;
992 union si_state queued;
993 union si_state emitted;
994
995 /* Atom declarations. */
996 struct si_framebuffer framebuffer;
997 unsigned sample_locs_num_samples;
998 uint16_t sample_mask;
999 unsigned last_cb_target_mask;
1000 struct si_blend_color blend_color;
1001 struct si_clip_state clip_state;
1002 struct si_shader_data shader_pointers;
1003 struct si_stencil_ref stencil_ref;
1004 struct pipe_scissor_state scissors[SI_MAX_VIEWPORTS];
1005 struct si_streamout streamout;
1006 struct si_viewports viewports;
1007 unsigned num_window_rectangles;
1008 bool window_rectangles_include;
1009 struct pipe_scissor_state window_rectangles[4];
1010
1011 /* Precomputed states. */
1012 struct si_pm4_state *init_config;
1013 struct si_pm4_state *init_config_gs_rings;
1014 bool init_config_has_vgt_flush;
1015 struct si_pm4_state *vgt_shader_config[SI_NUM_VGT_STAGES_STATES];
1016
1017 /* shaders */
1018 struct si_shader_ctx_state ps_shader;
1019 struct si_shader_ctx_state gs_shader;
1020 struct si_shader_ctx_state vs_shader;
1021 struct si_shader_ctx_state tcs_shader;
1022 struct si_shader_ctx_state tes_shader;
1023 struct si_shader_ctx_state cs_prim_discard_state;
1024 struct si_cs_shader_state cs_shader_state;
1025
1026 /* shader information */
1027 struct si_vertex_elements *vertex_elements;
1028 unsigned num_vertex_elements;
1029 unsigned sprite_coord_enable;
1030 unsigned cs_max_waves_per_sh;
1031 bool flatshade;
1032 bool do_update_shaders;
1033
1034 /* shader descriptors */
1035 struct si_descriptors descriptors[SI_NUM_DESCS];
1036 unsigned descriptors_dirty;
1037 unsigned shader_pointers_dirty;
1038 unsigned shader_needs_decompress_mask;
1039 struct si_buffer_resources rw_buffers;
1040 struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
1041 struct si_samplers samplers[SI_NUM_SHADERS];
1042 struct si_images images[SI_NUM_SHADERS];
1043 bool bo_list_add_all_resident_resources;
1044 bool bo_list_add_all_gfx_resources;
1045 bool bo_list_add_all_compute_resources;
1046
1047 /* other shader resources */
1048 struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on GFX7 */
1049 struct pipe_resource *esgs_ring;
1050 struct pipe_resource *gsvs_ring;
1051 struct pipe_resource *tess_rings;
1052 union pipe_color_union *border_color_table; /* in CPU memory, any endian */
1053 struct si_resource *border_color_buffer;
1054 union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
1055 unsigned border_color_count;
1056 unsigned num_vs_blit_sgprs;
1057 uint32_t vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
1058 uint32_t cs_user_data[4];
1059
1060 /* Vertex buffers. */
1061 bool vertex_buffers_dirty;
1062 bool vertex_buffer_pointer_dirty;
1063 bool vertex_buffer_user_sgprs_dirty;
1064 struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
1065 uint16_t vertex_buffer_unaligned; /* bitmask of not dword-aligned buffers */
1066 uint32_t *vb_descriptors_gpu_list;
1067 struct si_resource *vb_descriptors_buffer;
1068 unsigned vb_descriptors_offset;
1069 unsigned vb_descriptor_user_sgprs[5 * 4];
1070
1071 /* MSAA config state. */
1072 int ps_iter_samples;
1073 bool ps_uses_fbfetch;
1074 bool smoothing_enabled;
1075
1076 /* DB render state. */
1077 unsigned ps_db_shader_control;
1078 unsigned dbcb_copy_sample;
1079 bool dbcb_depth_copy_enabled : 1;
1080 bool dbcb_stencil_copy_enabled : 1;
1081 bool db_flush_depth_inplace : 1;
1082 bool db_flush_stencil_inplace : 1;
1083 bool db_depth_clear : 1;
1084 bool db_depth_disable_expclear : 1;
1085 bool db_stencil_clear : 1;
1086 bool db_stencil_disable_expclear : 1;
1087 bool occlusion_queries_disabled : 1;
1088 bool generate_mipmap_for_depth : 1;
1089
1090 /* Emitted draw state. */
1091 bool gs_tri_strip_adj_fix : 1;
1092 bool ls_vgpr_fix : 1;
1093 bool prim_discard_cs_instancing : 1;
1094 bool ngg : 1;
1095 uint8_t ngg_culling;
1096 int last_index_size;
1097 int last_base_vertex;
1098 int last_start_instance;
1099 int last_instance_count;
1100 int last_drawid;
1101 int last_sh_base_reg;
1102 int last_primitive_restart_en;
1103 int last_restart_index;
1104 int last_prim;
1105 int last_multi_vgt_param;
1106 int last_gs_out_prim;
1107 int last_binning_enabled;
1108 unsigned current_vs_state;
1109 unsigned last_vs_state;
1110 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
1111
1112 struct si_small_prim_cull_info last_small_prim_cull_info;
1113 struct si_resource *small_prim_cull_info_buf;
1114 uint64_t small_prim_cull_info_address;
1115 bool small_prim_cull_info_dirty;
1116
1117 /* Scratch buffer */
1118 struct si_resource *scratch_buffer;
1119 unsigned scratch_waves;
1120 unsigned spi_tmpring_size;
1121 unsigned max_seen_scratch_bytes_per_wave;
1122 unsigned max_seen_compute_scratch_bytes_per_wave;
1123
1124 struct si_resource *compute_scratch_buffer;
1125
1126 /* Emitted derived tessellation state. */
1127 /* Local shader (VS), or HS if LS-HS are merged. */
1128 struct si_shader *last_ls;
1129 struct si_shader_selector *last_tcs;
1130 int last_num_tcs_input_cp;
1131 int last_tes_sh_base;
1132 bool last_tess_uses_primid;
1133 unsigned last_num_patches;
1134 int last_ls_hs_config;
1135
1136 /* Debug state. */
1137 bool is_debug;
1138 struct si_saved_cs *current_saved_cs;
1139 uint64_t dmesg_timestamp;
1140 unsigned apitrace_call_number;
1141
1142 /* Other state */
1143 bool need_check_render_feedback;
1144 bool decompression_enabled;
1145 bool dpbb_force_off;
1146 bool vs_writes_viewport_index;
1147 bool vs_disables_clipping_viewport;
1148
1149 /* Precomputed IA_MULTI_VGT_PARAM */
1150 union si_vgt_param_key ia_multi_vgt_param_key;
1151 unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
1152
1153 /* Bindless descriptors. */
1154 struct si_descriptors bindless_descriptors;
1155 struct util_idalloc bindless_used_slots;
1156 unsigned num_bindless_descriptors;
1157 bool bindless_descriptors_dirty;
1158 bool graphics_bindless_pointer_dirty;
1159 bool compute_bindless_pointer_dirty;
1160
1161 /* Allocated bindless handles */
1162 struct hash_table *tex_handles;
1163 struct hash_table *img_handles;
1164
1165 /* Resident bindless handles */
1166 struct util_dynarray resident_tex_handles;
1167 struct util_dynarray resident_img_handles;
1168
1169 /* Resident bindless handles which need decompression */
1170 struct util_dynarray resident_tex_needs_color_decompress;
1171 struct util_dynarray resident_img_needs_color_decompress;
1172 struct util_dynarray resident_tex_needs_depth_decompress;
1173
1174 /* Bindless state */
1175 bool uses_bindless_samplers;
1176 bool uses_bindless_images;
1177
1178 /* MSAA sample locations.
1179 * The first index is the sample index.
1180 * The second index is the coordinate: X, Y. */
1181 struct {
1182 float x1[1][2];
1183 float x2[2][2];
1184 float x4[4][2];
1185 float x8[8][2];
1186 float x16[16][2];
1187 } sample_positions;
1188 struct pipe_resource *sample_pos_buffer;
1189
1190 /* Misc stats. */
1191 unsigned num_draw_calls;
1192 unsigned num_decompress_calls;
1193 unsigned num_mrt_draw_calls;
1194 unsigned num_prim_restart_calls;
1195 unsigned num_spill_draw_calls;
1196 unsigned num_compute_calls;
1197 unsigned num_spill_compute_calls;
1198 unsigned num_dma_calls;
1199 unsigned num_cp_dma_calls;
1200 unsigned num_vs_flushes;
1201 unsigned num_ps_flushes;
1202 unsigned num_cs_flushes;
1203 unsigned num_cb_cache_flushes;
1204 unsigned num_db_cache_flushes;
1205 unsigned num_L2_invalidates;
1206 unsigned num_L2_writebacks;
1207 unsigned num_resident_handles;
1208 uint64_t num_alloc_tex_transfer_bytes;
1209 unsigned last_tex_ps_draw_ratio; /* for query */
1210 unsigned compute_num_verts_accepted;
1211 unsigned compute_num_verts_rejected;
1212 unsigned compute_num_verts_ineligible; /* due to low vertex count */
1213 unsigned context_roll;
1214
1215 /* Queries. */
1216 /* Maintain the list of active queries for pausing between IBs. */
1217 int num_occlusion_queries;
1218 int num_perfect_occlusion_queries;
1219 int num_pipeline_stat_queries;
1220 struct list_head active_queries;
1221 unsigned num_cs_dw_queries_suspend;
1222
1223 /* Render condition. */
1224 struct pipe_query *render_cond;
1225 unsigned render_cond_mode;
1226 bool render_cond_invert;
1227 bool render_cond_force_off; /* for u_blitter */
1228
1229 /* For uploading data via GTT and copy to VRAM on context flush via SDMA. */
1230 bool sdma_uploads_in_progress;
1231 struct si_sdma_upload *sdma_uploads;
1232 unsigned num_sdma_uploads;
1233 unsigned max_sdma_uploads;
1234
1235 /* Shader-based queries. */
1236 struct list_head shader_query_buffers;
1237 unsigned num_active_shader_queries;
1238
1239 /* Statistics gathering for the DCC enablement heuristic. It can't be
1240 * in si_texture because si_texture can be shared by multiple
1241 * contexts. This is for back buffers only. We shouldn't get too many
1242 * of those.
1243 *
1244 * X11 DRI3 rotates among a finite set of back buffers. They should
1245 * all fit in this array. If they don't, separate DCC might never be
1246 * enabled by DCC stat gathering.
1247 */
1248 struct {
1249 struct si_texture *tex;
1250 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1251 struct pipe_query *ps_stats[3];
1252 /* If all slots are used and another slot is needed,
1253 * the least recently used slot is evicted based on this. */
1254 int64_t last_use_timestamp;
1255 bool query_active;
1256 } dcc_stats[5];
1257
1258 /* Copy one resource to another using async DMA. */
1259 void (*dma_copy)(struct pipe_context *ctx, struct pipe_resource *dst, unsigned dst_level,
1260 unsigned dst_x, unsigned dst_y, unsigned dst_z, struct pipe_resource *src,
1261 unsigned src_level, const struct pipe_box *src_box);
1262
1263 struct si_tracked_regs tracked_regs;
1264 };
1265
1266 /* cik_sdma.c */
1267 void cik_init_sdma_functions(struct si_context *sctx);
1268
1269 /* si_blit.c */
1270 enum si_blitter_op /* bitmask */
1271 {
1272 SI_SAVE_TEXTURES = 1,
1273 SI_SAVE_FRAMEBUFFER = 2,
1274 SI_SAVE_FRAGMENT_STATE = 4,
1275 SI_DISABLE_RENDER_COND = 8,
1276 };
1277
1278 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
1279 void si_blitter_end(struct si_context *sctx);
1280 void si_init_blit_functions(struct si_context *sctx);
1281 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
1282 void si_decompress_subresource(struct pipe_context *ctx, struct pipe_resource *tex, unsigned planes,
1283 unsigned level, unsigned first_layer, unsigned last_layer);
1284 void si_resource_copy_region(struct pipe_context *ctx, struct pipe_resource *dst,
1285 unsigned dst_level, unsigned dstx, unsigned dsty, unsigned dstz,
1286 struct pipe_resource *src, unsigned src_level,
1287 const struct pipe_box *src_box);
1288 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex);
1289
1290 /* si_buffer.c */
1291 bool si_rings_is_buffer_referenced(struct si_context *sctx, struct pb_buffer *buf,
1292 enum radeon_bo_usage usage);
1293 void *si_buffer_map_sync_with_rings(struct si_context *sctx, struct si_resource *resource,
1294 unsigned usage);
1295 void si_init_resource_fields(struct si_screen *sscreen, struct si_resource *res, uint64_t size,
1296 unsigned alignment);
1297 bool si_alloc_resource(struct si_screen *sscreen, struct si_resource *res);
1298 struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen, unsigned flags,
1299 unsigned usage, unsigned size, unsigned alignment);
1300 struct si_resource *si_aligned_buffer_create(struct pipe_screen *screen, unsigned flags,
1301 unsigned usage, unsigned size, unsigned alignment);
1302 void si_replace_buffer_storage(struct pipe_context *ctx, struct pipe_resource *dst,
1303 struct pipe_resource *src);
1304 void si_init_screen_buffer_functions(struct si_screen *sscreen);
1305 void si_init_buffer_functions(struct si_context *sctx);
1306
1307 /* si_clear.c */
1308 enum pipe_format si_simplify_cb_format(enum pipe_format format);
1309 bool vi_alpha_is_on_msb(struct si_screen *sscreen, enum pipe_format format);
1310 bool vi_dcc_clear_level(struct si_context *sctx, struct si_texture *tex, unsigned level,
1311 unsigned clear_value);
1312 void si_init_clear_functions(struct si_context *sctx);
1313
1314 /* si_compute_blit.c */
1315 unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher,
1316 enum si_cache_policy cache_policy);
1317 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst, uint64_t offset,
1318 uint64_t size, uint32_t *clear_value, uint32_t clear_value_size,
1319 enum si_coherency coher, bool force_cpdma);
1320 void si_copy_buffer(struct si_context *sctx, struct pipe_resource *dst, struct pipe_resource *src,
1321 uint64_t dst_offset, uint64_t src_offset, unsigned size);
1322 void si_compute_copy_image(struct si_context *sctx, struct pipe_resource *dst, unsigned dst_level,
1323 struct pipe_resource *src, unsigned src_level, unsigned dstx,
1324 unsigned dsty, unsigned dstz, const struct pipe_box *src_box,
1325 bool is_dcc_decompress);
1326 void si_compute_clear_render_target(struct pipe_context *ctx, struct pipe_surface *dstsurf,
1327 const union pipe_color_union *color, unsigned dstx,
1328 unsigned dsty, unsigned width, unsigned height,
1329 bool render_condition_enabled);
1330 void si_retile_dcc(struct si_context *sctx, struct si_texture *tex);
1331 void si_compute_expand_fmask(struct pipe_context *ctx, struct pipe_resource *tex);
1332 void si_init_compute_blit_functions(struct si_context *sctx);
1333
1334 /* si_cp_dma.c */
1335 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1336 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1337 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1338 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1339 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1340 #define SI_CPDMA_SKIP_TMZ (1 << 5) /* don't update tmz state */
1341 #define SI_CPDMA_SKIP_ALL \
1342 (SI_CPDMA_SKIP_CHECK_CS_SPACE | SI_CPDMA_SKIP_SYNC_AFTER | SI_CPDMA_SKIP_SYNC_BEFORE | \
1343 SI_CPDMA_SKIP_GFX_SYNC | SI_CPDMA_SKIP_BO_LIST_UPDATE | SI_CPDMA_SKIP_TMZ)
1344
1345 void si_cp_dma_wait_for_idle(struct si_context *sctx);
1346 void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
1347 struct pipe_resource *dst, uint64_t offset, uint64_t size,
1348 unsigned value, unsigned user_flags, enum si_coherency coher,
1349 enum si_cache_policy cache_policy);
1350 void si_cp_dma_copy_buffer(struct si_context *sctx, struct pipe_resource *dst,
1351 struct pipe_resource *src, uint64_t dst_offset, uint64_t src_offset,
1352 unsigned size, unsigned user_flags, enum si_coherency coher,
1353 enum si_cache_policy cache_policy);
1354 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf, uint64_t offset,
1355 unsigned size);
1356 void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only);
1357 void si_test_gds(struct si_context *sctx);
1358 void si_cp_write_data(struct si_context *sctx, struct si_resource *buf, unsigned offset,
1359 unsigned size, unsigned dst_sel, unsigned engine, const void *data);
1360 void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs, unsigned dst_sel,
1361 struct si_resource *dst, unsigned dst_offset, unsigned src_sel,
1362 struct si_resource *src, unsigned src_offset);
1363
1364 /* si_debug.c */
1365 void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, struct radeon_saved_cs *saved,
1366 bool get_buffer_list);
1367 void si_clear_saved_cs(struct radeon_saved_cs *saved);
1368 void si_destroy_saved_cs(struct si_saved_cs *scs);
1369 void si_auto_log_cs(void *data, struct u_log_context *log);
1370 void si_log_hw_flush(struct si_context *sctx);
1371 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
1372 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
1373 void si_init_debug_functions(struct si_context *sctx);
1374 void si_check_vm_faults(struct si_context *sctx, struct radeon_saved_cs *saved,
1375 enum ring_type ring);
1376 bool si_replace_shader(unsigned num, struct si_shader_binary *binary);
1377
1378 /* si_dma_cs.c */
1379 void si_dma_emit_timestamp(struct si_context *sctx, struct si_resource *dst, uint64_t offset);
1380 void si_sdma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst, uint64_t offset,
1381 uint64_t size, unsigned clear_value);
1382 void si_sdma_copy_buffer(struct si_context *sctx, struct pipe_resource *dst,
1383 struct pipe_resource *src, uint64_t dst_offset, uint64_t src_offset,
1384 uint64_t size);
1385 void si_need_dma_space(struct si_context *ctx, unsigned num_dw, struct si_resource *dst,
1386 struct si_resource *src);
1387 void si_flush_dma_cs(struct si_context *ctx, unsigned flags, struct pipe_fence_handle **fence);
1388 void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst, uint64_t offset,
1389 uint64_t size, unsigned value);
1390
1391 /* si_fence.c */
1392 void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, unsigned event,
1393 unsigned event_flags, unsigned dst_sel, unsigned int_sel, unsigned data_sel,
1394 struct si_resource *buf, uint64_t va, uint32_t new_fence,
1395 unsigned query_type);
1396 unsigned si_cp_write_fence_dwords(struct si_screen *screen);
1397 void si_cp_wait_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, uint64_t va, uint32_t ref,
1398 uint32_t mask, unsigned flags);
1399 void si_init_fence_functions(struct si_context *ctx);
1400 void si_init_screen_fence_functions(struct si_screen *screen);
1401 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
1402 struct tc_unflushed_batch_token *tc_token);
1403
1404 /* si_get.c */
1405 void si_init_screen_get_functions(struct si_screen *sscreen);
1406
1407 /* si_gfx_cs.c */
1408 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags, struct pipe_fence_handle **fence);
1409 void si_allocate_gds(struct si_context *ctx);
1410 void si_set_tracked_regs_to_clear_state(struct si_context *ctx);
1411 void si_begin_new_gfx_cs(struct si_context *ctx);
1412 void si_need_gfx_cs_space(struct si_context *ctx);
1413 void si_unref_sdma_uploads(struct si_context *sctx);
1414
1415 /* si_gpu_load.c */
1416 void si_gpu_load_kill_thread(struct si_screen *sscreen);
1417 uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
1418 unsigned si_end_counter(struct si_screen *sscreen, unsigned type, uint64_t begin);
1419
1420 /* si_compute.c */
1421 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs);
1422 void si_init_compute_functions(struct si_context *sctx);
1423
1424 /* si_compute_prim_discard.c */
1425 enum si_prim_discard_outcome
1426 {
1427 SI_PRIM_DISCARD_ENABLED,
1428 SI_PRIM_DISCARD_DISABLED,
1429 SI_PRIM_DISCARD_DRAW_SPLIT,
1430 };
1431
1432 void si_build_prim_discard_compute_shader(struct si_shader_context *ctx);
1433 enum si_prim_discard_outcome
1434 si_prepare_prim_discard_or_split_draw(struct si_context *sctx, const struct pipe_draw_info *info,
1435 bool primitive_restart);
1436 void si_compute_signal_gfx(struct si_context *sctx);
1437 void si_dispatch_prim_discard_cs_and_draw(struct si_context *sctx,
1438 const struct pipe_draw_info *info, unsigned index_size,
1439 unsigned base_vertex, uint64_t input_indexbuf_va,
1440 unsigned input_indexbuf_max_elements);
1441 void si_initialize_prim_discard_tunables(struct si_screen *sscreen, bool is_aux_context,
1442 unsigned *prim_discard_vertex_count_threshold,
1443 unsigned *index_ring_size_per_ib);
1444
1445 /* si_pipe.c */
1446 void si_init_compiler(struct si_screen *sscreen, struct ac_llvm_compiler *compiler);
1447
1448 /* si_perfcounters.c */
1449 void si_init_perfcounters(struct si_screen *screen);
1450 void si_destroy_perfcounters(struct si_screen *screen);
1451
1452 /* si_query.c */
1453 void si_init_screen_query_functions(struct si_screen *sscreen);
1454 void si_init_query_functions(struct si_context *sctx);
1455 void si_suspend_queries(struct si_context *sctx);
1456 void si_resume_queries(struct si_context *sctx);
1457
1458 /* si_shaderlib_tgsi.c */
1459 void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
1460 unsigned num_layers);
1461 void *si_create_fixed_func_tcs(struct si_context *sctx);
1462 void *si_create_dma_compute_shader(struct pipe_context *ctx, unsigned num_dwords_per_thread,
1463 bool dst_stream_cache_policy, bool is_copy);
1464 void *si_create_copy_image_compute_shader(struct pipe_context *ctx);
1465 void *si_create_copy_image_compute_shader_1d_array(struct pipe_context *ctx);
1466 void *si_create_dcc_decompress_cs(struct pipe_context *ctx);
1467 void *si_clear_render_target_shader(struct pipe_context *ctx);
1468 void *si_clear_render_target_shader_1d_array(struct pipe_context *ctx);
1469 void *si_clear_12bytes_buffer_shader(struct pipe_context *ctx);
1470 void *si_create_dcc_retile_cs(struct pipe_context *ctx);
1471 void *si_create_fmask_expand_cs(struct pipe_context *ctx, unsigned num_samples, bool is_array);
1472 void *si_create_query_result_cs(struct si_context *sctx);
1473 void *gfx10_create_sh_query_result_cs(struct si_context *sctx);
1474
1475 /* gfx10_query.c */
1476 void gfx10_init_query(struct si_context *sctx);
1477 void gfx10_destroy_query(struct si_context *sctx);
1478
1479 /* si_test_dma.c */
1480 void si_test_dma(struct si_screen *sscreen);
1481
1482 /* si_test_clearbuffer.c */
1483 void si_test_dma_perf(struct si_screen *sscreen);
1484
1485 /* si_uvd.c */
1486 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
1487 const struct pipe_video_codec *templ);
1488
1489 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
1490 const struct pipe_video_buffer *tmpl);
1491
1492 /* si_viewport.c */
1493 void si_update_ngg_small_prim_precision(struct si_context *ctx);
1494 void si_get_small_prim_cull_info(struct si_context *sctx, struct si_small_prim_cull_info *out);
1495 void si_update_vs_viewport_state(struct si_context *ctx);
1496 void si_init_viewport_functions(struct si_context *ctx);
1497
1498 /* si_texture.c */
1499 bool si_prepare_for_dma_blit(struct si_context *sctx, struct si_texture *dst, unsigned dst_level,
1500 unsigned dstx, unsigned dsty, unsigned dstz, struct si_texture *src,
1501 unsigned src_level, const struct pipe_box *src_box);
1502 void si_eliminate_fast_color_clear(struct si_context *sctx, struct si_texture *tex,
1503 bool *ctx_flushed);
1504 void si_texture_discard_cmask(struct si_screen *sscreen, struct si_texture *tex);
1505 bool si_init_flushed_depth_texture(struct pipe_context *ctx, struct pipe_resource *texture);
1506 void si_print_texture_info(struct si_screen *sscreen, struct si_texture *tex,
1507 struct u_log_context *log);
1508 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
1509 const struct pipe_resource *templ);
1510 bool vi_dcc_formats_compatible(struct si_screen *sscreen, enum pipe_format format1,
1511 enum pipe_format format2);
1512 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex, unsigned level,
1513 enum pipe_format view_format);
1514 void vi_disable_dcc_if_incompatible_format(struct si_context *sctx, struct pipe_resource *tex,
1515 unsigned level, enum pipe_format view_format);
1516 struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
1517 struct pipe_resource *texture,
1518 const struct pipe_surface *templ, unsigned width0,
1519 unsigned height0, unsigned width, unsigned height);
1520 unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
1521 void vi_separate_dcc_try_enable(struct si_context *sctx, struct si_texture *tex);
1522 void vi_separate_dcc_start_query(struct si_context *sctx, struct si_texture *tex);
1523 void vi_separate_dcc_stop_query(struct si_context *sctx, struct si_texture *tex);
1524 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx, struct si_texture *tex);
1525 bool si_texture_disable_dcc(struct si_context *sctx, struct si_texture *tex);
1526 void si_init_screen_texture_functions(struct si_screen *sscreen);
1527 void si_init_context_texture_functions(struct si_context *sctx);
1528
1529 /*
1530 * common helpers
1531 */
1532
1533 static inline struct si_resource *si_resource(struct pipe_resource *r)
1534 {
1535 return (struct si_resource *)r;
1536 }
1537
1538 static inline void si_resource_reference(struct si_resource **ptr, struct si_resource *res)
1539 {
1540 pipe_resource_reference((struct pipe_resource **)ptr, (struct pipe_resource *)res);
1541 }
1542
1543 static inline void si_texture_reference(struct si_texture **ptr, struct si_texture *res)
1544 {
1545 pipe_resource_reference((struct pipe_resource **)ptr, &res->buffer.b.b);
1546 }
1547
1548 static inline void
1549 si_shader_selector_reference(struct si_context *sctx, /* sctx can optionally be NULL */
1550 struct si_shader_selector **dst, struct si_shader_selector *src)
1551 {
1552 if (*dst == src)
1553 return;
1554
1555 struct si_screen *sscreen = src ? src->screen : (*dst)->screen;
1556 util_shader_reference(&sctx->b, &sscreen->live_shader_cache, (void **)dst, src);
1557 }
1558
1559 static inline bool vi_dcc_enabled(struct si_texture *tex, unsigned level)
1560 {
1561 return tex->surface.dcc_offset && level < tex->surface.num_dcc_levels;
1562 }
1563
1564 static inline unsigned si_tile_mode_index(struct si_texture *tex, unsigned level, bool stencil)
1565 {
1566 if (stencil)
1567 return tex->surface.u.legacy.stencil_tiling_index[level];
1568 else
1569 return tex->surface.u.legacy.tiling_index[level];
1570 }
1571
1572 static inline unsigned si_get_minimum_num_gfx_cs_dwords(struct si_context *sctx)
1573 {
1574 /* Don't count the needed CS space exactly and just use an upper bound.
1575 *
1576 * Also reserve space for stopping queries at the end of IB, because
1577 * the number of active queries is unlimited in theory.
1578 */
1579 return 2048 + sctx->num_cs_dw_queries_suspend;
1580 }
1581
1582 static inline void si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r)
1583 {
1584 if (r) {
1585 /* Add memory usage for need_gfx_cs_space */
1586 sctx->vram += si_resource(r)->vram_usage;
1587 sctx->gtt += si_resource(r)->gart_usage;
1588 }
1589 }
1590
1591 static inline void si_invalidate_draw_sh_constants(struct si_context *sctx)
1592 {
1593 sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
1594 sctx->last_instance_count = SI_INSTANCE_COUNT_UNKNOWN;
1595 }
1596
1597 static inline unsigned si_get_atom_bit(struct si_context *sctx, struct si_atom *atom)
1598 {
1599 return 1 << (atom - sctx->atoms.array);
1600 }
1601
1602 static inline void si_set_atom_dirty(struct si_context *sctx, struct si_atom *atom, bool dirty)
1603 {
1604 unsigned bit = si_get_atom_bit(sctx, atom);
1605
1606 if (dirty)
1607 sctx->dirty_atoms |= bit;
1608 else
1609 sctx->dirty_atoms &= ~bit;
1610 }
1611
1612 static inline bool si_is_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1613 {
1614 return (sctx->dirty_atoms & si_get_atom_bit(sctx, atom)) != 0;
1615 }
1616
1617 static inline void si_mark_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1618 {
1619 si_set_atom_dirty(sctx, atom, true);
1620 }
1621
1622 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
1623 {
1624 if (sctx->gs_shader.cso)
1625 return &sctx->gs_shader;
1626 if (sctx->tes_shader.cso)
1627 return &sctx->tes_shader;
1628
1629 return &sctx->vs_shader;
1630 }
1631
1632 static inline struct si_shader_info *si_get_vs_info(struct si_context *sctx)
1633 {
1634 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1635
1636 return vs->cso ? &vs->cso->info : NULL;
1637 }
1638
1639 static inline struct si_shader *si_get_vs_state(struct si_context *sctx)
1640 {
1641 if (sctx->gs_shader.cso && sctx->gs_shader.current && !sctx->gs_shader.current->key.as_ngg)
1642 return sctx->gs_shader.cso->gs_copy_shader;
1643
1644 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1645 return vs->current ? vs->current : NULL;
1646 }
1647
1648 static inline bool si_can_dump_shader(struct si_screen *sscreen, unsigned processor)
1649 {
1650 return sscreen->debug_flags & (1 << processor);
1651 }
1652
1653 static inline bool si_get_strmout_en(struct si_context *sctx)
1654 {
1655 return sctx->streamout.streamout_enabled || sctx->streamout.prims_gen_query_enabled;
1656 }
1657
1658 static inline unsigned si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
1659 {
1660 unsigned alignment, tcc_cache_line_size;
1661
1662 /* If the upload size is less than the cache line size (e.g. 16, 32),
1663 * the whole thing will fit into a cache line if we align it to its size.
1664 * The idea is that multiple small uploads can share a cache line.
1665 * If the upload size is greater, align it to the cache line size.
1666 */
1667 alignment = util_next_power_of_two(upload_size);
1668 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
1669 return MIN2(alignment, tcc_cache_line_size);
1670 }
1671
1672 static inline void si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
1673 {
1674 if (pipe_reference(&(*dst)->reference, &src->reference))
1675 si_destroy_saved_cs(*dst);
1676
1677 *dst = src;
1678 }
1679
1680 static inline void si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1681 bool shaders_read_metadata, bool dcc_pipe_aligned)
1682 {
1683 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_INV_VCACHE;
1684
1685 if (sctx->chip_class >= GFX10) {
1686 if (sctx->screen->info.tcc_harvested)
1687 sctx->flags |= SI_CONTEXT_INV_L2;
1688 else if (shaders_read_metadata)
1689 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1690 } else if (sctx->chip_class == GFX9) {
1691 /* Single-sample color is coherent with shaders on GFX9, but
1692 * L2 metadata must be flushed if shaders read metadata.
1693 * (DCC, CMASK).
1694 */
1695 if (num_samples >= 2 || (shaders_read_metadata && !dcc_pipe_aligned))
1696 sctx->flags |= SI_CONTEXT_INV_L2;
1697 else if (shaders_read_metadata)
1698 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1699 } else {
1700 /* GFX6-GFX8 */
1701 sctx->flags |= SI_CONTEXT_INV_L2;
1702 }
1703 }
1704
1705 static inline void si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1706 bool include_stencil, bool shaders_read_metadata)
1707 {
1708 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB | SI_CONTEXT_INV_VCACHE;
1709
1710 if (sctx->chip_class >= GFX10) {
1711 if (sctx->screen->info.tcc_harvested)
1712 sctx->flags |= SI_CONTEXT_INV_L2;
1713 else if (shaders_read_metadata)
1714 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1715 } else if (sctx->chip_class == GFX9) {
1716 /* Single-sample depth (not stencil) is coherent with shaders
1717 * on GFX9, but L2 metadata must be flushed if shaders read
1718 * metadata.
1719 */
1720 if (num_samples >= 2 || include_stencil)
1721 sctx->flags |= SI_CONTEXT_INV_L2;
1722 else if (shaders_read_metadata)
1723 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1724 } else {
1725 /* GFX6-GFX8 */
1726 sctx->flags |= SI_CONTEXT_INV_L2;
1727 }
1728 }
1729
1730 static inline bool si_can_sample_zs(struct si_texture *tex, bool stencil_sampler)
1731 {
1732 return (stencil_sampler && tex->can_sample_s) || (!stencil_sampler && tex->can_sample_z);
1733 }
1734
1735 static inline bool si_htile_enabled(struct si_texture *tex, unsigned level, unsigned zs_mask)
1736 {
1737 if (zs_mask == PIPE_MASK_S && tex->htile_stencil_disabled)
1738 return false;
1739
1740 return tex->surface.htile_offset && level == 0;
1741 }
1742
1743 static inline bool vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level,
1744 unsigned zs_mask)
1745 {
1746 assert(!tex->tc_compatible_htile || tex->surface.htile_offset);
1747 return tex->tc_compatible_htile && si_htile_enabled(tex, level, zs_mask);
1748 }
1749
1750 static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
1751 {
1752 if (sctx->ps_uses_fbfetch)
1753 return sctx->framebuffer.nr_color_samples;
1754
1755 return MIN2(sctx->ps_iter_samples, sctx->framebuffer.nr_color_samples);
1756 }
1757
1758 static inline unsigned si_get_total_colormask(struct si_context *sctx)
1759 {
1760 if (sctx->queued.named.rasterizer->rasterizer_discard)
1761 return 0;
1762
1763 struct si_shader_selector *ps = sctx->ps_shader.cso;
1764 if (!ps)
1765 return 0;
1766
1767 unsigned colormask =
1768 sctx->framebuffer.colorbuf_enabled_4bit & sctx->queued.named.blend->cb_target_mask;
1769
1770 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1771 colormask &= ps->colors_written_4bit;
1772 else if (!ps->colors_written_4bit)
1773 colormask = 0; /* color0 writes all cbufs, but it's not written */
1774
1775 return colormask;
1776 }
1777
1778 #define UTIL_ALL_PRIM_LINE_MODES \
1779 ((1 << PIPE_PRIM_LINES) | (1 << PIPE_PRIM_LINE_LOOP) | (1 << PIPE_PRIM_LINE_STRIP) | \
1780 (1 << PIPE_PRIM_LINES_ADJACENCY) | (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1781
1782 static inline bool util_prim_is_lines(unsigned prim)
1783 {
1784 return ((1 << prim) & UTIL_ALL_PRIM_LINE_MODES) != 0;
1785 }
1786
1787 static inline bool util_prim_is_points_or_lines(unsigned prim)
1788 {
1789 return ((1 << prim) & (UTIL_ALL_PRIM_LINE_MODES | (1 << PIPE_PRIM_POINTS))) != 0;
1790 }
1791
1792 static inline bool util_rast_prim_is_triangles(unsigned prim)
1793 {
1794 return ((1 << prim) &
1795 ((1 << PIPE_PRIM_TRIANGLES) | (1 << PIPE_PRIM_TRIANGLE_STRIP) |
1796 (1 << PIPE_PRIM_TRIANGLE_FAN) | (1 << PIPE_PRIM_QUADS) | (1 << PIPE_PRIM_QUAD_STRIP) |
1797 (1 << PIPE_PRIM_POLYGON) | (1 << PIPE_PRIM_TRIANGLES_ADJACENCY) |
1798 (1 << PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY)));
1799 }
1800
1801 /**
1802 * Return true if there is enough memory in VRAM and GTT for the buffers
1803 * added so far.
1804 *
1805 * \param vram VRAM memory size not added to the buffer list yet
1806 * \param gtt GTT memory size not added to the buffer list yet
1807 */
1808 static inline bool radeon_cs_memory_below_limit(struct si_screen *screen, struct radeon_cmdbuf *cs,
1809 uint64_t vram, uint64_t gtt)
1810 {
1811 vram += cs->used_vram;
1812 gtt += cs->used_gart;
1813
1814 /* Anything that goes above the VRAM size should go to GTT. */
1815 if (vram > screen->info.vram_size)
1816 gtt += vram - screen->info.vram_size;
1817
1818 /* Now we just need to check if we have enough GTT. */
1819 return gtt < screen->info.gart_size * 0.7;
1820 }
1821
1822 /**
1823 * Add a buffer to the buffer list for the given command stream (CS).
1824 *
1825 * All buffers used by a CS must be added to the list. This tells the kernel
1826 * driver which buffers are used by GPU commands. Other buffers can
1827 * be swapped out (not accessible) during execution.
1828 *
1829 * The buffer list becomes empty after every context flush and must be
1830 * rebuilt.
1831 */
1832 static inline void radeon_add_to_buffer_list(struct si_context *sctx, struct radeon_cmdbuf *cs,
1833 struct si_resource *bo, enum radeon_bo_usage usage,
1834 enum radeon_bo_priority priority)
1835 {
1836 assert(usage);
1837 sctx->ws->cs_add_buffer(cs, bo->buf, (enum radeon_bo_usage)(usage | RADEON_USAGE_SYNCHRONIZED),
1838 bo->domains, priority);
1839 }
1840
1841 /**
1842 * Same as above, but also checks memory usage and flushes the context
1843 * accordingly.
1844 *
1845 * When this SHOULD NOT be used:
1846 *
1847 * - if si_context_add_resource_size has been called for the buffer
1848 * followed by *_need_cs_space for checking the memory usage
1849 *
1850 * - if si_need_dma_space has been called for the buffer
1851 *
1852 * - when emitting state packets and draw packets (because preceding packets
1853 * can't be re-emitted at that point)
1854 *
1855 * - if shader resource "enabled_mask" is not up-to-date or there is
1856 * a different constraint disallowing a context flush
1857 */
1858 static inline void radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx,
1859 struct si_resource *bo,
1860 enum radeon_bo_usage usage,
1861 enum radeon_bo_priority priority,
1862 bool check_mem)
1863 {
1864 if (check_mem &&
1865 !radeon_cs_memory_below_limit(sctx->screen, sctx->gfx_cs, sctx->vram + bo->vram_usage,
1866 sctx->gtt + bo->gart_usage))
1867 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1868
1869 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, bo, usage, priority);
1870 }
1871
1872 static inline bool si_compute_prim_discard_enabled(struct si_context *sctx)
1873 {
1874 return sctx->prim_discard_vertex_count_threshold != UINT_MAX;
1875 }
1876
1877 static inline unsigned si_get_wave_size(struct si_screen *sscreen,
1878 enum pipe_shader_type shader_type, bool ngg, bool es,
1879 bool prim_discard_cs)
1880 {
1881 if (shader_type == PIPE_SHADER_COMPUTE)
1882 return sscreen->compute_wave_size;
1883 else if (shader_type == PIPE_SHADER_FRAGMENT)
1884 return sscreen->ps_wave_size;
1885 else if ((shader_type == PIPE_SHADER_VERTEX && prim_discard_cs) || /* only Wave64 implemented */
1886 (shader_type == PIPE_SHADER_VERTEX && es && !ngg) ||
1887 (shader_type == PIPE_SHADER_TESS_EVAL && es && !ngg) ||
1888 (shader_type == PIPE_SHADER_GEOMETRY && !ngg)) /* legacy GS only supports Wave64 */
1889 return 64;
1890 else
1891 return sscreen->ge_wave_size;
1892 }
1893
1894 static inline unsigned si_get_shader_wave_size(struct si_shader *shader)
1895 {
1896 return si_get_wave_size(shader->selector->screen, shader->selector->type, shader->key.as_ngg,
1897 shader->key.as_es, shader->key.opt.vs_as_prim_discard_cs);
1898 }
1899
1900 #define PRINT_ERR(fmt, args...) \
1901 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
1902
1903 #endif