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radeonsi: add AMD_DEBUG=nodmaclear for debugging
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25 #ifndef SI_PIPE_H
26 #define SI_PIPE_H
27
28 #include "si_shader.h"
29 #include "si_state.h"
30
31 #include "util/u_dynarray.h"
32 #include "util/u_idalloc.h"
33 #include "util/u_threaded_context.h"
34
35 #if UTIL_ARCH_BIG_ENDIAN
36 #define SI_BIG_ENDIAN 1
37 #else
38 #define SI_BIG_ENDIAN 0
39 #endif
40
41 #define ATI_VENDOR_ID 0x1002
42 #define SI_PRIM_DISCARD_DEBUG 0
43 #define SI_NOT_QUERY 0xffffffff
44
45 /* The base vertex and primitive restart can be any number, but we must pick
46 * one which will mean "unknown" for the purpose of state tracking and
47 * the number shouldn't be a commonly-used one. */
48 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
49 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
50 #define SI_INSTANCE_COUNT_UNKNOWN INT_MIN
51 #define SI_NUM_SMOOTH_AA_SAMPLES 8
52 #define SI_MAX_POINT_SIZE 2048
53 #define SI_GS_PER_ES 128
54 /* Alignment for optimal CP DMA performance. */
55 #define SI_CPDMA_ALIGNMENT 32
56
57 /* Tunables for compute-based clear_buffer and copy_buffer: */
58 #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
59 #define SI_COMPUTE_COPY_DW_PER_THREAD 4
60 #define SI_COMPUTE_DST_CACHE_POLICY L2_STREAM
61
62 /* Pipeline & streamout query controls. */
63 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
64 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
65 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
66 /* Instruction cache. */
67 #define SI_CONTEXT_INV_ICACHE (1 << 3)
68 /* Scalar cache. (GFX6-9: scalar L1; GFX10: scalar L0)
69 * GFX10: This also invalidates the L1 shader array cache. */
70 #define SI_CONTEXT_INV_SCACHE (1 << 4)
71 /* Vector cache. (GFX6-9: vector L1; GFX10: vector L0)
72 * GFX10: This also invalidates the L1 shader array cache. */
73 #define SI_CONTEXT_INV_VCACHE (1 << 5)
74 /* L2 cache + L2 metadata cache writeback & invalidate.
75 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
76 #define SI_CONTEXT_INV_L2 (1 << 6)
77 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
78 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
79 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
80 #define SI_CONTEXT_WB_L2 (1 << 7)
81 /* Writeback & invalidate the L2 metadata cache only. It can only be coupled with
82 * a CB or DB flush. */
83 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
84 /* Framebuffer caches. */
85 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
86 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
87 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
88 /* Engine synchronization. */
89 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
90 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
91 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
92 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
93 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
94
95 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
96 #define SI_PREFETCH_LS (1 << 1)
97 #define SI_PREFETCH_HS (1 << 2)
98 #define SI_PREFETCH_ES (1 << 3)
99 #define SI_PREFETCH_GS (1 << 4)
100 #define SI_PREFETCH_VS (1 << 5)
101 #define SI_PREFETCH_PS (1 << 6)
102
103 #define SI_MAX_BORDER_COLORS 4096
104 #define SI_MAX_VIEWPORTS 16
105 #define SIX_BITS 0x3F
106 #define SI_MAP_BUFFER_ALIGNMENT 64
107 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
108
109 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
110 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
111 #define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
112 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
113 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
114 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
115 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
116 #define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
117 /* For const_uploader, upload data via GTT and copy to VRAM on context flush via SDMA. */
118 #define SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA (PIPE_RESOURCE_FLAG_DRV_PRIV << 8)
119
120 enum si_clear_code
121 {
122 DCC_CLEAR_COLOR_0000 = 0x00000000,
123 DCC_CLEAR_COLOR_0001 = 0x40404040,
124 DCC_CLEAR_COLOR_1110 = 0x80808080,
125 DCC_CLEAR_COLOR_1111 = 0xC0C0C0C0,
126 DCC_CLEAR_COLOR_REG = 0x20202020,
127 DCC_UNCOMPRESSED = 0xFFFFFFFF,
128 };
129
130 #define SI_IMAGE_ACCESS_AS_BUFFER (1 << 7)
131
132 /* Debug flags. */
133 enum {
134 /* Shader logging options: */
135 DBG_VS = PIPE_SHADER_VERTEX,
136 DBG_PS = PIPE_SHADER_FRAGMENT,
137 DBG_GS = PIPE_SHADER_GEOMETRY,
138 DBG_TCS = PIPE_SHADER_TESS_CTRL,
139 DBG_TES = PIPE_SHADER_TESS_EVAL,
140 DBG_CS = PIPE_SHADER_COMPUTE,
141 DBG_NO_IR,
142 DBG_NO_TGSI,
143 DBG_NO_ASM,
144 DBG_PREOPT_IR,
145
146 /* Shader compiler options the shader cache should be aware of: */
147 DBG_FS_CORRECT_DERIVS_AFTER_KILL,
148 DBG_SI_SCHED,
149 DBG_GISEL,
150 DBG_W32_GE,
151 DBG_W32_PS,
152 DBG_W32_CS,
153 DBG_W64_GE,
154 DBG_W64_PS,
155 DBG_W64_CS,
156
157 /* Shader compiler options (with no effect on the shader cache): */
158 DBG_CHECK_IR,
159 DBG_MONOLITHIC_SHADERS,
160 DBG_NO_OPT_VARIANT,
161
162 /* Information logging options: */
163 DBG_INFO,
164 DBG_TEX,
165 DBG_COMPUTE,
166 DBG_VM,
167
168 /* Driver options: */
169 DBG_FORCE_SDMA,
170 DBG_NO_SDMA,
171 DBG_NO_SDMA_CLEARS,
172 DBG_NO_WC,
173 DBG_CHECK_VM,
174 DBG_RESERVE_VMID,
175 DBG_ZERO_VRAM,
176
177 /* 3D engine options: */
178 DBG_NO_GFX,
179 DBG_NO_NGG,
180 DBG_ALWAYS_PD,
181 DBG_PD,
182 DBG_NO_PD,
183 DBG_SWITCH_ON_EOP,
184 DBG_NO_OUT_OF_ORDER,
185 DBG_NO_DPBB,
186 DBG_NO_DFSM,
187 DBG_DPBB,
188 DBG_DFSM,
189 DBG_NO_HYPERZ,
190 DBG_NO_RB_PLUS,
191 DBG_NO_2D_TILING,
192 DBG_NO_TILING,
193 DBG_NO_DCC,
194 DBG_NO_DCC_CLEAR,
195 DBG_NO_DCC_FB,
196 DBG_NO_DCC_MSAA,
197 DBG_NO_FMASK,
198
199 /* Tests: */
200 DBG_TEST_DMA,
201 DBG_TEST_VMFAULT_CP,
202 DBG_TEST_VMFAULT_SDMA,
203 DBG_TEST_VMFAULT_SHADER,
204 DBG_TEST_DMA_PERF,
205 DBG_TEST_GDS,
206 DBG_TEST_GDS_MM,
207 DBG_TEST_GDS_OA_MM,
208 };
209
210 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
211 #define DBG(name) (1ull << DBG_##name)
212
213 enum si_cache_policy {
214 L2_BYPASS,
215 L2_STREAM, /* same as SLC=1 */
216 L2_LRU, /* same as SLC=0 */
217 };
218
219 enum si_coherency {
220 SI_COHERENCY_NONE, /* no cache flushes needed */
221 SI_COHERENCY_SHADER,
222 SI_COHERENCY_CB_META,
223 SI_COHERENCY_CP,
224 };
225
226 struct si_compute;
227 struct si_shader_context;
228 struct hash_table;
229 struct u_suballocator;
230
231 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
232 * at the moment.
233 */
234 struct si_resource {
235 struct threaded_resource b;
236
237 /* Winsys objects. */
238 struct pb_buffer *buf;
239 uint64_t gpu_address;
240 /* Memory usage if the buffer placement is optimal. */
241 uint64_t vram_usage;
242 uint64_t gart_usage;
243
244 /* Resource properties. */
245 uint64_t bo_size;
246 unsigned bo_alignment;
247 enum radeon_bo_domain domains;
248 enum radeon_bo_flag flags;
249 unsigned bind_history;
250 int max_forced_staging_uploads;
251
252 /* The buffer range which is initialized (with a write transfer,
253 * streamout, DMA, or as a random access target). The rest of
254 * the buffer is considered invalid and can be mapped unsynchronized.
255 *
256 * This allows unsychronized mapping of a buffer range which hasn't
257 * been used yet. It's for applications which forget to use
258 * the unsynchronized map flag and expect the driver to figure it out.
259 */
260 struct util_range valid_buffer_range;
261
262 /* For buffers only. This indicates that a write operation has been
263 * performed by TC L2, but the cache hasn't been flushed.
264 * Any hw block which doesn't use or bypasses TC L2 should check this
265 * flag and flush the cache before using the buffer.
266 *
267 * For example, TC L2 must be flushed if a buffer which has been
268 * modified by a shader store instruction is about to be used as
269 * an index buffer. The reason is that VGT DMA index fetching doesn't
270 * use TC L2.
271 */
272 bool TC_L2_dirty;
273
274 /* Whether this resource is referenced by bindless handles. */
275 bool texture_handle_allocated;
276 bool image_handle_allocated;
277
278 /* Whether the resource has been exported via resource_get_handle. */
279 unsigned external_usage; /* PIPE_HANDLE_USAGE_* */
280 };
281
282 struct si_transfer {
283 struct threaded_transfer b;
284 struct si_resource *staging;
285 unsigned offset;
286 };
287
288 struct si_texture {
289 struct si_resource buffer;
290
291 struct radeon_surf surface;
292 struct si_texture *flushed_depth_texture;
293
294 /* One texture allocation can contain these buffers:
295 * - image (pixel data)
296 * - FMASK buffer (MSAA compression)
297 * - CMASK buffer (MSAA compression and/or legacy fast color clear)
298 * - HTILE buffer (Z/S compression and fast Z/S clear)
299 * - DCC buffer (color compression and new fast color clear)
300 * - displayable DCC buffer (if the DCC buffer is not displayable)
301 * - DCC retile mapping buffer (if the DCC buffer is not displayable)
302 */
303 uint64_t cmask_base_address_reg;
304 struct si_resource *cmask_buffer;
305 unsigned cb_color_info; /* fast clear enable bit */
306 unsigned color_clear_value[2];
307 unsigned last_msaa_resolve_target_micro_mode;
308 unsigned num_level0_transfers;
309 unsigned plane_index; /* other planes are different pipe_resources */
310 unsigned num_planes;
311
312 /* Depth buffer compression and fast clear. */
313 float depth_clear_value;
314 uint16_t dirty_level_mask; /* each bit says if that mipmap is compressed */
315 uint16_t stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
316 enum pipe_format db_render_format:16;
317 uint8_t stencil_clear_value;
318 bool fmask_is_not_identity:1;
319 bool tc_compatible_htile:1;
320 bool htile_stencil_disabled:1;
321 bool depth_cleared:1; /* if it was cleared at least once */
322 bool stencil_cleared:1; /* if it was cleared at least once */
323 bool upgraded_depth:1; /* upgraded from unorm to Z32_FLOAT */
324 bool is_depth:1;
325 bool db_compatible:1;
326 bool can_sample_z:1;
327 bool can_sample_s:1;
328
329 /* We need to track DCC dirtiness, because st/dri usually calls
330 * flush_resource twice per frame (not a bug) and we don't wanna
331 * decompress DCC twice. Also, the dirty tracking must be done even
332 * if DCC isn't used, because it's required by the DCC usage analysis
333 * for a possible future enablement.
334 */
335 bool separate_dcc_dirty:1;
336 bool displayable_dcc_dirty:1;
337
338 /* Statistics gathering for the DCC enablement heuristic. */
339 bool dcc_gather_statistics:1;
340 /* Counter that should be non-zero if the texture is bound to a
341 * framebuffer.
342 */
343 unsigned framebuffers_bound;
344 /* Whether the texture is a displayable back buffer and needs DCC
345 * decompression, which is expensive. Therefore, it's enabled only
346 * if statistics suggest that it will pay off and it's allocated
347 * separately. It can't be bound as a sampler by apps. Limited to
348 * target == 2D and last_level == 0. If enabled, dcc_offset contains
349 * the absolute GPUVM address, not the relative one.
350 */
351 struct si_resource *dcc_separate_buffer;
352 /* When DCC is temporarily disabled, the separate buffer is here. */
353 struct si_resource *last_dcc_separate_buffer;
354 /* Estimate of how much this color buffer is written to in units of
355 * full-screen draws: ps_invocations / (width * height)
356 * Shader kills, late Z, and blending with trivial discards make it
357 * inaccurate (we need to count CB updates, not PS invocations).
358 */
359 unsigned ps_draw_ratio;
360 /* The number of clears since the last DCC usage analysis. */
361 unsigned num_slow_clears;
362 };
363
364 struct si_surface {
365 struct pipe_surface base;
366
367 /* These can vary with block-compressed textures. */
368 uint16_t width0;
369 uint16_t height0;
370
371 bool color_initialized:1;
372 bool depth_initialized:1;
373
374 /* Misc. color flags. */
375 bool color_is_int8:1;
376 bool color_is_int10:1;
377 bool dcc_incompatible:1;
378
379 /* Color registers. */
380 unsigned cb_color_info;
381 unsigned cb_color_view;
382 unsigned cb_color_attrib;
383 unsigned cb_color_attrib2; /* GFX9 and later */
384 unsigned cb_color_attrib3; /* GFX10 and later */
385 unsigned cb_dcc_control; /* GFX8 and later */
386 unsigned spi_shader_col_format:8; /* no blending, no alpha-to-coverage. */
387 unsigned spi_shader_col_format_alpha:8; /* alpha-to-coverage */
388 unsigned spi_shader_col_format_blend:8; /* blending without alpha. */
389 unsigned spi_shader_col_format_blend_alpha:8; /* blending with alpha. */
390
391 /* DB registers. */
392 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE */
393 uint64_t db_stencil_base;
394 uint64_t db_htile_data_base;
395 unsigned db_depth_info;
396 unsigned db_z_info;
397 unsigned db_z_info2; /* GFX9 only */
398 unsigned db_depth_view;
399 unsigned db_depth_size;
400 unsigned db_depth_slice;
401 unsigned db_stencil_info;
402 unsigned db_stencil_info2; /* GFX9 only */
403 unsigned db_htile_surface;
404 };
405
406 struct si_mmio_counter {
407 unsigned busy;
408 unsigned idle;
409 };
410
411 union si_mmio_counters {
412 struct {
413 /* For global GPU load including SDMA. */
414 struct si_mmio_counter gpu;
415
416 /* GRBM_STATUS */
417 struct si_mmio_counter spi;
418 struct si_mmio_counter gui;
419 struct si_mmio_counter ta;
420 struct si_mmio_counter gds;
421 struct si_mmio_counter vgt;
422 struct si_mmio_counter ia;
423 struct si_mmio_counter sx;
424 struct si_mmio_counter wd;
425 struct si_mmio_counter bci;
426 struct si_mmio_counter sc;
427 struct si_mmio_counter pa;
428 struct si_mmio_counter db;
429 struct si_mmio_counter cp;
430 struct si_mmio_counter cb;
431
432 /* SRBM_STATUS2 */
433 struct si_mmio_counter sdma;
434
435 /* CP_STAT */
436 struct si_mmio_counter pfp;
437 struct si_mmio_counter meq;
438 struct si_mmio_counter me;
439 struct si_mmio_counter surf_sync;
440 struct si_mmio_counter cp_dma;
441 struct si_mmio_counter scratch_ram;
442 } named;
443 unsigned array[0];
444 };
445
446 struct si_memory_object {
447 struct pipe_memory_object b;
448 struct pb_buffer *buf;
449 uint32_t stride;
450 };
451
452 /* Saved CS data for debugging features. */
453 struct radeon_saved_cs {
454 uint32_t *ib;
455 unsigned num_dw;
456
457 struct radeon_bo_list_item *bo_list;
458 unsigned bo_count;
459 };
460
461 struct si_screen {
462 struct pipe_screen b;
463 struct radeon_winsys *ws;
464 struct disk_cache *disk_shader_cache;
465
466 struct radeon_info info;
467 uint64_t debug_flags;
468 char renderer_string[183];
469
470 void (*make_texture_descriptor)(
471 struct si_screen *screen,
472 struct si_texture *tex,
473 bool sampler,
474 enum pipe_texture_target target,
475 enum pipe_format pipe_format,
476 const unsigned char state_swizzle[4],
477 unsigned first_level, unsigned last_level,
478 unsigned first_layer, unsigned last_layer,
479 unsigned width, unsigned height, unsigned depth,
480 uint32_t *state,
481 uint32_t *fmask_state);
482
483 unsigned pa_sc_raster_config;
484 unsigned pa_sc_raster_config_1;
485 unsigned se_tile_repeat;
486 unsigned gs_table_depth;
487 unsigned tess_offchip_block_dw_size;
488 unsigned tess_offchip_ring_size;
489 unsigned tess_factor_ring_size;
490 unsigned vgt_hs_offchip_param;
491 unsigned eqaa_force_coverage_samples;
492 unsigned eqaa_force_z_samples;
493 unsigned eqaa_force_color_samples;
494 bool has_draw_indirect_multi;
495 bool has_out_of_order_rast;
496 bool assume_no_z_fights;
497 bool commutative_blend_add;
498 bool dpbb_allowed;
499 bool dfsm_allowed;
500 bool llvm_has_working_vgpr_indexing;
501 bool use_ngg;
502 bool use_ngg_streamout;
503
504 struct {
505 #define OPT_BOOL(name, dflt, description) bool name:1;
506 #include "si_debug_options.h"
507 } options;
508
509 /* Whether shaders are monolithic (1-part) or separate (3-part). */
510 bool use_monolithic_shaders;
511 bool record_llvm_ir;
512 bool dcc_msaa_allowed;
513
514 struct slab_parent_pool pool_transfers;
515
516 /* Texture filter settings. */
517 int force_aniso; /* -1 = disabled */
518
519 /* Auxiliary context. Mainly used to initialize resources.
520 * It must be locked prior to using and flushed before unlocking. */
521 struct pipe_context *aux_context;
522 simple_mtx_t aux_context_lock;
523
524 /* This must be in the screen, because UE4 uses one context for
525 * compilation and another one for rendering.
526 */
527 unsigned num_compilations;
528 /* Along with ST_DEBUG=precompile, this should show if applications
529 * are loading shaders on demand. This is a monotonic counter.
530 */
531 unsigned num_shaders_created;
532 unsigned num_shader_cache_hits;
533
534 /* GPU load thread. */
535 simple_mtx_t gpu_load_mutex;
536 thrd_t gpu_load_thread;
537 union si_mmio_counters mmio_counters;
538 volatile unsigned gpu_load_stop_thread; /* bool */
539
540 /* Performance counters. */
541 struct si_perfcounters *perfcounters;
542
543 /* If pipe_screen wants to recompute and re-emit the framebuffer,
544 * sampler, and image states of all contexts, it should atomically
545 * increment this.
546 *
547 * Each context will compare this with its own last known value of
548 * the counter before drawing and re-emit the states accordingly.
549 */
550 unsigned dirty_tex_counter;
551 unsigned dirty_buf_counter;
552
553 /* Atomically increment this counter when an existing texture's
554 * metadata is enabled or disabled in a way that requires changing
555 * contexts' compressed texture binding masks.
556 */
557 unsigned compressed_colortex_counter;
558
559 struct {
560 /* Context flags to set so that all writes from earlier jobs
561 * in the CP are seen by L2 clients.
562 */
563 unsigned cp_to_L2;
564
565 /* Context flags to set so that all writes from earlier jobs
566 * that end in L2 are seen by CP.
567 */
568 unsigned L2_to_cp;
569 } barrier_flags;
570
571 simple_mtx_t shader_parts_mutex;
572 struct si_shader_part *vs_prologs;
573 struct si_shader_part *tcs_epilogs;
574 struct si_shader_part *gs_prologs;
575 struct si_shader_part *ps_prologs;
576 struct si_shader_part *ps_epilogs;
577
578 /* Shader cache in memory.
579 *
580 * Design & limitations:
581 * - The shader cache is per screen (= per process), never saved to
582 * disk, and skips redundant shader compilations from TGSI to bytecode.
583 * - It can only be used with one-variant-per-shader support, in which
584 * case only the main (typically middle) part of shaders is cached.
585 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
586 * variants of VS and TES are cached, so LS and ES aren't.
587 * - GS and CS aren't cached, but it's certainly possible to cache
588 * those as well.
589 */
590 simple_mtx_t shader_cache_mutex;
591 struct hash_table *shader_cache;
592
593 /* Shader compiler queue for multithreaded compilation. */
594 struct util_queue shader_compiler_queue;
595 /* Use at most 3 normal compiler threads on quadcore and better.
596 * Hyperthreaded CPUs report the number of threads, but we want
597 * the number of cores. We only need this many threads for shader-db. */
598 struct ac_llvm_compiler compiler[24]; /* used by the queue only */
599
600 struct util_queue shader_compiler_queue_low_priority;
601 /* Use at most 2 low priority threads on quadcore and better.
602 * We want to minimize the impact on multithreaded Mesa. */
603 struct ac_llvm_compiler compiler_lowp[10];
604
605 unsigned compute_wave_size;
606 unsigned ps_wave_size;
607 unsigned ge_wave_size;
608 };
609
610 struct si_blend_color {
611 struct pipe_blend_color state;
612 bool any_nonzeros;
613 };
614
615 struct si_sampler_view {
616 struct pipe_sampler_view base;
617 /* [0..7] = image descriptor
618 * [4..7] = buffer descriptor */
619 uint32_t state[8];
620 uint32_t fmask_state[8];
621 const struct legacy_surf_level *base_level_info;
622 ubyte base_level;
623 ubyte block_width;
624 bool is_stencil_sampler;
625 bool is_integer;
626 bool dcc_incompatible;
627 };
628
629 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
630
631 struct si_sampler_state {
632 #ifndef NDEBUG
633 unsigned magic;
634 #endif
635 uint32_t val[4];
636 uint32_t integer_val[4];
637 uint32_t upgraded_depth_val[4];
638 };
639
640 struct si_cs_shader_state {
641 struct si_compute *program;
642 struct si_compute *emitted_program;
643 unsigned offset;
644 bool initialized;
645 bool uses_scratch;
646 };
647
648 struct si_samplers {
649 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
650 struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS];
651
652 /* The i-th bit is set if that element is enabled (non-NULL resource). */
653 unsigned enabled_mask;
654 uint32_t needs_depth_decompress_mask;
655 uint32_t needs_color_decompress_mask;
656 };
657
658 struct si_images {
659 struct pipe_image_view views[SI_NUM_IMAGES];
660 uint32_t needs_color_decompress_mask;
661 unsigned enabled_mask;
662 };
663
664 struct si_framebuffer {
665 struct pipe_framebuffer_state state;
666 unsigned colorbuf_enabled_4bit;
667 unsigned spi_shader_col_format;
668 unsigned spi_shader_col_format_alpha;
669 unsigned spi_shader_col_format_blend;
670 unsigned spi_shader_col_format_blend_alpha;
671 ubyte nr_samples:5; /* at most 16xAA */
672 ubyte log_samples:3; /* at most 4 = 16xAA */
673 ubyte nr_color_samples; /* at most 8xAA */
674 ubyte compressed_cb_mask;
675 ubyte uncompressed_cb_mask;
676 ubyte displayable_dcc_cb_mask;
677 ubyte color_is_int8;
678 ubyte color_is_int10;
679 ubyte dirty_cbufs;
680 ubyte dcc_overwrite_combiner_watermark;
681 ubyte min_bytes_per_pixel;
682 bool dirty_zsbuf;
683 bool any_dst_linear;
684 bool CB_has_shader_readable_metadata;
685 bool DB_has_shader_readable_metadata;
686 bool all_DCC_pipe_aligned;
687 };
688
689 enum si_quant_mode {
690 /* This is the list we want to support. */
691 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH,
692 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH,
693 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH,
694 };
695
696 struct si_signed_scissor {
697 int minx;
698 int miny;
699 int maxx;
700 int maxy;
701 enum si_quant_mode quant_mode;
702 };
703
704 struct si_viewports {
705 struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
706 struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS];
707 bool y_inverted;
708 };
709
710 struct si_clip_state {
711 struct pipe_clip_state state;
712 bool any_nonzeros;
713 };
714
715 struct si_streamout_target {
716 struct pipe_stream_output_target b;
717
718 /* The buffer where BUFFER_FILLED_SIZE is stored. */
719 struct si_resource *buf_filled_size;
720 unsigned buf_filled_size_offset;
721 bool buf_filled_size_valid;
722
723 unsigned stride_in_dw;
724 };
725
726 struct si_streamout {
727 bool begin_emitted;
728
729 unsigned enabled_mask;
730 unsigned num_targets;
731 struct si_streamout_target *targets[PIPE_MAX_SO_BUFFERS];
732
733 unsigned append_bitmask;
734 bool suspended;
735
736 /* External state which comes from the vertex shader,
737 * it must be set explicitly when binding a shader. */
738 uint16_t *stride_in_dw;
739 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
740
741 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
742 unsigned hw_enabled_mask;
743
744 /* The state of VGT_STRMOUT_(CONFIG|EN). */
745 bool streamout_enabled;
746 bool prims_gen_query_enabled;
747 int num_prims_gen_queries;
748 };
749
750 /* A shader state consists of the shader selector, which is a constant state
751 * object shared by multiple contexts and shouldn't be modified, and
752 * the current shader variant selected for this context.
753 */
754 struct si_shader_ctx_state {
755 struct si_shader_selector *cso;
756 struct si_shader *current;
757 };
758
759 #define SI_NUM_VGT_PARAM_KEY_BITS 12
760 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
761
762 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
763 * Some fields are set by state-change calls, most are set by draw_vbo.
764 */
765 union si_vgt_param_key {
766 struct {
767 #if UTIL_ARCH_LITTLE_ENDIAN
768 unsigned prim:4;
769 unsigned uses_instancing:1;
770 unsigned multi_instances_smaller_than_primgroup:1;
771 unsigned primitive_restart:1;
772 unsigned count_from_stream_output:1;
773 unsigned line_stipple_enabled:1;
774 unsigned uses_tess:1;
775 unsigned tess_uses_prim_id:1;
776 unsigned uses_gs:1;
777 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
778 #else /* UTIL_ARCH_BIG_ENDIAN */
779 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
780 unsigned uses_gs:1;
781 unsigned tess_uses_prim_id:1;
782 unsigned uses_tess:1;
783 unsigned line_stipple_enabled:1;
784 unsigned count_from_stream_output:1;
785 unsigned primitive_restart:1;
786 unsigned multi_instances_smaller_than_primgroup:1;
787 unsigned uses_instancing:1;
788 unsigned prim:4;
789 #endif
790 } u;
791 uint32_t index;
792 };
793
794 #define SI_NUM_VGT_STAGES_KEY_BITS 5
795 #define SI_NUM_VGT_STAGES_STATES (1 << SI_NUM_VGT_STAGES_KEY_BITS)
796
797 /* The VGT_SHADER_STAGES key used to index the table of precomputed values.
798 * Some fields are set by state-change calls, most are set by draw_vbo.
799 */
800 union si_vgt_stages_key {
801 struct {
802 #if UTIL_ARCH_LITTLE_ENDIAN
803 unsigned tess:1;
804 unsigned gs:1;
805 unsigned ngg_passthrough:1;
806 unsigned ngg:1; /* gfx10+ */
807 unsigned streamout:1; /* only used with NGG */
808 unsigned _pad:32 - SI_NUM_VGT_STAGES_KEY_BITS;
809 #else /* UTIL_ARCH_BIG_ENDIAN */
810 unsigned _pad:32 - SI_NUM_VGT_STAGES_KEY_BITS;
811 unsigned streamout:1;
812 unsigned ngg:1;
813 unsigned ngg_passthrough:1;
814 unsigned gs:1;
815 unsigned tess:1;
816 #endif
817 } u;
818 uint32_t index;
819 };
820
821 struct si_texture_handle
822 {
823 unsigned desc_slot;
824 bool desc_dirty;
825 struct pipe_sampler_view *view;
826 struct si_sampler_state sstate;
827 };
828
829 struct si_image_handle
830 {
831 unsigned desc_slot;
832 bool desc_dirty;
833 struct pipe_image_view view;
834 };
835
836 struct si_saved_cs {
837 struct pipe_reference reference;
838 struct si_context *ctx;
839 struct radeon_saved_cs gfx;
840 struct radeon_saved_cs compute;
841 struct si_resource *trace_buf;
842 unsigned trace_id;
843
844 unsigned gfx_last_dw;
845 unsigned compute_last_dw;
846 bool flushed;
847 int64_t time_flush;
848 };
849
850 struct si_sdma_upload {
851 struct si_resource *dst;
852 struct si_resource *src;
853 unsigned src_offset;
854 unsigned dst_offset;
855 unsigned size;
856 };
857
858 struct si_context {
859 struct pipe_context b; /* base class */
860
861 enum radeon_family family;
862 enum chip_class chip_class;
863
864 struct radeon_winsys *ws;
865 struct radeon_winsys_ctx *ctx;
866 struct radeon_cmdbuf *gfx_cs; /* compute IB if graphics is disabled */
867 struct radeon_cmdbuf *dma_cs;
868 struct pipe_fence_handle *last_gfx_fence;
869 struct pipe_fence_handle *last_sdma_fence;
870 struct si_resource *eop_bug_scratch;
871 struct u_upload_mgr *cached_gtt_allocator;
872 struct threaded_context *tc;
873 struct u_suballocator *allocator_zeroed_memory;
874 struct slab_child_pool pool_transfers;
875 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
876 struct pipe_device_reset_callback device_reset_callback;
877 struct u_log_context *log;
878 void *query_result_shader;
879 void *sh_query_result_shader;
880
881 void (*emit_cache_flush)(struct si_context *ctx);
882
883 struct blitter_context *blitter;
884 void *noop_blend;
885 void *noop_dsa;
886 void *discard_rasterizer_state;
887 void *custom_dsa_flush;
888 void *custom_blend_resolve;
889 void *custom_blend_fmask_decompress;
890 void *custom_blend_eliminate_fastclear;
891 void *custom_blend_dcc_decompress;
892 void *vs_blit_pos;
893 void *vs_blit_pos_layered;
894 void *vs_blit_color;
895 void *vs_blit_color_layered;
896 void *vs_blit_texcoord;
897 void *cs_clear_buffer;
898 void *cs_copy_buffer;
899 void *cs_copy_image;
900 void *cs_copy_image_1d_array;
901 void *cs_clear_render_target;
902 void *cs_clear_render_target_1d_array;
903 void *cs_clear_12bytes_buffer;
904 void *cs_dcc_retile;
905 void *cs_fmask_expand[3][2]; /* [log2(samples)-1][is_array] */
906 struct si_screen *screen;
907 struct pipe_debug_callback debug;
908 struct ac_llvm_compiler compiler; /* only non-threaded compilation */
909 struct si_shader_ctx_state fixed_func_tcs_shader;
910 /* Offset 0: EOP flush number; Offset 4: GDS prim restart counter */
911 struct si_resource *wait_mem_scratch;
912 unsigned wait_mem_number;
913 uint16_t prefetch_L2_mask;
914
915 bool has_graphics;
916 bool gfx_flush_in_progress:1;
917 bool gfx_last_ib_is_busy:1;
918 bool compute_is_busy:1;
919
920 unsigned num_gfx_cs_flushes;
921 unsigned initial_gfx_cs_size;
922 unsigned last_dirty_tex_counter;
923 unsigned last_dirty_buf_counter;
924 unsigned last_compressed_colortex_counter;
925 unsigned last_num_draw_calls;
926 unsigned flags; /* flush flags */
927 /* Current unaccounted memory usage. */
928 uint64_t vram;
929 uint64_t gtt;
930
931 /* Compute-based primitive discard. */
932 unsigned prim_discard_vertex_count_threshold;
933 struct pb_buffer *gds;
934 struct pb_buffer *gds_oa;
935 struct radeon_cmdbuf *prim_discard_compute_cs;
936 unsigned compute_gds_offset;
937 struct si_shader *compute_ib_last_shader;
938 uint32_t compute_rewind_va;
939 unsigned compute_num_prims_in_batch;
940 bool preserve_prim_restart_gds_at_flush;
941 /* index_ring is divided into 2 halves for doublebuffering. */
942 struct si_resource *index_ring;
943 unsigned index_ring_base; /* offset of a per-IB portion */
944 unsigned index_ring_offset; /* offset within a per-IB portion */
945 unsigned index_ring_size_per_ib; /* max available size per IB */
946 bool prim_discard_compute_ib_initialized;
947 /* For tracking the last execution barrier - it can be either
948 * a WRITE_DATA packet or a fence. */
949 uint32_t *last_pkt3_write_data;
950 struct si_resource *barrier_buf;
951 unsigned barrier_buf_offset;
952 struct pipe_fence_handle *last_ib_barrier_fence;
953 struct si_resource *last_ib_barrier_buf;
954 unsigned last_ib_barrier_buf_offset;
955
956 /* Atoms (direct states). */
957 union si_state_atoms atoms;
958 unsigned dirty_atoms; /* mask */
959 /* PM4 states (precomputed immutable states) */
960 unsigned dirty_states;
961 union si_state queued;
962 union si_state emitted;
963
964 /* Atom declarations. */
965 struct si_framebuffer framebuffer;
966 unsigned sample_locs_num_samples;
967 uint16_t sample_mask;
968 unsigned last_cb_target_mask;
969 struct si_blend_color blend_color;
970 struct si_clip_state clip_state;
971 struct si_shader_data shader_pointers;
972 struct si_stencil_ref stencil_ref;
973 struct pipe_scissor_state scissors[SI_MAX_VIEWPORTS];
974 struct si_streamout streamout;
975 struct si_viewports viewports;
976 unsigned num_window_rectangles;
977 bool window_rectangles_include;
978 struct pipe_scissor_state window_rectangles[4];
979
980 /* Precomputed states. */
981 struct si_pm4_state *init_config;
982 struct si_pm4_state *init_config_gs_rings;
983 bool init_config_has_vgt_flush;
984 struct si_pm4_state *vgt_shader_config[SI_NUM_VGT_STAGES_STATES];
985
986 /* shaders */
987 struct si_shader_ctx_state ps_shader;
988 struct si_shader_ctx_state gs_shader;
989 struct si_shader_ctx_state vs_shader;
990 struct si_shader_ctx_state tcs_shader;
991 struct si_shader_ctx_state tes_shader;
992 struct si_shader_ctx_state cs_prim_discard_state;
993 struct si_cs_shader_state cs_shader_state;
994
995 /* shader information */
996 struct si_vertex_elements *vertex_elements;
997 unsigned sprite_coord_enable;
998 unsigned cs_max_waves_per_sh;
999 bool flatshade;
1000 bool do_update_shaders;
1001
1002 /* vertex buffer descriptors */
1003 uint32_t *vb_descriptors_gpu_list;
1004 struct si_resource *vb_descriptors_buffer;
1005 unsigned vb_descriptors_offset;
1006
1007 /* shader descriptors */
1008 struct si_descriptors descriptors[SI_NUM_DESCS];
1009 unsigned descriptors_dirty;
1010 unsigned shader_pointers_dirty;
1011 unsigned shader_needs_decompress_mask;
1012 struct si_buffer_resources rw_buffers;
1013 struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
1014 struct si_samplers samplers[SI_NUM_SHADERS];
1015 struct si_images images[SI_NUM_SHADERS];
1016 bool bo_list_add_all_resident_resources;
1017 bool bo_list_add_all_gfx_resources;
1018 bool bo_list_add_all_compute_resources;
1019
1020 /* other shader resources */
1021 struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on GFX7 */
1022 struct pipe_resource *esgs_ring;
1023 struct pipe_resource *gsvs_ring;
1024 struct pipe_resource *tess_rings;
1025 union pipe_color_union *border_color_table; /* in CPU memory, any endian */
1026 struct si_resource *border_color_buffer;
1027 union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
1028 unsigned border_color_count;
1029 unsigned num_vs_blit_sgprs;
1030 uint32_t vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
1031 uint32_t cs_user_data[4];
1032
1033 /* Vertex and index buffers. */
1034 bool vertex_buffers_dirty;
1035 bool vertex_buffer_pointer_dirty;
1036 struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
1037 uint16_t vertex_buffer_unaligned; /* bitmask of not dword-aligned buffers */
1038
1039 /* MSAA config state. */
1040 int ps_iter_samples;
1041 bool ps_uses_fbfetch;
1042 bool smoothing_enabled;
1043
1044 /* DB render state. */
1045 unsigned ps_db_shader_control;
1046 unsigned dbcb_copy_sample;
1047 bool dbcb_depth_copy_enabled:1;
1048 bool dbcb_stencil_copy_enabled:1;
1049 bool db_flush_depth_inplace:1;
1050 bool db_flush_stencil_inplace:1;
1051 bool db_depth_clear:1;
1052 bool db_depth_disable_expclear:1;
1053 bool db_stencil_clear:1;
1054 bool db_stencil_disable_expclear:1;
1055 bool occlusion_queries_disabled:1;
1056 bool generate_mipmap_for_depth:1;
1057
1058 /* Emitted draw state. */
1059 bool gs_tri_strip_adj_fix:1;
1060 bool ls_vgpr_fix:1;
1061 bool prim_discard_cs_instancing:1;
1062 bool ngg:1;
1063 int last_index_size;
1064 int last_base_vertex;
1065 int last_start_instance;
1066 int last_instance_count;
1067 int last_drawid;
1068 int last_sh_base_reg;
1069 int last_primitive_restart_en;
1070 int last_restart_index;
1071 int last_prim;
1072 int last_multi_vgt_param;
1073 int last_rast_prim;
1074 int last_flatshade_first;
1075 int last_binning_enabled;
1076 unsigned last_sc_line_stipple;
1077 unsigned current_vs_state;
1078 unsigned last_vs_state;
1079 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
1080
1081 /* Scratch buffer */
1082 struct si_resource *scratch_buffer;
1083 unsigned scratch_waves;
1084 unsigned spi_tmpring_size;
1085 unsigned max_seen_scratch_bytes_per_wave;
1086 unsigned max_seen_compute_scratch_bytes_per_wave;
1087
1088 struct si_resource *compute_scratch_buffer;
1089
1090 /* Emitted derived tessellation state. */
1091 /* Local shader (VS), or HS if LS-HS are merged. */
1092 struct si_shader *last_ls;
1093 struct si_shader_selector *last_tcs;
1094 int last_num_tcs_input_cp;
1095 int last_tes_sh_base;
1096 bool last_tess_uses_primid;
1097 unsigned last_num_patches;
1098 int last_ls_hs_config;
1099
1100 /* Debug state. */
1101 bool is_debug;
1102 struct si_saved_cs *current_saved_cs;
1103 uint64_t dmesg_timestamp;
1104 unsigned apitrace_call_number;
1105
1106 /* Other state */
1107 bool need_check_render_feedback;
1108 bool decompression_enabled;
1109 bool dpbb_force_off;
1110 bool vs_writes_viewport_index;
1111 bool vs_disables_clipping_viewport;
1112
1113 /* Precomputed IA_MULTI_VGT_PARAM */
1114 union si_vgt_param_key ia_multi_vgt_param_key;
1115 unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
1116
1117 /* Bindless descriptors. */
1118 struct si_descriptors bindless_descriptors;
1119 struct util_idalloc bindless_used_slots;
1120 unsigned num_bindless_descriptors;
1121 bool bindless_descriptors_dirty;
1122 bool graphics_bindless_pointer_dirty;
1123 bool compute_bindless_pointer_dirty;
1124
1125 /* Allocated bindless handles */
1126 struct hash_table *tex_handles;
1127 struct hash_table *img_handles;
1128
1129 /* Resident bindless handles */
1130 struct util_dynarray resident_tex_handles;
1131 struct util_dynarray resident_img_handles;
1132
1133 /* Resident bindless handles which need decompression */
1134 struct util_dynarray resident_tex_needs_color_decompress;
1135 struct util_dynarray resident_img_needs_color_decompress;
1136 struct util_dynarray resident_tex_needs_depth_decompress;
1137
1138 /* Bindless state */
1139 bool uses_bindless_samplers;
1140 bool uses_bindless_images;
1141
1142 /* MSAA sample locations.
1143 * The first index is the sample index.
1144 * The second index is the coordinate: X, Y. */
1145 struct {
1146 float x1[1][2];
1147 float x2[2][2];
1148 float x4[4][2];
1149 float x8[8][2];
1150 float x16[16][2];
1151 } sample_positions;
1152 struct pipe_resource *sample_pos_buffer;
1153
1154 /* Misc stats. */
1155 unsigned num_draw_calls;
1156 unsigned num_decompress_calls;
1157 unsigned num_mrt_draw_calls;
1158 unsigned num_prim_restart_calls;
1159 unsigned num_spill_draw_calls;
1160 unsigned num_compute_calls;
1161 unsigned num_spill_compute_calls;
1162 unsigned num_dma_calls;
1163 unsigned num_cp_dma_calls;
1164 unsigned num_vs_flushes;
1165 unsigned num_ps_flushes;
1166 unsigned num_cs_flushes;
1167 unsigned num_cb_cache_flushes;
1168 unsigned num_db_cache_flushes;
1169 unsigned num_L2_invalidates;
1170 unsigned num_L2_writebacks;
1171 unsigned num_resident_handles;
1172 uint64_t num_alloc_tex_transfer_bytes;
1173 unsigned last_tex_ps_draw_ratio; /* for query */
1174 unsigned compute_num_verts_accepted;
1175 unsigned compute_num_verts_rejected;
1176 unsigned compute_num_verts_ineligible; /* due to low vertex count */
1177 unsigned context_roll;
1178
1179 /* Queries. */
1180 /* Maintain the list of active queries for pausing between IBs. */
1181 int num_occlusion_queries;
1182 int num_perfect_occlusion_queries;
1183 int num_pipeline_stat_queries;
1184 struct list_head active_queries;
1185 unsigned num_cs_dw_queries_suspend;
1186
1187 /* Render condition. */
1188 struct pipe_query *render_cond;
1189 unsigned render_cond_mode;
1190 bool render_cond_invert;
1191 bool render_cond_force_off; /* for u_blitter */
1192
1193 /* For uploading data via GTT and copy to VRAM on context flush via SDMA. */
1194 bool sdma_uploads_in_progress;
1195 struct si_sdma_upload *sdma_uploads;
1196 unsigned num_sdma_uploads;
1197 unsigned max_sdma_uploads;
1198
1199 /* Shader-based queries. */
1200 struct list_head shader_query_buffers;
1201 unsigned num_active_shader_queries;
1202
1203 /* Statistics gathering for the DCC enablement heuristic. It can't be
1204 * in si_texture because si_texture can be shared by multiple
1205 * contexts. This is for back buffers only. We shouldn't get too many
1206 * of those.
1207 *
1208 * X11 DRI3 rotates among a finite set of back buffers. They should
1209 * all fit in this array. If they don't, separate DCC might never be
1210 * enabled by DCC stat gathering.
1211 */
1212 struct {
1213 struct si_texture *tex;
1214 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1215 struct pipe_query *ps_stats[3];
1216 /* If all slots are used and another slot is needed,
1217 * the least recently used slot is evicted based on this. */
1218 int64_t last_use_timestamp;
1219 bool query_active;
1220 } dcc_stats[5];
1221
1222 /* Copy one resource to another using async DMA. */
1223 void (*dma_copy)(struct pipe_context *ctx,
1224 struct pipe_resource *dst,
1225 unsigned dst_level,
1226 unsigned dst_x, unsigned dst_y, unsigned dst_z,
1227 struct pipe_resource *src,
1228 unsigned src_level,
1229 const struct pipe_box *src_box);
1230
1231 struct si_tracked_regs tracked_regs;
1232 };
1233
1234 /* cik_sdma.c */
1235 void cik_init_sdma_functions(struct si_context *sctx);
1236
1237 /* si_blit.c */
1238 enum si_blitter_op /* bitmask */
1239 {
1240 SI_SAVE_TEXTURES = 1,
1241 SI_SAVE_FRAMEBUFFER = 2,
1242 SI_SAVE_FRAGMENT_STATE = 4,
1243 SI_DISABLE_RENDER_COND = 8,
1244 };
1245
1246 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
1247 void si_blitter_end(struct si_context *sctx);
1248 void si_init_blit_functions(struct si_context *sctx);
1249 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
1250 void si_resource_copy_region(struct pipe_context *ctx,
1251 struct pipe_resource *dst,
1252 unsigned dst_level,
1253 unsigned dstx, unsigned dsty, unsigned dstz,
1254 struct pipe_resource *src,
1255 unsigned src_level,
1256 const struct pipe_box *src_box);
1257 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex);
1258
1259 /* si_buffer.c */
1260 bool si_rings_is_buffer_referenced(struct si_context *sctx,
1261 struct pb_buffer *buf,
1262 enum radeon_bo_usage usage);
1263 void *si_buffer_map_sync_with_rings(struct si_context *sctx,
1264 struct si_resource *resource,
1265 unsigned usage);
1266 void si_init_resource_fields(struct si_screen *sscreen,
1267 struct si_resource *res,
1268 uint64_t size, unsigned alignment);
1269 bool si_alloc_resource(struct si_screen *sscreen,
1270 struct si_resource *res);
1271 struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen,
1272 unsigned flags, unsigned usage,
1273 unsigned size, unsigned alignment);
1274 struct si_resource *si_aligned_buffer_create(struct pipe_screen *screen,
1275 unsigned flags, unsigned usage,
1276 unsigned size, unsigned alignment);
1277 void si_replace_buffer_storage(struct pipe_context *ctx,
1278 struct pipe_resource *dst,
1279 struct pipe_resource *src);
1280 void si_init_screen_buffer_functions(struct si_screen *sscreen);
1281 void si_init_buffer_functions(struct si_context *sctx);
1282
1283 /* si_clear.c */
1284 enum pipe_format si_simplify_cb_format(enum pipe_format format);
1285 bool vi_alpha_is_on_msb(struct si_screen *sscreen, enum pipe_format format);
1286 bool vi_dcc_clear_level(struct si_context *sctx,
1287 struct si_texture *tex,
1288 unsigned level, unsigned clear_value);
1289 void si_init_clear_functions(struct si_context *sctx);
1290
1291 /* si_compute_blit.c */
1292 unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher,
1293 enum si_cache_policy cache_policy);
1294 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1295 uint64_t offset, uint64_t size, uint32_t *clear_value,
1296 uint32_t clear_value_size, enum si_coherency coher,
1297 bool force_cpdma);
1298 void si_copy_buffer(struct si_context *sctx,
1299 struct pipe_resource *dst, struct pipe_resource *src,
1300 uint64_t dst_offset, uint64_t src_offset, unsigned size);
1301 void si_compute_copy_image(struct si_context *sctx,
1302 struct pipe_resource *dst,
1303 unsigned dst_level,
1304 struct pipe_resource *src,
1305 unsigned src_level,
1306 unsigned dstx, unsigned dsty, unsigned dstz,
1307 const struct pipe_box *src_box);
1308 void si_compute_clear_render_target(struct pipe_context *ctx,
1309 struct pipe_surface *dstsurf,
1310 const union pipe_color_union *color,
1311 unsigned dstx, unsigned dsty,
1312 unsigned width, unsigned height,
1313 bool render_condition_enabled);
1314 void si_retile_dcc(struct si_context *sctx, struct si_texture *tex);
1315 void si_compute_expand_fmask(struct pipe_context *ctx, struct pipe_resource *tex);
1316 void si_init_compute_blit_functions(struct si_context *sctx);
1317
1318 /* si_cp_dma.c */
1319 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1320 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1321 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1322 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1323 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1324 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
1325 SI_CPDMA_SKIP_SYNC_AFTER | \
1326 SI_CPDMA_SKIP_SYNC_BEFORE | \
1327 SI_CPDMA_SKIP_GFX_SYNC | \
1328 SI_CPDMA_SKIP_BO_LIST_UPDATE)
1329
1330 void si_cp_dma_wait_for_idle(struct si_context *sctx);
1331 void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
1332 struct pipe_resource *dst, uint64_t offset,
1333 uint64_t size, unsigned value, unsigned user_flags,
1334 enum si_coherency coher, enum si_cache_policy cache_policy);
1335 void si_cp_dma_copy_buffer(struct si_context *sctx,
1336 struct pipe_resource *dst, struct pipe_resource *src,
1337 uint64_t dst_offset, uint64_t src_offset, unsigned size,
1338 unsigned user_flags, enum si_coherency coher,
1339 enum si_cache_policy cache_policy);
1340 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
1341 uint64_t offset, unsigned size);
1342 void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only);
1343 void si_test_gds(struct si_context *sctx);
1344 void si_cp_write_data(struct si_context *sctx, struct si_resource *buf,
1345 unsigned offset, unsigned size, unsigned dst_sel,
1346 unsigned engine, const void *data);
1347 void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs,
1348 unsigned dst_sel, struct si_resource *dst, unsigned dst_offset,
1349 unsigned src_sel, struct si_resource *src, unsigned src_offset);
1350
1351 /* si_debug.c */
1352 void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
1353 struct radeon_saved_cs *saved, bool get_buffer_list);
1354 void si_clear_saved_cs(struct radeon_saved_cs *saved);
1355 void si_destroy_saved_cs(struct si_saved_cs *scs);
1356 void si_auto_log_cs(void *data, struct u_log_context *log);
1357 void si_log_hw_flush(struct si_context *sctx);
1358 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
1359 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
1360 void si_init_debug_functions(struct si_context *sctx);
1361 void si_check_vm_faults(struct si_context *sctx,
1362 struct radeon_saved_cs *saved, enum ring_type ring);
1363 bool si_replace_shader(unsigned num, struct si_shader_binary *binary);
1364
1365 /* si_dma.c */
1366 void si_init_dma_functions(struct si_context *sctx);
1367
1368 /* si_dma_cs.c */
1369 void si_dma_emit_timestamp(struct si_context *sctx, struct si_resource *dst,
1370 uint64_t offset);
1371 void si_sdma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1372 uint64_t offset, uint64_t size, unsigned clear_value);
1373 void si_need_dma_space(struct si_context *ctx, unsigned num_dw,
1374 struct si_resource *dst, struct si_resource *src);
1375 void si_flush_dma_cs(struct si_context *ctx, unsigned flags,
1376 struct pipe_fence_handle **fence);
1377 void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst,
1378 uint64_t offset, uint64_t size, unsigned value);
1379
1380 /* si_fence.c */
1381 void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
1382 unsigned event, unsigned event_flags,
1383 unsigned dst_sel, unsigned int_sel, unsigned data_sel,
1384 struct si_resource *buf, uint64_t va,
1385 uint32_t new_fence, unsigned query_type);
1386 unsigned si_cp_write_fence_dwords(struct si_screen *screen);
1387 void si_cp_wait_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
1388 uint64_t va, uint32_t ref, uint32_t mask, unsigned flags);
1389 void si_init_fence_functions(struct si_context *ctx);
1390 void si_init_screen_fence_functions(struct si_screen *screen);
1391 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
1392 struct tc_unflushed_batch_token *tc_token);
1393
1394 /* si_get.c */
1395 void si_init_screen_get_functions(struct si_screen *sscreen);
1396
1397 /* si_gfx_cs.c */
1398 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
1399 struct pipe_fence_handle **fence);
1400 void si_allocate_gds(struct si_context *ctx);
1401 void si_begin_new_gfx_cs(struct si_context *ctx);
1402 void si_need_gfx_cs_space(struct si_context *ctx);
1403 void si_unref_sdma_uploads(struct si_context *sctx);
1404
1405 /* si_gpu_load.c */
1406 void si_gpu_load_kill_thread(struct si_screen *sscreen);
1407 uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
1408 unsigned si_end_counter(struct si_screen *sscreen, unsigned type,
1409 uint64_t begin);
1410
1411 /* si_compute.c */
1412 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs);
1413 void si_init_compute_functions(struct si_context *sctx);
1414
1415 /* si_compute_prim_discard.c */
1416 enum si_prim_discard_outcome {
1417 SI_PRIM_DISCARD_ENABLED,
1418 SI_PRIM_DISCARD_DISABLED,
1419 SI_PRIM_DISCARD_DRAW_SPLIT,
1420 };
1421
1422 void si_build_prim_discard_compute_shader(struct si_shader_context *ctx);
1423 enum si_prim_discard_outcome
1424 si_prepare_prim_discard_or_split_draw(struct si_context *sctx,
1425 const struct pipe_draw_info *info,
1426 bool primitive_restart);
1427 void si_compute_signal_gfx(struct si_context *sctx);
1428 void si_dispatch_prim_discard_cs_and_draw(struct si_context *sctx,
1429 const struct pipe_draw_info *info,
1430 unsigned index_size,
1431 unsigned base_vertex,
1432 uint64_t input_indexbuf_va,
1433 unsigned input_indexbuf_max_elements);
1434 void si_initialize_prim_discard_tunables(struct si_context *sctx);
1435
1436 /* si_pipe.c */
1437 void si_init_compiler(struct si_screen *sscreen, struct ac_llvm_compiler *compiler);
1438
1439 /* si_perfcounters.c */
1440 void si_init_perfcounters(struct si_screen *screen);
1441 void si_destroy_perfcounters(struct si_screen *screen);
1442
1443 /* si_query.c */
1444 void si_init_screen_query_functions(struct si_screen *sscreen);
1445 void si_init_query_functions(struct si_context *sctx);
1446 void si_suspend_queries(struct si_context *sctx);
1447 void si_resume_queries(struct si_context *sctx);
1448
1449 /* si_shaderlib_tgsi.c */
1450 void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
1451 unsigned num_layers);
1452 void *si_create_fixed_func_tcs(struct si_context *sctx);
1453 void *si_create_dma_compute_shader(struct pipe_context *ctx,
1454 unsigned num_dwords_per_thread,
1455 bool dst_stream_cache_policy, bool is_copy);
1456 void *si_create_copy_image_compute_shader(struct pipe_context *ctx);
1457 void *si_create_copy_image_compute_shader_1d_array(struct pipe_context *ctx);
1458 void *si_clear_render_target_shader(struct pipe_context *ctx);
1459 void *si_clear_render_target_shader_1d_array(struct pipe_context *ctx);
1460 void *si_clear_12bytes_buffer_shader(struct pipe_context *ctx);
1461 void *si_create_dcc_retile_cs(struct pipe_context *ctx);
1462 void *si_create_fmask_expand_cs(struct pipe_context *ctx, unsigned num_samples,
1463 bool is_array);
1464 void *si_create_query_result_cs(struct si_context *sctx);
1465 void *gfx10_create_sh_query_result_cs(struct si_context *sctx);
1466
1467 /* gfx10_query.c */
1468 void gfx10_init_query(struct si_context *sctx);
1469 void gfx10_destroy_query(struct si_context *sctx);
1470
1471 /* si_test_dma.c */
1472 void si_test_dma(struct si_screen *sscreen);
1473
1474 /* si_test_clearbuffer.c */
1475 void si_test_dma_perf(struct si_screen *sscreen);
1476
1477 /* si_uvd.c */
1478 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
1479 const struct pipe_video_codec *templ);
1480
1481 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
1482 const struct pipe_video_buffer *tmpl);
1483
1484 /* si_viewport.c */
1485 void si_update_vs_viewport_state(struct si_context *ctx);
1486 void si_init_viewport_functions(struct si_context *ctx);
1487
1488 /* si_texture.c */
1489 bool si_prepare_for_dma_blit(struct si_context *sctx,
1490 struct si_texture *dst,
1491 unsigned dst_level, unsigned dstx,
1492 unsigned dsty, unsigned dstz,
1493 struct si_texture *src,
1494 unsigned src_level,
1495 const struct pipe_box *src_box);
1496 void si_eliminate_fast_color_clear(struct si_context *sctx,
1497 struct si_texture *tex);
1498 void si_texture_discard_cmask(struct si_screen *sscreen,
1499 struct si_texture *tex);
1500 bool si_init_flushed_depth_texture(struct pipe_context *ctx,
1501 struct pipe_resource *texture);
1502 void si_print_texture_info(struct si_screen *sscreen,
1503 struct si_texture *tex, struct u_log_context *log);
1504 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
1505 const struct pipe_resource *templ);
1506 bool vi_dcc_formats_compatible(struct si_screen *sscreen,
1507 enum pipe_format format1,
1508 enum pipe_format format2);
1509 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
1510 unsigned level,
1511 enum pipe_format view_format);
1512 void vi_disable_dcc_if_incompatible_format(struct si_context *sctx,
1513 struct pipe_resource *tex,
1514 unsigned level,
1515 enum pipe_format view_format);
1516 struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
1517 struct pipe_resource *texture,
1518 const struct pipe_surface *templ,
1519 unsigned width0, unsigned height0,
1520 unsigned width, unsigned height);
1521 unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
1522 void vi_separate_dcc_try_enable(struct si_context *sctx,
1523 struct si_texture *tex);
1524 void vi_separate_dcc_start_query(struct si_context *sctx,
1525 struct si_texture *tex);
1526 void vi_separate_dcc_stop_query(struct si_context *sctx,
1527 struct si_texture *tex);
1528 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
1529 struct si_texture *tex);
1530 bool si_texture_disable_dcc(struct si_context *sctx,
1531 struct si_texture *tex);
1532 void si_init_screen_texture_functions(struct si_screen *sscreen);
1533 void si_init_context_texture_functions(struct si_context *sctx);
1534
1535
1536 /*
1537 * common helpers
1538 */
1539
1540 static inline struct si_resource *si_resource(struct pipe_resource *r)
1541 {
1542 return (struct si_resource*)r;
1543 }
1544
1545 static inline void
1546 si_resource_reference(struct si_resource **ptr, struct si_resource *res)
1547 {
1548 pipe_resource_reference((struct pipe_resource **)ptr,
1549 (struct pipe_resource *)res);
1550 }
1551
1552 static inline void
1553 si_texture_reference(struct si_texture **ptr, struct si_texture *res)
1554 {
1555 pipe_resource_reference((struct pipe_resource **)ptr, &res->buffer.b.b);
1556 }
1557
1558 static inline bool
1559 vi_dcc_enabled(struct si_texture *tex, unsigned level)
1560 {
1561 return tex->surface.dcc_offset && level < tex->surface.num_dcc_levels;
1562 }
1563
1564 static inline unsigned
1565 si_tile_mode_index(struct si_texture *tex, unsigned level, bool stencil)
1566 {
1567 if (stencil)
1568 return tex->surface.u.legacy.stencil_tiling_index[level];
1569 else
1570 return tex->surface.u.legacy.tiling_index[level];
1571 }
1572
1573 static inline unsigned
1574 si_get_minimum_num_gfx_cs_dwords(struct si_context *sctx)
1575 {
1576 /* Don't count the needed CS space exactly and just use an upper bound.
1577 *
1578 * Also reserve space for stopping queries at the end of IB, because
1579 * the number of active queries is unlimited in theory.
1580 */
1581 return 2048 + sctx->num_cs_dw_queries_suspend;
1582 }
1583
1584 static inline void
1585 si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r)
1586 {
1587 if (r) {
1588 /* Add memory usage for need_gfx_cs_space */
1589 sctx->vram += si_resource(r)->vram_usage;
1590 sctx->gtt += si_resource(r)->gart_usage;
1591 }
1592 }
1593
1594 static inline void
1595 si_invalidate_draw_sh_constants(struct si_context *sctx)
1596 {
1597 sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
1598 sctx->last_instance_count = SI_INSTANCE_COUNT_UNKNOWN;
1599 }
1600
1601 static inline unsigned
1602 si_get_atom_bit(struct si_context *sctx, struct si_atom *atom)
1603 {
1604 return 1 << (atom - sctx->atoms.array);
1605 }
1606
1607 static inline void
1608 si_set_atom_dirty(struct si_context *sctx, struct si_atom *atom, bool dirty)
1609 {
1610 unsigned bit = si_get_atom_bit(sctx, atom);
1611
1612 if (dirty)
1613 sctx->dirty_atoms |= bit;
1614 else
1615 sctx->dirty_atoms &= ~bit;
1616 }
1617
1618 static inline bool
1619 si_is_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1620 {
1621 return (sctx->dirty_atoms & si_get_atom_bit(sctx, atom)) != 0;
1622 }
1623
1624 static inline void
1625 si_mark_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1626 {
1627 si_set_atom_dirty(sctx, atom, true);
1628 }
1629
1630 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
1631 {
1632 if (sctx->gs_shader.cso)
1633 return &sctx->gs_shader;
1634 if (sctx->tes_shader.cso)
1635 return &sctx->tes_shader;
1636
1637 return &sctx->vs_shader;
1638 }
1639
1640 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
1641 {
1642 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1643
1644 return vs->cso ? &vs->cso->info : NULL;
1645 }
1646
1647 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
1648 {
1649 if (sctx->gs_shader.cso &&
1650 sctx->gs_shader.current &&
1651 !sctx->gs_shader.current->key.as_ngg)
1652 return sctx->gs_shader.cso->gs_copy_shader;
1653
1654 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1655 return vs->current ? vs->current : NULL;
1656 }
1657
1658 static inline bool si_can_dump_shader(struct si_screen *sscreen,
1659 unsigned processor)
1660 {
1661 return sscreen->debug_flags & (1 << processor);
1662 }
1663
1664 static inline bool si_get_strmout_en(struct si_context *sctx)
1665 {
1666 return sctx->streamout.streamout_enabled ||
1667 sctx->streamout.prims_gen_query_enabled;
1668 }
1669
1670 static inline unsigned
1671 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
1672 {
1673 unsigned alignment, tcc_cache_line_size;
1674
1675 /* If the upload size is less than the cache line size (e.g. 16, 32),
1676 * the whole thing will fit into a cache line if we align it to its size.
1677 * The idea is that multiple small uploads can share a cache line.
1678 * If the upload size is greater, align it to the cache line size.
1679 */
1680 alignment = util_next_power_of_two(upload_size);
1681 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
1682 return MIN2(alignment, tcc_cache_line_size);
1683 }
1684
1685 static inline void
1686 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
1687 {
1688 if (pipe_reference(&(*dst)->reference, &src->reference))
1689 si_destroy_saved_cs(*dst);
1690
1691 *dst = src;
1692 }
1693
1694 static inline void
1695 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1696 bool shaders_read_metadata, bool dcc_pipe_aligned)
1697 {
1698 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
1699 SI_CONTEXT_INV_VCACHE;
1700
1701 if (sctx->chip_class >= GFX10) {
1702 if (sctx->screen->info.tcc_harvested)
1703 sctx->flags |= SI_CONTEXT_INV_L2;
1704 else if (shaders_read_metadata)
1705 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1706 } else if (sctx->chip_class == GFX9) {
1707 /* Single-sample color is coherent with shaders on GFX9, but
1708 * L2 metadata must be flushed if shaders read metadata.
1709 * (DCC, CMASK).
1710 */
1711 if (num_samples >= 2 ||
1712 (shaders_read_metadata && !dcc_pipe_aligned))
1713 sctx->flags |= SI_CONTEXT_INV_L2;
1714 else if (shaders_read_metadata)
1715 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1716 } else {
1717 /* GFX6-GFX8 */
1718 sctx->flags |= SI_CONTEXT_INV_L2;
1719 }
1720 }
1721
1722 static inline void
1723 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1724 bool include_stencil, bool shaders_read_metadata)
1725 {
1726 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
1727 SI_CONTEXT_INV_VCACHE;
1728
1729 if (sctx->chip_class >= GFX10) {
1730 if (sctx->screen->info.tcc_harvested)
1731 sctx->flags |= SI_CONTEXT_INV_L2;
1732 else if (shaders_read_metadata)
1733 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1734 } else if (sctx->chip_class == GFX9) {
1735 /* Single-sample depth (not stencil) is coherent with shaders
1736 * on GFX9, but L2 metadata must be flushed if shaders read
1737 * metadata.
1738 */
1739 if (num_samples >= 2 || include_stencil)
1740 sctx->flags |= SI_CONTEXT_INV_L2;
1741 else if (shaders_read_metadata)
1742 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1743 } else {
1744 /* GFX6-GFX8 */
1745 sctx->flags |= SI_CONTEXT_INV_L2;
1746 }
1747 }
1748
1749 static inline bool
1750 si_can_sample_zs(struct si_texture *tex, bool stencil_sampler)
1751 {
1752 return (stencil_sampler && tex->can_sample_s) ||
1753 (!stencil_sampler && tex->can_sample_z);
1754 }
1755
1756 static inline bool
1757 si_htile_enabled(struct si_texture *tex, unsigned level, unsigned zs_mask)
1758 {
1759 if (zs_mask == PIPE_MASK_S && tex->htile_stencil_disabled)
1760 return false;
1761
1762 return tex->surface.htile_offset && level == 0;
1763 }
1764
1765 static inline bool
1766 vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level, unsigned zs_mask)
1767 {
1768 assert(!tex->tc_compatible_htile || tex->surface.htile_offset);
1769 return tex->tc_compatible_htile && si_htile_enabled(tex, level, zs_mask);
1770 }
1771
1772 static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
1773 {
1774 if (sctx->ps_uses_fbfetch)
1775 return sctx->framebuffer.nr_color_samples;
1776
1777 return MIN2(sctx->ps_iter_samples, sctx->framebuffer.nr_color_samples);
1778 }
1779
1780 static inline unsigned si_get_total_colormask(struct si_context *sctx)
1781 {
1782 if (sctx->queued.named.rasterizer->rasterizer_discard)
1783 return 0;
1784
1785 struct si_shader_selector *ps = sctx->ps_shader.cso;
1786 if (!ps)
1787 return 0;
1788
1789 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1790 sctx->queued.named.blend->cb_target_mask;
1791
1792 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1793 colormask &= ps->colors_written_4bit;
1794 else if (!ps->colors_written_4bit)
1795 colormask = 0; /* color0 writes all cbufs, but it's not written */
1796
1797 return colormask;
1798 }
1799
1800 #define UTIL_ALL_PRIM_LINE_MODES ((1 << PIPE_PRIM_LINES) | \
1801 (1 << PIPE_PRIM_LINE_LOOP) | \
1802 (1 << PIPE_PRIM_LINE_STRIP) | \
1803 (1 << PIPE_PRIM_LINES_ADJACENCY) | \
1804 (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1805
1806 static inline bool util_prim_is_lines(unsigned prim)
1807 {
1808 return ((1 << prim) & UTIL_ALL_PRIM_LINE_MODES) != 0;
1809 }
1810
1811 static inline bool util_prim_is_points_or_lines(unsigned prim)
1812 {
1813 return ((1 << prim) & (UTIL_ALL_PRIM_LINE_MODES |
1814 (1 << PIPE_PRIM_POINTS))) != 0;
1815 }
1816
1817 static inline bool util_rast_prim_is_triangles(unsigned prim)
1818 {
1819 return ((1 << prim) & ((1 << PIPE_PRIM_TRIANGLES) |
1820 (1 << PIPE_PRIM_TRIANGLE_STRIP) |
1821 (1 << PIPE_PRIM_TRIANGLE_FAN) |
1822 (1 << PIPE_PRIM_QUADS) |
1823 (1 << PIPE_PRIM_QUAD_STRIP) |
1824 (1 << PIPE_PRIM_POLYGON) |
1825 (1 << PIPE_PRIM_TRIANGLES_ADJACENCY) |
1826 (1 << PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY)));
1827 }
1828
1829 /**
1830 * Return true if there is enough memory in VRAM and GTT for the buffers
1831 * added so far.
1832 *
1833 * \param vram VRAM memory size not added to the buffer list yet
1834 * \param gtt GTT memory size not added to the buffer list yet
1835 */
1836 static inline bool
1837 radeon_cs_memory_below_limit(struct si_screen *screen,
1838 struct radeon_cmdbuf *cs,
1839 uint64_t vram, uint64_t gtt)
1840 {
1841 vram += cs->used_vram;
1842 gtt += cs->used_gart;
1843
1844 /* Anything that goes above the VRAM size should go to GTT. */
1845 if (vram > screen->info.vram_size)
1846 gtt += vram - screen->info.vram_size;
1847
1848 /* Now we just need to check if we have enough GTT. */
1849 return gtt < screen->info.gart_size * 0.7;
1850 }
1851
1852 /**
1853 * Add a buffer to the buffer list for the given command stream (CS).
1854 *
1855 * All buffers used by a CS must be added to the list. This tells the kernel
1856 * driver which buffers are used by GPU commands. Other buffers can
1857 * be swapped out (not accessible) during execution.
1858 *
1859 * The buffer list becomes empty after every context flush and must be
1860 * rebuilt.
1861 */
1862 static inline void radeon_add_to_buffer_list(struct si_context *sctx,
1863 struct radeon_cmdbuf *cs,
1864 struct si_resource *bo,
1865 enum radeon_bo_usage usage,
1866 enum radeon_bo_priority priority)
1867 {
1868 assert(usage);
1869 sctx->ws->cs_add_buffer(
1870 cs, bo->buf,
1871 (enum radeon_bo_usage)(usage | RADEON_USAGE_SYNCHRONIZED),
1872 bo->domains, priority);
1873 }
1874
1875 /**
1876 * Same as above, but also checks memory usage and flushes the context
1877 * accordingly.
1878 *
1879 * When this SHOULD NOT be used:
1880 *
1881 * - if si_context_add_resource_size has been called for the buffer
1882 * followed by *_need_cs_space for checking the memory usage
1883 *
1884 * - if si_need_dma_space has been called for the buffer
1885 *
1886 * - when emitting state packets and draw packets (because preceding packets
1887 * can't be re-emitted at that point)
1888 *
1889 * - if shader resource "enabled_mask" is not up-to-date or there is
1890 * a different constraint disallowing a context flush
1891 */
1892 static inline void
1893 radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx,
1894 struct si_resource *bo,
1895 enum radeon_bo_usage usage,
1896 enum radeon_bo_priority priority,
1897 bool check_mem)
1898 {
1899 if (check_mem &&
1900 !radeon_cs_memory_below_limit(sctx->screen, sctx->gfx_cs,
1901 sctx->vram + bo->vram_usage,
1902 sctx->gtt + bo->gart_usage))
1903 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1904
1905 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, bo, usage, priority);
1906 }
1907
1908 static inline bool si_compute_prim_discard_enabled(struct si_context *sctx)
1909 {
1910 return sctx->prim_discard_vertex_count_threshold != UINT_MAX;
1911 }
1912
1913 static inline unsigned si_get_wave_size(struct si_screen *sscreen,
1914 enum pipe_shader_type shader_type,
1915 bool ngg, bool es)
1916 {
1917 if (shader_type == PIPE_SHADER_COMPUTE)
1918 return sscreen->compute_wave_size;
1919 else if (shader_type == PIPE_SHADER_FRAGMENT)
1920 return sscreen->ps_wave_size;
1921 else if ((shader_type == PIPE_SHADER_VERTEX && es && !ngg) ||
1922 (shader_type == PIPE_SHADER_TESS_EVAL && es && !ngg) ||
1923 (shader_type == PIPE_SHADER_GEOMETRY && !ngg)) /* legacy GS only supports Wave64 */
1924 return 64;
1925 else
1926 return sscreen->ge_wave_size;
1927 }
1928
1929 static inline unsigned si_get_shader_wave_size(struct si_shader *shader)
1930 {
1931 return si_get_wave_size(shader->selector->screen, shader->selector->type,
1932 shader->key.as_ngg, shader->key.as_es);
1933 }
1934
1935 #define PRINT_ERR(fmt, args...) \
1936 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
1937
1938 #endif