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radeonsi/gfx10: fix corruption for chips with harvested TCCs
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25 #ifndef SI_PIPE_H
26 #define SI_PIPE_H
27
28 #include "si_shader.h"
29 #include "si_state.h"
30
31 #include "util/u_dynarray.h"
32 #include "util/u_idalloc.h"
33 #include "util/u_threaded_context.h"
34
35 #ifdef PIPE_ARCH_BIG_ENDIAN
36 #define SI_BIG_ENDIAN 1
37 #else
38 #define SI_BIG_ENDIAN 0
39 #endif
40
41 #define ATI_VENDOR_ID 0x1002
42 #define SI_PRIM_DISCARD_DEBUG 0
43 #define SI_NOT_QUERY 0xffffffff
44
45 /* The base vertex and primitive restart can be any number, but we must pick
46 * one which will mean "unknown" for the purpose of state tracking and
47 * the number shouldn't be a commonly-used one. */
48 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
49 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
50 #define SI_INSTANCE_COUNT_UNKNOWN INT_MIN
51 #define SI_NUM_SMOOTH_AA_SAMPLES 8
52 #define SI_MAX_POINT_SIZE 2048
53 #define SI_GS_PER_ES 128
54 /* Alignment for optimal CP DMA performance. */
55 #define SI_CPDMA_ALIGNMENT 32
56
57 /* Tunables for compute-based clear_buffer and copy_buffer: */
58 #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
59 #define SI_COMPUTE_COPY_DW_PER_THREAD 4
60 #define SI_COMPUTE_DST_CACHE_POLICY L2_STREAM
61
62 /* Pipeline & streamout query controls. */
63 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
64 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
65 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
66 /* Instruction cache. */
67 #define SI_CONTEXT_INV_ICACHE (1 << 3)
68 /* Scalar cache. (GFX6-9: scalar L1; GFX10: scalar L0)
69 * GFX10: This also invalidates the L1 shader array cache. */
70 #define SI_CONTEXT_INV_SCACHE (1 << 4)
71 /* Vector cache. (GFX6-9: vector L1; GFX10: vector L0)
72 * GFX10: This also invalidates the L1 shader array cache. */
73 #define SI_CONTEXT_INV_VCACHE (1 << 5)
74 /* L2 cache + L2 metadata cache writeback & invalidate.
75 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
76 #define SI_CONTEXT_INV_L2 (1 << 6)
77 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
78 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
79 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
80 #define SI_CONTEXT_WB_L2 (1 << 7)
81 /* Writeback & invalidate the L2 metadata cache only. It can only be coupled with
82 * a CB or DB flush. */
83 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
84 /* Framebuffer caches. */
85 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
86 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
87 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
88 /* Engine synchronization. */
89 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
90 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
91 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
92 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
93 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
94
95 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
96 #define SI_PREFETCH_LS (1 << 1)
97 #define SI_PREFETCH_HS (1 << 2)
98 #define SI_PREFETCH_ES (1 << 3)
99 #define SI_PREFETCH_GS (1 << 4)
100 #define SI_PREFETCH_VS (1 << 5)
101 #define SI_PREFETCH_PS (1 << 6)
102
103 #define SI_MAX_BORDER_COLORS 4096
104 #define SI_MAX_VIEWPORTS 16
105 #define SIX_BITS 0x3F
106 #define SI_MAP_BUFFER_ALIGNMENT 64
107 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
108
109 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
110 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
111 #define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
112 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
113 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
114 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
115 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
116 #define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
117 /* For const_uploader, upload data via GTT and copy to VRAM on context flush via SDMA. */
118 #define SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA (PIPE_RESOURCE_FLAG_DRV_PRIV << 8)
119
120 enum si_clear_code
121 {
122 DCC_CLEAR_COLOR_0000 = 0x00000000,
123 DCC_CLEAR_COLOR_0001 = 0x40404040,
124 DCC_CLEAR_COLOR_1110 = 0x80808080,
125 DCC_CLEAR_COLOR_1111 = 0xC0C0C0C0,
126 DCC_CLEAR_COLOR_REG = 0x20202020,
127 DCC_UNCOMPRESSED = 0xFFFFFFFF,
128 };
129
130 #define SI_IMAGE_ACCESS_AS_BUFFER (1 << 7)
131
132 /* Debug flags. */
133 enum {
134 /* Shader logging options: */
135 DBG_VS = PIPE_SHADER_VERTEX,
136 DBG_PS = PIPE_SHADER_FRAGMENT,
137 DBG_GS = PIPE_SHADER_GEOMETRY,
138 DBG_TCS = PIPE_SHADER_TESS_CTRL,
139 DBG_TES = PIPE_SHADER_TESS_EVAL,
140 DBG_CS = PIPE_SHADER_COMPUTE,
141 DBG_NO_IR,
142 DBG_NO_TGSI,
143 DBG_NO_ASM,
144 DBG_PREOPT_IR,
145
146 /* Shader compiler options the shader cache should be aware of: */
147 DBG_FS_CORRECT_DERIVS_AFTER_KILL,
148 DBG_SI_SCHED,
149 DBG_GISEL,
150 DBG_W32_GE,
151 DBG_W32_PS,
152 DBG_W32_CS,
153 DBG_W64_GE,
154 DBG_W64_PS,
155 DBG_W64_CS,
156
157 /* Shader compiler options (with no effect on the shader cache): */
158 DBG_CHECK_IR,
159 DBG_MONOLITHIC_SHADERS,
160 DBG_NO_OPT_VARIANT,
161
162 /* Information logging options: */
163 DBG_INFO,
164 DBG_TEX,
165 DBG_COMPUTE,
166 DBG_VM,
167
168 /* Driver options: */
169 DBG_FORCE_DMA,
170 DBG_NO_ASYNC_DMA,
171 DBG_NO_WC,
172 DBG_CHECK_VM,
173 DBG_RESERVE_VMID,
174 DBG_ZERO_VRAM,
175
176 /* 3D engine options: */
177 DBG_NO_GFX,
178 DBG_NO_NGG,
179 DBG_ALWAYS_PD,
180 DBG_PD,
181 DBG_NO_PD,
182 DBG_SWITCH_ON_EOP,
183 DBG_NO_OUT_OF_ORDER,
184 DBG_NO_DPBB,
185 DBG_NO_DFSM,
186 DBG_DPBB,
187 DBG_DFSM,
188 DBG_NO_HYPERZ,
189 DBG_NO_RB_PLUS,
190 DBG_NO_2D_TILING,
191 DBG_NO_TILING,
192 DBG_NO_DCC,
193 DBG_NO_DCC_CLEAR,
194 DBG_NO_DCC_FB,
195 DBG_NO_DCC_MSAA,
196 DBG_NO_FMASK,
197
198 /* Tests: */
199 DBG_TEST_DMA,
200 DBG_TEST_VMFAULT_CP,
201 DBG_TEST_VMFAULT_SDMA,
202 DBG_TEST_VMFAULT_SHADER,
203 DBG_TEST_DMA_PERF,
204 DBG_TEST_GDS,
205 DBG_TEST_GDS_MM,
206 DBG_TEST_GDS_OA_MM,
207 };
208
209 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
210 #define DBG(name) (1ull << DBG_##name)
211
212 enum si_cache_policy {
213 L2_BYPASS,
214 L2_STREAM, /* same as SLC=1 */
215 L2_LRU, /* same as SLC=0 */
216 };
217
218 enum si_coherency {
219 SI_COHERENCY_NONE, /* no cache flushes needed */
220 SI_COHERENCY_SHADER,
221 SI_COHERENCY_CB_META,
222 SI_COHERENCY_CP,
223 };
224
225 struct si_compute;
226 struct si_shader_context;
227 struct hash_table;
228 struct u_suballocator;
229
230 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
231 * at the moment.
232 */
233 struct si_resource {
234 struct threaded_resource b;
235
236 /* Winsys objects. */
237 struct pb_buffer *buf;
238 uint64_t gpu_address;
239 /* Memory usage if the buffer placement is optimal. */
240 uint64_t vram_usage;
241 uint64_t gart_usage;
242
243 /* Resource properties. */
244 uint64_t bo_size;
245 unsigned bo_alignment;
246 enum radeon_bo_domain domains;
247 enum radeon_bo_flag flags;
248 unsigned bind_history;
249 int max_forced_staging_uploads;
250
251 /* The buffer range which is initialized (with a write transfer,
252 * streamout, DMA, or as a random access target). The rest of
253 * the buffer is considered invalid and can be mapped unsynchronized.
254 *
255 * This allows unsychronized mapping of a buffer range which hasn't
256 * been used yet. It's for applications which forget to use
257 * the unsynchronized map flag and expect the driver to figure it out.
258 */
259 struct util_range valid_buffer_range;
260
261 /* For buffers only. This indicates that a write operation has been
262 * performed by TC L2, but the cache hasn't been flushed.
263 * Any hw block which doesn't use or bypasses TC L2 should check this
264 * flag and flush the cache before using the buffer.
265 *
266 * For example, TC L2 must be flushed if a buffer which has been
267 * modified by a shader store instruction is about to be used as
268 * an index buffer. The reason is that VGT DMA index fetching doesn't
269 * use TC L2.
270 */
271 bool TC_L2_dirty;
272
273 /* Whether this resource is referenced by bindless handles. */
274 bool texture_handle_allocated;
275 bool image_handle_allocated;
276
277 /* Whether the resource has been exported via resource_get_handle. */
278 unsigned external_usage; /* PIPE_HANDLE_USAGE_* */
279 };
280
281 struct si_transfer {
282 struct threaded_transfer b;
283 struct si_resource *staging;
284 unsigned offset;
285 };
286
287 struct si_texture {
288 struct si_resource buffer;
289
290 struct radeon_surf surface;
291 struct si_texture *flushed_depth_texture;
292
293 /* One texture allocation can contain these buffers:
294 * - image (pixel data)
295 * - FMASK buffer (MSAA compression)
296 * - CMASK buffer (MSAA compression and/or legacy fast color clear)
297 * - HTILE buffer (Z/S compression and fast Z/S clear)
298 * - DCC buffer (color compression and new fast color clear)
299 * - displayable DCC buffer (if the DCC buffer is not displayable)
300 * - DCC retile mapping buffer (if the DCC buffer is not displayable)
301 */
302 uint64_t cmask_base_address_reg;
303 struct si_resource *cmask_buffer;
304 unsigned cb_color_info; /* fast clear enable bit */
305 unsigned color_clear_value[2];
306 unsigned last_msaa_resolve_target_micro_mode;
307 unsigned num_level0_transfers;
308
309 /* Depth buffer compression and fast clear. */
310 float depth_clear_value;
311 uint16_t dirty_level_mask; /* each bit says if that mipmap is compressed */
312 uint16_t stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
313 enum pipe_format db_render_format:16;
314 uint8_t stencil_clear_value;
315 bool tc_compatible_htile:1;
316 bool htile_stencil_disabled:1;
317 bool depth_cleared:1; /* if it was cleared at least once */
318 bool stencil_cleared:1; /* if it was cleared at least once */
319 bool upgraded_depth:1; /* upgraded from unorm to Z32_FLOAT */
320 bool is_depth:1;
321 bool db_compatible:1;
322 bool can_sample_z:1;
323 bool can_sample_s:1;
324
325 /* We need to track DCC dirtiness, because st/dri usually calls
326 * flush_resource twice per frame (not a bug) and we don't wanna
327 * decompress DCC twice. Also, the dirty tracking must be done even
328 * if DCC isn't used, because it's required by the DCC usage analysis
329 * for a possible future enablement.
330 */
331 bool separate_dcc_dirty:1;
332 /* Statistics gathering for the DCC enablement heuristic. */
333 bool dcc_gather_statistics:1;
334 /* Counter that should be non-zero if the texture is bound to a
335 * framebuffer.
336 */
337 unsigned framebuffers_bound;
338 /* Whether the texture is a displayable back buffer and needs DCC
339 * decompression, which is expensive. Therefore, it's enabled only
340 * if statistics suggest that it will pay off and it's allocated
341 * separately. It can't be bound as a sampler by apps. Limited to
342 * target == 2D and last_level == 0. If enabled, dcc_offset contains
343 * the absolute GPUVM address, not the relative one.
344 */
345 struct si_resource *dcc_separate_buffer;
346 /* When DCC is temporarily disabled, the separate buffer is here. */
347 struct si_resource *last_dcc_separate_buffer;
348 /* Estimate of how much this color buffer is written to in units of
349 * full-screen draws: ps_invocations / (width * height)
350 * Shader kills, late Z, and blending with trivial discards make it
351 * inaccurate (we need to count CB updates, not PS invocations).
352 */
353 unsigned ps_draw_ratio;
354 /* The number of clears since the last DCC usage analysis. */
355 unsigned num_slow_clears;
356 };
357
358 struct si_surface {
359 struct pipe_surface base;
360
361 /* These can vary with block-compressed textures. */
362 uint16_t width0;
363 uint16_t height0;
364
365 bool color_initialized:1;
366 bool depth_initialized:1;
367
368 /* Misc. color flags. */
369 bool color_is_int8:1;
370 bool color_is_int10:1;
371 bool dcc_incompatible:1;
372
373 /* Color registers. */
374 unsigned cb_color_info;
375 unsigned cb_color_view;
376 unsigned cb_color_attrib;
377 unsigned cb_color_attrib2; /* GFX9 and later */
378 unsigned cb_color_attrib3; /* GFX10 and later */
379 unsigned cb_dcc_control; /* GFX8 and later */
380 unsigned spi_shader_col_format:8; /* no blending, no alpha-to-coverage. */
381 unsigned spi_shader_col_format_alpha:8; /* alpha-to-coverage */
382 unsigned spi_shader_col_format_blend:8; /* blending without alpha. */
383 unsigned spi_shader_col_format_blend_alpha:8; /* blending with alpha. */
384
385 /* DB registers. */
386 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE */
387 uint64_t db_stencil_base;
388 uint64_t db_htile_data_base;
389 unsigned db_depth_info;
390 unsigned db_z_info;
391 unsigned db_z_info2; /* GFX9 only */
392 unsigned db_depth_view;
393 unsigned db_depth_size;
394 unsigned db_depth_slice;
395 unsigned db_stencil_info;
396 unsigned db_stencil_info2; /* GFX9 only */
397 unsigned db_htile_surface;
398 };
399
400 struct si_mmio_counter {
401 unsigned busy;
402 unsigned idle;
403 };
404
405 union si_mmio_counters {
406 struct {
407 /* For global GPU load including SDMA. */
408 struct si_mmio_counter gpu;
409
410 /* GRBM_STATUS */
411 struct si_mmio_counter spi;
412 struct si_mmio_counter gui;
413 struct si_mmio_counter ta;
414 struct si_mmio_counter gds;
415 struct si_mmio_counter vgt;
416 struct si_mmio_counter ia;
417 struct si_mmio_counter sx;
418 struct si_mmio_counter wd;
419 struct si_mmio_counter bci;
420 struct si_mmio_counter sc;
421 struct si_mmio_counter pa;
422 struct si_mmio_counter db;
423 struct si_mmio_counter cp;
424 struct si_mmio_counter cb;
425
426 /* SRBM_STATUS2 */
427 struct si_mmio_counter sdma;
428
429 /* CP_STAT */
430 struct si_mmio_counter pfp;
431 struct si_mmio_counter meq;
432 struct si_mmio_counter me;
433 struct si_mmio_counter surf_sync;
434 struct si_mmio_counter cp_dma;
435 struct si_mmio_counter scratch_ram;
436 } named;
437 unsigned array[0];
438 };
439
440 struct si_memory_object {
441 struct pipe_memory_object b;
442 struct pb_buffer *buf;
443 uint32_t stride;
444 };
445
446 /* Saved CS data for debugging features. */
447 struct radeon_saved_cs {
448 uint32_t *ib;
449 unsigned num_dw;
450
451 struct radeon_bo_list_item *bo_list;
452 unsigned bo_count;
453 };
454
455 struct si_screen {
456 struct pipe_screen b;
457 struct radeon_winsys *ws;
458 struct disk_cache *disk_shader_cache;
459
460 struct radeon_info info;
461 uint64_t debug_flags;
462 char renderer_string[183];
463
464 void (*make_texture_descriptor)(
465 struct si_screen *screen,
466 struct si_texture *tex,
467 bool sampler,
468 enum pipe_texture_target target,
469 enum pipe_format pipe_format,
470 const unsigned char state_swizzle[4],
471 unsigned first_level, unsigned last_level,
472 unsigned first_layer, unsigned last_layer,
473 unsigned width, unsigned height, unsigned depth,
474 uint32_t *state,
475 uint32_t *fmask_state);
476
477 unsigned pa_sc_raster_config;
478 unsigned pa_sc_raster_config_1;
479 unsigned se_tile_repeat;
480 unsigned gs_table_depth;
481 unsigned tess_offchip_block_dw_size;
482 unsigned tess_offchip_ring_size;
483 unsigned tess_factor_ring_size;
484 unsigned vgt_hs_offchip_param;
485 unsigned eqaa_force_coverage_samples;
486 unsigned eqaa_force_z_samples;
487 unsigned eqaa_force_color_samples;
488 bool has_draw_indirect_multi;
489 bool has_out_of_order_rast;
490 bool assume_no_z_fights;
491 bool commutative_blend_add;
492 bool dpbb_allowed;
493 bool dfsm_allowed;
494 bool llvm_has_working_vgpr_indexing;
495 bool use_ngg;
496 bool use_ngg_streamout;
497
498 struct {
499 #define OPT_BOOL(name, dflt, description) bool name:1;
500 #include "si_debug_options.h"
501 } options;
502
503 /* Whether shaders are monolithic (1-part) or separate (3-part). */
504 bool use_monolithic_shaders;
505 bool record_llvm_ir;
506 bool dcc_msaa_allowed;
507
508 struct slab_parent_pool pool_transfers;
509
510 /* Texture filter settings. */
511 int force_aniso; /* -1 = disabled */
512
513 /* Auxiliary context. Mainly used to initialize resources.
514 * It must be locked prior to using and flushed before unlocking. */
515 struct pipe_context *aux_context;
516 mtx_t aux_context_lock;
517
518 /* This must be in the screen, because UE4 uses one context for
519 * compilation and another one for rendering.
520 */
521 unsigned num_compilations;
522 /* Along with ST_DEBUG=precompile, this should show if applications
523 * are loading shaders on demand. This is a monotonic counter.
524 */
525 unsigned num_shaders_created;
526 unsigned num_shader_cache_hits;
527
528 /* GPU load thread. */
529 mtx_t gpu_load_mutex;
530 thrd_t gpu_load_thread;
531 union si_mmio_counters mmio_counters;
532 volatile unsigned gpu_load_stop_thread; /* bool */
533
534 /* Performance counters. */
535 struct si_perfcounters *perfcounters;
536
537 /* If pipe_screen wants to recompute and re-emit the framebuffer,
538 * sampler, and image states of all contexts, it should atomically
539 * increment this.
540 *
541 * Each context will compare this with its own last known value of
542 * the counter before drawing and re-emit the states accordingly.
543 */
544 unsigned dirty_tex_counter;
545 unsigned dirty_buf_counter;
546
547 /* Atomically increment this counter when an existing texture's
548 * metadata is enabled or disabled in a way that requires changing
549 * contexts' compressed texture binding masks.
550 */
551 unsigned compressed_colortex_counter;
552
553 struct {
554 /* Context flags to set so that all writes from earlier jobs
555 * in the CP are seen by L2 clients.
556 */
557 unsigned cp_to_L2;
558
559 /* Context flags to set so that all writes from earlier jobs
560 * that end in L2 are seen by CP.
561 */
562 unsigned L2_to_cp;
563 } barrier_flags;
564
565 mtx_t shader_parts_mutex;
566 struct si_shader_part *vs_prologs;
567 struct si_shader_part *tcs_epilogs;
568 struct si_shader_part *gs_prologs;
569 struct si_shader_part *ps_prologs;
570 struct si_shader_part *ps_epilogs;
571
572 /* Shader cache in memory.
573 *
574 * Design & limitations:
575 * - The shader cache is per screen (= per process), never saved to
576 * disk, and skips redundant shader compilations from TGSI to bytecode.
577 * - It can only be used with one-variant-per-shader support, in which
578 * case only the main (typically middle) part of shaders is cached.
579 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
580 * variants of VS and TES are cached, so LS and ES aren't.
581 * - GS and CS aren't cached, but it's certainly possible to cache
582 * those as well.
583 */
584 mtx_t shader_cache_mutex;
585 struct hash_table *shader_cache;
586
587 /* Shader compiler queue for multithreaded compilation. */
588 struct util_queue shader_compiler_queue;
589 /* Use at most 3 normal compiler threads on quadcore and better.
590 * Hyperthreaded CPUs report the number of threads, but we want
591 * the number of cores. We only need this many threads for shader-db. */
592 struct ac_llvm_compiler compiler[24]; /* used by the queue only */
593
594 struct util_queue shader_compiler_queue_low_priority;
595 /* Use at most 2 low priority threads on quadcore and better.
596 * We want to minimize the impact on multithreaded Mesa. */
597 struct ac_llvm_compiler compiler_lowp[10];
598
599 unsigned compute_wave_size;
600 unsigned ps_wave_size;
601 unsigned ge_wave_size;
602 };
603
604 struct si_blend_color {
605 struct pipe_blend_color state;
606 bool any_nonzeros;
607 };
608
609 struct si_sampler_view {
610 struct pipe_sampler_view base;
611 /* [0..7] = image descriptor
612 * [4..7] = buffer descriptor */
613 uint32_t state[8];
614 uint32_t fmask_state[8];
615 const struct legacy_surf_level *base_level_info;
616 ubyte base_level;
617 ubyte block_width;
618 bool is_stencil_sampler;
619 bool is_integer;
620 bool dcc_incompatible;
621 };
622
623 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
624
625 struct si_sampler_state {
626 #ifndef NDEBUG
627 unsigned magic;
628 #endif
629 uint32_t val[4];
630 uint32_t integer_val[4];
631 uint32_t upgraded_depth_val[4];
632 };
633
634 struct si_cs_shader_state {
635 struct si_compute *program;
636 struct si_compute *emitted_program;
637 unsigned offset;
638 bool initialized;
639 bool uses_scratch;
640 };
641
642 struct si_samplers {
643 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
644 struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS];
645
646 /* The i-th bit is set if that element is enabled (non-NULL resource). */
647 unsigned enabled_mask;
648 uint32_t needs_depth_decompress_mask;
649 uint32_t needs_color_decompress_mask;
650 };
651
652 struct si_images {
653 struct pipe_image_view views[SI_NUM_IMAGES];
654 uint32_t needs_color_decompress_mask;
655 unsigned enabled_mask;
656 };
657
658 struct si_framebuffer {
659 struct pipe_framebuffer_state state;
660 unsigned colorbuf_enabled_4bit;
661 unsigned spi_shader_col_format;
662 unsigned spi_shader_col_format_alpha;
663 unsigned spi_shader_col_format_blend;
664 unsigned spi_shader_col_format_blend_alpha;
665 ubyte nr_samples:5; /* at most 16xAA */
666 ubyte log_samples:3; /* at most 4 = 16xAA */
667 ubyte nr_color_samples; /* at most 8xAA */
668 ubyte compressed_cb_mask;
669 ubyte uncompressed_cb_mask;
670 ubyte color_is_int8;
671 ubyte color_is_int10;
672 ubyte dirty_cbufs;
673 ubyte dcc_overwrite_combiner_watermark;
674 ubyte min_bytes_per_pixel;
675 bool dirty_zsbuf;
676 bool any_dst_linear;
677 bool CB_has_shader_readable_metadata;
678 bool DB_has_shader_readable_metadata;
679 bool all_DCC_pipe_aligned;
680 };
681
682 enum si_quant_mode {
683 /* This is the list we want to support. */
684 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH,
685 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH,
686 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH,
687 };
688
689 struct si_signed_scissor {
690 int minx;
691 int miny;
692 int maxx;
693 int maxy;
694 enum si_quant_mode quant_mode;
695 };
696
697 struct si_viewports {
698 struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
699 struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS];
700 bool y_inverted;
701 };
702
703 struct si_clip_state {
704 struct pipe_clip_state state;
705 bool any_nonzeros;
706 };
707
708 struct si_streamout_target {
709 struct pipe_stream_output_target b;
710
711 /* The buffer where BUFFER_FILLED_SIZE is stored. */
712 struct si_resource *buf_filled_size;
713 unsigned buf_filled_size_offset;
714 bool buf_filled_size_valid;
715
716 unsigned stride_in_dw;
717 };
718
719 struct si_streamout {
720 bool begin_emitted;
721
722 unsigned enabled_mask;
723 unsigned num_targets;
724 struct si_streamout_target *targets[PIPE_MAX_SO_BUFFERS];
725
726 unsigned append_bitmask;
727 bool suspended;
728
729 /* External state which comes from the vertex shader,
730 * it must be set explicitly when binding a shader. */
731 uint16_t *stride_in_dw;
732 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
733
734 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
735 unsigned hw_enabled_mask;
736
737 /* The state of VGT_STRMOUT_(CONFIG|EN). */
738 bool streamout_enabled;
739 bool prims_gen_query_enabled;
740 int num_prims_gen_queries;
741 };
742
743 /* A shader state consists of the shader selector, which is a constant state
744 * object shared by multiple contexts and shouldn't be modified, and
745 * the current shader variant selected for this context.
746 */
747 struct si_shader_ctx_state {
748 struct si_shader_selector *cso;
749 struct si_shader *current;
750 };
751
752 #define SI_NUM_VGT_PARAM_KEY_BITS 12
753 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
754
755 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
756 * Some fields are set by state-change calls, most are set by draw_vbo.
757 */
758 union si_vgt_param_key {
759 struct {
760 #ifdef PIPE_ARCH_LITTLE_ENDIAN
761 unsigned prim:4;
762 unsigned uses_instancing:1;
763 unsigned multi_instances_smaller_than_primgroup:1;
764 unsigned primitive_restart:1;
765 unsigned count_from_stream_output:1;
766 unsigned line_stipple_enabled:1;
767 unsigned uses_tess:1;
768 unsigned tess_uses_prim_id:1;
769 unsigned uses_gs:1;
770 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
771 #else /* PIPE_ARCH_BIG_ENDIAN */
772 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
773 unsigned uses_gs:1;
774 unsigned tess_uses_prim_id:1;
775 unsigned uses_tess:1;
776 unsigned line_stipple_enabled:1;
777 unsigned count_from_stream_output:1;
778 unsigned primitive_restart:1;
779 unsigned multi_instances_smaller_than_primgroup:1;
780 unsigned uses_instancing:1;
781 unsigned prim:4;
782 #endif
783 } u;
784 uint32_t index;
785 };
786
787 #define SI_NUM_VGT_STAGES_KEY_BITS 4
788 #define SI_NUM_VGT_STAGES_STATES (1 << SI_NUM_VGT_STAGES_KEY_BITS)
789
790 /* The VGT_SHADER_STAGES key used to index the table of precomputed values.
791 * Some fields are set by state-change calls, most are set by draw_vbo.
792 */
793 union si_vgt_stages_key {
794 struct {
795 #ifdef PIPE_ARCH_LITTLE_ENDIAN
796 unsigned tess:1;
797 unsigned gs:1;
798 unsigned ngg:1; /* gfx10+ */
799 unsigned streamout:1; /* only used with NGG */
800 unsigned _pad:32 - SI_NUM_VGT_STAGES_KEY_BITS;
801 #else /* PIPE_ARCH_BIG_ENDIAN */
802 unsigned _pad:32 - SI_NUM_VGT_STAGES_KEY_BITS;
803 unsigned streamout:1;
804 unsigned ngg:1;
805 unsigned gs:1;
806 unsigned tess:1;
807 #endif
808 } u;
809 uint32_t index;
810 };
811
812 struct si_texture_handle
813 {
814 unsigned desc_slot;
815 bool desc_dirty;
816 struct pipe_sampler_view *view;
817 struct si_sampler_state sstate;
818 };
819
820 struct si_image_handle
821 {
822 unsigned desc_slot;
823 bool desc_dirty;
824 struct pipe_image_view view;
825 };
826
827 struct si_saved_cs {
828 struct pipe_reference reference;
829 struct si_context *ctx;
830 struct radeon_saved_cs gfx;
831 struct radeon_saved_cs compute;
832 struct si_resource *trace_buf;
833 unsigned trace_id;
834
835 unsigned gfx_last_dw;
836 unsigned compute_last_dw;
837 bool flushed;
838 int64_t time_flush;
839 };
840
841 struct si_sdma_upload {
842 struct si_resource *dst;
843 struct si_resource *src;
844 unsigned src_offset;
845 unsigned dst_offset;
846 unsigned size;
847 };
848
849 struct si_context {
850 struct pipe_context b; /* base class */
851
852 enum radeon_family family;
853 enum chip_class chip_class;
854
855 struct radeon_winsys *ws;
856 struct radeon_winsys_ctx *ctx;
857 struct radeon_cmdbuf *gfx_cs; /* compute IB if graphics is disabled */
858 struct radeon_cmdbuf *dma_cs;
859 struct pipe_fence_handle *last_gfx_fence;
860 struct pipe_fence_handle *last_sdma_fence;
861 struct si_resource *eop_bug_scratch;
862 struct u_upload_mgr *cached_gtt_allocator;
863 struct threaded_context *tc;
864 struct u_suballocator *allocator_zeroed_memory;
865 struct slab_child_pool pool_transfers;
866 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
867 struct pipe_device_reset_callback device_reset_callback;
868 struct u_log_context *log;
869 void *query_result_shader;
870 void *sh_query_result_shader;
871
872 void (*emit_cache_flush)(struct si_context *ctx);
873
874 struct blitter_context *blitter;
875 void *noop_blend;
876 void *noop_dsa;
877 void *discard_rasterizer_state;
878 void *custom_dsa_flush;
879 void *custom_blend_resolve;
880 void *custom_blend_fmask_decompress;
881 void *custom_blend_eliminate_fastclear;
882 void *custom_blend_dcc_decompress;
883 void *vs_blit_pos;
884 void *vs_blit_pos_layered;
885 void *vs_blit_color;
886 void *vs_blit_color_layered;
887 void *vs_blit_texcoord;
888 void *cs_clear_buffer;
889 void *cs_copy_buffer;
890 void *cs_copy_image;
891 void *cs_copy_image_1d_array;
892 void *cs_clear_render_target;
893 void *cs_clear_render_target_1d_array;
894 void *cs_dcc_retile;
895 struct si_screen *screen;
896 struct pipe_debug_callback debug;
897 struct ac_llvm_compiler compiler; /* only non-threaded compilation */
898 struct si_shader_ctx_state fixed_func_tcs_shader;
899 /* Offset 0: EOP flush number; Offset 4: GDS prim restart counter */
900 struct si_resource *wait_mem_scratch;
901 unsigned wait_mem_number;
902 uint16_t prefetch_L2_mask;
903
904 bool has_graphics;
905 bool gfx_flush_in_progress:1;
906 bool gfx_last_ib_is_busy:1;
907 bool compute_is_busy:1;
908
909 unsigned num_gfx_cs_flushes;
910 unsigned initial_gfx_cs_size;
911 unsigned last_dirty_tex_counter;
912 unsigned last_dirty_buf_counter;
913 unsigned last_compressed_colortex_counter;
914 unsigned last_num_draw_calls;
915 unsigned flags; /* flush flags */
916 /* Current unaccounted memory usage. */
917 uint64_t vram;
918 uint64_t gtt;
919
920 /* Compute-based primitive discard. */
921 unsigned prim_discard_vertex_count_threshold;
922 struct pb_buffer *gds;
923 struct pb_buffer *gds_oa;
924 struct radeon_cmdbuf *prim_discard_compute_cs;
925 unsigned compute_gds_offset;
926 struct si_shader *compute_ib_last_shader;
927 uint32_t compute_rewind_va;
928 unsigned compute_num_prims_in_batch;
929 bool preserve_prim_restart_gds_at_flush;
930 /* index_ring is divided into 2 halves for doublebuffering. */
931 struct si_resource *index_ring;
932 unsigned index_ring_base; /* offset of a per-IB portion */
933 unsigned index_ring_offset; /* offset within a per-IB portion */
934 unsigned index_ring_size_per_ib; /* max available size per IB */
935 bool prim_discard_compute_ib_initialized;
936 /* For tracking the last execution barrier - it can be either
937 * a WRITE_DATA packet or a fence. */
938 uint32_t *last_pkt3_write_data;
939 struct si_resource *barrier_buf;
940 unsigned barrier_buf_offset;
941 struct pipe_fence_handle *last_ib_barrier_fence;
942 struct si_resource *last_ib_barrier_buf;
943 unsigned last_ib_barrier_buf_offset;
944
945 /* Atoms (direct states). */
946 union si_state_atoms atoms;
947 unsigned dirty_atoms; /* mask */
948 /* PM4 states (precomputed immutable states) */
949 unsigned dirty_states;
950 union si_state queued;
951 union si_state emitted;
952
953 /* Atom declarations. */
954 struct si_framebuffer framebuffer;
955 unsigned sample_locs_num_samples;
956 uint16_t sample_mask;
957 unsigned last_cb_target_mask;
958 struct si_blend_color blend_color;
959 struct si_clip_state clip_state;
960 struct si_shader_data shader_pointers;
961 struct si_stencil_ref stencil_ref;
962 struct pipe_scissor_state scissors[SI_MAX_VIEWPORTS];
963 struct si_streamout streamout;
964 struct si_viewports viewports;
965 unsigned num_window_rectangles;
966 bool window_rectangles_include;
967 struct pipe_scissor_state window_rectangles[4];
968
969 /* Precomputed states. */
970 struct si_pm4_state *init_config;
971 struct si_pm4_state *init_config_gs_rings;
972 bool init_config_has_vgt_flush;
973 struct si_pm4_state *vgt_shader_config[SI_NUM_VGT_STAGES_STATES];
974
975 /* shaders */
976 struct si_shader_ctx_state ps_shader;
977 struct si_shader_ctx_state gs_shader;
978 struct si_shader_ctx_state vs_shader;
979 struct si_shader_ctx_state tcs_shader;
980 struct si_shader_ctx_state tes_shader;
981 struct si_shader_ctx_state cs_prim_discard_state;
982 struct si_cs_shader_state cs_shader_state;
983
984 /* shader information */
985 struct si_vertex_elements *vertex_elements;
986 unsigned sprite_coord_enable;
987 unsigned cs_max_waves_per_sh;
988 bool flatshade;
989 bool do_update_shaders;
990
991 /* vertex buffer descriptors */
992 uint32_t *vb_descriptors_gpu_list;
993 struct si_resource *vb_descriptors_buffer;
994 unsigned vb_descriptors_offset;
995
996 /* shader descriptors */
997 struct si_descriptors descriptors[SI_NUM_DESCS];
998 unsigned descriptors_dirty;
999 unsigned shader_pointers_dirty;
1000 unsigned shader_needs_decompress_mask;
1001 struct si_buffer_resources rw_buffers;
1002 struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
1003 struct si_samplers samplers[SI_NUM_SHADERS];
1004 struct si_images images[SI_NUM_SHADERS];
1005 bool bo_list_add_all_resident_resources;
1006 bool bo_list_add_all_gfx_resources;
1007 bool bo_list_add_all_compute_resources;
1008
1009 /* other shader resources */
1010 struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on GFX7 */
1011 struct pipe_resource *esgs_ring;
1012 struct pipe_resource *gsvs_ring;
1013 struct pipe_resource *tess_rings;
1014 union pipe_color_union *border_color_table; /* in CPU memory, any endian */
1015 struct si_resource *border_color_buffer;
1016 union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
1017 unsigned border_color_count;
1018 unsigned num_vs_blit_sgprs;
1019 uint32_t vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
1020 uint32_t cs_user_data[4];
1021
1022 /* Vertex and index buffers. */
1023 bool vertex_buffers_dirty;
1024 bool vertex_buffer_pointer_dirty;
1025 struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
1026 uint16_t vertex_buffer_unaligned; /* bitmask of not dword-aligned buffers */
1027
1028 /* MSAA config state. */
1029 int ps_iter_samples;
1030 bool ps_uses_fbfetch;
1031 bool smoothing_enabled;
1032
1033 /* DB render state. */
1034 unsigned ps_db_shader_control;
1035 unsigned dbcb_copy_sample;
1036 bool dbcb_depth_copy_enabled:1;
1037 bool dbcb_stencil_copy_enabled:1;
1038 bool db_flush_depth_inplace:1;
1039 bool db_flush_stencil_inplace:1;
1040 bool db_depth_clear:1;
1041 bool db_depth_disable_expclear:1;
1042 bool db_stencil_clear:1;
1043 bool db_stencil_disable_expclear:1;
1044 bool occlusion_queries_disabled:1;
1045 bool generate_mipmap_for_depth:1;
1046
1047 /* Emitted draw state. */
1048 bool gs_tri_strip_adj_fix:1;
1049 bool ls_vgpr_fix:1;
1050 bool prim_discard_cs_instancing:1;
1051 bool ngg:1;
1052 int last_index_size;
1053 int last_base_vertex;
1054 int last_start_instance;
1055 int last_instance_count;
1056 int last_drawid;
1057 int last_sh_base_reg;
1058 int last_primitive_restart_en;
1059 int last_restart_index;
1060 int last_prim;
1061 int last_multi_vgt_param;
1062 int last_rast_prim;
1063 int last_flatshade_first;
1064 int last_binning_enabled;
1065 unsigned last_sc_line_stipple;
1066 unsigned current_vs_state;
1067 unsigned last_vs_state;
1068 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
1069
1070 /* Scratch buffer */
1071 struct si_resource *scratch_buffer;
1072 unsigned scratch_waves;
1073 unsigned spi_tmpring_size;
1074 unsigned max_seen_scratch_bytes_per_wave;
1075 unsigned max_seen_compute_scratch_bytes_per_wave;
1076
1077 struct si_resource *compute_scratch_buffer;
1078
1079 /* Emitted derived tessellation state. */
1080 /* Local shader (VS), or HS if LS-HS are merged. */
1081 struct si_shader *last_ls;
1082 struct si_shader_selector *last_tcs;
1083 int last_num_tcs_input_cp;
1084 int last_tes_sh_base;
1085 bool last_tess_uses_primid;
1086 unsigned last_num_patches;
1087 int last_ls_hs_config;
1088
1089 /* Debug state. */
1090 bool is_debug;
1091 struct si_saved_cs *current_saved_cs;
1092 uint64_t dmesg_timestamp;
1093 unsigned apitrace_call_number;
1094
1095 /* Other state */
1096 bool need_check_render_feedback;
1097 bool decompression_enabled;
1098 bool dpbb_force_off;
1099 bool vs_writes_viewport_index;
1100 bool vs_disables_clipping_viewport;
1101
1102 /* Precomputed IA_MULTI_VGT_PARAM */
1103 union si_vgt_param_key ia_multi_vgt_param_key;
1104 unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
1105
1106 /* Bindless descriptors. */
1107 struct si_descriptors bindless_descriptors;
1108 struct util_idalloc bindless_used_slots;
1109 unsigned num_bindless_descriptors;
1110 bool bindless_descriptors_dirty;
1111 bool graphics_bindless_pointer_dirty;
1112 bool compute_bindless_pointer_dirty;
1113
1114 /* Allocated bindless handles */
1115 struct hash_table *tex_handles;
1116 struct hash_table *img_handles;
1117
1118 /* Resident bindless handles */
1119 struct util_dynarray resident_tex_handles;
1120 struct util_dynarray resident_img_handles;
1121
1122 /* Resident bindless handles which need decompression */
1123 struct util_dynarray resident_tex_needs_color_decompress;
1124 struct util_dynarray resident_img_needs_color_decompress;
1125 struct util_dynarray resident_tex_needs_depth_decompress;
1126
1127 /* Bindless state */
1128 bool uses_bindless_samplers;
1129 bool uses_bindless_images;
1130
1131 /* MSAA sample locations.
1132 * The first index is the sample index.
1133 * The second index is the coordinate: X, Y. */
1134 struct {
1135 float x1[1][2];
1136 float x2[2][2];
1137 float x4[4][2];
1138 float x8[8][2];
1139 float x16[16][2];
1140 } sample_positions;
1141 struct pipe_resource *sample_pos_buffer;
1142
1143 /* Misc stats. */
1144 unsigned num_draw_calls;
1145 unsigned num_decompress_calls;
1146 unsigned num_mrt_draw_calls;
1147 unsigned num_prim_restart_calls;
1148 unsigned num_spill_draw_calls;
1149 unsigned num_compute_calls;
1150 unsigned num_spill_compute_calls;
1151 unsigned num_dma_calls;
1152 unsigned num_cp_dma_calls;
1153 unsigned num_vs_flushes;
1154 unsigned num_ps_flushes;
1155 unsigned num_cs_flushes;
1156 unsigned num_cb_cache_flushes;
1157 unsigned num_db_cache_flushes;
1158 unsigned num_L2_invalidates;
1159 unsigned num_L2_writebacks;
1160 unsigned num_resident_handles;
1161 uint64_t num_alloc_tex_transfer_bytes;
1162 unsigned last_tex_ps_draw_ratio; /* for query */
1163 unsigned compute_num_verts_accepted;
1164 unsigned compute_num_verts_rejected;
1165 unsigned compute_num_verts_ineligible; /* due to low vertex count */
1166 unsigned context_roll;
1167
1168 /* Queries. */
1169 /* Maintain the list of active queries for pausing between IBs. */
1170 int num_occlusion_queries;
1171 int num_perfect_occlusion_queries;
1172 int num_pipeline_stat_queries;
1173 struct list_head active_queries;
1174 unsigned num_cs_dw_queries_suspend;
1175
1176 /* Render condition. */
1177 struct pipe_query *render_cond;
1178 unsigned render_cond_mode;
1179 bool render_cond_invert;
1180 bool render_cond_force_off; /* for u_blitter */
1181
1182 /* For uploading data via GTT and copy to VRAM on context flush via SDMA. */
1183 bool sdma_uploads_in_progress;
1184 struct si_sdma_upload *sdma_uploads;
1185 unsigned num_sdma_uploads;
1186 unsigned max_sdma_uploads;
1187
1188 /* Shader-based queries. */
1189 struct list_head shader_query_buffers;
1190 unsigned num_active_shader_queries;
1191
1192 /* Statistics gathering for the DCC enablement heuristic. It can't be
1193 * in si_texture because si_texture can be shared by multiple
1194 * contexts. This is for back buffers only. We shouldn't get too many
1195 * of those.
1196 *
1197 * X11 DRI3 rotates among a finite set of back buffers. They should
1198 * all fit in this array. If they don't, separate DCC might never be
1199 * enabled by DCC stat gathering.
1200 */
1201 struct {
1202 struct si_texture *tex;
1203 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1204 struct pipe_query *ps_stats[3];
1205 /* If all slots are used and another slot is needed,
1206 * the least recently used slot is evicted based on this. */
1207 int64_t last_use_timestamp;
1208 bool query_active;
1209 } dcc_stats[5];
1210
1211 /* Copy one resource to another using async DMA. */
1212 void (*dma_copy)(struct pipe_context *ctx,
1213 struct pipe_resource *dst,
1214 unsigned dst_level,
1215 unsigned dst_x, unsigned dst_y, unsigned dst_z,
1216 struct pipe_resource *src,
1217 unsigned src_level,
1218 const struct pipe_box *src_box);
1219
1220 struct si_tracked_regs tracked_regs;
1221 };
1222
1223 /* cik_sdma.c */
1224 void cik_init_sdma_functions(struct si_context *sctx);
1225
1226 /* si_blit.c */
1227 enum si_blitter_op /* bitmask */
1228 {
1229 SI_SAVE_TEXTURES = 1,
1230 SI_SAVE_FRAMEBUFFER = 2,
1231 SI_SAVE_FRAGMENT_STATE = 4,
1232 SI_DISABLE_RENDER_COND = 8,
1233 };
1234
1235 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
1236 void si_blitter_end(struct si_context *sctx);
1237 void si_init_blit_functions(struct si_context *sctx);
1238 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
1239 void si_resource_copy_region(struct pipe_context *ctx,
1240 struct pipe_resource *dst,
1241 unsigned dst_level,
1242 unsigned dstx, unsigned dsty, unsigned dstz,
1243 struct pipe_resource *src,
1244 unsigned src_level,
1245 const struct pipe_box *src_box);
1246 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex);
1247
1248 /* si_buffer.c */
1249 bool si_rings_is_buffer_referenced(struct si_context *sctx,
1250 struct pb_buffer *buf,
1251 enum radeon_bo_usage usage);
1252 void *si_buffer_map_sync_with_rings(struct si_context *sctx,
1253 struct si_resource *resource,
1254 unsigned usage);
1255 void si_init_resource_fields(struct si_screen *sscreen,
1256 struct si_resource *res,
1257 uint64_t size, unsigned alignment);
1258 bool si_alloc_resource(struct si_screen *sscreen,
1259 struct si_resource *res);
1260 struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen,
1261 unsigned flags, unsigned usage,
1262 unsigned size, unsigned alignment);
1263 struct si_resource *si_aligned_buffer_create(struct pipe_screen *screen,
1264 unsigned flags, unsigned usage,
1265 unsigned size, unsigned alignment);
1266 void si_replace_buffer_storage(struct pipe_context *ctx,
1267 struct pipe_resource *dst,
1268 struct pipe_resource *src);
1269 void si_init_screen_buffer_functions(struct si_screen *sscreen);
1270 void si_init_buffer_functions(struct si_context *sctx);
1271
1272 /* si_clear.c */
1273 enum pipe_format si_simplify_cb_format(enum pipe_format format);
1274 bool vi_alpha_is_on_msb(struct si_screen *sscreen, enum pipe_format format);
1275 bool vi_dcc_clear_level(struct si_context *sctx,
1276 struct si_texture *tex,
1277 unsigned level, unsigned clear_value);
1278 void si_init_clear_functions(struct si_context *sctx);
1279
1280 /* si_compute_blit.c */
1281 unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher,
1282 enum si_cache_policy cache_policy);
1283 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1284 uint64_t offset, uint64_t size, uint32_t *clear_value,
1285 uint32_t clear_value_size, enum si_coherency coher,
1286 bool force_cpdma);
1287 void si_copy_buffer(struct si_context *sctx,
1288 struct pipe_resource *dst, struct pipe_resource *src,
1289 uint64_t dst_offset, uint64_t src_offset, unsigned size);
1290 void si_compute_copy_image(struct si_context *sctx,
1291 struct pipe_resource *dst,
1292 unsigned dst_level,
1293 struct pipe_resource *src,
1294 unsigned src_level,
1295 unsigned dstx, unsigned dsty, unsigned dstz,
1296 const struct pipe_box *src_box);
1297 void si_compute_clear_render_target(struct pipe_context *ctx,
1298 struct pipe_surface *dstsurf,
1299 const union pipe_color_union *color,
1300 unsigned dstx, unsigned dsty,
1301 unsigned width, unsigned height,
1302 bool render_condition_enabled);
1303 void si_retile_dcc(struct si_context *sctx, struct si_texture *tex);
1304 void si_init_compute_blit_functions(struct si_context *sctx);
1305
1306 /* si_cp_dma.c */
1307 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1308 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1309 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1310 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1311 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1312 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
1313 SI_CPDMA_SKIP_SYNC_AFTER | \
1314 SI_CPDMA_SKIP_SYNC_BEFORE | \
1315 SI_CPDMA_SKIP_GFX_SYNC | \
1316 SI_CPDMA_SKIP_BO_LIST_UPDATE)
1317
1318 void si_cp_dma_wait_for_idle(struct si_context *sctx);
1319 void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
1320 struct pipe_resource *dst, uint64_t offset,
1321 uint64_t size, unsigned value, unsigned user_flags,
1322 enum si_coherency coher, enum si_cache_policy cache_policy);
1323 void si_cp_dma_copy_buffer(struct si_context *sctx,
1324 struct pipe_resource *dst, struct pipe_resource *src,
1325 uint64_t dst_offset, uint64_t src_offset, unsigned size,
1326 unsigned user_flags, enum si_coherency coher,
1327 enum si_cache_policy cache_policy);
1328 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
1329 uint64_t offset, unsigned size);
1330 void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only);
1331 void si_test_gds(struct si_context *sctx);
1332 void si_cp_write_data(struct si_context *sctx, struct si_resource *buf,
1333 unsigned offset, unsigned size, unsigned dst_sel,
1334 unsigned engine, const void *data);
1335 void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs,
1336 unsigned dst_sel, struct si_resource *dst, unsigned dst_offset,
1337 unsigned src_sel, struct si_resource *src, unsigned src_offset);
1338
1339 /* si_debug.c */
1340 void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
1341 struct radeon_saved_cs *saved, bool get_buffer_list);
1342 void si_clear_saved_cs(struct radeon_saved_cs *saved);
1343 void si_destroy_saved_cs(struct si_saved_cs *scs);
1344 void si_auto_log_cs(void *data, struct u_log_context *log);
1345 void si_log_hw_flush(struct si_context *sctx);
1346 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
1347 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
1348 void si_init_debug_functions(struct si_context *sctx);
1349 void si_check_vm_faults(struct si_context *sctx,
1350 struct radeon_saved_cs *saved, enum ring_type ring);
1351 bool si_replace_shader(unsigned num, struct si_shader_binary *binary);
1352
1353 /* si_dma.c */
1354 void si_init_dma_functions(struct si_context *sctx);
1355
1356 /* si_dma_cs.c */
1357 void si_dma_emit_timestamp(struct si_context *sctx, struct si_resource *dst,
1358 uint64_t offset);
1359 void si_sdma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1360 uint64_t offset, uint64_t size, unsigned clear_value);
1361 void si_need_dma_space(struct si_context *ctx, unsigned num_dw,
1362 struct si_resource *dst, struct si_resource *src);
1363 void si_flush_dma_cs(struct si_context *ctx, unsigned flags,
1364 struct pipe_fence_handle **fence);
1365 void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst,
1366 uint64_t offset, uint64_t size, unsigned value);
1367
1368 /* si_fence.c */
1369 void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
1370 unsigned event, unsigned event_flags,
1371 unsigned dst_sel, unsigned int_sel, unsigned data_sel,
1372 struct si_resource *buf, uint64_t va,
1373 uint32_t new_fence, unsigned query_type);
1374 unsigned si_cp_write_fence_dwords(struct si_screen *screen);
1375 void si_cp_wait_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
1376 uint64_t va, uint32_t ref, uint32_t mask, unsigned flags);
1377 void si_init_fence_functions(struct si_context *ctx);
1378 void si_init_screen_fence_functions(struct si_screen *screen);
1379 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
1380 struct tc_unflushed_batch_token *tc_token);
1381
1382 /* si_get.c */
1383 void si_init_screen_get_functions(struct si_screen *sscreen);
1384
1385 /* si_gfx_cs.c */
1386 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
1387 struct pipe_fence_handle **fence);
1388 void si_allocate_gds(struct si_context *ctx);
1389 void si_begin_new_gfx_cs(struct si_context *ctx);
1390 void si_need_gfx_cs_space(struct si_context *ctx);
1391 void si_unref_sdma_uploads(struct si_context *sctx);
1392
1393 /* si_gpu_load.c */
1394 void si_gpu_load_kill_thread(struct si_screen *sscreen);
1395 uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
1396 unsigned si_end_counter(struct si_screen *sscreen, unsigned type,
1397 uint64_t begin);
1398
1399 /* si_compute.c */
1400 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs);
1401 void si_init_compute_functions(struct si_context *sctx);
1402
1403 /* si_compute_prim_discard.c */
1404 enum si_prim_discard_outcome {
1405 SI_PRIM_DISCARD_ENABLED,
1406 SI_PRIM_DISCARD_DISABLED,
1407 SI_PRIM_DISCARD_DRAW_SPLIT,
1408 };
1409
1410 void si_build_prim_discard_compute_shader(struct si_shader_context *ctx);
1411 enum si_prim_discard_outcome
1412 si_prepare_prim_discard_or_split_draw(struct si_context *sctx,
1413 const struct pipe_draw_info *info,
1414 bool primitive_restart);
1415 void si_compute_signal_gfx(struct si_context *sctx);
1416 void si_dispatch_prim_discard_cs_and_draw(struct si_context *sctx,
1417 const struct pipe_draw_info *info,
1418 unsigned index_size,
1419 unsigned base_vertex,
1420 uint64_t input_indexbuf_va,
1421 unsigned input_indexbuf_max_elements);
1422 void si_initialize_prim_discard_tunables(struct si_context *sctx);
1423
1424 /* si_perfcounters.c */
1425 void si_init_perfcounters(struct si_screen *screen);
1426 void si_destroy_perfcounters(struct si_screen *screen);
1427
1428 /* si_pipe.c */
1429 bool si_check_device_reset(struct si_context *sctx);
1430
1431 /* si_query.c */
1432 void si_init_screen_query_functions(struct si_screen *sscreen);
1433 void si_init_query_functions(struct si_context *sctx);
1434 void si_suspend_queries(struct si_context *sctx);
1435 void si_resume_queries(struct si_context *sctx);
1436
1437 /* si_shaderlib_tgsi.c */
1438 void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
1439 unsigned num_layers);
1440 void *si_create_fixed_func_tcs(struct si_context *sctx);
1441 void *si_create_dma_compute_shader(struct pipe_context *ctx,
1442 unsigned num_dwords_per_thread,
1443 bool dst_stream_cache_policy, bool is_copy);
1444 void *si_create_copy_image_compute_shader(struct pipe_context *ctx);
1445 void *si_create_copy_image_compute_shader_1d_array(struct pipe_context *ctx);
1446 void *si_clear_render_target_shader(struct pipe_context *ctx);
1447 void *si_clear_render_target_shader_1d_array(struct pipe_context *ctx);
1448 void *si_create_dcc_retile_cs(struct pipe_context *ctx);
1449 void *si_create_query_result_cs(struct si_context *sctx);
1450 void *gfx10_create_sh_query_result_cs(struct si_context *sctx);
1451
1452 /* gfx10_query.c */
1453 void gfx10_init_query(struct si_context *sctx);
1454 void gfx10_destroy_query(struct si_context *sctx);
1455
1456 /* si_test_dma.c */
1457 void si_test_dma(struct si_screen *sscreen);
1458
1459 /* si_test_clearbuffer.c */
1460 void si_test_dma_perf(struct si_screen *sscreen);
1461
1462 /* si_uvd.c */
1463 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
1464 const struct pipe_video_codec *templ);
1465
1466 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
1467 const struct pipe_video_buffer *tmpl);
1468
1469 /* si_viewport.c */
1470 void si_update_vs_viewport_state(struct si_context *ctx);
1471 void si_init_viewport_functions(struct si_context *ctx);
1472
1473 /* si_texture.c */
1474 bool si_prepare_for_dma_blit(struct si_context *sctx,
1475 struct si_texture *dst,
1476 unsigned dst_level, unsigned dstx,
1477 unsigned dsty, unsigned dstz,
1478 struct si_texture *src,
1479 unsigned src_level,
1480 const struct pipe_box *src_box);
1481 void si_eliminate_fast_color_clear(struct si_context *sctx,
1482 struct si_texture *tex);
1483 void si_texture_discard_cmask(struct si_screen *sscreen,
1484 struct si_texture *tex);
1485 bool si_init_flushed_depth_texture(struct pipe_context *ctx,
1486 struct pipe_resource *texture);
1487 void si_print_texture_info(struct si_screen *sscreen,
1488 struct si_texture *tex, struct u_log_context *log);
1489 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
1490 const struct pipe_resource *templ);
1491 bool vi_dcc_formats_compatible(struct si_screen *sscreen,
1492 enum pipe_format format1,
1493 enum pipe_format format2);
1494 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
1495 unsigned level,
1496 enum pipe_format view_format);
1497 void vi_disable_dcc_if_incompatible_format(struct si_context *sctx,
1498 struct pipe_resource *tex,
1499 unsigned level,
1500 enum pipe_format view_format);
1501 struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
1502 struct pipe_resource *texture,
1503 const struct pipe_surface *templ,
1504 unsigned width0, unsigned height0,
1505 unsigned width, unsigned height);
1506 unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
1507 void vi_separate_dcc_try_enable(struct si_context *sctx,
1508 struct si_texture *tex);
1509 void vi_separate_dcc_start_query(struct si_context *sctx,
1510 struct si_texture *tex);
1511 void vi_separate_dcc_stop_query(struct si_context *sctx,
1512 struct si_texture *tex);
1513 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
1514 struct si_texture *tex);
1515 bool si_texture_disable_dcc(struct si_context *sctx,
1516 struct si_texture *tex);
1517 void si_init_screen_texture_functions(struct si_screen *sscreen);
1518 void si_init_context_texture_functions(struct si_context *sctx);
1519
1520
1521 /*
1522 * common helpers
1523 */
1524
1525 static inline struct si_resource *si_resource(struct pipe_resource *r)
1526 {
1527 return (struct si_resource*)r;
1528 }
1529
1530 static inline void
1531 si_resource_reference(struct si_resource **ptr, struct si_resource *res)
1532 {
1533 pipe_resource_reference((struct pipe_resource **)ptr,
1534 (struct pipe_resource *)res);
1535 }
1536
1537 static inline void
1538 si_texture_reference(struct si_texture **ptr, struct si_texture *res)
1539 {
1540 pipe_resource_reference((struct pipe_resource **)ptr, &res->buffer.b.b);
1541 }
1542
1543 static inline bool
1544 vi_dcc_enabled(struct si_texture *tex, unsigned level)
1545 {
1546 return tex->surface.dcc_offset && level < tex->surface.num_dcc_levels;
1547 }
1548
1549 static inline unsigned
1550 si_tile_mode_index(struct si_texture *tex, unsigned level, bool stencil)
1551 {
1552 if (stencil)
1553 return tex->surface.u.legacy.stencil_tiling_index[level];
1554 else
1555 return tex->surface.u.legacy.tiling_index[level];
1556 }
1557
1558 static inline unsigned
1559 si_get_minimum_num_gfx_cs_dwords(struct si_context *sctx)
1560 {
1561 /* Don't count the needed CS space exactly and just use an upper bound.
1562 *
1563 * Also reserve space for stopping queries at the end of IB, because
1564 * the number of active queries is unlimited in theory.
1565 */
1566 return 2048 + sctx->num_cs_dw_queries_suspend;
1567 }
1568
1569 static inline void
1570 si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r)
1571 {
1572 if (r) {
1573 /* Add memory usage for need_gfx_cs_space */
1574 sctx->vram += si_resource(r)->vram_usage;
1575 sctx->gtt += si_resource(r)->gart_usage;
1576 }
1577 }
1578
1579 static inline void
1580 si_invalidate_draw_sh_constants(struct si_context *sctx)
1581 {
1582 sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
1583 sctx->last_instance_count = SI_INSTANCE_COUNT_UNKNOWN;
1584 }
1585
1586 static inline unsigned
1587 si_get_atom_bit(struct si_context *sctx, struct si_atom *atom)
1588 {
1589 return 1 << (atom - sctx->atoms.array);
1590 }
1591
1592 static inline void
1593 si_set_atom_dirty(struct si_context *sctx, struct si_atom *atom, bool dirty)
1594 {
1595 unsigned bit = si_get_atom_bit(sctx, atom);
1596
1597 if (dirty)
1598 sctx->dirty_atoms |= bit;
1599 else
1600 sctx->dirty_atoms &= ~bit;
1601 }
1602
1603 static inline bool
1604 si_is_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1605 {
1606 return (sctx->dirty_atoms & si_get_atom_bit(sctx, atom)) != 0;
1607 }
1608
1609 static inline void
1610 si_mark_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1611 {
1612 si_set_atom_dirty(sctx, atom, true);
1613 }
1614
1615 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
1616 {
1617 if (sctx->gs_shader.cso)
1618 return &sctx->gs_shader;
1619 if (sctx->tes_shader.cso)
1620 return &sctx->tes_shader;
1621
1622 return &sctx->vs_shader;
1623 }
1624
1625 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
1626 {
1627 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1628
1629 return vs->cso ? &vs->cso->info : NULL;
1630 }
1631
1632 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
1633 {
1634 if (sctx->gs_shader.cso &&
1635 sctx->gs_shader.current &&
1636 !sctx->gs_shader.current->key.as_ngg)
1637 return sctx->gs_shader.cso->gs_copy_shader;
1638
1639 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1640 return vs->current ? vs->current : NULL;
1641 }
1642
1643 static inline bool si_can_dump_shader(struct si_screen *sscreen,
1644 unsigned processor)
1645 {
1646 return sscreen->debug_flags & (1 << processor);
1647 }
1648
1649 static inline bool si_get_strmout_en(struct si_context *sctx)
1650 {
1651 return sctx->streamout.streamout_enabled ||
1652 sctx->streamout.prims_gen_query_enabled;
1653 }
1654
1655 static inline unsigned
1656 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
1657 {
1658 unsigned alignment, tcc_cache_line_size;
1659
1660 /* If the upload size is less than the cache line size (e.g. 16, 32),
1661 * the whole thing will fit into a cache line if we align it to its size.
1662 * The idea is that multiple small uploads can share a cache line.
1663 * If the upload size is greater, align it to the cache line size.
1664 */
1665 alignment = util_next_power_of_two(upload_size);
1666 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
1667 return MIN2(alignment, tcc_cache_line_size);
1668 }
1669
1670 static inline void
1671 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
1672 {
1673 if (pipe_reference(&(*dst)->reference, &src->reference))
1674 si_destroy_saved_cs(*dst);
1675
1676 *dst = src;
1677 }
1678
1679 static inline void
1680 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1681 bool shaders_read_metadata, bool dcc_pipe_aligned)
1682 {
1683 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
1684 SI_CONTEXT_INV_VCACHE;
1685
1686 if (sctx->chip_class >= GFX10) {
1687 if (sctx->screen->info.tcc_harvested)
1688 sctx->flags |= SI_CONTEXT_INV_L2;
1689 else if (shaders_read_metadata)
1690 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1691 } else if (sctx->chip_class == GFX9) {
1692 /* Single-sample color is coherent with shaders on GFX9, but
1693 * L2 metadata must be flushed if shaders read metadata.
1694 * (DCC, CMASK).
1695 */
1696 if (num_samples >= 2 ||
1697 (shaders_read_metadata && !dcc_pipe_aligned))
1698 sctx->flags |= SI_CONTEXT_INV_L2;
1699 else if (shaders_read_metadata)
1700 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1701 } else {
1702 /* GFX6-GFX8 */
1703 sctx->flags |= SI_CONTEXT_INV_L2;
1704 }
1705 }
1706
1707 static inline void
1708 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1709 bool include_stencil, bool shaders_read_metadata)
1710 {
1711 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
1712 SI_CONTEXT_INV_VCACHE;
1713
1714 if (sctx->chip_class >= GFX10) {
1715 if (sctx->screen->info.tcc_harvested)
1716 sctx->flags |= SI_CONTEXT_INV_L2;
1717 else if (shaders_read_metadata)
1718 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1719 } else if (sctx->chip_class == GFX9) {
1720 /* Single-sample depth (not stencil) is coherent with shaders
1721 * on GFX9, but L2 metadata must be flushed if shaders read
1722 * metadata.
1723 */
1724 if (num_samples >= 2 || include_stencil)
1725 sctx->flags |= SI_CONTEXT_INV_L2;
1726 else if (shaders_read_metadata)
1727 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1728 } else {
1729 /* GFX6-GFX8 */
1730 sctx->flags |= SI_CONTEXT_INV_L2;
1731 }
1732 }
1733
1734 static inline bool
1735 si_can_sample_zs(struct si_texture *tex, bool stencil_sampler)
1736 {
1737 return (stencil_sampler && tex->can_sample_s) ||
1738 (!stencil_sampler && tex->can_sample_z);
1739 }
1740
1741 static inline bool
1742 si_htile_enabled(struct si_texture *tex, unsigned level, unsigned zs_mask)
1743 {
1744 if (zs_mask == PIPE_MASK_S && tex->htile_stencil_disabled)
1745 return false;
1746
1747 return tex->surface.htile_offset && level == 0;
1748 }
1749
1750 static inline bool
1751 vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level, unsigned zs_mask)
1752 {
1753 assert(!tex->tc_compatible_htile || tex->surface.htile_offset);
1754 return tex->tc_compatible_htile && si_htile_enabled(tex, level, zs_mask);
1755 }
1756
1757 static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
1758 {
1759 if (sctx->ps_uses_fbfetch)
1760 return sctx->framebuffer.nr_color_samples;
1761
1762 return MIN2(sctx->ps_iter_samples, sctx->framebuffer.nr_color_samples);
1763 }
1764
1765 static inline unsigned si_get_total_colormask(struct si_context *sctx)
1766 {
1767 if (sctx->queued.named.rasterizer->rasterizer_discard)
1768 return 0;
1769
1770 struct si_shader_selector *ps = sctx->ps_shader.cso;
1771 if (!ps)
1772 return 0;
1773
1774 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1775 sctx->queued.named.blend->cb_target_mask;
1776
1777 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1778 colormask &= ps->colors_written_4bit;
1779 else if (!ps->colors_written_4bit)
1780 colormask = 0; /* color0 writes all cbufs, but it's not written */
1781
1782 return colormask;
1783 }
1784
1785 #define UTIL_ALL_PRIM_LINE_MODES ((1 << PIPE_PRIM_LINES) | \
1786 (1 << PIPE_PRIM_LINE_LOOP) | \
1787 (1 << PIPE_PRIM_LINE_STRIP) | \
1788 (1 << PIPE_PRIM_LINES_ADJACENCY) | \
1789 (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1790
1791 static inline bool util_prim_is_lines(unsigned prim)
1792 {
1793 return ((1 << prim) & UTIL_ALL_PRIM_LINE_MODES) != 0;
1794 }
1795
1796 static inline bool util_prim_is_points_or_lines(unsigned prim)
1797 {
1798 return ((1 << prim) & (UTIL_ALL_PRIM_LINE_MODES |
1799 (1 << PIPE_PRIM_POINTS))) != 0;
1800 }
1801
1802 static inline bool util_rast_prim_is_triangles(unsigned prim)
1803 {
1804 return ((1 << prim) & ((1 << PIPE_PRIM_TRIANGLES) |
1805 (1 << PIPE_PRIM_TRIANGLE_STRIP) |
1806 (1 << PIPE_PRIM_TRIANGLE_FAN) |
1807 (1 << PIPE_PRIM_QUADS) |
1808 (1 << PIPE_PRIM_QUAD_STRIP) |
1809 (1 << PIPE_PRIM_POLYGON) |
1810 (1 << PIPE_PRIM_TRIANGLES_ADJACENCY) |
1811 (1 << PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY)));
1812 }
1813
1814 /**
1815 * Return true if there is enough memory in VRAM and GTT for the buffers
1816 * added so far.
1817 *
1818 * \param vram VRAM memory size not added to the buffer list yet
1819 * \param gtt GTT memory size not added to the buffer list yet
1820 */
1821 static inline bool
1822 radeon_cs_memory_below_limit(struct si_screen *screen,
1823 struct radeon_cmdbuf *cs,
1824 uint64_t vram, uint64_t gtt)
1825 {
1826 vram += cs->used_vram;
1827 gtt += cs->used_gart;
1828
1829 /* Anything that goes above the VRAM size should go to GTT. */
1830 if (vram > screen->info.vram_size)
1831 gtt += vram - screen->info.vram_size;
1832
1833 /* Now we just need to check if we have enough GTT. */
1834 return gtt < screen->info.gart_size * 0.7;
1835 }
1836
1837 /**
1838 * Add a buffer to the buffer list for the given command stream (CS).
1839 *
1840 * All buffers used by a CS must be added to the list. This tells the kernel
1841 * driver which buffers are used by GPU commands. Other buffers can
1842 * be swapped out (not accessible) during execution.
1843 *
1844 * The buffer list becomes empty after every context flush and must be
1845 * rebuilt.
1846 */
1847 static inline void radeon_add_to_buffer_list(struct si_context *sctx,
1848 struct radeon_cmdbuf *cs,
1849 struct si_resource *bo,
1850 enum radeon_bo_usage usage,
1851 enum radeon_bo_priority priority)
1852 {
1853 assert(usage);
1854 sctx->ws->cs_add_buffer(
1855 cs, bo->buf,
1856 (enum radeon_bo_usage)(usage | RADEON_USAGE_SYNCHRONIZED),
1857 bo->domains, priority);
1858 }
1859
1860 /**
1861 * Same as above, but also checks memory usage and flushes the context
1862 * accordingly.
1863 *
1864 * When this SHOULD NOT be used:
1865 *
1866 * - if si_context_add_resource_size has been called for the buffer
1867 * followed by *_need_cs_space for checking the memory usage
1868 *
1869 * - if si_need_dma_space has been called for the buffer
1870 *
1871 * - when emitting state packets and draw packets (because preceding packets
1872 * can't be re-emitted at that point)
1873 *
1874 * - if shader resource "enabled_mask" is not up-to-date or there is
1875 * a different constraint disallowing a context flush
1876 */
1877 static inline void
1878 radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx,
1879 struct si_resource *bo,
1880 enum radeon_bo_usage usage,
1881 enum radeon_bo_priority priority,
1882 bool check_mem)
1883 {
1884 if (check_mem &&
1885 !radeon_cs_memory_below_limit(sctx->screen, sctx->gfx_cs,
1886 sctx->vram + bo->vram_usage,
1887 sctx->gtt + bo->gart_usage))
1888 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1889
1890 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, bo, usage, priority);
1891 }
1892
1893 static inline bool si_compute_prim_discard_enabled(struct si_context *sctx)
1894 {
1895 return sctx->prim_discard_vertex_count_threshold != UINT_MAX;
1896 }
1897
1898 static inline unsigned si_get_wave_size(struct si_screen *sscreen,
1899 enum pipe_shader_type shader_type,
1900 bool ngg, bool es)
1901 {
1902 if (shader_type == PIPE_SHADER_COMPUTE)
1903 return sscreen->compute_wave_size;
1904 else if (shader_type == PIPE_SHADER_FRAGMENT)
1905 return sscreen->ps_wave_size;
1906 else if ((shader_type == PIPE_SHADER_VERTEX && es && !ngg) ||
1907 (shader_type == PIPE_SHADER_TESS_EVAL && es && !ngg) ||
1908 (shader_type == PIPE_SHADER_GEOMETRY && !ngg)) /* legacy GS only supports Wave64 */
1909 return 64;
1910 else
1911 return sscreen->ge_wave_size;
1912 }
1913
1914 static inline unsigned si_get_shader_wave_size(struct si_shader *shader)
1915 {
1916 return si_get_wave_size(shader->selector->screen, shader->selector->type,
1917 shader->key.as_ngg, shader->key.as_es);
1918 }
1919
1920 #define PRINT_ERR(fmt, args...) \
1921 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
1922
1923 #endif