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radeonsi/gfx9: force the micro tile mode for MSAA resolve correctly on gfx9
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25 #ifndef SI_PIPE_H
26 #define SI_PIPE_H
27
28 #include "si_shader.h"
29 #include "si_state.h"
30
31 #include "util/u_dynarray.h"
32 #include "util/u_idalloc.h"
33 #include "util/u_threaded_context.h"
34
35 #if UTIL_ARCH_BIG_ENDIAN
36 #define SI_BIG_ENDIAN 1
37 #else
38 #define SI_BIG_ENDIAN 0
39 #endif
40
41 #define ATI_VENDOR_ID 0x1002
42 #define SI_PRIM_DISCARD_DEBUG 0
43 #define SI_NOT_QUERY 0xffffffff
44
45 /* The base vertex and primitive restart can be any number, but we must pick
46 * one which will mean "unknown" for the purpose of state tracking and
47 * the number shouldn't be a commonly-used one. */
48 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
49 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
50 #define SI_INSTANCE_COUNT_UNKNOWN INT_MIN
51 #define SI_NUM_SMOOTH_AA_SAMPLES 8
52 #define SI_MAX_POINT_SIZE 2048
53 #define SI_GS_PER_ES 128
54 /* Alignment for optimal CP DMA performance. */
55 #define SI_CPDMA_ALIGNMENT 32
56
57 /* Tunables for compute-based clear_buffer and copy_buffer: */
58 #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
59 #define SI_COMPUTE_COPY_DW_PER_THREAD 4
60 #define SI_COMPUTE_DST_CACHE_POLICY L2_STREAM
61
62 /* Pipeline & streamout query controls. */
63 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
64 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
65 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
66 /* Instruction cache. */
67 #define SI_CONTEXT_INV_ICACHE (1 << 3)
68 /* Scalar cache. (GFX6-9: scalar L1; GFX10: scalar L0)
69 * GFX10: This also invalidates the L1 shader array cache. */
70 #define SI_CONTEXT_INV_SCACHE (1 << 4)
71 /* Vector cache. (GFX6-9: vector L1; GFX10: vector L0)
72 * GFX10: This also invalidates the L1 shader array cache. */
73 #define SI_CONTEXT_INV_VCACHE (1 << 5)
74 /* L2 cache + L2 metadata cache writeback & invalidate.
75 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
76 #define SI_CONTEXT_INV_L2 (1 << 6)
77 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
78 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
79 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
80 #define SI_CONTEXT_WB_L2 (1 << 7)
81 /* Writeback & invalidate the L2 metadata cache only. It can only be coupled with
82 * a CB or DB flush. */
83 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
84 /* Framebuffer caches. */
85 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
86 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
87 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
88 /* Engine synchronization. */
89 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
90 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
91 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
92 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
93 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
94
95 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
96 #define SI_PREFETCH_LS (1 << 1)
97 #define SI_PREFETCH_HS (1 << 2)
98 #define SI_PREFETCH_ES (1 << 3)
99 #define SI_PREFETCH_GS (1 << 4)
100 #define SI_PREFETCH_VS (1 << 5)
101 #define SI_PREFETCH_PS (1 << 6)
102
103 #define SI_MAX_BORDER_COLORS 4096
104 #define SI_MAX_VIEWPORTS 16
105 #define SIX_BITS 0x3F
106 #define SI_MAP_BUFFER_ALIGNMENT 64
107 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
108
109 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
110 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
111 #define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
112 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
113 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
114 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
115 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
116 #define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
117 /* For const_uploader, upload data via GTT and copy to VRAM on context flush via SDMA. */
118 #define SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA (PIPE_RESOURCE_FLAG_DRV_PRIV << 8)
119 /* Set a micro tile mode: */
120 #define SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE (PIPE_RESOURCE_FLAG_DRV_PRIV << 9)
121 #define SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT (util_logbase2(PIPE_RESOURCE_FLAG_DRV_PRIV) + 10)
122 #define SI_RESOURCE_FLAG_MICRO_TILE_MODE_SET(x) (((x) & 0x3) << SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT)
123 #define SI_RESOURCE_FLAG_MICRO_TILE_MODE_GET(x) (((x) >> SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT) & 0x3)
124
125 enum si_clear_code
126 {
127 DCC_CLEAR_COLOR_0000 = 0x00000000,
128 DCC_CLEAR_COLOR_0001 = 0x40404040,
129 DCC_CLEAR_COLOR_1110 = 0x80808080,
130 DCC_CLEAR_COLOR_1111 = 0xC0C0C0C0,
131 DCC_CLEAR_COLOR_REG = 0x20202020,
132 DCC_UNCOMPRESSED = 0xFFFFFFFF,
133 };
134
135 #define SI_IMAGE_ACCESS_AS_BUFFER (1 << 7)
136
137 /* Debug flags. */
138 enum {
139 /* Shader logging options: */
140 DBG_VS = PIPE_SHADER_VERTEX,
141 DBG_PS = PIPE_SHADER_FRAGMENT,
142 DBG_GS = PIPE_SHADER_GEOMETRY,
143 DBG_TCS = PIPE_SHADER_TESS_CTRL,
144 DBG_TES = PIPE_SHADER_TESS_EVAL,
145 DBG_CS = PIPE_SHADER_COMPUTE,
146 DBG_NO_IR,
147 DBG_NO_TGSI,
148 DBG_NO_ASM,
149 DBG_PREOPT_IR,
150
151 /* Shader compiler options the shader cache should be aware of: */
152 DBG_FS_CORRECT_DERIVS_AFTER_KILL,
153 DBG_SI_SCHED,
154 DBG_GISEL,
155 DBG_W32_GE,
156 DBG_W32_PS,
157 DBG_W32_CS,
158 DBG_W64_GE,
159 DBG_W64_PS,
160 DBG_W64_CS,
161
162 /* Shader compiler options (with no effect on the shader cache): */
163 DBG_CHECK_IR,
164 DBG_MONOLITHIC_SHADERS,
165 DBG_NO_OPT_VARIANT,
166
167 /* Information logging options: */
168 DBG_INFO,
169 DBG_TEX,
170 DBG_COMPUTE,
171 DBG_VM,
172
173 /* Driver options: */
174 DBG_FORCE_SDMA,
175 DBG_NO_SDMA,
176 DBG_NO_SDMA_CLEARS,
177 DBG_NO_SDMA_COPY_IMAGE,
178 DBG_NO_WC,
179 DBG_CHECK_VM,
180 DBG_RESERVE_VMID,
181 DBG_ZERO_VRAM,
182
183 /* 3D engine options: */
184 DBG_NO_GFX,
185 DBG_NO_NGG,
186 DBG_ALWAYS_PD,
187 DBG_PD,
188 DBG_NO_PD,
189 DBG_SWITCH_ON_EOP,
190 DBG_NO_OUT_OF_ORDER,
191 DBG_NO_DPBB,
192 DBG_NO_DFSM,
193 DBG_DPBB,
194 DBG_DFSM,
195 DBG_NO_HYPERZ,
196 DBG_NO_RB_PLUS,
197 DBG_NO_2D_TILING,
198 DBG_NO_TILING,
199 DBG_NO_DCC,
200 DBG_NO_DCC_CLEAR,
201 DBG_NO_DCC_FB,
202 DBG_NO_DCC_MSAA,
203 DBG_NO_FMASK,
204
205 /* Tests: */
206 DBG_TEST_DMA,
207 DBG_TEST_VMFAULT_CP,
208 DBG_TEST_VMFAULT_SDMA,
209 DBG_TEST_VMFAULT_SHADER,
210 DBG_TEST_DMA_PERF,
211 DBG_TEST_GDS,
212 DBG_TEST_GDS_MM,
213 DBG_TEST_GDS_OA_MM,
214 };
215
216 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
217 #define DBG(name) (1ull << DBG_##name)
218
219 enum si_cache_policy {
220 L2_BYPASS,
221 L2_STREAM, /* same as SLC=1 */
222 L2_LRU, /* same as SLC=0 */
223 };
224
225 enum si_coherency {
226 SI_COHERENCY_NONE, /* no cache flushes needed */
227 SI_COHERENCY_SHADER,
228 SI_COHERENCY_CB_META,
229 SI_COHERENCY_CP,
230 };
231
232 struct si_compute;
233 struct si_shader_context;
234 struct hash_table;
235 struct u_suballocator;
236
237 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
238 * at the moment.
239 */
240 struct si_resource {
241 struct threaded_resource b;
242
243 /* Winsys objects. */
244 struct pb_buffer *buf;
245 uint64_t gpu_address;
246 /* Memory usage if the buffer placement is optimal. */
247 uint64_t vram_usage;
248 uint64_t gart_usage;
249
250 /* Resource properties. */
251 uint64_t bo_size;
252 unsigned bo_alignment;
253 enum radeon_bo_domain domains;
254 enum radeon_bo_flag flags;
255 unsigned bind_history;
256 int max_forced_staging_uploads;
257
258 /* The buffer range which is initialized (with a write transfer,
259 * streamout, DMA, or as a random access target). The rest of
260 * the buffer is considered invalid and can be mapped unsynchronized.
261 *
262 * This allows unsychronized mapping of a buffer range which hasn't
263 * been used yet. It's for applications which forget to use
264 * the unsynchronized map flag and expect the driver to figure it out.
265 */
266 struct util_range valid_buffer_range;
267
268 /* For buffers only. This indicates that a write operation has been
269 * performed by TC L2, but the cache hasn't been flushed.
270 * Any hw block which doesn't use or bypasses TC L2 should check this
271 * flag and flush the cache before using the buffer.
272 *
273 * For example, TC L2 must be flushed if a buffer which has been
274 * modified by a shader store instruction is about to be used as
275 * an index buffer. The reason is that VGT DMA index fetching doesn't
276 * use TC L2.
277 */
278 bool TC_L2_dirty;
279
280 /* Whether this resource is referenced by bindless handles. */
281 bool texture_handle_allocated;
282 bool image_handle_allocated;
283
284 /* Whether the resource has been exported via resource_get_handle. */
285 unsigned external_usage; /* PIPE_HANDLE_USAGE_* */
286 };
287
288 struct si_transfer {
289 struct threaded_transfer b;
290 struct si_resource *staging;
291 unsigned offset;
292 };
293
294 struct si_texture {
295 struct si_resource buffer;
296
297 struct radeon_surf surface;
298 struct si_texture *flushed_depth_texture;
299
300 /* One texture allocation can contain these buffers:
301 * - image (pixel data)
302 * - FMASK buffer (MSAA compression)
303 * - CMASK buffer (MSAA compression and/or legacy fast color clear)
304 * - HTILE buffer (Z/S compression and fast Z/S clear)
305 * - DCC buffer (color compression and new fast color clear)
306 * - displayable DCC buffer (if the DCC buffer is not displayable)
307 * - DCC retile mapping buffer (if the DCC buffer is not displayable)
308 */
309 uint64_t cmask_base_address_reg;
310 struct si_resource *cmask_buffer;
311 unsigned cb_color_info; /* fast clear enable bit */
312 unsigned color_clear_value[2];
313 unsigned last_msaa_resolve_target_micro_mode;
314 unsigned num_level0_transfers;
315 unsigned plane_index; /* other planes are different pipe_resources */
316 unsigned num_planes;
317
318 /* Depth buffer compression and fast clear. */
319 float depth_clear_value;
320 uint16_t dirty_level_mask; /* each bit says if that mipmap is compressed */
321 uint16_t stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
322 enum pipe_format db_render_format:16;
323 uint8_t stencil_clear_value;
324 bool fmask_is_not_identity:1;
325 bool tc_compatible_htile:1;
326 bool htile_stencil_disabled:1;
327 bool depth_cleared:1; /* if it was cleared at least once */
328 bool stencil_cleared:1; /* if it was cleared at least once */
329 bool upgraded_depth:1; /* upgraded from unorm to Z32_FLOAT */
330 bool is_depth:1;
331 bool db_compatible:1;
332 bool can_sample_z:1;
333 bool can_sample_s:1;
334
335 /* We need to track DCC dirtiness, because st/dri usually calls
336 * flush_resource twice per frame (not a bug) and we don't wanna
337 * decompress DCC twice. Also, the dirty tracking must be done even
338 * if DCC isn't used, because it's required by the DCC usage analysis
339 * for a possible future enablement.
340 */
341 bool separate_dcc_dirty:1;
342 bool displayable_dcc_dirty:1;
343
344 /* Statistics gathering for the DCC enablement heuristic. */
345 bool dcc_gather_statistics:1;
346 /* Counter that should be non-zero if the texture is bound to a
347 * framebuffer.
348 */
349 unsigned framebuffers_bound;
350 /* Whether the texture is a displayable back buffer and needs DCC
351 * decompression, which is expensive. Therefore, it's enabled only
352 * if statistics suggest that it will pay off and it's allocated
353 * separately. It can't be bound as a sampler by apps. Limited to
354 * target == 2D and last_level == 0. If enabled, dcc_offset contains
355 * the absolute GPUVM address, not the relative one.
356 */
357 struct si_resource *dcc_separate_buffer;
358 /* When DCC is temporarily disabled, the separate buffer is here. */
359 struct si_resource *last_dcc_separate_buffer;
360 /* Estimate of how much this color buffer is written to in units of
361 * full-screen draws: ps_invocations / (width * height)
362 * Shader kills, late Z, and blending with trivial discards make it
363 * inaccurate (we need to count CB updates, not PS invocations).
364 */
365 unsigned ps_draw_ratio;
366 /* The number of clears since the last DCC usage analysis. */
367 unsigned num_slow_clears;
368 };
369
370 struct si_surface {
371 struct pipe_surface base;
372
373 /* These can vary with block-compressed textures. */
374 uint16_t width0;
375 uint16_t height0;
376
377 bool color_initialized:1;
378 bool depth_initialized:1;
379
380 /* Misc. color flags. */
381 bool color_is_int8:1;
382 bool color_is_int10:1;
383 bool dcc_incompatible:1;
384
385 /* Color registers. */
386 unsigned cb_color_info;
387 unsigned cb_color_view;
388 unsigned cb_color_attrib;
389 unsigned cb_color_attrib2; /* GFX9 and later */
390 unsigned cb_color_attrib3; /* GFX10 and later */
391 unsigned cb_dcc_control; /* GFX8 and later */
392 unsigned spi_shader_col_format:8; /* no blending, no alpha-to-coverage. */
393 unsigned spi_shader_col_format_alpha:8; /* alpha-to-coverage */
394 unsigned spi_shader_col_format_blend:8; /* blending without alpha. */
395 unsigned spi_shader_col_format_blend_alpha:8; /* blending with alpha. */
396
397 /* DB registers. */
398 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE */
399 uint64_t db_stencil_base;
400 uint64_t db_htile_data_base;
401 unsigned db_depth_info;
402 unsigned db_z_info;
403 unsigned db_z_info2; /* GFX9 only */
404 unsigned db_depth_view;
405 unsigned db_depth_size;
406 unsigned db_depth_slice;
407 unsigned db_stencil_info;
408 unsigned db_stencil_info2; /* GFX9 only */
409 unsigned db_htile_surface;
410 };
411
412 struct si_mmio_counter {
413 unsigned busy;
414 unsigned idle;
415 };
416
417 union si_mmio_counters {
418 struct {
419 /* For global GPU load including SDMA. */
420 struct si_mmio_counter gpu;
421
422 /* GRBM_STATUS */
423 struct si_mmio_counter spi;
424 struct si_mmio_counter gui;
425 struct si_mmio_counter ta;
426 struct si_mmio_counter gds;
427 struct si_mmio_counter vgt;
428 struct si_mmio_counter ia;
429 struct si_mmio_counter sx;
430 struct si_mmio_counter wd;
431 struct si_mmio_counter bci;
432 struct si_mmio_counter sc;
433 struct si_mmio_counter pa;
434 struct si_mmio_counter db;
435 struct si_mmio_counter cp;
436 struct si_mmio_counter cb;
437
438 /* SRBM_STATUS2 */
439 struct si_mmio_counter sdma;
440
441 /* CP_STAT */
442 struct si_mmio_counter pfp;
443 struct si_mmio_counter meq;
444 struct si_mmio_counter me;
445 struct si_mmio_counter surf_sync;
446 struct si_mmio_counter cp_dma;
447 struct si_mmio_counter scratch_ram;
448 } named;
449 unsigned array[0];
450 };
451
452 struct si_memory_object {
453 struct pipe_memory_object b;
454 struct pb_buffer *buf;
455 uint32_t stride;
456 };
457
458 /* Saved CS data for debugging features. */
459 struct radeon_saved_cs {
460 uint32_t *ib;
461 unsigned num_dw;
462
463 struct radeon_bo_list_item *bo_list;
464 unsigned bo_count;
465 };
466
467 struct si_screen {
468 struct pipe_screen b;
469 struct radeon_winsys *ws;
470 struct disk_cache *disk_shader_cache;
471
472 struct radeon_info info;
473 uint64_t debug_flags;
474 char renderer_string[183];
475
476 void (*make_texture_descriptor)(
477 struct si_screen *screen,
478 struct si_texture *tex,
479 bool sampler,
480 enum pipe_texture_target target,
481 enum pipe_format pipe_format,
482 const unsigned char state_swizzle[4],
483 unsigned first_level, unsigned last_level,
484 unsigned first_layer, unsigned last_layer,
485 unsigned width, unsigned height, unsigned depth,
486 uint32_t *state,
487 uint32_t *fmask_state);
488
489 unsigned pa_sc_raster_config;
490 unsigned pa_sc_raster_config_1;
491 unsigned se_tile_repeat;
492 unsigned gs_table_depth;
493 unsigned tess_offchip_block_dw_size;
494 unsigned tess_offchip_ring_size;
495 unsigned tess_factor_ring_size;
496 unsigned vgt_hs_offchip_param;
497 unsigned eqaa_force_coverage_samples;
498 unsigned eqaa_force_z_samples;
499 unsigned eqaa_force_color_samples;
500 bool has_draw_indirect_multi;
501 bool has_out_of_order_rast;
502 bool assume_no_z_fights;
503 bool commutative_blend_add;
504 bool dpbb_allowed;
505 bool dfsm_allowed;
506 bool llvm_has_working_vgpr_indexing;
507 bool use_ngg;
508 bool use_ngg_streamout;
509
510 struct {
511 #define OPT_BOOL(name, dflt, description) bool name:1;
512 #include "si_debug_options.h"
513 } options;
514
515 /* Whether shaders are monolithic (1-part) or separate (3-part). */
516 bool use_monolithic_shaders;
517 bool record_llvm_ir;
518 bool dcc_msaa_allowed;
519
520 struct slab_parent_pool pool_transfers;
521
522 /* Texture filter settings. */
523 int force_aniso; /* -1 = disabled */
524
525 /* Auxiliary context. Mainly used to initialize resources.
526 * It must be locked prior to using and flushed before unlocking. */
527 struct pipe_context *aux_context;
528 simple_mtx_t aux_context_lock;
529
530 /* This must be in the screen, because UE4 uses one context for
531 * compilation and another one for rendering.
532 */
533 unsigned num_compilations;
534 /* Along with ST_DEBUG=precompile, this should show if applications
535 * are loading shaders on demand. This is a monotonic counter.
536 */
537 unsigned num_shaders_created;
538 unsigned num_shader_cache_hits;
539
540 /* GPU load thread. */
541 simple_mtx_t gpu_load_mutex;
542 thrd_t gpu_load_thread;
543 union si_mmio_counters mmio_counters;
544 volatile unsigned gpu_load_stop_thread; /* bool */
545
546 /* Performance counters. */
547 struct si_perfcounters *perfcounters;
548
549 /* If pipe_screen wants to recompute and re-emit the framebuffer,
550 * sampler, and image states of all contexts, it should atomically
551 * increment this.
552 *
553 * Each context will compare this with its own last known value of
554 * the counter before drawing and re-emit the states accordingly.
555 */
556 unsigned dirty_tex_counter;
557 unsigned dirty_buf_counter;
558
559 /* Atomically increment this counter when an existing texture's
560 * metadata is enabled or disabled in a way that requires changing
561 * contexts' compressed texture binding masks.
562 */
563 unsigned compressed_colortex_counter;
564
565 struct {
566 /* Context flags to set so that all writes from earlier jobs
567 * in the CP are seen by L2 clients.
568 */
569 unsigned cp_to_L2;
570
571 /* Context flags to set so that all writes from earlier jobs
572 * that end in L2 are seen by CP.
573 */
574 unsigned L2_to_cp;
575 } barrier_flags;
576
577 simple_mtx_t shader_parts_mutex;
578 struct si_shader_part *vs_prologs;
579 struct si_shader_part *tcs_epilogs;
580 struct si_shader_part *gs_prologs;
581 struct si_shader_part *ps_prologs;
582 struct si_shader_part *ps_epilogs;
583
584 /* Shader cache in memory.
585 *
586 * Design & limitations:
587 * - The shader cache is per screen (= per process), never saved to
588 * disk, and skips redundant shader compilations from TGSI to bytecode.
589 * - It can only be used with one-variant-per-shader support, in which
590 * case only the main (typically middle) part of shaders is cached.
591 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
592 * variants of VS and TES are cached, so LS and ES aren't.
593 * - GS and CS aren't cached, but it's certainly possible to cache
594 * those as well.
595 */
596 simple_mtx_t shader_cache_mutex;
597 struct hash_table *shader_cache;
598
599 /* Shader compiler queue for multithreaded compilation. */
600 struct util_queue shader_compiler_queue;
601 /* Use at most 3 normal compiler threads on quadcore and better.
602 * Hyperthreaded CPUs report the number of threads, but we want
603 * the number of cores. We only need this many threads for shader-db. */
604 struct ac_llvm_compiler compiler[24]; /* used by the queue only */
605
606 struct util_queue shader_compiler_queue_low_priority;
607 /* Use at most 2 low priority threads on quadcore and better.
608 * We want to minimize the impact on multithreaded Mesa. */
609 struct ac_llvm_compiler compiler_lowp[10];
610
611 unsigned compute_wave_size;
612 unsigned ps_wave_size;
613 unsigned ge_wave_size;
614 };
615
616 struct si_blend_color {
617 struct pipe_blend_color state;
618 bool any_nonzeros;
619 };
620
621 struct si_sampler_view {
622 struct pipe_sampler_view base;
623 /* [0..7] = image descriptor
624 * [4..7] = buffer descriptor */
625 uint32_t state[8];
626 uint32_t fmask_state[8];
627 const struct legacy_surf_level *base_level_info;
628 ubyte base_level;
629 ubyte block_width;
630 bool is_stencil_sampler;
631 bool is_integer;
632 bool dcc_incompatible;
633 };
634
635 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
636
637 struct si_sampler_state {
638 #ifndef NDEBUG
639 unsigned magic;
640 #endif
641 uint32_t val[4];
642 uint32_t integer_val[4];
643 uint32_t upgraded_depth_val[4];
644 };
645
646 struct si_cs_shader_state {
647 struct si_compute *program;
648 struct si_compute *emitted_program;
649 unsigned offset;
650 bool initialized;
651 bool uses_scratch;
652 };
653
654 struct si_samplers {
655 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
656 struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS];
657
658 /* The i-th bit is set if that element is enabled (non-NULL resource). */
659 unsigned enabled_mask;
660 uint32_t needs_depth_decompress_mask;
661 uint32_t needs_color_decompress_mask;
662 };
663
664 struct si_images {
665 struct pipe_image_view views[SI_NUM_IMAGES];
666 uint32_t needs_color_decompress_mask;
667 unsigned enabled_mask;
668 };
669
670 struct si_framebuffer {
671 struct pipe_framebuffer_state state;
672 unsigned colorbuf_enabled_4bit;
673 unsigned spi_shader_col_format;
674 unsigned spi_shader_col_format_alpha;
675 unsigned spi_shader_col_format_blend;
676 unsigned spi_shader_col_format_blend_alpha;
677 ubyte nr_samples:5; /* at most 16xAA */
678 ubyte log_samples:3; /* at most 4 = 16xAA */
679 ubyte nr_color_samples; /* at most 8xAA */
680 ubyte compressed_cb_mask;
681 ubyte uncompressed_cb_mask;
682 ubyte displayable_dcc_cb_mask;
683 ubyte color_is_int8;
684 ubyte color_is_int10;
685 ubyte dirty_cbufs;
686 ubyte dcc_overwrite_combiner_watermark;
687 ubyte min_bytes_per_pixel;
688 bool dirty_zsbuf;
689 bool any_dst_linear;
690 bool CB_has_shader_readable_metadata;
691 bool DB_has_shader_readable_metadata;
692 bool all_DCC_pipe_aligned;
693 };
694
695 enum si_quant_mode {
696 /* This is the list we want to support. */
697 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH,
698 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH,
699 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH,
700 };
701
702 struct si_signed_scissor {
703 int minx;
704 int miny;
705 int maxx;
706 int maxy;
707 enum si_quant_mode quant_mode;
708 };
709
710 struct si_viewports {
711 struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
712 struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS];
713 bool y_inverted;
714 };
715
716 struct si_clip_state {
717 struct pipe_clip_state state;
718 bool any_nonzeros;
719 };
720
721 struct si_streamout_target {
722 struct pipe_stream_output_target b;
723
724 /* The buffer where BUFFER_FILLED_SIZE is stored. */
725 struct si_resource *buf_filled_size;
726 unsigned buf_filled_size_offset;
727 bool buf_filled_size_valid;
728
729 unsigned stride_in_dw;
730 };
731
732 struct si_streamout {
733 bool begin_emitted;
734
735 unsigned enabled_mask;
736 unsigned num_targets;
737 struct si_streamout_target *targets[PIPE_MAX_SO_BUFFERS];
738
739 unsigned append_bitmask;
740 bool suspended;
741
742 /* External state which comes from the vertex shader,
743 * it must be set explicitly when binding a shader. */
744 uint16_t *stride_in_dw;
745 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
746
747 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
748 unsigned hw_enabled_mask;
749
750 /* The state of VGT_STRMOUT_(CONFIG|EN). */
751 bool streamout_enabled;
752 bool prims_gen_query_enabled;
753 int num_prims_gen_queries;
754 };
755
756 /* A shader state consists of the shader selector, which is a constant state
757 * object shared by multiple contexts and shouldn't be modified, and
758 * the current shader variant selected for this context.
759 */
760 struct si_shader_ctx_state {
761 struct si_shader_selector *cso;
762 struct si_shader *current;
763 };
764
765 #define SI_NUM_VGT_PARAM_KEY_BITS 12
766 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
767
768 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
769 * Some fields are set by state-change calls, most are set by draw_vbo.
770 */
771 union si_vgt_param_key {
772 struct {
773 #if UTIL_ARCH_LITTLE_ENDIAN
774 unsigned prim:4;
775 unsigned uses_instancing:1;
776 unsigned multi_instances_smaller_than_primgroup:1;
777 unsigned primitive_restart:1;
778 unsigned count_from_stream_output:1;
779 unsigned line_stipple_enabled:1;
780 unsigned uses_tess:1;
781 unsigned tess_uses_prim_id:1;
782 unsigned uses_gs:1;
783 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
784 #else /* UTIL_ARCH_BIG_ENDIAN */
785 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
786 unsigned uses_gs:1;
787 unsigned tess_uses_prim_id:1;
788 unsigned uses_tess:1;
789 unsigned line_stipple_enabled:1;
790 unsigned count_from_stream_output:1;
791 unsigned primitive_restart:1;
792 unsigned multi_instances_smaller_than_primgroup:1;
793 unsigned uses_instancing:1;
794 unsigned prim:4;
795 #endif
796 } u;
797 uint32_t index;
798 };
799
800 #define SI_NUM_VGT_STAGES_KEY_BITS 5
801 #define SI_NUM_VGT_STAGES_STATES (1 << SI_NUM_VGT_STAGES_KEY_BITS)
802
803 /* The VGT_SHADER_STAGES key used to index the table of precomputed values.
804 * Some fields are set by state-change calls, most are set by draw_vbo.
805 */
806 union si_vgt_stages_key {
807 struct {
808 #if UTIL_ARCH_LITTLE_ENDIAN
809 unsigned tess:1;
810 unsigned gs:1;
811 unsigned ngg_passthrough:1;
812 unsigned ngg:1; /* gfx10+ */
813 unsigned streamout:1; /* only used with NGG */
814 unsigned _pad:32 - SI_NUM_VGT_STAGES_KEY_BITS;
815 #else /* UTIL_ARCH_BIG_ENDIAN */
816 unsigned _pad:32 - SI_NUM_VGT_STAGES_KEY_BITS;
817 unsigned streamout:1;
818 unsigned ngg:1;
819 unsigned ngg_passthrough:1;
820 unsigned gs:1;
821 unsigned tess:1;
822 #endif
823 } u;
824 uint32_t index;
825 };
826
827 struct si_texture_handle
828 {
829 unsigned desc_slot;
830 bool desc_dirty;
831 struct pipe_sampler_view *view;
832 struct si_sampler_state sstate;
833 };
834
835 struct si_image_handle
836 {
837 unsigned desc_slot;
838 bool desc_dirty;
839 struct pipe_image_view view;
840 };
841
842 struct si_saved_cs {
843 struct pipe_reference reference;
844 struct si_context *ctx;
845 struct radeon_saved_cs gfx;
846 struct radeon_saved_cs compute;
847 struct si_resource *trace_buf;
848 unsigned trace_id;
849
850 unsigned gfx_last_dw;
851 unsigned compute_last_dw;
852 bool flushed;
853 int64_t time_flush;
854 };
855
856 struct si_sdma_upload {
857 struct si_resource *dst;
858 struct si_resource *src;
859 unsigned src_offset;
860 unsigned dst_offset;
861 unsigned size;
862 };
863
864 struct si_context {
865 struct pipe_context b; /* base class */
866
867 enum radeon_family family;
868 enum chip_class chip_class;
869
870 struct radeon_winsys *ws;
871 struct radeon_winsys_ctx *ctx;
872 struct radeon_cmdbuf *gfx_cs; /* compute IB if graphics is disabled */
873 struct radeon_cmdbuf *sdma_cs;
874 struct pipe_fence_handle *last_gfx_fence;
875 struct pipe_fence_handle *last_sdma_fence;
876 struct si_resource *eop_bug_scratch;
877 struct u_upload_mgr *cached_gtt_allocator;
878 struct threaded_context *tc;
879 struct u_suballocator *allocator_zeroed_memory;
880 struct slab_child_pool pool_transfers;
881 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
882 struct pipe_device_reset_callback device_reset_callback;
883 struct u_log_context *log;
884 void *query_result_shader;
885 void *sh_query_result_shader;
886
887 void (*emit_cache_flush)(struct si_context *ctx);
888
889 struct blitter_context *blitter;
890 void *noop_blend;
891 void *noop_dsa;
892 void *discard_rasterizer_state;
893 void *custom_dsa_flush;
894 void *custom_blend_resolve;
895 void *custom_blend_fmask_decompress;
896 void *custom_blend_eliminate_fastclear;
897 void *custom_blend_dcc_decompress;
898 void *vs_blit_pos;
899 void *vs_blit_pos_layered;
900 void *vs_blit_color;
901 void *vs_blit_color_layered;
902 void *vs_blit_texcoord;
903 void *cs_clear_buffer;
904 void *cs_copy_buffer;
905 void *cs_copy_image;
906 void *cs_copy_image_1d_array;
907 void *cs_clear_render_target;
908 void *cs_clear_render_target_1d_array;
909 void *cs_clear_12bytes_buffer;
910 void *cs_dcc_retile;
911 void *cs_fmask_expand[3][2]; /* [log2(samples)-1][is_array] */
912 struct si_screen *screen;
913 struct pipe_debug_callback debug;
914 struct ac_llvm_compiler compiler; /* only non-threaded compilation */
915 struct si_shader_ctx_state fixed_func_tcs_shader;
916 /* Offset 0: EOP flush number; Offset 4: GDS prim restart counter */
917 struct si_resource *wait_mem_scratch;
918 unsigned wait_mem_number;
919 uint16_t prefetch_L2_mask;
920
921 bool has_graphics;
922 bool gfx_flush_in_progress:1;
923 bool gfx_last_ib_is_busy:1;
924 bool compute_is_busy:1;
925
926 unsigned num_gfx_cs_flushes;
927 unsigned initial_gfx_cs_size;
928 unsigned last_dirty_tex_counter;
929 unsigned last_dirty_buf_counter;
930 unsigned last_compressed_colortex_counter;
931 unsigned last_num_draw_calls;
932 unsigned flags; /* flush flags */
933 /* Current unaccounted memory usage. */
934 uint64_t vram;
935 uint64_t gtt;
936
937 /* Compute-based primitive discard. */
938 unsigned prim_discard_vertex_count_threshold;
939 struct pb_buffer *gds;
940 struct pb_buffer *gds_oa;
941 struct radeon_cmdbuf *prim_discard_compute_cs;
942 unsigned compute_gds_offset;
943 struct si_shader *compute_ib_last_shader;
944 uint32_t compute_rewind_va;
945 unsigned compute_num_prims_in_batch;
946 bool preserve_prim_restart_gds_at_flush;
947 /* index_ring is divided into 2 halves for doublebuffering. */
948 struct si_resource *index_ring;
949 unsigned index_ring_base; /* offset of a per-IB portion */
950 unsigned index_ring_offset; /* offset within a per-IB portion */
951 unsigned index_ring_size_per_ib; /* max available size per IB */
952 bool prim_discard_compute_ib_initialized;
953 /* For tracking the last execution barrier - it can be either
954 * a WRITE_DATA packet or a fence. */
955 uint32_t *last_pkt3_write_data;
956 struct si_resource *barrier_buf;
957 unsigned barrier_buf_offset;
958 struct pipe_fence_handle *last_ib_barrier_fence;
959 struct si_resource *last_ib_barrier_buf;
960 unsigned last_ib_barrier_buf_offset;
961
962 /* Atoms (direct states). */
963 union si_state_atoms atoms;
964 unsigned dirty_atoms; /* mask */
965 /* PM4 states (precomputed immutable states) */
966 unsigned dirty_states;
967 union si_state queued;
968 union si_state emitted;
969
970 /* Atom declarations. */
971 struct si_framebuffer framebuffer;
972 unsigned sample_locs_num_samples;
973 uint16_t sample_mask;
974 unsigned last_cb_target_mask;
975 struct si_blend_color blend_color;
976 struct si_clip_state clip_state;
977 struct si_shader_data shader_pointers;
978 struct si_stencil_ref stencil_ref;
979 struct pipe_scissor_state scissors[SI_MAX_VIEWPORTS];
980 struct si_streamout streamout;
981 struct si_viewports viewports;
982 unsigned num_window_rectangles;
983 bool window_rectangles_include;
984 struct pipe_scissor_state window_rectangles[4];
985
986 /* Precomputed states. */
987 struct si_pm4_state *init_config;
988 struct si_pm4_state *init_config_gs_rings;
989 bool init_config_has_vgt_flush;
990 struct si_pm4_state *vgt_shader_config[SI_NUM_VGT_STAGES_STATES];
991
992 /* shaders */
993 struct si_shader_ctx_state ps_shader;
994 struct si_shader_ctx_state gs_shader;
995 struct si_shader_ctx_state vs_shader;
996 struct si_shader_ctx_state tcs_shader;
997 struct si_shader_ctx_state tes_shader;
998 struct si_shader_ctx_state cs_prim_discard_state;
999 struct si_cs_shader_state cs_shader_state;
1000
1001 /* shader information */
1002 struct si_vertex_elements *vertex_elements;
1003 unsigned sprite_coord_enable;
1004 unsigned cs_max_waves_per_sh;
1005 bool flatshade;
1006 bool do_update_shaders;
1007
1008 /* vertex buffer descriptors */
1009 uint32_t *vb_descriptors_gpu_list;
1010 struct si_resource *vb_descriptors_buffer;
1011 unsigned vb_descriptors_offset;
1012
1013 /* shader descriptors */
1014 struct si_descriptors descriptors[SI_NUM_DESCS];
1015 unsigned descriptors_dirty;
1016 unsigned shader_pointers_dirty;
1017 unsigned shader_needs_decompress_mask;
1018 struct si_buffer_resources rw_buffers;
1019 struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
1020 struct si_samplers samplers[SI_NUM_SHADERS];
1021 struct si_images images[SI_NUM_SHADERS];
1022 bool bo_list_add_all_resident_resources;
1023 bool bo_list_add_all_gfx_resources;
1024 bool bo_list_add_all_compute_resources;
1025
1026 /* other shader resources */
1027 struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on GFX7 */
1028 struct pipe_resource *esgs_ring;
1029 struct pipe_resource *gsvs_ring;
1030 struct pipe_resource *tess_rings;
1031 union pipe_color_union *border_color_table; /* in CPU memory, any endian */
1032 struct si_resource *border_color_buffer;
1033 union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
1034 unsigned border_color_count;
1035 unsigned num_vs_blit_sgprs;
1036 uint32_t vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
1037 uint32_t cs_user_data[4];
1038
1039 /* Vertex and index buffers. */
1040 bool vertex_buffers_dirty;
1041 bool vertex_buffer_pointer_dirty;
1042 struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
1043 uint16_t vertex_buffer_unaligned; /* bitmask of not dword-aligned buffers */
1044
1045 /* MSAA config state. */
1046 int ps_iter_samples;
1047 bool ps_uses_fbfetch;
1048 bool smoothing_enabled;
1049
1050 /* DB render state. */
1051 unsigned ps_db_shader_control;
1052 unsigned dbcb_copy_sample;
1053 bool dbcb_depth_copy_enabled:1;
1054 bool dbcb_stencil_copy_enabled:1;
1055 bool db_flush_depth_inplace:1;
1056 bool db_flush_stencil_inplace:1;
1057 bool db_depth_clear:1;
1058 bool db_depth_disable_expclear:1;
1059 bool db_stencil_clear:1;
1060 bool db_stencil_disable_expclear:1;
1061 bool occlusion_queries_disabled:1;
1062 bool generate_mipmap_for_depth:1;
1063
1064 /* Emitted draw state. */
1065 bool gs_tri_strip_adj_fix:1;
1066 bool ls_vgpr_fix:1;
1067 bool prim_discard_cs_instancing:1;
1068 bool ngg:1;
1069 int last_index_size;
1070 int last_base_vertex;
1071 int last_start_instance;
1072 int last_instance_count;
1073 int last_drawid;
1074 int last_sh_base_reg;
1075 int last_primitive_restart_en;
1076 int last_restart_index;
1077 int last_prim;
1078 int last_multi_vgt_param;
1079 int last_gs_out_prim;
1080 int last_binning_enabled;
1081 unsigned current_vs_state;
1082 unsigned last_vs_state;
1083 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
1084
1085 /* Scratch buffer */
1086 struct si_resource *scratch_buffer;
1087 unsigned scratch_waves;
1088 unsigned spi_tmpring_size;
1089 unsigned max_seen_scratch_bytes_per_wave;
1090 unsigned max_seen_compute_scratch_bytes_per_wave;
1091
1092 struct si_resource *compute_scratch_buffer;
1093
1094 /* Emitted derived tessellation state. */
1095 /* Local shader (VS), or HS if LS-HS are merged. */
1096 struct si_shader *last_ls;
1097 struct si_shader_selector *last_tcs;
1098 int last_num_tcs_input_cp;
1099 int last_tes_sh_base;
1100 bool last_tess_uses_primid;
1101 unsigned last_num_patches;
1102 int last_ls_hs_config;
1103
1104 /* Debug state. */
1105 bool is_debug;
1106 struct si_saved_cs *current_saved_cs;
1107 uint64_t dmesg_timestamp;
1108 unsigned apitrace_call_number;
1109
1110 /* Other state */
1111 bool need_check_render_feedback;
1112 bool decompression_enabled;
1113 bool dpbb_force_off;
1114 bool vs_writes_viewport_index;
1115 bool vs_disables_clipping_viewport;
1116
1117 /* Precomputed IA_MULTI_VGT_PARAM */
1118 union si_vgt_param_key ia_multi_vgt_param_key;
1119 unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
1120
1121 /* Bindless descriptors. */
1122 struct si_descriptors bindless_descriptors;
1123 struct util_idalloc bindless_used_slots;
1124 unsigned num_bindless_descriptors;
1125 bool bindless_descriptors_dirty;
1126 bool graphics_bindless_pointer_dirty;
1127 bool compute_bindless_pointer_dirty;
1128
1129 /* Allocated bindless handles */
1130 struct hash_table *tex_handles;
1131 struct hash_table *img_handles;
1132
1133 /* Resident bindless handles */
1134 struct util_dynarray resident_tex_handles;
1135 struct util_dynarray resident_img_handles;
1136
1137 /* Resident bindless handles which need decompression */
1138 struct util_dynarray resident_tex_needs_color_decompress;
1139 struct util_dynarray resident_img_needs_color_decompress;
1140 struct util_dynarray resident_tex_needs_depth_decompress;
1141
1142 /* Bindless state */
1143 bool uses_bindless_samplers;
1144 bool uses_bindless_images;
1145
1146 /* MSAA sample locations.
1147 * The first index is the sample index.
1148 * The second index is the coordinate: X, Y. */
1149 struct {
1150 float x1[1][2];
1151 float x2[2][2];
1152 float x4[4][2];
1153 float x8[8][2];
1154 float x16[16][2];
1155 } sample_positions;
1156 struct pipe_resource *sample_pos_buffer;
1157
1158 /* Misc stats. */
1159 unsigned num_draw_calls;
1160 unsigned num_decompress_calls;
1161 unsigned num_mrt_draw_calls;
1162 unsigned num_prim_restart_calls;
1163 unsigned num_spill_draw_calls;
1164 unsigned num_compute_calls;
1165 unsigned num_spill_compute_calls;
1166 unsigned num_dma_calls;
1167 unsigned num_cp_dma_calls;
1168 unsigned num_vs_flushes;
1169 unsigned num_ps_flushes;
1170 unsigned num_cs_flushes;
1171 unsigned num_cb_cache_flushes;
1172 unsigned num_db_cache_flushes;
1173 unsigned num_L2_invalidates;
1174 unsigned num_L2_writebacks;
1175 unsigned num_resident_handles;
1176 uint64_t num_alloc_tex_transfer_bytes;
1177 unsigned last_tex_ps_draw_ratio; /* for query */
1178 unsigned compute_num_verts_accepted;
1179 unsigned compute_num_verts_rejected;
1180 unsigned compute_num_verts_ineligible; /* due to low vertex count */
1181 unsigned context_roll;
1182
1183 /* Queries. */
1184 /* Maintain the list of active queries for pausing between IBs. */
1185 int num_occlusion_queries;
1186 int num_perfect_occlusion_queries;
1187 int num_pipeline_stat_queries;
1188 struct list_head active_queries;
1189 unsigned num_cs_dw_queries_suspend;
1190
1191 /* Render condition. */
1192 struct pipe_query *render_cond;
1193 unsigned render_cond_mode;
1194 bool render_cond_invert;
1195 bool render_cond_force_off; /* for u_blitter */
1196
1197 /* For uploading data via GTT and copy to VRAM on context flush via SDMA. */
1198 bool sdma_uploads_in_progress;
1199 struct si_sdma_upload *sdma_uploads;
1200 unsigned num_sdma_uploads;
1201 unsigned max_sdma_uploads;
1202
1203 /* Shader-based queries. */
1204 struct list_head shader_query_buffers;
1205 unsigned num_active_shader_queries;
1206
1207 /* Statistics gathering for the DCC enablement heuristic. It can't be
1208 * in si_texture because si_texture can be shared by multiple
1209 * contexts. This is for back buffers only. We shouldn't get too many
1210 * of those.
1211 *
1212 * X11 DRI3 rotates among a finite set of back buffers. They should
1213 * all fit in this array. If they don't, separate DCC might never be
1214 * enabled by DCC stat gathering.
1215 */
1216 struct {
1217 struct si_texture *tex;
1218 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1219 struct pipe_query *ps_stats[3];
1220 /* If all slots are used and another slot is needed,
1221 * the least recently used slot is evicted based on this. */
1222 int64_t last_use_timestamp;
1223 bool query_active;
1224 } dcc_stats[5];
1225
1226 /* Copy one resource to another using async DMA. */
1227 void (*dma_copy)(struct pipe_context *ctx,
1228 struct pipe_resource *dst,
1229 unsigned dst_level,
1230 unsigned dst_x, unsigned dst_y, unsigned dst_z,
1231 struct pipe_resource *src,
1232 unsigned src_level,
1233 const struct pipe_box *src_box);
1234
1235 struct si_tracked_regs tracked_regs;
1236 };
1237
1238 /* cik_sdma.c */
1239 void cik_init_sdma_functions(struct si_context *sctx);
1240
1241 /* si_blit.c */
1242 enum si_blitter_op /* bitmask */
1243 {
1244 SI_SAVE_TEXTURES = 1,
1245 SI_SAVE_FRAMEBUFFER = 2,
1246 SI_SAVE_FRAGMENT_STATE = 4,
1247 SI_DISABLE_RENDER_COND = 8,
1248 };
1249
1250 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
1251 void si_blitter_end(struct si_context *sctx);
1252 void si_init_blit_functions(struct si_context *sctx);
1253 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
1254 void si_resource_copy_region(struct pipe_context *ctx,
1255 struct pipe_resource *dst,
1256 unsigned dst_level,
1257 unsigned dstx, unsigned dsty, unsigned dstz,
1258 struct pipe_resource *src,
1259 unsigned src_level,
1260 const struct pipe_box *src_box);
1261 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex);
1262
1263 /* si_buffer.c */
1264 bool si_rings_is_buffer_referenced(struct si_context *sctx,
1265 struct pb_buffer *buf,
1266 enum radeon_bo_usage usage);
1267 void *si_buffer_map_sync_with_rings(struct si_context *sctx,
1268 struct si_resource *resource,
1269 unsigned usage);
1270 void si_init_resource_fields(struct si_screen *sscreen,
1271 struct si_resource *res,
1272 uint64_t size, unsigned alignment);
1273 bool si_alloc_resource(struct si_screen *sscreen,
1274 struct si_resource *res);
1275 struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen,
1276 unsigned flags, unsigned usage,
1277 unsigned size, unsigned alignment);
1278 struct si_resource *si_aligned_buffer_create(struct pipe_screen *screen,
1279 unsigned flags, unsigned usage,
1280 unsigned size, unsigned alignment);
1281 void si_replace_buffer_storage(struct pipe_context *ctx,
1282 struct pipe_resource *dst,
1283 struct pipe_resource *src);
1284 void si_init_screen_buffer_functions(struct si_screen *sscreen);
1285 void si_init_buffer_functions(struct si_context *sctx);
1286
1287 /* si_clear.c */
1288 enum pipe_format si_simplify_cb_format(enum pipe_format format);
1289 bool vi_alpha_is_on_msb(struct si_screen *sscreen, enum pipe_format format);
1290 bool vi_dcc_clear_level(struct si_context *sctx,
1291 struct si_texture *tex,
1292 unsigned level, unsigned clear_value);
1293 void si_init_clear_functions(struct si_context *sctx);
1294
1295 /* si_compute_blit.c */
1296 unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher,
1297 enum si_cache_policy cache_policy);
1298 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1299 uint64_t offset, uint64_t size, uint32_t *clear_value,
1300 uint32_t clear_value_size, enum si_coherency coher,
1301 bool force_cpdma);
1302 void si_copy_buffer(struct si_context *sctx,
1303 struct pipe_resource *dst, struct pipe_resource *src,
1304 uint64_t dst_offset, uint64_t src_offset, unsigned size);
1305 void si_compute_copy_image(struct si_context *sctx,
1306 struct pipe_resource *dst,
1307 unsigned dst_level,
1308 struct pipe_resource *src,
1309 unsigned src_level,
1310 unsigned dstx, unsigned dsty, unsigned dstz,
1311 const struct pipe_box *src_box);
1312 void si_compute_clear_render_target(struct pipe_context *ctx,
1313 struct pipe_surface *dstsurf,
1314 const union pipe_color_union *color,
1315 unsigned dstx, unsigned dsty,
1316 unsigned width, unsigned height,
1317 bool render_condition_enabled);
1318 void si_retile_dcc(struct si_context *sctx, struct si_texture *tex);
1319 void si_compute_expand_fmask(struct pipe_context *ctx, struct pipe_resource *tex);
1320 void si_init_compute_blit_functions(struct si_context *sctx);
1321
1322 /* si_cp_dma.c */
1323 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1324 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1325 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1326 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1327 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1328 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
1329 SI_CPDMA_SKIP_SYNC_AFTER | \
1330 SI_CPDMA_SKIP_SYNC_BEFORE | \
1331 SI_CPDMA_SKIP_GFX_SYNC | \
1332 SI_CPDMA_SKIP_BO_LIST_UPDATE)
1333
1334 void si_cp_dma_wait_for_idle(struct si_context *sctx);
1335 void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
1336 struct pipe_resource *dst, uint64_t offset,
1337 uint64_t size, unsigned value, unsigned user_flags,
1338 enum si_coherency coher, enum si_cache_policy cache_policy);
1339 void si_cp_dma_copy_buffer(struct si_context *sctx,
1340 struct pipe_resource *dst, struct pipe_resource *src,
1341 uint64_t dst_offset, uint64_t src_offset, unsigned size,
1342 unsigned user_flags, enum si_coherency coher,
1343 enum si_cache_policy cache_policy);
1344 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
1345 uint64_t offset, unsigned size);
1346 void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only);
1347 void si_test_gds(struct si_context *sctx);
1348 void si_cp_write_data(struct si_context *sctx, struct si_resource *buf,
1349 unsigned offset, unsigned size, unsigned dst_sel,
1350 unsigned engine, const void *data);
1351 void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs,
1352 unsigned dst_sel, struct si_resource *dst, unsigned dst_offset,
1353 unsigned src_sel, struct si_resource *src, unsigned src_offset);
1354
1355 /* si_debug.c */
1356 void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
1357 struct radeon_saved_cs *saved, bool get_buffer_list);
1358 void si_clear_saved_cs(struct radeon_saved_cs *saved);
1359 void si_destroy_saved_cs(struct si_saved_cs *scs);
1360 void si_auto_log_cs(void *data, struct u_log_context *log);
1361 void si_log_hw_flush(struct si_context *sctx);
1362 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
1363 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
1364 void si_init_debug_functions(struct si_context *sctx);
1365 void si_check_vm_faults(struct si_context *sctx,
1366 struct radeon_saved_cs *saved, enum ring_type ring);
1367 bool si_replace_shader(unsigned num, struct si_shader_binary *binary);
1368
1369 /* si_dma_cs.c */
1370 void si_dma_emit_timestamp(struct si_context *sctx, struct si_resource *dst,
1371 uint64_t offset);
1372 void si_sdma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1373 uint64_t offset, uint64_t size, unsigned clear_value);
1374 void si_sdma_copy_buffer(struct si_context *sctx, struct pipe_resource *dst,
1375 struct pipe_resource *src, uint64_t dst_offset,
1376 uint64_t src_offset, uint64_t size);
1377 void si_need_dma_space(struct si_context *ctx, unsigned num_dw,
1378 struct si_resource *dst, struct si_resource *src);
1379 void si_flush_dma_cs(struct si_context *ctx, unsigned flags,
1380 struct pipe_fence_handle **fence);
1381 void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst,
1382 uint64_t offset, uint64_t size, unsigned value);
1383
1384 /* si_fence.c */
1385 void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
1386 unsigned event, unsigned event_flags,
1387 unsigned dst_sel, unsigned int_sel, unsigned data_sel,
1388 struct si_resource *buf, uint64_t va,
1389 uint32_t new_fence, unsigned query_type);
1390 unsigned si_cp_write_fence_dwords(struct si_screen *screen);
1391 void si_cp_wait_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
1392 uint64_t va, uint32_t ref, uint32_t mask, unsigned flags);
1393 void si_init_fence_functions(struct si_context *ctx);
1394 void si_init_screen_fence_functions(struct si_screen *screen);
1395 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
1396 struct tc_unflushed_batch_token *tc_token);
1397
1398 /* si_get.c */
1399 void si_init_screen_get_functions(struct si_screen *sscreen);
1400
1401 /* si_gfx_cs.c */
1402 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
1403 struct pipe_fence_handle **fence);
1404 void si_allocate_gds(struct si_context *ctx);
1405 void si_begin_new_gfx_cs(struct si_context *ctx);
1406 void si_need_gfx_cs_space(struct si_context *ctx);
1407 void si_unref_sdma_uploads(struct si_context *sctx);
1408
1409 /* si_gpu_load.c */
1410 void si_gpu_load_kill_thread(struct si_screen *sscreen);
1411 uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
1412 unsigned si_end_counter(struct si_screen *sscreen, unsigned type,
1413 uint64_t begin);
1414
1415 /* si_compute.c */
1416 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs);
1417 void si_init_compute_functions(struct si_context *sctx);
1418
1419 /* si_compute_prim_discard.c */
1420 enum si_prim_discard_outcome {
1421 SI_PRIM_DISCARD_ENABLED,
1422 SI_PRIM_DISCARD_DISABLED,
1423 SI_PRIM_DISCARD_DRAW_SPLIT,
1424 };
1425
1426 void si_build_prim_discard_compute_shader(struct si_shader_context *ctx);
1427 enum si_prim_discard_outcome
1428 si_prepare_prim_discard_or_split_draw(struct si_context *sctx,
1429 const struct pipe_draw_info *info,
1430 bool primitive_restart);
1431 void si_compute_signal_gfx(struct si_context *sctx);
1432 void si_dispatch_prim_discard_cs_and_draw(struct si_context *sctx,
1433 const struct pipe_draw_info *info,
1434 unsigned index_size,
1435 unsigned base_vertex,
1436 uint64_t input_indexbuf_va,
1437 unsigned input_indexbuf_max_elements);
1438 void si_initialize_prim_discard_tunables(struct si_context *sctx);
1439
1440 /* si_pipe.c */
1441 void si_init_compiler(struct si_screen *sscreen, struct ac_llvm_compiler *compiler);
1442
1443 /* si_perfcounters.c */
1444 void si_init_perfcounters(struct si_screen *screen);
1445 void si_destroy_perfcounters(struct si_screen *screen);
1446
1447 /* si_query.c */
1448 void si_init_screen_query_functions(struct si_screen *sscreen);
1449 void si_init_query_functions(struct si_context *sctx);
1450 void si_suspend_queries(struct si_context *sctx);
1451 void si_resume_queries(struct si_context *sctx);
1452
1453 /* si_shaderlib_tgsi.c */
1454 void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
1455 unsigned num_layers);
1456 void *si_create_fixed_func_tcs(struct si_context *sctx);
1457 void *si_create_dma_compute_shader(struct pipe_context *ctx,
1458 unsigned num_dwords_per_thread,
1459 bool dst_stream_cache_policy, bool is_copy);
1460 void *si_create_copy_image_compute_shader(struct pipe_context *ctx);
1461 void *si_create_copy_image_compute_shader_1d_array(struct pipe_context *ctx);
1462 void *si_clear_render_target_shader(struct pipe_context *ctx);
1463 void *si_clear_render_target_shader_1d_array(struct pipe_context *ctx);
1464 void *si_clear_12bytes_buffer_shader(struct pipe_context *ctx);
1465 void *si_create_dcc_retile_cs(struct pipe_context *ctx);
1466 void *si_create_fmask_expand_cs(struct pipe_context *ctx, unsigned num_samples,
1467 bool is_array);
1468 void *si_create_query_result_cs(struct si_context *sctx);
1469 void *gfx10_create_sh_query_result_cs(struct si_context *sctx);
1470
1471 /* gfx10_query.c */
1472 void gfx10_init_query(struct si_context *sctx);
1473 void gfx10_destroy_query(struct si_context *sctx);
1474
1475 /* si_test_dma.c */
1476 void si_test_dma(struct si_screen *sscreen);
1477
1478 /* si_test_clearbuffer.c */
1479 void si_test_dma_perf(struct si_screen *sscreen);
1480
1481 /* si_uvd.c */
1482 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
1483 const struct pipe_video_codec *templ);
1484
1485 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
1486 const struct pipe_video_buffer *tmpl);
1487
1488 /* si_viewport.c */
1489 void si_update_vs_viewport_state(struct si_context *ctx);
1490 void si_init_viewport_functions(struct si_context *ctx);
1491
1492 /* si_texture.c */
1493 bool si_prepare_for_dma_blit(struct si_context *sctx,
1494 struct si_texture *dst,
1495 unsigned dst_level, unsigned dstx,
1496 unsigned dsty, unsigned dstz,
1497 struct si_texture *src,
1498 unsigned src_level,
1499 const struct pipe_box *src_box);
1500 void si_eliminate_fast_color_clear(struct si_context *sctx,
1501 struct si_texture *tex);
1502 void si_texture_discard_cmask(struct si_screen *sscreen,
1503 struct si_texture *tex);
1504 bool si_init_flushed_depth_texture(struct pipe_context *ctx,
1505 struct pipe_resource *texture);
1506 void si_print_texture_info(struct si_screen *sscreen,
1507 struct si_texture *tex, struct u_log_context *log);
1508 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
1509 const struct pipe_resource *templ);
1510 bool vi_dcc_formats_compatible(struct si_screen *sscreen,
1511 enum pipe_format format1,
1512 enum pipe_format format2);
1513 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
1514 unsigned level,
1515 enum pipe_format view_format);
1516 void vi_disable_dcc_if_incompatible_format(struct si_context *sctx,
1517 struct pipe_resource *tex,
1518 unsigned level,
1519 enum pipe_format view_format);
1520 struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
1521 struct pipe_resource *texture,
1522 const struct pipe_surface *templ,
1523 unsigned width0, unsigned height0,
1524 unsigned width, unsigned height);
1525 unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
1526 void vi_separate_dcc_try_enable(struct si_context *sctx,
1527 struct si_texture *tex);
1528 void vi_separate_dcc_start_query(struct si_context *sctx,
1529 struct si_texture *tex);
1530 void vi_separate_dcc_stop_query(struct si_context *sctx,
1531 struct si_texture *tex);
1532 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
1533 struct si_texture *tex);
1534 bool si_texture_disable_dcc(struct si_context *sctx,
1535 struct si_texture *tex);
1536 void si_init_screen_texture_functions(struct si_screen *sscreen);
1537 void si_init_context_texture_functions(struct si_context *sctx);
1538
1539
1540 /*
1541 * common helpers
1542 */
1543
1544 static inline struct si_resource *si_resource(struct pipe_resource *r)
1545 {
1546 return (struct si_resource*)r;
1547 }
1548
1549 static inline void
1550 si_resource_reference(struct si_resource **ptr, struct si_resource *res)
1551 {
1552 pipe_resource_reference((struct pipe_resource **)ptr,
1553 (struct pipe_resource *)res);
1554 }
1555
1556 static inline void
1557 si_texture_reference(struct si_texture **ptr, struct si_texture *res)
1558 {
1559 pipe_resource_reference((struct pipe_resource **)ptr, &res->buffer.b.b);
1560 }
1561
1562 static inline bool
1563 vi_dcc_enabled(struct si_texture *tex, unsigned level)
1564 {
1565 return tex->surface.dcc_offset && level < tex->surface.num_dcc_levels;
1566 }
1567
1568 static inline unsigned
1569 si_tile_mode_index(struct si_texture *tex, unsigned level, bool stencil)
1570 {
1571 if (stencil)
1572 return tex->surface.u.legacy.stencil_tiling_index[level];
1573 else
1574 return tex->surface.u.legacy.tiling_index[level];
1575 }
1576
1577 static inline unsigned
1578 si_get_minimum_num_gfx_cs_dwords(struct si_context *sctx)
1579 {
1580 /* Don't count the needed CS space exactly and just use an upper bound.
1581 *
1582 * Also reserve space for stopping queries at the end of IB, because
1583 * the number of active queries is unlimited in theory.
1584 */
1585 return 2048 + sctx->num_cs_dw_queries_suspend;
1586 }
1587
1588 static inline void
1589 si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r)
1590 {
1591 if (r) {
1592 /* Add memory usage for need_gfx_cs_space */
1593 sctx->vram += si_resource(r)->vram_usage;
1594 sctx->gtt += si_resource(r)->gart_usage;
1595 }
1596 }
1597
1598 static inline void
1599 si_invalidate_draw_sh_constants(struct si_context *sctx)
1600 {
1601 sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
1602 sctx->last_instance_count = SI_INSTANCE_COUNT_UNKNOWN;
1603 }
1604
1605 static inline unsigned
1606 si_get_atom_bit(struct si_context *sctx, struct si_atom *atom)
1607 {
1608 return 1 << (atom - sctx->atoms.array);
1609 }
1610
1611 static inline void
1612 si_set_atom_dirty(struct si_context *sctx, struct si_atom *atom, bool dirty)
1613 {
1614 unsigned bit = si_get_atom_bit(sctx, atom);
1615
1616 if (dirty)
1617 sctx->dirty_atoms |= bit;
1618 else
1619 sctx->dirty_atoms &= ~bit;
1620 }
1621
1622 static inline bool
1623 si_is_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1624 {
1625 return (sctx->dirty_atoms & si_get_atom_bit(sctx, atom)) != 0;
1626 }
1627
1628 static inline void
1629 si_mark_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1630 {
1631 si_set_atom_dirty(sctx, atom, true);
1632 }
1633
1634 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
1635 {
1636 if (sctx->gs_shader.cso)
1637 return &sctx->gs_shader;
1638 if (sctx->tes_shader.cso)
1639 return &sctx->tes_shader;
1640
1641 return &sctx->vs_shader;
1642 }
1643
1644 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
1645 {
1646 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1647
1648 return vs->cso ? &vs->cso->info : NULL;
1649 }
1650
1651 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
1652 {
1653 if (sctx->gs_shader.cso &&
1654 sctx->gs_shader.current &&
1655 !sctx->gs_shader.current->key.as_ngg)
1656 return sctx->gs_shader.cso->gs_copy_shader;
1657
1658 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1659 return vs->current ? vs->current : NULL;
1660 }
1661
1662 static inline bool si_can_dump_shader(struct si_screen *sscreen,
1663 unsigned processor)
1664 {
1665 return sscreen->debug_flags & (1 << processor);
1666 }
1667
1668 static inline bool si_get_strmout_en(struct si_context *sctx)
1669 {
1670 return sctx->streamout.streamout_enabled ||
1671 sctx->streamout.prims_gen_query_enabled;
1672 }
1673
1674 static inline unsigned
1675 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
1676 {
1677 unsigned alignment, tcc_cache_line_size;
1678
1679 /* If the upload size is less than the cache line size (e.g. 16, 32),
1680 * the whole thing will fit into a cache line if we align it to its size.
1681 * The idea is that multiple small uploads can share a cache line.
1682 * If the upload size is greater, align it to the cache line size.
1683 */
1684 alignment = util_next_power_of_two(upload_size);
1685 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
1686 return MIN2(alignment, tcc_cache_line_size);
1687 }
1688
1689 static inline void
1690 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
1691 {
1692 if (pipe_reference(&(*dst)->reference, &src->reference))
1693 si_destroy_saved_cs(*dst);
1694
1695 *dst = src;
1696 }
1697
1698 static inline void
1699 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1700 bool shaders_read_metadata, bool dcc_pipe_aligned)
1701 {
1702 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
1703 SI_CONTEXT_INV_VCACHE;
1704
1705 if (sctx->chip_class >= GFX10) {
1706 if (sctx->screen->info.tcc_harvested)
1707 sctx->flags |= SI_CONTEXT_INV_L2;
1708 else if (shaders_read_metadata)
1709 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1710 } else if (sctx->chip_class == GFX9) {
1711 /* Single-sample color is coherent with shaders on GFX9, but
1712 * L2 metadata must be flushed if shaders read metadata.
1713 * (DCC, CMASK).
1714 */
1715 if (num_samples >= 2 ||
1716 (shaders_read_metadata && !dcc_pipe_aligned))
1717 sctx->flags |= SI_CONTEXT_INV_L2;
1718 else if (shaders_read_metadata)
1719 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1720 } else {
1721 /* GFX6-GFX8 */
1722 sctx->flags |= SI_CONTEXT_INV_L2;
1723 }
1724 }
1725
1726 static inline void
1727 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1728 bool include_stencil, bool shaders_read_metadata)
1729 {
1730 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
1731 SI_CONTEXT_INV_VCACHE;
1732
1733 if (sctx->chip_class >= GFX10) {
1734 if (sctx->screen->info.tcc_harvested)
1735 sctx->flags |= SI_CONTEXT_INV_L2;
1736 else if (shaders_read_metadata)
1737 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1738 } else if (sctx->chip_class == GFX9) {
1739 /* Single-sample depth (not stencil) is coherent with shaders
1740 * on GFX9, but L2 metadata must be flushed if shaders read
1741 * metadata.
1742 */
1743 if (num_samples >= 2 || include_stencil)
1744 sctx->flags |= SI_CONTEXT_INV_L2;
1745 else if (shaders_read_metadata)
1746 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1747 } else {
1748 /* GFX6-GFX8 */
1749 sctx->flags |= SI_CONTEXT_INV_L2;
1750 }
1751 }
1752
1753 static inline bool
1754 si_can_sample_zs(struct si_texture *tex, bool stencil_sampler)
1755 {
1756 return (stencil_sampler && tex->can_sample_s) ||
1757 (!stencil_sampler && tex->can_sample_z);
1758 }
1759
1760 static inline bool
1761 si_htile_enabled(struct si_texture *tex, unsigned level, unsigned zs_mask)
1762 {
1763 if (zs_mask == PIPE_MASK_S && tex->htile_stencil_disabled)
1764 return false;
1765
1766 return tex->surface.htile_offset && level == 0;
1767 }
1768
1769 static inline bool
1770 vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level, unsigned zs_mask)
1771 {
1772 assert(!tex->tc_compatible_htile || tex->surface.htile_offset);
1773 return tex->tc_compatible_htile && si_htile_enabled(tex, level, zs_mask);
1774 }
1775
1776 static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
1777 {
1778 if (sctx->ps_uses_fbfetch)
1779 return sctx->framebuffer.nr_color_samples;
1780
1781 return MIN2(sctx->ps_iter_samples, sctx->framebuffer.nr_color_samples);
1782 }
1783
1784 static inline unsigned si_get_total_colormask(struct si_context *sctx)
1785 {
1786 if (sctx->queued.named.rasterizer->rasterizer_discard)
1787 return 0;
1788
1789 struct si_shader_selector *ps = sctx->ps_shader.cso;
1790 if (!ps)
1791 return 0;
1792
1793 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1794 sctx->queued.named.blend->cb_target_mask;
1795
1796 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1797 colormask &= ps->colors_written_4bit;
1798 else if (!ps->colors_written_4bit)
1799 colormask = 0; /* color0 writes all cbufs, but it's not written */
1800
1801 return colormask;
1802 }
1803
1804 #define UTIL_ALL_PRIM_LINE_MODES ((1 << PIPE_PRIM_LINES) | \
1805 (1 << PIPE_PRIM_LINE_LOOP) | \
1806 (1 << PIPE_PRIM_LINE_STRIP) | \
1807 (1 << PIPE_PRIM_LINES_ADJACENCY) | \
1808 (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1809
1810 static inline bool util_prim_is_lines(unsigned prim)
1811 {
1812 return ((1 << prim) & UTIL_ALL_PRIM_LINE_MODES) != 0;
1813 }
1814
1815 static inline bool util_prim_is_points_or_lines(unsigned prim)
1816 {
1817 return ((1 << prim) & (UTIL_ALL_PRIM_LINE_MODES |
1818 (1 << PIPE_PRIM_POINTS))) != 0;
1819 }
1820
1821 static inline bool util_rast_prim_is_triangles(unsigned prim)
1822 {
1823 return ((1 << prim) & ((1 << PIPE_PRIM_TRIANGLES) |
1824 (1 << PIPE_PRIM_TRIANGLE_STRIP) |
1825 (1 << PIPE_PRIM_TRIANGLE_FAN) |
1826 (1 << PIPE_PRIM_QUADS) |
1827 (1 << PIPE_PRIM_QUAD_STRIP) |
1828 (1 << PIPE_PRIM_POLYGON) |
1829 (1 << PIPE_PRIM_TRIANGLES_ADJACENCY) |
1830 (1 << PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY)));
1831 }
1832
1833 /**
1834 * Return true if there is enough memory in VRAM and GTT for the buffers
1835 * added so far.
1836 *
1837 * \param vram VRAM memory size not added to the buffer list yet
1838 * \param gtt GTT memory size not added to the buffer list yet
1839 */
1840 static inline bool
1841 radeon_cs_memory_below_limit(struct si_screen *screen,
1842 struct radeon_cmdbuf *cs,
1843 uint64_t vram, uint64_t gtt)
1844 {
1845 vram += cs->used_vram;
1846 gtt += cs->used_gart;
1847
1848 /* Anything that goes above the VRAM size should go to GTT. */
1849 if (vram > screen->info.vram_size)
1850 gtt += vram - screen->info.vram_size;
1851
1852 /* Now we just need to check if we have enough GTT. */
1853 return gtt < screen->info.gart_size * 0.7;
1854 }
1855
1856 /**
1857 * Add a buffer to the buffer list for the given command stream (CS).
1858 *
1859 * All buffers used by a CS must be added to the list. This tells the kernel
1860 * driver which buffers are used by GPU commands. Other buffers can
1861 * be swapped out (not accessible) during execution.
1862 *
1863 * The buffer list becomes empty after every context flush and must be
1864 * rebuilt.
1865 */
1866 static inline void radeon_add_to_buffer_list(struct si_context *sctx,
1867 struct radeon_cmdbuf *cs,
1868 struct si_resource *bo,
1869 enum radeon_bo_usage usage,
1870 enum radeon_bo_priority priority)
1871 {
1872 assert(usage);
1873 sctx->ws->cs_add_buffer(
1874 cs, bo->buf,
1875 (enum radeon_bo_usage)(usage | RADEON_USAGE_SYNCHRONIZED),
1876 bo->domains, priority);
1877 }
1878
1879 /**
1880 * Same as above, but also checks memory usage and flushes the context
1881 * accordingly.
1882 *
1883 * When this SHOULD NOT be used:
1884 *
1885 * - if si_context_add_resource_size has been called for the buffer
1886 * followed by *_need_cs_space for checking the memory usage
1887 *
1888 * - if si_need_dma_space has been called for the buffer
1889 *
1890 * - when emitting state packets and draw packets (because preceding packets
1891 * can't be re-emitted at that point)
1892 *
1893 * - if shader resource "enabled_mask" is not up-to-date or there is
1894 * a different constraint disallowing a context flush
1895 */
1896 static inline void
1897 radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx,
1898 struct si_resource *bo,
1899 enum radeon_bo_usage usage,
1900 enum radeon_bo_priority priority,
1901 bool check_mem)
1902 {
1903 if (check_mem &&
1904 !radeon_cs_memory_below_limit(sctx->screen, sctx->gfx_cs,
1905 sctx->vram + bo->vram_usage,
1906 sctx->gtt + bo->gart_usage))
1907 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1908
1909 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, bo, usage, priority);
1910 }
1911
1912 static inline bool si_compute_prim_discard_enabled(struct si_context *sctx)
1913 {
1914 return sctx->prim_discard_vertex_count_threshold != UINT_MAX;
1915 }
1916
1917 static inline unsigned si_get_wave_size(struct si_screen *sscreen,
1918 enum pipe_shader_type shader_type,
1919 bool ngg, bool es)
1920 {
1921 if (shader_type == PIPE_SHADER_COMPUTE)
1922 return sscreen->compute_wave_size;
1923 else if (shader_type == PIPE_SHADER_FRAGMENT)
1924 return sscreen->ps_wave_size;
1925 else if ((shader_type == PIPE_SHADER_VERTEX && es && !ngg) ||
1926 (shader_type == PIPE_SHADER_TESS_EVAL && es && !ngg) ||
1927 (shader_type == PIPE_SHADER_GEOMETRY && !ngg)) /* legacy GS only supports Wave64 */
1928 return 64;
1929 else
1930 return sscreen->ge_wave_size;
1931 }
1932
1933 static inline unsigned si_get_shader_wave_size(struct si_shader *shader)
1934 {
1935 return si_get_wave_size(shader->selector->screen, shader->selector->type,
1936 shader->key.as_ngg, shader->key.as_es);
1937 }
1938
1939 #define PRINT_ERR(fmt, args...) \
1940 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
1941
1942 #endif